diff --git a/.properties b/.properties index 6979eeef74..dcf7d79095 100644 --- a/.properties +++ b/.properties @@ -1,6 +1,6 @@ id=com.silabs.sdk.stack.sisdk -version=2024.12.0 +version=2024.12.1 label=Simplicity SDK Suite description=Simplicity SDK Suite diff --git a/app/bluetooth/bluetooth_experimental_demos.xml b/app/bluetooth/bluetooth_experimental_demos.xml index 7e711389ff..a0923eaca9 100644 --- a/app/bluetooth/bluetooth_experimental_demos.xml +++ b/app/bluetooth/bluetooth_experimental_demos.xml @@ -6,7 +6,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -28,7 +28,7 @@ - + @@ -39,7 +39,7 @@ - + @@ -50,7 +50,7 @@ - + @@ -61,7 +61,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -83,18 +83,18 @@ - + - + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - + + + @@ -105,7 +105,7 @@ - + @@ -116,7 +116,7 @@ - + @@ -127,7 +127,7 @@ - + @@ -138,18 +138,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -160,7 +149,7 @@ - + @@ -171,7 +160,7 @@ - + @@ -182,7 +171,7 @@ - + @@ -193,7 +182,7 @@ - + @@ -204,7 +193,7 @@ - + @@ -215,7 +204,7 @@ - + @@ -226,7 +215,7 @@ - + @@ -237,7 +226,7 @@ - + @@ -248,7 +237,7 @@ - + @@ -259,7 +248,7 @@ - + @@ -270,7 +259,29 @@ - + + + + + + + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. + + + + + + + + + + + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. + + + + + @@ -281,7 +292,7 @@ - + @@ -292,7 +303,7 @@ - + @@ -303,7 +314,7 @@ - + @@ -314,7 +325,7 @@ - + @@ -325,7 +336,7 @@ - + @@ -336,7 +347,7 @@ - + @@ -347,84 +358,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -435,7 +369,7 @@ - + @@ -446,7 +380,7 @@ - + @@ -457,7 +391,7 @@ - + @@ -468,7 +402,7 @@ - + @@ -479,7 +413,7 @@ - + @@ -490,7 +424,7 @@ - + @@ -501,7 +435,7 @@ - + @@ -512,18 +446,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -534,7 +457,7 @@ - + @@ -545,7 +468,7 @@ - + @@ -556,7 +479,7 @@ - + @@ -567,7 +490,7 @@ - + @@ -578,7 +501,7 @@ - + @@ -589,7 +512,7 @@ - + @@ -600,7 +523,7 @@ - + @@ -611,7 +534,7 @@ - + @@ -622,7 +545,7 @@ - + @@ -633,7 +556,7 @@ - + @@ -644,7 +567,7 @@ - + @@ -655,7 +578,7 @@ - + @@ -666,62 +589,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -732,7 +600,7 @@ - + @@ -743,7 +611,7 @@ - + @@ -754,7 +622,7 @@ - + @@ -765,29 +633,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -798,7 +644,7 @@ - + @@ -809,7 +655,7 @@ - + @@ -818,9 +664,9 @@ Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - + - + @@ -829,9 +675,9 @@ Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - + - + @@ -842,7 +688,7 @@ - + @@ -853,7 +699,7 @@ - + @@ -864,7 +710,7 @@ - + @@ -875,7 +721,7 @@ - + @@ -886,7 +732,7 @@ - + @@ -897,51 +743,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -952,7 +754,7 @@ - + @@ -963,18 +765,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -985,7 +776,7 @@ - + @@ -996,7 +787,7 @@ - + @@ -1007,7 +798,7 @@ - + @@ -1018,7 +809,7 @@ - + @@ -1029,7 +820,7 @@ - + @@ -1040,7 +831,7 @@ - + @@ -1051,7 +842,7 @@ - + @@ -1062,18 +853,18 @@ - + - + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - + + + @@ -1084,7 +875,7 @@ - + @@ -1095,7 +886,7 @@ - + @@ -1106,7 +897,7 @@ - + @@ -1117,18 +908,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -1139,7 +919,7 @@ - + @@ -1150,7 +930,7 @@ - + @@ -1161,7 +941,7 @@ - + @@ -1172,7 +952,7 @@ - + @@ -1183,7 +963,7 @@ - + @@ -1194,7 +974,7 @@ - + @@ -1205,7 +985,7 @@ - + @@ -1216,7 +996,7 @@ - + @@ -1227,7 +1007,7 @@ - + @@ -1238,7 +1018,7 @@ - + @@ -1249,7 +1029,29 @@ - + + + + + + + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. + + + + + + + + + + + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. + + + + + @@ -1260,7 +1062,7 @@ - + @@ -1271,7 +1073,7 @@ - + @@ -1282,7 +1084,7 @@ - + @@ -1293,7 +1095,7 @@ - + @@ -1304,7 +1106,7 @@ - + @@ -1315,7 +1117,7 @@ - + @@ -1326,84 +1128,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -1414,7 +1139,7 @@ - + @@ -1425,7 +1150,7 @@ - + @@ -1436,7 +1161,7 @@ - + @@ -1447,7 +1172,7 @@ - + @@ -1458,7 +1183,7 @@ - + @@ -1469,7 +1194,7 @@ - + @@ -1480,7 +1205,7 @@ - + @@ -1491,18 +1216,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -1513,7 +1227,7 @@ - + @@ -1524,7 +1238,7 @@ - + @@ -1535,7 +1249,7 @@ - + @@ -1546,7 +1260,7 @@ - + @@ -1557,7 +1271,7 @@ - + @@ -1568,7 +1282,7 @@ - + @@ -1579,7 +1293,7 @@ - + @@ -1590,7 +1304,7 @@ - + @@ -1601,7 +1315,7 @@ - + @@ -1612,7 +1326,7 @@ - + @@ -1623,7 +1337,7 @@ - + @@ -1634,7 +1348,7 @@ - + @@ -1645,62 +1359,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -1711,7 +1370,7 @@ - + @@ -1722,7 +1381,7 @@ - + @@ -1733,7 +1392,7 @@ - + @@ -1744,29 +1403,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -1777,7 +1414,7 @@ - + @@ -1788,7 +1425,7 @@ - + @@ -1797,9 +1434,9 @@ Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - + - + @@ -1808,9 +1445,9 @@ Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - + - + @@ -1821,7 +1458,7 @@ - + @@ -1832,7 +1469,7 @@ - + @@ -1843,7 +1480,7 @@ - + @@ -1854,7 +1491,7 @@ - + @@ -1865,7 +1502,7 @@ - + @@ -1876,51 +1513,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + @@ -1931,7 +1524,7 @@ - + @@ -1942,18 +1535,7 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + diff --git a/app/bluetooth/bluetooth_experimental_templates.xml b/app/bluetooth/bluetooth_experimental_templates.xml index 0f01aa9901..003634591b 100644 --- a/app/bluetooth/bluetooth_experimental_templates.xml +++ b/app/bluetooth/bluetooth_experimental_templates.xml @@ -6,7 +6,7 @@ - + @@ -22,7 +22,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -53,7 +53,7 @@ - + @@ -68,7 +68,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -98,8 +98,8 @@ - - + + @@ -113,8 +113,8 @@ - - + + @@ -128,8 +128,8 @@ - - + + @@ -143,8 +143,8 @@ - - + + @@ -158,8 +158,8 @@ - - + + @@ -173,8 +173,8 @@ - - + + @@ -188,8 +188,8 @@ - - + + @@ -203,7 +203,7 @@ - + @@ -233,7 +233,7 @@ - + @@ -263,8 +263,8 @@ - - + + @@ -278,8 +278,8 @@ - - + + @@ -293,8 +293,8 @@ - - + + @@ -308,8 +308,8 @@ - - + + @@ -323,8 +323,8 @@ - - + + @@ -338,8 +338,8 @@ - - + + diff --git a/app/bluetooth/bluetooth_internal_demos.xml b/app/bluetooth/bluetooth_internal_demos.xml index c35b4c2bc5..7bb54cb388 100644 --- a/app/bluetooth/bluetooth_internal_demos.xml +++ b/app/bluetooth/bluetooth_internal_demos.xml @@ -1,40 +1,28 @@ - - This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. - - - - - - - - - - - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. - - - + + + - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. - - - + + + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -42,11 +30,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -54,11 +42,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -66,11 +54,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -78,11 +66,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -90,11 +78,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -102,11 +90,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -114,11 +102,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -126,11 +114,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -138,11 +126,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -150,11 +138,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -162,11 +150,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -174,11 +162,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -186,11 +174,47 @@ - + + + + + + + + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. + + + + + + + + + + + + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. + + + + + + + + + + + + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. + + + + + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -198,10 +222,10 @@ - + - + diff --git a/app/bluetooth/bluetooth_production_demos.xml b/app/bluetooth/bluetooth_production_demos.xml index 5313b64fa7..7475cbabab 100644 --- a/app/bluetooth/bluetooth_production_demos.xml +++ b/app/bluetooth/bluetooth_production_demos.xml @@ -6,11 +6,11 @@ - + - + Network Co-Processor (NCP) target application for Channel Sounding (CS). Runs the Bluetooth stack and provides access to it by exposing the Bluetooth API (BGAPI) via UART connection. In addition to the standard NCP features, it listens to Channel Sounding specific user messages, and executes them. This application also features a CS Initiator with Real Time Locating (RTL) library and a CS Reflector device role that can be instantiated or deleted with the CS specific user messages. @@ -18,11 +18,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -30,11 +30,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -42,11 +42,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -54,11 +54,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -66,11 +66,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -78,11 +78,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -90,11 +90,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -102,11 +102,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -114,11 +114,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -126,11 +126,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -138,11 +138,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -150,11 +150,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -162,11 +162,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -174,11 +174,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -186,11 +186,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -198,11 +198,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -210,11 +210,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -222,11 +222,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -234,11 +234,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -246,11 +246,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -258,11 +258,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -270,11 +270,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -282,11 +282,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -294,11 +294,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -306,11 +306,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -318,11 +318,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -330,11 +330,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -342,11 +342,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -354,11 +354,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -366,47 +366,35 @@ - + - + - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. - - - - - - - - - - - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. - - - + + + - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. - - - + + + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -414,11 +402,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -426,11 +414,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -438,11 +426,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -450,11 +438,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -462,11 +450,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -474,11 +462,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -486,11 +474,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -498,11 +486,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -510,11 +498,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -522,11 +510,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -534,11 +522,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -546,11 +534,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -558,11 +546,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -570,11 +558,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -582,11 +570,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -594,11 +582,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -606,11 +594,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -618,11 +606,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -630,11 +618,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -642,11 +630,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -654,11 +642,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -666,11 +654,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -678,11 +666,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -690,11 +678,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -702,11 +690,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -714,11 +702,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -726,11 +714,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -738,11 +726,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -750,11 +738,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -762,11 +750,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -774,11 +762,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -786,11 +774,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -798,11 +786,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -810,11 +798,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -822,11 +810,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -834,11 +822,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -846,11 +834,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -858,11 +846,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -870,11 +858,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -882,11 +870,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -894,11 +882,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -906,11 +894,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the Simplicity Connect mobile app. @@ -918,11 +906,11 @@ - + - + Channel Sounding (CS) Initiator for Bluetooth LE. This example connects to a CS Reflector device and starts the distance measurement. Results are printed on the display of the main board if available and can be read via the serial port VCOM. It can measure in two CS measurement modes PBR (default) and RTT. RTT mode can be selected by setting the `CS_INITIATOR_DEFAULT_CS_MODE` macro to `sl_bt_cs_mode_rtt`. It can measure in two object tracking modes as well: in moving object tracking mode (default) or in stationary object tracking mode. In moving object tracking mode measurement results will be calculated for every procedure. In stationary object tracking mode multiple CS procedure data is required for the estimation process. The progress of the estimation will be shown on the LCD and in the logs in percentages. Once the estimation process is done the measurement results will be shown similarly like in the moving object tracking mode. The push button BTN1 will change the object tracking mode to the opposite of the default values. Default values can be found and modified in the component configuration file (config/cs_initiator_config.h). The actual mode can be checked on the serial output and in the captured logs. @@ -930,11 +918,11 @@ - + - + Channel Sounding (CS) Initiator for Bluetooth LE. This example connects to a CS Reflector device and starts the distance measurement. Results are printed on the display of the main board if available and can be read via the serial port VCOM. It can measure in two CS measurement modes PBR (default) and RTT. RTT mode can be selected by setting the `CS_INITIATOR_DEFAULT_CS_MODE` macro to `sl_bt_cs_mode_rtt`. It can measure in two object tracking modes as well: in moving object tracking mode (default) or in stationary object tracking mode. In moving object tracking mode measurement results will be calculated for every procedure. In stationary object tracking mode multiple CS procedure data is required for the estimation process. The progress of the estimation will be shown on the LCD and in the logs in percentages. Once the estimation process is done the measurement results will be shown similarly like in the moving object tracking mode. The push button BTN1 will change the object tracking mode to the opposite of the default values. Default values can be found and modified in the component configuration file (config/cs_initiator_config.h). The actual mode can be checked on the serial output and in the captured logs. @@ -942,11 +930,11 @@ - + - + Channel Sounding (CS) Reflector for Bluetooth LE. This example sends measurement results back to the CS Initiator device via GATT notifications using a custom CS Ranging Service. The CS Reflector has to connect to at least one CS Initiator device to start the measurement. It can connect to a maximum of four CS Initiators at a time. The application starts advertising after boot and keeps advertising until every connection slots are occupied. If a connection slot becomes free, the device will start advertising again. @@ -954,11 +942,11 @@ - + - + Channel Sounding (CS) Reflector for Bluetooth LE. This example sends measurement results back to the CS Initiator device via GATT notifications using a custom CS Ranging Service. The CS Reflector has to connect to at least one CS Initiator device to start the measurement. It can connect to a maximum of four CS Initiators at a time. The application starts advertising after boot and keeps advertising until every connection slots are occupied. If a connection slot becomes free, the device will start advertising again. @@ -966,11 +954,11 @@ - + - + Demonstrates the features of the EFR32xG24 Dev Kit Board. This can be tested with the Simplicity Connect mobile app. @@ -978,11 +966,11 @@ - + - + Demonstrates the features of the EFR32xG26 Dev Kit Board. This can be tested with the Simplicity Connect mobile app. @@ -990,11 +978,11 @@ - + - + Demonstrates the features of the EFR32xG27 DevKit board. Features can be evaluated with the Simplicity Connect mobile app. @@ -1002,11 +990,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1014,11 +1002,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1026,11 +1014,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1038,11 +1026,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1050,11 +1038,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1062,11 +1050,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1074,11 +1062,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1086,11 +1074,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1098,11 +1086,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1110,11 +1098,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1122,11 +1110,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1134,11 +1122,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1146,11 +1134,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1158,11 +1146,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1170,11 +1158,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1182,11 +1170,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1194,11 +1182,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1206,11 +1194,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1218,11 +1206,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1230,11 +1218,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1242,11 +1230,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1254,11 +1242,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1266,11 +1254,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1278,11 +1266,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1290,11 +1278,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1302,11 +1290,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1314,11 +1302,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1326,11 +1314,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1338,11 +1326,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1350,11 +1338,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1362,11 +1350,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1374,11 +1362,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1386,11 +1374,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1398,11 +1386,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1410,11 +1398,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1422,11 +1410,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1434,11 +1422,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1446,11 +1434,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1458,11 +1446,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1470,11 +1458,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1482,11 +1470,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1494,11 +1482,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1506,11 +1494,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1518,11 +1506,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1530,11 +1518,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1542,11 +1530,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1554,11 +1542,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1566,11 +1554,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1578,11 +1566,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using Simplicity Connect mobile app, through the Throughput demo tile. @@ -1590,11 +1578,11 @@ - + - + Demonstrates the features of the Thunderboard EFR32BG22 Kit. This can be tested with the Simplicity Connect mobile app. @@ -1602,11 +1590,11 @@ - + - + Demonstrates the features of the Thunderboard EFR32BG22 Kit. This can be tested with the Simplicity Connect mobile app. @@ -1614,11 +1602,11 @@ - + - + Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. @@ -1626,11 +1614,11 @@ - + - + Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. @@ -1638,11 +1626,11 @@ - + - + Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. @@ -1650,11 +1638,11 @@ - + - + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. @@ -1662,7 +1650,7 @@ - + @@ -1673,7 +1661,7 @@ - + @@ -1684,7 +1672,7 @@ - + @@ -1695,7 +1683,7 @@ - + @@ -1706,7 +1694,7 @@ - + @@ -1717,7 +1705,7 @@ - + @@ -1728,7 +1716,7 @@ - + @@ -1739,7 +1727,7 @@ - + @@ -1750,7 +1738,7 @@ - + @@ -1761,7 +1749,7 @@ - + @@ -1772,40 +1760,29 @@ - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - - - + - + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - + + + - + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the Simplicity Connect mobile app. - - - + + + @@ -1816,7 +1793,7 @@ - + @@ -1827,7 +1804,7 @@ - + @@ -1838,7 +1815,7 @@ - + @@ -1849,7 +1826,7 @@ - + @@ -1860,7 +1837,7 @@ - + @@ -1871,7 +1848,7 @@ - + @@ -1882,7 +1859,7 @@ - + @@ -1893,7 +1870,7 @@ - + @@ -1904,7 +1881,7 @@ - + @@ -1915,7 +1892,7 @@ - + @@ -1926,7 +1903,7 @@ - + @@ -1937,7 +1914,7 @@ - + @@ -1948,7 +1925,7 @@ - + @@ -1959,7 +1936,7 @@ - + @@ -1970,7 +1947,7 @@ - + @@ -1981,7 +1958,7 @@ - + @@ -1992,7 +1969,7 @@ - + @@ -2003,7 +1980,7 @@ - + @@ -2014,7 +1991,7 @@ - + @@ -2025,7 +2002,7 @@ - + @@ -2036,7 +2013,7 @@ - + @@ -2047,11 +2024,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Arrival (AoA) calculation. Use this application with Direction Finding host examples. @@ -2059,11 +2036,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2071,11 +2048,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2083,11 +2060,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2095,11 +2072,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2107,11 +2084,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2119,11 +2096,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2131,11 +2108,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2143,11 +2120,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2155,11 +2132,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2167,11 +2144,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2179,11 +2156,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as a locator beacon in a Direction Finding setup estimating Angle of Departure (AoD). @@ -2191,11 +2168,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as a locator beacon in a Direction Finding setup estimating Angle of Departure (AoD). @@ -2203,11 +2180,11 @@ - + - + This is a Dynamic Multiprotocol reference application demonstrating a light bulb that can be switched both via Bluetooth and via a Proprietary protocol. Can be tested with the Simplicity Connect mobile app and RAIL - SoC Switch sample app. @@ -2215,7 +2192,7 @@ - + @@ -2226,7 +2203,7 @@ - + @@ -2237,7 +2214,29 @@ - + + + + + + + This is a Dynamic Multiprotocol reference application demonstrating a light bulb that can be switched both via Bluetooth and via a Proprietary protocol. Can be tested with the Simplicity Connect mobile app and RAIL - SoC Switch sample app. + + + + + + + + + + + This is a Dynamic Multiprotocol reference application demonstrating a light bulb that can be switched both via Bluetooth and via a Proprietary protocol. Can be tested with the Simplicity Connect mobile app and RAIL - SoC Switch sample app. + + + + + @@ -2248,7 +2247,7 @@ - + @@ -2259,7 +2258,7 @@ - + @@ -2270,7 +2269,7 @@ - + @@ -2281,7 +2280,7 @@ - + @@ -2292,7 +2291,7 @@ - + @@ -2303,7 +2302,7 @@ - + @@ -2314,7 +2313,7 @@ - + @@ -2325,7 +2324,7 @@ - + @@ -2336,7 +2335,7 @@ - + @@ -2347,7 +2346,7 @@ - + @@ -2358,7 +2357,7 @@ - + @@ -2369,7 +2368,7 @@ - + @@ -2380,7 +2379,7 @@ - + @@ -2391,7 +2390,7 @@ - + diff --git a/app/bluetooth/bluetooth_production_templates.xml b/app/bluetooth/bluetooth_production_templates.xml index 3308c48478..76873f085d 100644 --- a/app/bluetooth/bluetooth_production_templates.xml +++ b/app/bluetooth/bluetooth_production_templates.xml @@ -21,7 +21,7 @@ - + @@ -36,7 +36,7 @@ - + @@ -111,7 +111,7 @@ - + @@ -126,7 +126,7 @@ - + @@ -141,7 +141,7 @@ - + @@ -156,7 +156,7 @@ - + @@ -171,7 +171,7 @@ - + @@ -186,8 +186,8 @@ - - + + @@ -201,7 +201,7 @@ - + @@ -216,8 +216,8 @@ - - + + @@ -231,7 +231,7 @@ - + @@ -246,7 +246,7 @@ - + @@ -261,7 +261,7 @@ - + @@ -321,7 +321,7 @@ - + @@ -351,7 +351,7 @@ - + @@ -366,7 +366,7 @@ - + @@ -381,7 +381,7 @@ - + @@ -396,7 +396,7 @@ - + @@ -411,7 +411,7 @@ - + @@ -426,7 +426,7 @@ - + @@ -441,8 +441,8 @@ - - + + @@ -456,8 +456,8 @@ - - + + @@ -471,7 +471,7 @@ - + @@ -486,7 +486,7 @@ - + @@ -501,7 +501,7 @@ - + @@ -516,7 +516,7 @@ - + @@ -531,7 +531,7 @@ - + @@ -546,7 +546,7 @@ - + @@ -561,7 +561,7 @@ - + diff --git a/app/bluetooth/common/ead_core/sl_bt_ead_core.c b/app/bluetooth/common/ead_core/sl_bt_ead_core.c index 0ea14beeed..4a50c1aa11 100644 --- a/app/bluetooth/common/ead_core/sl_bt_ead_core.c +++ b/app/bluetooth/common/ead_core/sl_bt_ead_core.c @@ -29,12 +29,12 @@ ******************************************************************************/ #include #include -#include #include "sl_common.h" #include "sl_memory_manager.h" #include "psa/crypto.h" #include "sl_bt_ead_core.h" #include "psa/crypto_values.h" +#include "mbedtls/platform_util.h" #include "sli_protocol_crypto.h" #include "sl_bt_ead_core_config.h" @@ -53,9 +53,14 @@ static const uint8_t aad[] = { SL_BT_ENCRYPTED_DATA_B1_HEADER }; sl_status_t sl_bt_ead_randomizer_update(sl_bt_ead_nonce_p nonce) { sl_status_t result = SL_STATUS_FAIL; + // Keep calling the psa_crypto_init() as it allows doing so, explicitly + // (see the comment in it's implementation) This is safer than accidentally + // not doing it at all. psa_status_t status = psa_crypto_init(); - assert(nonce != NULL); + if (nonce == NULL) { + return SL_STATUS_NULL_POINTER; + } if (status == PSA_SUCCESS) { status = psa_generate_random((uint8_t *)(nonce->randomizer), @@ -76,7 +81,9 @@ sl_status_t sl_bt_ead_randomizer_set(sl_bt_ead_randomizer_t randomizer, { sl_status_t result = SL_STATUS_NOT_SUPPORTED; - assert(nonce != NULL); + if (nonce == NULL) { + return SL_STATUS_NULL_POINTER; + } if (randomizer != NULL) { memcpy((void *)(nonce->randomizer), @@ -152,7 +159,7 @@ sl_status_t sl_bt_ead_store_key(psa_key_usage_t key_usage, key_id); if (status == PSA_SUCCESS) { - memset(key_material->key, 0, sizeof(key_material->key)); + mbedtls_platform_zeroize(key_material->key, sizeof(key_material->key)); key_material->key_id = *key_id; result = SL_STATUS_OK; } @@ -166,7 +173,7 @@ sl_status_t sl_bt_ead_store_key(psa_key_usage_t key_usage, } // Sanitize the copy before leaving as it is not needed anymore - memset(tmp, 0, sizeof(tmp)); + mbedtls_platform_zeroize(tmp, sizeof(tmp)); } return result; @@ -194,7 +201,8 @@ sl_status_t sl_bt_ead_delete_key(sl_bt_ead_key_material_p key_material) #endif // (SL_BT_EAD_CORE_ACCELERATOR == SL_BT_EAD_CORE_USE_RADIOAES) if (result == SL_STATUS_OK) { - memset(key_material, 0, sizeof(struct sl_bt_ead_key_material_s)); + mbedtls_platform_zeroize(key_material, + sizeof(struct sl_bt_ead_key_material_s)); } return result; } @@ -240,11 +248,15 @@ sl_status_t sl_bt_ead_encrypt(sl_bt_ead_key_material_p key_material, const size_t output_size = length + SL_BT_EAD_MIC_SIZE; #endif // (SL_BT_EAD_CORE_ACCELERATOR == SL_BT_EAD_CORE_USE_PSA_ACC) - assert(key_material != NULL); - assert(nonce != NULL); - assert(length >= 1); - assert(data != NULL); - assert(mic != NULL); + if (key_material == NULL + || nonce == NULL + || data == NULL + || mic == NULL) { + return SL_STATUS_NULL_POINTER; + } + if (length < 1) { + return SL_STATUS_INVALID_COUNT; + } #if (SL_BT_EAD_CORE_ACCELERATOR == SL_BT_EAD_CORE_USE_RADIOAES) // Use the RADIOAES accelerator instead of PSA Crypto library @@ -280,7 +292,8 @@ sl_status_t sl_bt_ead_encrypt(sl_bt_ead_key_material_p key_material, // Purge the key copies, if any psa_purge_key(key_material->key_id); - + // Purge local buffer + mbedtls_platform_zeroize(output_data, sizeof(output_data)); sl_free(output_data); output_data = NULL; } @@ -305,10 +318,16 @@ sl_status_t sl_bt_ead_decrypt(sl_bt_ead_key_material_p key_material, size_t output_length; const size_t output_size = length + SL_BT_EAD_MIC_SIZE; #endif // (SL_BT_EAD_CORE_ACCELERATOR == SL_BT_EAD_CORE_USE_PSA_ACC) - assert(key_material != NULL); - assert(length >= 1); - assert(data != NULL); - assert(mic != NULL); + + if (key_material == NULL + || nonce == NULL + || mic == NULL + || data == NULL) { + return SL_STATUS_NULL_POINTER; + } + if (length < 1) { + return SL_STATUS_INVALID_COUNT; + } #if (SL_BT_EAD_CORE_ACCELERATOR == SL_BT_EAD_CORE_USE_RADIOAES) // Use the RADIOAES accelerator instead of PSA Crypto library @@ -367,10 +386,14 @@ sl_status_t sl_bt_ead_unpack_decrypt(sl_bt_ead_key_material_p key_material, sl_status_t result = SL_STATUS_INVALID_TYPE; uint32_t data_length; - assert(key_material != NULL); - assert(length != NULL); - assert(data != NULL); - assert(*data != NULL); + if (key_material == NULL + || data == NULL + || length == NULL) { + return SL_STATUS_NULL_POINTER; + } + if (*data == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } data_length = (uint32_t)(*data)[0]; // Check if the encrypted data has the minimum expected size @@ -406,7 +429,7 @@ sl_status_t sl_bt_ead_unpack_decrypt(sl_bt_ead_key_material_p key_material, } } // Sanitize nonce copy - memset(&nonce, 0, sizeof(nonce)); + mbedtls_platform_zeroize(&nonce, sizeof(nonce)); } return result; @@ -424,14 +447,18 @@ sl_status_t sl_bt_ead_pack_ad_data(sl_bt_ead_ad_structure_p ad_info, uint32_t data_index; // Check for invalid parameters - assert(ad_info != NULL); - assert(size != NULL); - assert(pack_buf != NULL); + if (ad_info == NULL + || size == NULL + || pack_buf == NULL) { + return SL_STATUS_NULL_POINTER; + } // Check for uninitialized ad_info structure - assert(ad_info->randomizer != NULL); - assert(ad_info->ad_data != NULL); - assert(ad_info->mic != NULL); + if (ad_info->randomizer == NULL + || ad_info->ad_data == NULL + || ad_info->mic == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } // Check for valid encrypted length if (ad_info->length < 1) { @@ -475,11 +502,18 @@ sl_status_t sl_bt_ead_unpack_ad_data(uint8_t *packed_data, sl_status_t result = SL_STATUS_INVALID_TYPE; uint32_t data_length; - assert(packed_data != NULL); - assert(ad_info != NULL); - assert(ad_info->randomizer != NULL); - assert(ad_info->ad_data != NULL); - assert(ad_info->mic != NULL); + // Check for invalid parameters + if (ad_info == NULL + || packed_data == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Check for uninitialized ad_info structure + if (ad_info->randomizer == NULL + || ad_info->ad_data == NULL + || ad_info->mic == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } data_length = (uint32_t)packed_data[0]; ad_info->ad_type = packed_data[1]; diff --git a/app/bluetooth/common/esl_tag_core/src/esl_tag_battery_iadc.c b/app/bluetooth/common/esl_tag_core/src/esl_tag_battery_iadc.c index 957aca69cb..5bd17373ee 100644 --- a/app/bluetooth/common/esl_tag_core/src/esl_tag_battery_iadc.c +++ b/app/bluetooth/common/esl_tag_core/src/esl_tag_battery_iadc.c @@ -27,6 +27,7 @@ * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ +#include "em_iadc.h" #include "sl_common.h" #include "sl_core.h" #include "sl_status.h" diff --git a/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c b/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c index af5ff381f9..9ff3a9fa73 100644 --- a/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c +++ b/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c @@ -727,6 +727,10 @@ sl_status_t esl_core_process_opcode(esl_id_t self_id, bool has_notifications = esl_core_has_notifications(); bool needs_response = (has_notifications || (id == self_id)); + // validate data pointers before use, they must never be NULL + if (data == NULL || *data == NULL) { + return SL_STATUS_NULL_POINTER; + } // process only TLVs addressed to this ESL Tag or broadcasted (only over PAwR!) if (id == self_id || (id == ESL_BROADCAST_ID && !has_notifications)) { #ifdef ESL_TAG_VENDOR_OPCODES_ENABLED diff --git a/app/bluetooth/common/esl_tag_core/src/esl_tag_response.c b/app/bluetooth/common/esl_tag_core/src/esl_tag_response.c index e0225776af..f100f5d37a 100644 --- a/app/bluetooth/common/esl_tag_core/src/esl_tag_response.c +++ b/app/bluetooth/common/esl_tag_core/src/esl_tag_response.c @@ -63,7 +63,10 @@ sl_status_t esl_core_build_response(tlv_t tlv, const void *input_data) uint8_t length = esl_core_get_tlv_len(tlv); const uint8_t *data = (uint8_t *)input_data; - if (esl_response_queue.size - esl_response_queue.count > length) { + if (data == NULL) { + // input data pointer shall never be NULL + return SL_STATUS_NULL_POINTER; + } else if (esl_response_queue.size - esl_response_queue.count > length) { queueAdd(&esl_response_queue, (void *)(uint32_t)tlv); while (length--) { diff --git a/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c b/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c index c645a1cb51..459df0ca86 100644 --- a/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c +++ b/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c @@ -81,63 +81,63 @@ SL_WEAK int sl_bgapi_user_cmd_increase_security(uint8_t *public_key, static sl_status_t ec_ephemeral_key(ec_keypair_t *key) { // NOTE: OpenSSL random number generator is not thread safe - uint8_t priv_buf[ECDH_PRIVATE_KEY_SIZE] = { 0 }; - uint8_t pub_buf[1 + PUBLIC_KEYPAIR_SIZE] = { 0 }; EC_KEY *ec_key = NULL; EC_GROUP *group = NULL; - const BIGNUM *priv_bn = NULL; - const EC_POINT *pub_point = NULL; - sl_status_t e; - size_t s; + sl_status_t e = SL_STATUS_ALLOCATION_FAILED; - group = EC_GROUP_new_by_curve_name(NID_X9_62_prime256v1); - if (!group) { - e = SL_STATUS_FAIL; - goto out; - } + do { + const BIGNUM *priv_bn = NULL; + const EC_POINT *pub_point = NULL; + size_t s; + uint8_t priv_buf[ECDH_PRIVATE_KEY_SIZE] = { 0 }; + uint8_t pub_buf[1 + PUBLIC_KEYPAIR_SIZE] = { 0 }; - ec_key = EC_KEY_new(); - if (!ec_key) { - e = SL_STATUS_NO_MORE_RESOURCE; - goto out; - } - - if (EC_KEY_set_group(ec_key, group) < 1 - || EC_KEY_generate_key(ec_key) < 1) { - e = SL_STATUS_FAIL; - goto out; - } + group = EC_GROUP_new_by_curve_name(NID_X9_62_prime256v1); + if (!group) { + break; + } - priv_bn = EC_KEY_get0_private_key(ec_key); - if (!priv_bn || BN_num_bytes(priv_bn) != ECDH_PRIVATE_KEY_SIZE) { - e = SL_STATUS_FAIL; - goto out; - } - BN_bn2bin(priv_bn, priv_buf); + ec_key = EC_KEY_new(); + if (!ec_key) { + break; + } - pub_point = EC_KEY_get0_public_key(ec_key); - if (!pub_point) { - e = SL_STATUS_FAIL; - goto out; - } + if (EC_KEY_set_group(ec_key, group) < 1 + || EC_KEY_generate_key(ec_key) < 1) { + e = SL_STATUS_INITIALIZATION; + break; + } - s = EC_POINT_point2oct(group, pub_point, POINT_CONVERSION_UNCOMPRESSED, - NULL, 0, NULL); - if (s != sizeof(pub_buf)) { - e = SL_STATUS_FAIL; - goto out; - } + priv_bn = EC_KEY_get0_private_key(ec_key); + if (!priv_bn || BN_num_bytes(priv_bn) != ECDH_PRIVATE_KEY_SIZE) { + e = SL_STATUS_INVALID_KEY; + break; + } + BN_bn2bin(priv_bn, priv_buf); - EC_POINT_point2oct(group, pub_point, POINT_CONVERSION_UNCOMPRESSED, - pub_buf, sizeof(pub_buf), NULL); + pub_point = EC_KEY_get0_public_key(ec_key); + if (!pub_point) { + e = SL_STATUS_INVALID_KEY; + break; + } - memcpy(key->priv, priv_buf, ECDH_PRIVATE_KEY_SIZE); - memcpy(key->pub, pub_buf + 1, PUBLIC_KEYPAIR_SIZE); - e = SL_STATUS_OK; + e = SL_STATUS_FAIL; + s = EC_POINT_point2oct(group, pub_point, POINT_CONVERSION_UNCOMPRESSED, + NULL, 0, NULL); + if (s == sizeof(pub_buf)) { + s = EC_POINT_point2oct(group, pub_point, POINT_CONVERSION_UNCOMPRESSED, + pub_buf, sizeof(pub_buf), NULL); + + if (s != 0) { + memcpy(key->priv, priv_buf, ECDH_PRIVATE_KEY_SIZE); + memcpy(key->pub, pub_buf + 1, PUBLIC_KEYPAIR_SIZE); + e = SL_STATUS_OK; + } + } + } while (0); - out: - EC_KEY_free(ec_key); - EC_GROUP_free(group); + (void)EC_KEY_free(ec_key); + (void)EC_GROUP_free(group); return e; } @@ -154,59 +154,59 @@ static EVP_PKEY *ec_key(const ec_keypair_t *key, tmp[0] = POINT_CONVERSION_UNCOMPRESSED; memcpy(tmp + 1, key->pub, PUBLIC_KEYPAIR_SIZE); + do { + group = EC_GROUP_new_by_curve_name(NID_X9_62_prime256v1); + if (!group) { + break; + } - group = EC_GROUP_new_by_curve_name(NID_X9_62_prime256v1); - if (!group) { - goto out; - } + ec_key = EC_KEY_new(); + if (!ec_key) { + break; + } + if (EC_KEY_set_group(ec_key, group) < 1) { + break; + } - ec_key = EC_KEY_new(); - if (!ec_key) { - goto out; - } - if (EC_KEY_set_group(ec_key, group) < 1) { - goto out; - } + if (both_parts) { + priv_bn = BN_bin2bn(key->priv, ECDH_PRIVATE_KEY_SIZE, NULL); + if (!priv_bn) { + break; + } + if (EC_KEY_set_private_key(ec_key, priv_bn) != 1) { + break; + } + } - if (both_parts) { - priv_bn = BN_bin2bn(key->priv, ECDH_PRIVATE_KEY_SIZE, NULL); - if (!priv_bn) { - goto out; + pub_point = EC_POINT_new(group); + if (!pub_point) { + break; } - if (EC_KEY_set_private_key(ec_key, priv_bn) != 1) { - goto out; + if (EC_POINT_oct2point(group, pub_point, tmp, sizeof(tmp), NULL) < 1) { + break; + } + if (EC_KEY_set_public_key(ec_key, pub_point) != 1) { + break; } - } - - pub_point = EC_POINT_new(group); - if (!pub_point) { - goto out; - } - if (EC_POINT_oct2point(group, pub_point, tmp, sizeof(tmp), NULL) < 1) { - goto out; - } - if (EC_KEY_set_public_key(ec_key, pub_point) != 1) { - goto out; - } - evp_key = EVP_PKEY_new(); - if (!evp_key) { - goto out; - } + evp_key = EVP_PKEY_new(); + if (!evp_key) { + break; + } - if (EVP_PKEY_set1_EC_KEY(evp_key, ec_key) != 1) { - goto out; - } + if (EVP_PKEY_set1_EC_KEY(evp_key, ec_key) != 1) { + break; + } - result = evp_key; - evp_key = NULL; + result = evp_key; + evp_key = NULL; + } while (0); - out: - EVP_PKEY_free(evp_key); - EC_KEY_free(ec_key); - BN_free(priv_bn); - EC_POINT_free(pub_point); - EC_GROUP_free(group); + (void)EVP_PKEY_free(evp_key); + (void)EC_KEY_free(ec_key); + (void)BN_free(priv_bn); + (void)EC_POINT_free(pub_point); + (void)EC_GROUP_free(group); return result; } @@ -215,74 +215,63 @@ static sl_status_t ecdh_secret(const ec_keypair_t *remote_ec_key) { EVP_PKEY_CTX *ctxt = NULL; unsigned char *secret_ptr = NULL; - size_t secret_len; EVP_PKEY *local_pkey = NULL; EVP_PKEY *remote_pkey = NULL; - sl_status_t e; - - // Set up keys - local_pkey = ec_key(&local_ec_key, 1); - if (!local_pkey) { - e = SL_STATUS_FAIL; - goto out; - } - - remote_pkey = ec_key(remote_ec_key, 0); - if (!remote_pkey) { - e = SL_STATUS_FAIL; - goto out; - } - - ctxt = EVP_PKEY_CTX_new(local_pkey, NULL); - if (!ctxt) { - e = SL_STATUS_FAIL; - goto out; - } + sl_status_t e = SL_STATUS_ALLOCATION_FAILED; + + do { + size_t secret_len; + uint8_t *hash = NULL; + // Set up keys + local_pkey = ec_key(&local_ec_key, 1); + if (!local_pkey) { + break; + } - if (EVP_PKEY_derive_init(ctxt) < 1 - || EVP_PKEY_derive_set_peer(ctxt, remote_pkey) < 1 - || EVP_PKEY_derive(ctxt, NULL, &secret_len) < 1 - || secret_len != 32) { - e = SL_STATUS_FAIL; - goto out; - } + remote_pkey = ec_key(remote_ec_key, 0); + if (!remote_pkey) { + break; + } - secret_ptr = OPENSSL_malloc(secret_len); - if (!secret_ptr) { - e = SL_STATUS_NO_MORE_RESOURCE; - goto out; - } + ctxt = EVP_PKEY_CTX_new(local_pkey, NULL); + if (!ctxt) { + break; + } - if (EVP_PKEY_derive(ctxt, secret_ptr, &secret_len) < 1) { - e = SL_STATUS_FAIL; - goto out; - } + if (EVP_PKEY_derive_init(ctxt) < 1 + || EVP_PKEY_derive_set_peer(ctxt, remote_pkey) < 1 + || EVP_PKEY_derive(ctxt, NULL, &secret_len) < 1 + || secret_len != 32) { + e = SL_STATUS_INITIALIZATION; + break; + } - // Use sha256 to derive the AES CCM key. - // NOTE: This is not thread safe - uint8_t *hash = SHA256(secret_ptr, secret_len, NULL); - if (!hash) { - e = SL_STATUS_FAIL; - goto out; - } + secret_ptr = OPENSSL_malloc(secret_len); + if (!secret_ptr) { + e = SL_STATUS_NO_MORE_RESOURCE; + break; + } - memcpy(ccm_key, hash, AES_CCM_KEY_SIZE); - e = SL_STATUS_OK; + if (EVP_PKEY_derive(ctxt, secret_ptr, &secret_len) < 1) { + e = SL_STATUS_INVALID_KEY; + break; + } - out: - if (secret_ptr) { - OPENSSL_free(secret_ptr); - } - if (local_pkey) { - EVP_PKEY_free(local_pkey); - } - if (remote_pkey) { - EVP_PKEY_free(remote_pkey); - } - if (ctxt) { - EVP_PKEY_CTX_free(ctxt); - } + // Use sha256 to derive the AES CCM key. + // NOTE: This is not thread safe + hash = SHA256(secret_ptr, secret_len, NULL); + if (!hash) { + e = SL_STATUS_FAIL; + } else { + memcpy(ccm_key, hash, AES_CCM_KEY_SIZE); + e = SL_STATUS_OK; + } + } while (0); + (void)OPENSSL_free(secret_ptr); + (void)EVP_PKEY_free(local_pkey); + (void)EVP_PKEY_free(remote_pkey); + (void)EVP_PKEY_CTX_free(ctxt); return e; } @@ -294,74 +283,73 @@ static sl_status_t aes_ccm_encrypt(const uint8_t *key, const uint8_t *nonce, uint8_t *cipher_text, uint8_t *mac) { EVP_CIPHER_CTX *ccm = NULL; - int len; - sl_status_t r; + sl_status_t r = SL_STATUS_ALLOCATION_FAILED; ccm = EVP_CIPHER_CTX_new(); + if (!ccm) { - r = SL_STATUS_FAIL; - goto out; + return r; } - if (EVP_EncryptInit_ex(ccm, EVP_aes_128_ccm(), NULL, NULL, NULL) != 1 - || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_IVLEN, - NONCE_SIZE, NULL) != 1 - || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_TAG, - MAC_LEN, NULL) != 1 - || EVP_EncryptInit_ex(ccm, NULL, NULL, key, nonce) != 1) { - r = SL_STATUS_FAIL; - goto out; - } + do { + int len; - // Provide the total plain text length - if (EVP_EncryptUpdate(ccm, - NULL, &len, - NULL, text_len) != 1) { - r = SL_STATUS_FAIL; - goto out; - } + if (EVP_EncryptInit_ex(ccm, EVP_aes_128_ccm(), NULL, NULL, NULL) != 1 + || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_IVLEN, + NONCE_SIZE, NULL) != 1 + || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_TAG, + MAC_LEN, NULL) != 1 + || EVP_EncryptInit_ex(ccm, NULL, NULL, key, nonce) != 1) { + r = SL_STATUS_INITIALIZATION; + break; + } - // Provide any AAD data. This can be called zero or one times as required - if (additional) { + // Provide the total plain text length if (EVP_EncryptUpdate(ccm, NULL, &len, - additional, additional_len) != 1) { - r = SL_STATUS_FAIL; - goto out; + NULL, text_len) != 1) { + r = SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR; + break; } - } - if (len != additional_len) { - r = SL_STATUS_FAIL; - goto out; - } - /* Provide the message to be encrypted, and obtain the encrypted output. - EVP_EncryptUpdate can only be called once for this */ - if (EVP_EncryptUpdate(ccm, - cipher_text, &len, - plain_text, text_len) != 1) { - r = SL_STATUS_FAIL; - goto out; - } - if (len != text_len) { - r = SL_STATUS_FAIL; - goto out; - } + // Provide any AAD data. This can be called zero or one times as required + if (additional) { + if (EVP_EncryptUpdate(ccm, + NULL, &len, + additional, additional_len) != 1) { + r = SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR; + break; + } + } + if (len != additional_len) { + r = SL_STATUS_FAIL; + break; + } - // Get the tag - if (EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_GET_TAG, - MAC_LEN, mac) != 1) { - r = SL_STATUS_FAIL; - goto out; - } + /* Provide the message to be encrypted, and obtain the encrypted output. + EVP_EncryptUpdate can only be called once for this */ + if (EVP_EncryptUpdate(ccm, + cipher_text, &len, + plain_text, text_len) != 1) { + r = SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR; + break; + } + if (len != text_len) { + r = SL_STATUS_FAIL; + break; + } - r = SL_STATUS_OK; + // Get the tag + if (EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_GET_TAG, + MAC_LEN, mac) != 1) { + r = SL_STATUS_INVALID_SIGNATURE; + break; + } - out: - if (ccm) { - EVP_CIPHER_CTX_free(ccm); - } + r = SL_STATUS_OK; + } while (0); + (void)EVP_CIPHER_CTX_free(ccm); return r; } @@ -373,67 +361,65 @@ static sl_status_t aes_ccm_decrypt(const uint8_t *key, const uint8_t *nonce, uint8_t *plain_text, const uint8_t *mac) { EVP_CIPHER_CTX *ccm = NULL; - int len; - sl_status_t r; + sl_status_t r = SL_STATUS_ALLOCATION_FAILED; ccm = EVP_CIPHER_CTX_new(); - if (!ccm) { - r = SL_STATUS_FAIL; - goto out; - } - - if (EVP_DecryptInit_ex(ccm, EVP_aes_128_ccm(), NULL, NULL, NULL) != 1 - || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_IVLEN, - NONCE_SIZE, NULL) != 1 - || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_TAG, - MAC_LEN, (void *)mac) != 1 - || EVP_DecryptInit_ex(ccm, NULL, NULL, key, nonce) != 1) { - r = SL_STATUS_FAIL; - goto out; - } - // Provide the total plain text length - if (EVP_DecryptUpdate(ccm, - NULL, &len, - NULL, text_len) != 1) { - r = SL_STATUS_FAIL; - goto out; - } + if (!ccm) { + return r; + } + + do { + int len; + if (EVP_DecryptInit_ex(ccm, EVP_aes_128_ccm(), NULL, NULL, NULL) != 1 + || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_IVLEN, + NONCE_SIZE, NULL) != 1 + || EVP_CIPHER_CTX_ctrl(ccm, EVP_CTRL_CCM_SET_TAG, + MAC_LEN, (void *)mac) != 1 + || EVP_DecryptInit_ex(ccm, NULL, NULL, key, nonce) != 1) { + r = SL_STATUS_INITIALIZATION; + break; + } - // Provide any AAD data. This can be called zero or one times as required - if (additional) { + // Provide the total plain text length if (EVP_DecryptUpdate(ccm, NULL, &len, - additional, additional_len) != 1) { - r = SL_STATUS_FAIL; - goto out; + NULL, text_len) != 1) { + r = SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR; + break; } - } - if (len != additional_len) { - r = SL_STATUS_FAIL; - goto out; - } - /* Provide the message to be decrypted, and obtain the decrypted output. - EVP_DecryptUpdate can be called multiple times if necessary */ - if (EVP_DecryptUpdate(ccm, - plain_text, &len, - cipher_text, text_len) != 1) { - r = SL_STATUS_BT_CTRL_AUTHENTICATION_FAILURE; - goto out; - } - if (len != text_len) { - r = SL_STATUS_FAIL; - goto out; - } + // Provide any AAD data. This can be called zero or one times as required + if (additional) { + if (EVP_DecryptUpdate(ccm, + NULL, &len, + additional, additional_len) != 1) { + r = SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR; + break; + } + } + if (len != additional_len) { + r = SL_STATUS_FAIL; + break; + } - r = SL_STATUS_OK; + /* Provide the message to be decrypted, and obtain the decrypted output. + EVP_DecryptUpdate can be called multiple times if necessary */ + if (EVP_DecryptUpdate(ccm, + plain_text, &len, + cipher_text, text_len) != 1) { + r = SL_STATUS_SECURITY_DECRYPT_ERROR; + break; + } + if (len != text_len) { + r = SL_STATUS_FAIL; + break; + } - out: - if (ccm) { - EVP_CIPHER_CTX_free(ccm); - } + r = SL_STATUS_OK; + } while (0); + (void)EVP_CIPHER_CTX_free(ccm); return r; } diff --git a/app/bluetooth/component/cs_acp.slcc b/app/bluetooth/component/cs_acp.slcc index 1e473e5cbf..a1961ea40d 100644 --- a/app/bluetooth/component/cs_acp.slcc +++ b/app/bluetooth/component/cs_acp.slcc @@ -7,7 +7,7 @@ category: Bluetooth|Application|Miscellaneous metadata: sbom: license: Zlib -quality: evaluation +quality: production root_path: app/bluetooth/common/cs_acp include: diff --git a/app/bluetooth/component/cs_antenna.slcc b/app/bluetooth/component/cs_antenna.slcc index 4a20673715..648586ffaf 100644 --- a/app/bluetooth/component/cs_antenna.slcc +++ b/app/bluetooth/component/cs_antenna.slcc @@ -7,7 +7,7 @@ category: Bluetooth|Application|Miscellaneous metadata: sbom: license: Zlib -quality: evaluation +quality: production root_path: app/bluetooth/common/cs_antenna include: - path: . diff --git a/app/bluetooth/component/cs_initiator.slcc b/app/bluetooth/component/cs_initiator.slcc index 3d6d5c852d..3f87e0418a 100644 --- a/app/bluetooth/component/cs_initiator.slcc +++ b/app/bluetooth/component/cs_initiator.slcc @@ -10,7 +10,7 @@ category: Bluetooth|Application|Miscellaneous metadata: sbom: license: Zlib -quality: evaluation +quality: production root_path: app/bluetooth/common/cs_initiator include: diff --git a/app/bluetooth/component/cs_reflector.slcc b/app/bluetooth/component/cs_reflector.slcc index 64d72890a1..01ad46d32f 100644 --- a/app/bluetooth/component/cs_reflector.slcc +++ b/app/bluetooth/component/cs_reflector.slcc @@ -7,7 +7,7 @@ category: Bluetooth|Application|Miscellaneous metadata: sbom: license: Zlib -quality: evaluation +quality: production root_path: app/bluetooth/common/cs_reflector include: - path: . diff --git a/app/bluetooth/documentation/slBluetooth_docContent.xml b/app/bluetooth/documentation/slBluetooth_docContent.xml index 0c40a5e33d..8bbd86a2c8 100644 --- a/app/bluetooth/documentation/slBluetooth_docContent.xml +++ b/app/bluetooth/documentation/slBluetooth_docContent.xml @@ -1,6 +1,6 @@ - - + + Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -8,7 +8,7 @@ - + Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. @@ -16,7 +16,7 @@ - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -24,7 +24,7 @@ - + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. @@ -32,7 +32,7 @@ - + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -40,7 +40,7 @@ - + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. @@ -48,14 +48,14 @@ - + Describes how to measure the power consumption of EFR32BG devices running the Bluetooth i-Beacon example. For general instructions, see AN969: Measuring Power Consumption in Wireless Gecko Devices, available on silabs.com. - + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. @@ -63,7 +63,7 @@ - + Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode @@ -71,14 +71,14 @@ - + Describes how to integrate a v3.x Silicon Labs Bluetooth application with an RTOS, and demonstrate how a time- and event-driven application can be run in parallel with the Bluetooth stack. - + Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. @@ -86,7 +86,7 @@ - + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. @@ -94,14 +94,14 @@ - + Provides details on how to develop a dynamic multiprotocol application running Bluetooth and a proprietary protocol on RAIL in GSDK v3.x. - + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. @@ -109,28 +109,28 @@ - + Describes the sample applications provided to demonstrate the directing finding capabilities of Bluetooth 5.1. Angle of Arrival (AoA) estimation is demonstrated with the use of Silicon Labs' Real Time Locating (RTL) library. These techniques are applicable to the EFR32MGx and EFR32BGx series. - + Bluetooth 5.1 makes it possible to send Constant Tone Extensions (CTEs) in Bluetooth packets on which phase measurements can be done. This guide is for those implementing custom applications that take advantage of phase measurement and antenna switching capabilites. - + Provides details on designing Bluetooth Low Energy applications with security and privacy in mind. - + Describes how to provision and configure Series 2 devices through the DCI and SWD. @@ -138,14 +138,14 @@ - + Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Low Energy stack with Android and iOS smart phones. - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -153,7 +153,7 @@ - + Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. @@ -161,7 +161,7 @@ - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -169,14 +169,14 @@ - + Gives a short overview of the standard Host Controller Interface (HCI) and how to use it with a Silicon Labs Bluetooth LE controller. - + Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 Radio Co-processor (RCP) with multiprotocol and multi-PAN support, as well as how to run the Zigbee stack on the EFR32 as a network co-processor (NCP) alongside the OpenThread RCP. @@ -184,21 +184,21 @@ - + Summarizes Amazon FreeRTOS components and sample applications, and explains how to use the examples to communicate with the Amazon Web Services (AWS) cloud with a smart phone app. - + Describes how to exploit the different features of Bluetooth technology to achieve the minimum possible energy consumption for a given use case. - + Covers the basics of ARMv8-M TrustZone, describes how TrustZone is implemented on Series 2 devices, and provides application examples. @@ -206,70 +206,70 @@ - + Describes the theoretical background of certificate-based authentication and pairing, and demonstrates the usage of the related sample applications that can be found in the Silicon Labs Bluetooth SDK. - + This application note summarizes the results of Zigbee/BLE dynamic multiprotocol (DMP) large network performance tests using Zigbee unicast and broadcast packets to measure the reliability, latency, and loss of a variety of scenarios. - + Provides an overview and hyperlinks to all packaged documentation. - + Describes the differences between using Bluetooth SDK v2.x in Simplicity Studio 4 and using Bluetooth SDK v3.x in Simplicity Studio 5. Outlines the steps needed to migrate a v2.x project to v3.x. - + Describes the software components provided by Silicon Labs to support Direction Finding (DF) and provides instructions on how to start developing your own application. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Real-Time Locating Library. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth stack. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + Discusses the latest changes to the The Real-Time Locating (RTL) library, including added/deleted/deprecated APIs, and lists fixed and known issues. - + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. @@ -277,7 +277,7 @@ - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -285,7 +285,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. @@ -293,7 +293,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: PS Store and NVM3. @@ -301,14 +301,14 @@ - + Offers an overview for those new to the Bluetooth low energy technology. - + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. @@ -316,7 +316,7 @@ - + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. @@ -324,14 +324,14 @@ - + Explains the basics of Bluetooth Angle of Arrival (AoA) and Angle of Departure (AoD) direction finding technologies and provides the theory behind estimating angle of arrival. - + Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. @@ -339,7 +339,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface. @@ -347,7 +347,7 @@ - + Describes how to implement a dynamic multiprotocol solution. @@ -355,14 +355,14 @@ - + Covers the Bluetooth stack v7.x architecture, application development flow, using the MCU core and peripherals, stack configuration options, and stack resource usage. - + Describes how to use the Simplicity Studio 5 GATT Configurator, an intuitive interface providing access to all the Profiles, Services, Characteristics, and Descriptors as defined in the Bluetooth specification. @@ -370,7 +370,7 @@ - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. @@ -378,7 +378,7 @@ - + The Bluetooth Direction Finding Tool Suite is meant to ease development with the Silicon Labs' RTL library. It provides multiple tools to configure the system, and also helps the development with analyzer tools that calculate many output parameters from the observed IQ samples. diff --git a/app/bluetooth/esf.properties b/app/bluetooth/esf.properties index 23de5cbb11..aacb7963a3 100644 --- a/app/bluetooth/esf.properties +++ b/app/bluetooth/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.ble label=Bluetooth SDK description=Bluetooth Software Development Kit -version=9.0.0.0 -prop.subLabel=Bluetooth\\ 9.0.0 +version=9.0.1.0 +prop.subLabel=Bluetooth\\ 9.0.1 # Default compatibility of the BLE SDK prop.boardCompatibility=.* diff --git a/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp b/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp index f1845f8570..d4b7613691 100644 --- a/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp +++ b/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp @@ -46,7 +46,6 @@ requires: - name: bluetooth_feature_legacy_scanner - name: bluetooth_feature_advertiser_past - name: bluetooth_feature_pawr_advertiser - - name: bluetooth_feature_extended_scanner - name: bluetooth_feature_legacy_advertiser - name: bluetooth_feature_extended_advertiser - name: bluetooth_feature_periodic_advertiser diff --git a/app/bluetooth/example/bt_soc_esl_tag/app.c b/app/bluetooth/example/bt_soc_esl_tag/app.c index a8208e366b..65e977a43d 100644 --- a/app/bluetooth/example/bt_soc_esl_tag/app.c +++ b/app/bluetooth/example/bt_soc_esl_tag/app.c @@ -174,6 +174,10 @@ static void sw_pwm_led_on(led_sw_pwm_t *instance, uint8_t duty) { uint32_t duration = (sl_sleeptimer_ms_to_tick(16) / SW_PWM_MAX_DUTY_STEPS); + if (instance == NULL) { + return; // avoid accidental / malicious NULL dereference + } + // set SW PWM time base instance->pace = duration; // set an empirical offset to compensate the perceived brightness @@ -184,7 +188,7 @@ static void sw_pwm_led_on(led_sw_pwm_t *instance, uint8_t duty) // ESL LED specification if (duty < SW_PWM_MAX_DUTY_STEPS) { instance->duty = duty; - duration *= ++duty; + duration *= ++duty; // no need for OF check after max duty limit! } else { instance->duty = SW_PWM_MAX_DUTY_VALUE; } diff --git a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg27_dev_kit_brd2602a.slcp b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg27_dev_kit_brd2602a.slcp index b6a3943803..16eba22663 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg27_dev_kit_brd2602a.slcp +++ b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg27_dev_kit_brd2602a.slcp @@ -51,6 +51,9 @@ component: - id: i2cspm instance: - sensor + - id: iostream_usart + instance: + - vcom - id: simple_led instance: - led0 @@ -113,8 +116,6 @@ configuration: value: "1" - name: SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION value: "0" - - name: SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION - value: "0" - name: SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE value: "EMU_EM4CTRL_EM4IORETMODE_EM4EXIT" - name: SL_BOARD_ENABLE_SENSOR_RHT @@ -138,4 +139,4 @@ ui_hints: highlight: - path: config/btconf/gatt_configuration_dev_kit.btconf - path: readme.md - focus: true + focus: true \ No newline at end of file diff --git a/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py b/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py index 134dde3975..16c989b023 100755 --- a/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py @@ -146,6 +146,7 @@ def generate_qrcode(data, height, width): abort(-3) # Create black and white QR code image img = qr.make_image(fill_color="black", back_color="white") + img = img.convert("RGBA") # BG-18013: fix regression caused by Pillow module update v11, keeps backward compatibiliy with older Pillow versions qr_width, qr_height = img.size log.info(f"Generated QR code size: {qr_width}x{qr_height}") log.info(f"Scaling it to: {width}x{height}") diff --git a/app/btmesh/btmesh.properties b/app/btmesh/btmesh.properties index 25ca6ced28..90df520cf2 100644 --- a/app/btmesh/btmesh.properties +++ b/app/btmesh/btmesh.properties @@ -2,8 +2,8 @@ id=com.silabs.stack.btMesh label=Bluetooth Mesh SDK description=Bluetooth Mesh Software Development Kit -version=8.0.0.0 -prop.subLabel=Bluetooth\\ Mesh\\ 8.0.0 +version=8.0.1.0 +prop.subLabel=Bluetooth\\ Mesh\\ 8.0.1 # Default compatibility of the BT Mesh SDK (This is needed for the documentation only) prop.boardCompatibility=.* diff --git a/app/btmesh/btmesh_internal_demos.xml b/app/btmesh/btmesh_internal_demos.xml index 2f533885f8..00b0a9f855 100644 --- a/app/btmesh/btmesh_internal_demos.xml +++ b/app/btmesh/btmesh_internal_demos.xml @@ -6,11 +6,11 @@ - + - + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -18,11 +18,11 @@ - + - + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -30,11 +30,11 @@ - + - + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -42,11 +42,11 @@ - + - + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -54,11 +54,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -66,11 +66,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -78,11 +78,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -90,11 +90,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -102,11 +102,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -114,11 +114,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -126,11 +126,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -138,11 +138,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -150,11 +150,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -162,11 +162,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -174,11 +174,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -186,11 +186,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -198,11 +198,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -210,11 +210,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -222,11 +222,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -234,11 +234,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -246,10 +246,10 @@ - + - + diff --git a/app/btmesh/btmesh_production_demos.xml b/app/btmesh/btmesh_production_demos.xml index 483e2b3f2c..b05a49468b 100644 --- a/app/btmesh/btmesh_production_demos.xml +++ b/app/btmesh/btmesh_production_demos.xml @@ -6,11 +6,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -18,11 +18,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -30,11 +30,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -42,11 +42,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -54,11 +54,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -66,11 +66,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -78,11 +78,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -90,11 +90,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -102,11 +102,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -114,11 +114,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -126,11 +126,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -138,11 +138,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -150,11 +150,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -162,11 +162,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -174,11 +174,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -186,11 +186,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -198,11 +198,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -210,11 +210,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -222,11 +222,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -234,11 +234,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -246,11 +246,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -258,11 +258,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -270,11 +270,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -282,11 +282,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -294,11 +294,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -306,11 +306,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -318,11 +318,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -330,11 +330,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -342,11 +342,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -354,11 +354,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -366,11 +366,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -378,11 +378,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -390,11 +390,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -402,11 +402,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -414,11 +414,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -426,11 +426,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -438,11 +438,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -450,11 +450,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -462,11 +462,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -474,11 +474,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -486,11 +486,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -498,11 +498,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -510,11 +510,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -522,11 +522,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -534,11 +534,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -546,11 +546,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -558,11 +558,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -570,11 +570,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -582,11 +582,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -594,11 +594,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -606,11 +606,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -618,11 +618,11 @@ - + - + An out-of-the-box software demo where the device acts as a Basic Lightness Controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -631,11 +631,11 @@ This project uses the RGB LED on the xG24 Dev Kit. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -644,7 +644,7 @@ This project uses the LEDs on the mainboard. - + @@ -656,11 +656,11 @@ This project uses the LEDs on the mainboard. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -669,7 +669,7 @@ This project uses the LEDs on the mainboard. - + @@ -681,7 +681,7 @@ This project uses the LEDs on the mainboard. - + @@ -693,7 +693,7 @@ This project uses the LEDs on the mainboard. - + @@ -705,7 +705,7 @@ This project uses the LEDs on the mainboard. - + @@ -717,11 +717,11 @@ This project uses the LEDs on the mainboard. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -730,11 +730,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -743,11 +743,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -756,11 +756,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -769,11 +769,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -782,11 +782,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -795,11 +795,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -808,11 +808,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -821,11 +821,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -834,11 +834,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -847,11 +847,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -860,11 +860,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -873,11 +873,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -886,11 +886,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -899,11 +899,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -911,11 +911,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -923,11 +923,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -935,11 +935,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -947,11 +947,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -959,11 +959,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -971,11 +971,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -983,11 +983,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -995,11 +995,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1007,11 +1007,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1019,11 +1019,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1031,11 +1031,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1043,11 +1043,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1055,11 +1055,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1067,11 +1067,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1079,11 +1079,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1091,11 +1091,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1103,11 +1103,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1115,11 +1115,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1127,11 +1127,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1139,11 +1139,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1151,11 +1151,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1163,11 +1163,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1175,11 +1175,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1187,11 +1187,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1199,11 +1199,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1211,11 +1211,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1223,11 +1223,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1235,11 +1235,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1247,11 +1247,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1259,11 +1259,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1271,11 +1271,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1283,11 +1283,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1295,11 +1295,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1307,11 +1307,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1319,11 +1319,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1331,11 +1331,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1343,11 +1343,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1355,11 +1355,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1367,11 +1367,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1379,11 +1379,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1391,11 +1391,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1403,11 +1403,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1415,11 +1415,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1427,11 +1427,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1439,11 +1439,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1451,11 +1451,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1463,11 +1463,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1475,11 +1475,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1487,11 +1487,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1499,11 +1499,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1511,11 +1511,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1523,11 +1523,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1535,11 +1535,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1547,11 +1547,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1559,11 +1559,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1571,11 +1571,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1583,11 +1583,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1595,11 +1595,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1607,11 +1607,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1619,11 +1619,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1631,11 +1631,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1643,11 +1643,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1655,11 +1655,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1667,11 +1667,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1679,11 +1679,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1691,11 +1691,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1703,11 +1703,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1715,11 +1715,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1727,11 +1727,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1739,11 +1739,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1751,11 +1751,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1763,11 +1763,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1775,11 +1775,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1787,11 +1787,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1799,11 +1799,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1811,11 +1811,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1823,11 +1823,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1835,11 +1835,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1847,11 +1847,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1859,11 +1859,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1871,11 +1871,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1883,11 +1883,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1895,11 +1895,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1907,11 +1907,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1919,11 +1919,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1931,11 +1931,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1943,11 +1943,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1955,11 +1955,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1967,11 +1967,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1979,11 +1979,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1991,11 +1991,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2003,11 +2003,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2015,11 +2015,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2027,11 +2027,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2039,11 +2039,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2051,11 +2051,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2063,11 +2063,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2075,11 +2075,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2087,11 +2087,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2099,11 +2099,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2111,11 +2111,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2123,11 +2123,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2135,11 +2135,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2147,11 +2147,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2159,11 +2159,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2171,11 +2171,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2183,11 +2183,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2195,11 +2195,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2207,11 +2207,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2219,11 +2219,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2231,11 +2231,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2243,11 +2243,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2255,11 +2255,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2267,11 +2267,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2279,11 +2279,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2291,11 +2291,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2303,11 +2303,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2315,11 +2315,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2327,11 +2327,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2339,11 +2339,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2351,11 +2351,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2363,11 +2363,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2375,11 +2375,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2387,11 +2387,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2399,11 +2399,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2411,11 +2411,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2423,11 +2423,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2435,11 +2435,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2447,11 +2447,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2459,11 +2459,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2471,11 +2471,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2483,11 +2483,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2495,11 +2495,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2507,11 +2507,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2519,11 +2519,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2531,11 +2531,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2543,11 +2543,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2555,11 +2555,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2567,11 +2567,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2579,11 +2579,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2591,11 +2591,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2603,11 +2603,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2615,11 +2615,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2627,11 +2627,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2639,11 +2639,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2651,11 +2651,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2663,11 +2663,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2675,11 +2675,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2687,11 +2687,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2699,11 +2699,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2711,11 +2711,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2723,11 +2723,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2735,11 +2735,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2747,11 +2747,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2759,11 +2759,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2771,11 +2771,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2783,11 +2783,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2795,11 +2795,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2807,11 +2807,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2819,11 +2819,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2831,11 +2831,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2843,11 +2843,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2855,11 +2855,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -2867,11 +2867,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2879,11 +2879,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2891,11 +2891,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2903,11 +2903,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2915,11 +2915,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2927,11 +2927,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2939,11 +2939,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2951,11 +2951,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2963,11 +2963,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2975,11 +2975,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2987,11 +2987,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -2999,11 +2999,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3011,11 +3011,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3023,11 +3023,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3035,11 +3035,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3047,11 +3047,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3059,11 +3059,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3071,11 +3071,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3083,11 +3083,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3095,11 +3095,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3107,11 +3107,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3119,11 +3119,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3131,11 +3131,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3143,11 +3143,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3155,11 +3155,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3167,11 +3167,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3179,11 +3179,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3191,11 +3191,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3203,11 +3203,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3215,11 +3215,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3227,11 +3227,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3239,11 +3239,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3251,11 +3251,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3263,11 +3263,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3275,11 +3275,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3287,11 +3287,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3299,11 +3299,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3311,11 +3311,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3323,11 +3323,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3335,11 +3335,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3347,11 +3347,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3359,11 +3359,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3371,11 +3371,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3383,11 +3383,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3395,11 +3395,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3407,11 +3407,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3419,11 +3419,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3431,11 +3431,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3443,11 +3443,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3455,11 +3455,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3467,11 +3467,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3479,11 +3479,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3491,11 +3491,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3503,11 +3503,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3515,11 +3515,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3527,11 +3527,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3539,11 +3539,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3551,11 +3551,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3563,11 +3563,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3575,11 +3575,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3587,11 +3587,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3599,11 +3599,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3611,11 +3611,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3623,11 +3623,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3635,11 +3635,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3647,11 +3647,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3659,11 +3659,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3671,11 +3671,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3683,11 +3683,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3695,11 +3695,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3707,11 +3707,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3719,11 +3719,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3731,11 +3731,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3743,11 +3743,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3755,11 +3755,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3767,11 +3767,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3779,11 +3779,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3791,11 +3791,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3803,11 +3803,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3815,11 +3815,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3827,11 +3827,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3839,11 +3839,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3851,11 +3851,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3863,11 +3863,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3875,11 +3875,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3887,11 +3887,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3899,11 +3899,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3911,11 +3911,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3923,11 +3923,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3935,11 +3935,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -3947,11 +3947,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -3960,11 +3960,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -3973,11 +3973,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -3986,11 +3986,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -3999,11 +3999,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4012,11 +4012,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4025,11 +4025,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4038,11 +4038,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4051,11 +4051,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4064,11 +4064,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4077,11 +4077,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4090,11 +4090,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4103,11 +4103,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4116,11 +4116,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4129,11 +4129,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4142,11 +4142,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4155,11 +4155,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4168,11 +4168,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4181,11 +4181,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4194,11 +4194,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4207,11 +4207,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4220,11 +4220,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4233,11 +4233,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4246,11 +4246,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4259,11 +4259,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4272,11 +4272,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4285,11 +4285,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4298,11 +4298,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4311,11 +4311,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4324,11 +4324,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4337,11 +4337,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4350,11 +4350,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4363,11 +4363,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4376,11 +4376,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4389,11 +4389,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4402,11 +4402,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4415,11 +4415,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4428,11 +4428,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4441,11 +4441,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4454,11 +4454,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4467,11 +4467,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4480,11 +4480,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4493,11 +4493,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4506,11 +4506,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4519,11 +4519,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4532,11 +4532,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4545,11 +4545,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4558,11 +4558,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4571,11 +4571,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4584,11 +4584,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4597,11 +4597,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4610,11 +4610,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4623,11 +4623,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4636,11 +4636,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4649,10 +4649,10 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + diff --git a/app/btmesh/documentation/btmesh-release-highlights.txt b/app/btmesh/documentation/btmesh-release-highlights.txt index 56746690dc..a050c424a7 100644 --- a/app/btmesh/documentation/btmesh-release-highlights.txt +++ b/app/btmesh/documentation/btmesh-release-highlights.txt @@ -1,3 +1,2 @@ -Bluetooth Mesh SDK 8.0.0.0 -- Support added for Micrium and FreeRTOS. +Bluetooth Mesh SDK 8.0.1.0 - Bug fixes and minor enhancements. diff --git a/app/btmesh/documentation/slBtMesh_docContent.xml b/app/btmesh/documentation/slBtMesh_docContent.xml index 4b520de79b..ec0bb22695 100644 --- a/app/btmesh/documentation/slBtMesh_docContent.xml +++ b/app/btmesh/documentation/slBtMesh_docContent.xml @@ -1,6 +1,6 @@ - - + + Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -8,7 +8,7 @@ - + Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. @@ -16,7 +16,7 @@ - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -24,14 +24,14 @@ - + Details methods for testing Bluetooth mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - + Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. @@ -39,7 +39,7 @@ - + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. @@ -47,7 +47,7 @@ - + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -55,7 +55,7 @@ - + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. @@ -63,7 +63,7 @@ - + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. @@ -71,7 +71,7 @@ - + Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode @@ -79,7 +79,7 @@ - + Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. @@ -87,7 +87,7 @@ - + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. @@ -95,7 +95,7 @@ - + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. @@ -103,28 +103,28 @@ - + Describes the differences between using Bluetooth mesh SDK v1.x in Simplicity Studio 4 and using Bluetooth mesh SDK v2.x in Simplicity Studio 5. Outlines the steps needed to migrate a v1.x project to v2.x. - + Discusses the basics of Bluetooth mesh required to understand the Bluetooth mesh lighting example, and walks through key aspects of the application source code. - + Discusses the basics of sensor models and describe the related sample applications in the SDK that create a wireless network of sensors and sensor clients using Bluetooth mesh technology. - + Describes how to provision and configure Series 2 devices through the DCI and SWD. @@ -132,14 +132,14 @@ - + Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Mesh stack with Android and iOS smart phones. - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -147,21 +147,21 @@ - + Describes Low Power Node (LPN) and Friend operation and the parameters related to power consumption. It also describes how to measure the power consumption of EFR32BG devices acting as Bluetooth mesh LPNs using the setup and procedures recommended in AN969: Measuring Power Consumption in Wireless Gecko Devices. - + Describes in detail how the Bluetooth mesh toplogy can influence network operation. Provides tips on how to tune your network and its nodes to achieve best performance. - + Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. @@ -169,21 +169,21 @@ - + Provides background information on the sequence number and IV index in a Bluetooth mesh network and the IV Update and IV Index Recovery procedures. It also discusses how to implement IV Update functionality in a Bluetooth mesh application. - + Provides background information on the Bluetooth Mesh Device Firmware Update (DFU) feature, including the BLOB transfer, the DFU roles in a Bluetooth mesh network, the models required for these roles, and the firmware update process. - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -191,91 +191,91 @@ - + Describes the Bluetooth Mesh Remote Provisioning feature and provides an example walkthrough. With the feature, a device can be provisioned without a direct radio connection between the provisioner and the unprovisioned node. - + Describes the bootloader configurations and the device firmware update (DFU) models in the SDK's example projects, and walks through a firmware update demonstration. - + The NCP Host Provisioner example demonstrates how to run a provisioner on a computer with a NCP node connected. The user can provision, configure, and reset other nodes through the NCP node. - + Describes how certificates are used to establish the authenticity of devices wishing to join a mesh network. - + Describes the Bluetooth Mesh Advertising Extensions feature. The non-standard Bluetooth Mesh modification achieves better performance through utilizing the Bluetooth 5 Advertising Extensions feature, which allows sending much larger advertisement packets. - + Walks through a device firmware update demonstration using the DFU Python script. The script is an NCP host application that requires an NCP node connected. - + Describes the following Networked Lighting Control (NLC) profiles: ambient light sensor, basic scene selector, dimming control, basic lightness controller, and occupancy sensor. - + Provides an overview and hyperlinks to all packaged documentation. - + Describes how to get started with Bluetooth mesh development using the Bluetooth Mesh Software Development Kit (SDK) version 4.x and higher, and Simplicity Studio 5 with a compatible wireless starter kit. Contains information about features specific to Bluetooth mesh specification version 1.1. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Mesh stack. - + A reference for those developing C-based applications for the Silicon Labs EFR32 products using the Silicon Labs Bluetooth mesh stack. A companion to UG434: Silicon Labs Bluetooth C Application Developers Guide for SDK v3.x containing content specific to Bluetooth mesh application development. Covers Bluetooth mesh stack architecture, application development flow, use and limitations of the MCU core and peripherals, stack configuration options, and stack resource usage. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth mesh SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. @@ -283,7 +283,7 @@ - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -291,7 +291,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. @@ -299,7 +299,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: PS Store and NVM3. @@ -307,7 +307,7 @@ - + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. @@ -315,7 +315,7 @@ - + Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. @@ -323,7 +323,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface. @@ -331,7 +331,7 @@ - + Provides the information needed to effectively use the Bluetooth GATT Configurator provided as a part of Simplicity Studio 5 with Bluetooth SDK 3.x and higher and Bluetooth Mesh SDK 2.x and higher. @@ -339,14 +339,14 @@ - + Describes the components, stack, and DCD (Device Composition Data) configuration options for the Bluetooth Mesh v2.x SDK. - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. @@ -354,7 +354,7 @@ - + Introduces Simplicity Studio 5 Bluetooth Mesh SDK components. Describes how to modify the Device Composition Data (DCD), including device information, elements, and models. Describes the stack configuration options to optimize RAM and persistent storage usage. diff --git a/app/common/app_common.properties b/app/common/app_common.properties index cba224cb7a..42ef12f647 100644 --- a/app/common/app_common.properties +++ b/app/common/app_common.properties @@ -2,8 +2,8 @@ id=com.silabs.sdk.platform label=Platform description=Platform -version=5.1.0.0 -prop.subLabel=Platform\\ 5.1.0.0 +version=5.1.1.0 +prop.subLabel=Platform\\ 5.1.1.0 # General properties are prepended with "prop." prop.file.templatesFile=platform_deprecated_templates.xml platform_test_templates.xml platform_unknown_templates.xml platform_evaluation_templates.xml platform_experimental_templates.xml builtin_templates.xml platform_production_templates.xml platform_internal_templates.xml diff --git a/app/common/example/psa_crypto_asymmetric_key/app_process.c b/app/common/example/psa_crypto_asymmetric_key/app_process.c index 4dfd3eaf0c..73ce6ae258 100644 --- a/app/common/example/psa_crypto_asymmetric_key/app_process.c +++ b/app/common/example/psa_crypto_asymmetric_key/app_process.c @@ -440,7 +440,7 @@ void app_process_action(void) if (secpr1_key_size_select > SECPR1_SIZE_MAX) { secpr1_key_size_select = 0; } -#if defined(_SILICON_LABS_32B_SERIES_3) +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) if (asymmetric_key_storage_select > KEY_STORAGE_PLAIN_MAX) { if (secpr1_key_size_select > SECPR1_256_SIZE) { secpr1_key_size_select = 0; @@ -472,6 +472,11 @@ void app_process_action(void) if (montgomery_key_size_select > MONTGOMERY_SIZE_MAX) { montgomery_key_size_select = 0; } +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + if (asymmetric_key_storage_select > KEY_STORAGE_PLAIN_MAX) { + montgomery_key_size_select = 0; + } +#endif printf(" + Current %s key length is %d-bit (%s).\n", asymmetric_key_curve_string[asymmetric_key_curve_select], montgomery_key_size[montgomery_key_size_select], diff --git a/app/common/example/psa_crypto_asymmetric_key/app_process.h b/app/common/example/psa_crypto_asymmetric_key/app_process.h index 732bfcfd45..755dbfcf6b 100644 --- a/app/common/example/psa_crypto_asymmetric_key/app_process.h +++ b/app/common/example/psa_crypto_asymmetric_key/app_process.h @@ -60,7 +60,7 @@ typedef enum { #endif #define KEY_STORAGE_PLAIN_MAX PERSISTENT_PLAIN_KEY #define SECPR1_SIZE_MAX (3) -#define SECPR1_256_SIZE (3) +#define SECPR1_256_SIZE (1) #define KEY_USAGE_MAX (2) #define MONTGOMERY_SIZE_MAX (1) diff --git a/app/common/example/psa_crypto_dsa/app_process.c b/app/common/example/psa_crypto_dsa/app_process.c index 3a21c641b6..52ef8a6327 100644 --- a/app/common/example/psa_crypto_dsa/app_process.c +++ b/app/common/example/psa_crypto_dsa/app_process.c @@ -640,11 +640,17 @@ void app_process_action(void) "with public command key.\n"); set_key_id(SL_SE_BUILTIN_KEY_SECUREDEBUG_ID); } else { +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + app_state = SELECT_KEY_STORAGE; + print_key_storage(); + break; +#else printf("\n . Sign an already-calculated hash with private device " "key.\n"); dsa_state = ECDSA_DEVICE_KEY_SIGN_HASH; #if defined(SEMAILBOX_PRESENT) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) set_key_id(SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID); +#endif #endif } app_state = EXPORT_PUBLIC_BUILTIN_KEY; diff --git a/app/common/example/psa_crypto_x509/app_process.c b/app/common/example/psa_crypto_x509/app_process.c index 6c334a10e3..9785b624b6 100644 --- a/app/common/example/psa_crypto_x509/app_process.c +++ b/app/common/example/psa_crypto_x509/app_process.c @@ -149,6 +149,11 @@ void app_process_action(void) if (asymmetric_key_storage_select > KEY_STORAGE_MAX) { asymmetric_key_storage_select = VOLATILE_PLAIN_KEY; } +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + if (asymmetric_key_storage_select > PERSISTENT_WRAP_KEY) { + asymmetric_key_storage_select = 0; + } +#endif printf(" + Current asymmetric key is a %s key.\n", asymmetric_key_storage_string[asymmetric_key_storage_select]); } @@ -164,7 +169,13 @@ void app_process_action(void) app_state = SELECT_HASH_ALGO; break; } - +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + if (asymmetric_key_storage_select > KEY_STORAGE_PLAIN_MAX) { + if (secpr1_key_size_select > SECPR1_256_SIZE) { + secpr1_key_size_select = 0; + } + } +#endif printf("\n . Current SECPxxxR1 key length is %d-bit (%s).\n", secpr1_key_size[secpr1_key_size_select], secpr1_key_size_string[secpr1_key_size_select]); @@ -242,6 +253,7 @@ void app_process_action(void) case CREATE_ROOT_KEY: app_state = PSA_CRYPTO_EXIT; +#if !defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) if (asymmetric_key_storage_select > PERSISTENT_WRAP_KEY) { #if defined(SEMAILBOX_PRESENT) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) // Use built-in ECC key for root certificate @@ -249,7 +261,9 @@ void app_process_action(void) #endif root_cert_key_id = get_key_id(); app_state = WRAP_ROOT_PSA_KEY; - } else { + } else +#endif + { printf(" + Creating a %s (%d-bit) %s root certificate key... ", secpr1_key_size_string[secpr1_key_size_select], secpr1_key_size[secpr1_key_size_select], @@ -749,10 +763,23 @@ static void print_key_storage(void) } } +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + if (asymmetric_key_storage_select > PERSISTENT_WRAP_KEY) { + asymmetric_key_storage_select = 0; + } +#endif printf("\n . Current asymmetric key is a %s key.\n", asymmetric_key_storage_string[asymmetric_key_storage_select]); #if defined(SEMAILBOX_PRESENT) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + printf(" + Press SPACE to select a %s or %s or %s or %s key \n" + " press ENTER to next option.\n", + asymmetric_key_storage_string[0], + asymmetric_key_storage_string[1], + asymmetric_key_storage_string[2], + asymmetric_key_storage_string[3]); +#else printf(" + Press SPACE to select a %s or %s or %s or %s or \n" " %s or %s or %s or %s key, press ENTER to next option.\n", asymmetric_key_storage_string[0], @@ -763,6 +790,7 @@ static void print_key_storage(void) asymmetric_key_storage_string[5], asymmetric_key_storage_string[6], asymmetric_key_storage_string[7]); +#endif #else printf(" + Press SPACE to select a %s or %s key, press ENTER to next " "option.\n", asymmetric_key_storage_string[0], diff --git a/app/common/example/se_manager_host_firmware_upgrade/app_host_firmware_image.c b/app/common/example/se_manager_host_firmware_upgrade/app_host_firmware_image.c index ade88efcfd..65f4e1021c 100644 --- a/app/common/example/se_manager_host_firmware_upgrade/app_host_firmware_image.c +++ b/app/common/example/se_manager_host_firmware_upgrade/app_host_firmware_image.c @@ -2744,6 +2744,354 @@ SL_ALIGN(4) static const uint8_t host_firmware_image[] SL_ATTRIBUTE_ALIGN(4) SL_ 0x18, 0x13, 0x00, 0x20, 0x1C, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xC4, 0x4E, 0x00, 0x08, 0xE4, 0x4E, 0x00, 0x08, 0xA4, 0x4E, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x7D, 0x01, 0x00, 0x08, 0x59, 0x01, 0x00, 0x08, +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) + 0x00, 0x10, 0x00, 0x20, 0xF9, 0x03, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x6D, 0x24, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x5D, 0x08, 0x00, 0x08, 0x3D, 0x08, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, + 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x57, 0x29, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x38, 0x00, 0xD0, 0xFC, 0xE7, 0x70, 0x47, + 0x03, 0x48, 0x04, 0x4B, 0x83, 0x42, 0x02, 0xD0, 0x03, 0x4B, 0x03, 0xB1, 0x18, 0x47, 0x70, 0x47, 0xE4, 0x11, 0x00, 0x20, 0xE4, 0x11, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x06, 0x4B, 0x07, 0x49, 0xC9, 0x1A, 0x89, 0x10, 0x48, 0xBF, 0x01, 0x31, + 0x49, 0x10, 0x03, 0xD0, 0x04, 0x4B, 0x0B, 0xB1, 0x01, 0x48, 0x18, 0x47, 0x70, 0x47, 0x00, 0xBF, 0xE4, 0x11, 0x00, 0x20, 0xE4, 0x11, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x10, 0xB5, 0x06, 0x4C, 0x23, 0x78, 0x43, 0xB9, 0xFF, 0xF7, 0xD8, 0xFF, + 0x04, 0x4B, 0x13, 0xB1, 0x04, 0x48, 0xAF, 0xF3, 0x00, 0x80, 0x01, 0x23, 0x23, 0x70, 0x10, 0xBD, 0xB8, 0x11, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xF4, 0x35, 0x00, 0x08, 0x08, 0xB5, 0x05, 0x4B, 0x1B, 0xB1, 0x05, 0x49, 0x05, 0x48, 0xAF, 0xF3, + 0x00, 0x80, 0xBD, 0xE8, 0x08, 0x40, 0xFF, 0xF7, 0xCD, 0xBF, 0x00, 0xBF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0xF4, 0x35, 0x00, 0x08, 0xA3, 0xF5, 0x80, 0x3A, 0x70, 0x47, 0x00, 0xBF, 0x17, 0x4B, 0x00, 0x2B, 0x08, 0xBF, 0x13, 0x4B, + 0x9D, 0x46, 0xFF, 0xF7, 0xF5, 0xFF, 0x00, 0x21, 0x8B, 0x46, 0x0F, 0x46, 0x13, 0x48, 0x14, 0x4A, 0x12, 0x1A, 0x02, 0xF0, 0x90, 0xFC, 0x0E, 0x4B, 0x00, 0x2B, 0x00, 0xD0, 0x98, 0x47, 0x0D, 0x4B, 0x00, 0x2B, 0x00, 0xD0, 0x98, 0x47, 0x00, 0x20, + 0x00, 0x21, 0x04, 0x00, 0x0D, 0x00, 0x0D, 0x48, 0x00, 0x28, 0x02, 0xD0, 0x0C, 0x48, 0xAF, 0xF3, 0x00, 0x80, 0x02, 0xF0, 0x57, 0xFB, 0x20, 0x00, 0x29, 0x00, 0x02, 0xF0, 0x55, 0xFC, 0x02, 0xF0, 0x3F, 0xFB, 0x00, 0xBF, 0x00, 0x00, 0x08, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x10, 0x00, 0x20, 0xC4, 0x11, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xB5, 0x04, 0x48, 0x02, 0xF0, 0x16, 0xFC, 0x02, 0xF0, 0x46, 0xFC, + 0xBD, 0xE8, 0x08, 0x40, 0x00, 0xF0, 0x08, 0xB8, 0xB4, 0x34, 0x00, 0x08, 0x01, 0x48, 0x02, 0xF0, 0x0B, 0xBC, 0x00, 0xBF, 0xB4, 0x34, 0x00, 0x08, 0x2D, 0xE9, 0xF0, 0x41, 0x49, 0x4E, 0x8C, 0xB0, 0x35, 0x46, 0x05, 0xAC, 0x0F, 0xCD, 0x0F, 0xC4, + 0x95, 0xE8, 0x07, 0x00, 0x01, 0x25, 0xB3, 0x8B, 0xDF, 0xF8, 0x24, 0x81, 0xAD, 0xF8, 0x00, 0x30, 0xF3, 0x8B, 0x84, 0xE8, 0x07, 0x00, 0xAD, 0xF8, 0x04, 0x30, 0x33, 0x8C, 0x76, 0x8C, 0x40, 0x48, 0x40, 0x4F, 0xAD, 0xF8, 0x08, 0x30, 0xAD, 0xF8, + 0x0C, 0x60, 0x02, 0xF0, 0xE9, 0xFB, 0x40, 0x46, 0x02, 0xF0, 0xE6, 0xFB, 0x3C, 0x4B, 0x38, 0x46, 0x05, 0xA9, 0x07, 0x93, 0x8D, 0xF8, 0x22, 0x50, 0x01, 0xF0, 0x3A, 0xFD, 0x2A, 0x46, 0x04, 0x21, 0x68, 0x46, 0x00, 0xF0, 0xAB, 0xF9, 0x29, 0x46, + 0x00, 0x22, 0x01, 0xA8, 0x00, 0xF0, 0xA6, 0xF9, 0x2A, 0x46, 0x04, 0x21, 0x02, 0xA8, 0x00, 0xF0, 0xA1, 0xF9, 0x2A, 0x46, 0x04, 0x21, 0x03, 0xA8, 0x00, 0xF0, 0x9C, 0xF9, 0x4F, 0xF0, 0x02, 0x13, 0x2E, 0x4C, 0x4F, 0xF4, 0x48, 0x70, 0xC4, 0xF8, + 0x68, 0x36, 0x03, 0xF5, 0x80, 0x33, 0xC4, 0xF8, 0x64, 0x36, 0x03, 0xF5, 0x00, 0x33, 0xC4, 0xF8, 0x6C, 0x36, 0x1C, 0x23, 0xC4, 0xF8, 0x54, 0x36, 0x02, 0xF0, 0xB2, 0xF8, 0x04, 0xA8, 0xAD, 0xF8, 0x10, 0x60, 0x00, 0xF0, 0xEF, 0xF9, 0x14, 0x20, + 0x02, 0xF0, 0xAA, 0xF8, 0x04, 0xA8, 0xAD, 0xF8, 0x10, 0x60, 0x00, 0xF0, 0xBB, 0xF9, 0x23, 0x20, 0x02, 0xF0, 0xA2, 0xF8, 0x04, 0xA8, 0xAD, 0xF8, 0x10, 0x60, 0x00, 0xF0, 0xDF, 0xF9, 0xB9, 0x21, 0x38, 0x46, 0x02, 0xF0, 0x82, 0xFB, 0x04, 0xA8, + 0xAD, 0xF8, 0x10, 0x60, 0x00, 0xF0, 0xAA, 0xF9, 0x00, 0x22, 0x68, 0x46, 0x11, 0x46, 0x00, 0xF0, 0x65, 0xF9, 0x00, 0x22, 0x01, 0xA8, 0x11, 0x46, 0x00, 0xF0, 0x60, 0xF9, 0x2A, 0x46, 0x00, 0x21, 0x02, 0xA8, 0x00, 0xF0, 0x5B, 0xF9, 0x2A, 0x46, + 0x00, 0x21, 0x03, 0xA8, 0x00, 0xF0, 0x56, 0xF9, 0x38, 0x46, 0x01, 0xF0, 0xA5, 0xFC, 0x00, 0x23, 0x40, 0x46, 0xC4, 0xF8, 0x54, 0x36, 0xC4, 0xF8, 0x68, 0x36, 0xC4, 0xF8, 0x64, 0x36, 0xC4, 0xF8, 0x6C, 0x36, 0x02, 0xF0, 0x78, 0xFB, 0x0C, 0xB0, + 0xBD, 0xE8, 0xF0, 0x81, 0x18, 0x32, 0x00, 0x08, 0xB4, 0x34, 0x00, 0x08, 0x00, 0xC0, 0x05, 0x50, 0x00, 0x12, 0x7A, 0x00, 0x00, 0xC0, 0x03, 0x50, 0xAC, 0x34, 0x00, 0x08, 0x03, 0x48, 0x04, 0x4A, 0x04, 0x49, 0x12, 0x1A, 0x92, 0x10, 0x02, 0xF0, + 0xB7, 0xBA, 0x00, 0xBF, 0x58, 0x01, 0x00, 0x08, 0x58, 0x01, 0x00, 0x08, 0xC4, 0x11, 0x00, 0x20, 0x08, 0xB5, 0x00, 0xF0, 0x2F, 0xF8, 0xFF, 0xF7, 0xED, 0xFF, 0x12, 0x4B, 0x12, 0x49, 0x8B, 0x42, 0x12, 0xD3, 0x00, 0x20, 0x11, 0x4B, 0x12, 0x49, + 0x8B, 0x42, 0x18, 0xD3, 0xFF, 0xF7, 0xF4, 0xFE, 0x18, 0x68, 0x50, 0xF8, 0x22, 0x40, 0x58, 0x68, 0x40, 0xF8, 0x22, 0x40, 0x01, 0x32, 0x98, 0x68, 0x82, 0x42, 0xF5, 0xD3, 0x0C, 0x33, 0xEA, 0xE7, 0x00, 0x22, 0xF8, 0xE7, 0x1C, 0x68, 0x44, 0xF8, + 0x22, 0x00, 0x01, 0x32, 0x5C, 0x68, 0xA2, 0x42, 0xF8, 0xD3, 0x08, 0x33, 0xE4, 0xE7, 0x00, 0x22, 0xF8, 0xE7, 0x00, 0xBF, 0xFC, 0x35, 0x00, 0x08, 0x08, 0x36, 0x00, 0x08, 0x08, 0x36, 0x00, 0x08, 0x08, 0x36, 0x00, 0x08, 0x4F, 0xF4, 0x00, 0x41, + 0x12, 0x4B, 0x13, 0x4A, 0x70, 0xB5, 0x9A, 0x60, 0xD3, 0xF8, 0x88, 0x20, 0x11, 0x4D, 0x42, 0xF4, 0x70, 0x02, 0xC3, 0xF8, 0x88, 0x20, 0x10, 0x4A, 0x05, 0xF5, 0x00, 0x54, 0x91, 0x66, 0x4F, 0xF0, 0xFF, 0x32, 0x22, 0x66, 0x0D, 0x4A, 0x62, 0x66, + 0x02, 0x22, 0xC3, 0xF8, 0xD0, 0x20, 0xBF, 0xF3, 0x4F, 0x8F, 0xBF, 0xF3, 0x6F, 0x8F, 0x4F, 0xF4, 0x40, 0x36, 0x03, 0x20, 0x01, 0xF0, 0x1A, 0xFF, 0x03, 0x20, 0xE6, 0x60, 0x01, 0xF0, 0xE4, 0xFE, 0x2E, 0x61, 0x70, 0xBD, 0x00, 0xED, 0x00, 0xE0, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x44, 0x00, 0x90, 0x00, 0x50, 0xBF, 0xFF, 0x02, 0x00, 0x01, 0x4B, 0x18, 0x60, 0x70, 0x47, 0x00, 0xBF, 0xC8, 0x11, 0x00, 0x20, 0x05, 0x4B, 0x18, 0x60, 0x05, 0x4B, 0x1B, 0x6F, 0x03, 0xF0, 0x07, 0x03, + 0x03, 0x2B, 0x01, 0xD1, 0x02, 0xF0, 0x5E, 0xBB, 0x70, 0x47, 0x00, 0xBF, 0xD0, 0x11, 0x00, 0x20, 0x00, 0x80, 0x00, 0x50, 0x00, 0x23, 0x07, 0xB5, 0x29, 0x48, 0x01, 0x93, 0x02, 0xF0, 0xD8, 0xFA, 0x4F, 0xF4, 0x40, 0x73, 0x01, 0x22, 0x04, 0x21, + 0x68, 0x46, 0xAD, 0xF8, 0x00, 0x30, 0x00, 0xF0, 0xA1, 0xF8, 0x01, 0x22, 0x23, 0x4B, 0x05, 0x20, 0xC3, 0xF8, 0x44, 0x24, 0x01, 0xA9, 0x02, 0xF0, 0xFB, 0xFD, 0x00, 0x28, 0x39, 0xD1, 0x20, 0x4B, 0xD3, 0xF8, 0xF0, 0x20, 0x42, 0xF0, 0x01, 0x02, + 0xC3, 0xF8, 0xF0, 0x20, 0xD3, 0xF8, 0xFC, 0x20, 0x42, 0xF0, 0x80, 0x72, 0xC3, 0xF8, 0xFC, 0x20, 0x1A, 0x4A, 0xA3, 0xF5, 0x5D, 0x43, 0x1A, 0x60, 0x01, 0x9B, 0x19, 0x4A, 0x03, 0xF5, 0xD5, 0x23, 0x03, 0xF2, 0xFC, 0x43, 0xB3, 0xFB, 0xF2, 0xF3, + 0x16, 0x4A, 0x01, 0x3B, 0x13, 0x61, 0x02, 0x23, 0xC2, 0xF8, 0xF0, 0x30, 0x4F, 0xF4, 0x80, 0x73, 0xC2, 0xF8, 0x04, 0x33, 0x4F, 0xF0, 0x60, 0x43, 0x11, 0x4A, 0xC3, 0xF8, 0xB0, 0x2F, 0x11, 0x4A, 0xC3, 0xF8, 0x80, 0x2E, 0xD3, 0xF8, 0x00, 0x2E, + 0x42, 0xF4, 0x80, 0x72, 0xC3, 0xF8, 0x00, 0x2E, 0xFF, 0x22, 0x83, 0xF8, 0x20, 0x20, 0xD3, 0xF8, 0x00, 0x2E, 0x22, 0xF4, 0x80, 0x72, 0xC3, 0xF8, 0x00, 0x2E, 0x03, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, 0xB4, 0x34, 0x00, 0x08, 0x00, 0xD0, 0x03, 0x50, + 0x00, 0xED, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x40, 0xF8, 0x59, 0x0D, 0x00, 0x00, 0x00, 0x04, 0xE0, 0x55, 0xCE, 0xAC, 0xC5, 0x09, 0x00, 0x01, 0x00, 0x2D, 0xE9, 0xF0, 0x41, 0x04, 0x46, 0x0C, 0x25, 0x4F, 0xF0, 0x01, 0x08, 0x12, 0x4E, 0x0C, 0xB3, + 0x14, 0xF0, 0x01, 0x00, 0x0B, 0xD0, 0x00, 0x20, 0x24, 0xF0, 0x01, 0x04, 0x05, 0xFB, 0x00, 0x62, 0x57, 0x68, 0x00, 0x2F, 0xF3, 0xD0, 0x91, 0x68, 0xC0, 0xB2, 0xB8, 0x47, 0xEF, 0xE7, 0x22, 0x46, 0x01, 0x30, 0x20, 0x28, 0x4F, 0xEA, 0x52, 0x02, + 0x01, 0xD0, 0xD3, 0x07, 0xF8, 0xD5, 0x08, 0xFA, 0x00, 0xF2, 0x0F, 0x28, 0x24, 0xEA, 0x02, 0x04, 0xE8, 0xD9, 0x10, 0x38, 0x05, 0xFB, 0x00, 0x62, 0xB4, 0x32, 0xE5, 0xE7, 0xBD, 0xE8, 0xF0, 0x81, 0x18, 0x10, 0x00, 0x20, 0x08, 0xB5, 0x0C, 0x48, + 0x02, 0xF0, 0x46, 0xFA, 0x1E, 0x20, 0x01, 0xF0, 0x41, 0xFE, 0x28, 0xB1, 0x1E, 0x20, 0x01, 0xF0, 0x55, 0xFE, 0x1E, 0x20, 0x01, 0xF0, 0x20, 0xFE, 0x1F, 0x20, 0x01, 0xF0, 0x37, 0xFE, 0x28, 0xB1, 0x1F, 0x20, 0x01, 0xF0, 0x4B, 0xFE, 0x1F, 0x20, + 0x01, 0xF0, 0x16, 0xFE, 0x00, 0x20, 0x08, 0xBD, 0xB4, 0x34, 0x00, 0x08, 0x2D, 0xE9, 0xF0, 0x41, 0x0E, 0x46, 0x17, 0x46, 0x04, 0x46, 0x38, 0xB9, 0x91, 0x21, 0x19, 0x48, 0x02, 0xF0, 0x79, 0xF9, 0x22, 0x25, 0x28, 0x46, 0xBD, 0xE8, 0xF0, 0x81, + 0x0F, 0x29, 0x0B, 0xD8, 0x03, 0x78, 0x7B, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x12, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x07, 0xD4, 0x95, 0x21, 0x0E, 0x48, 0x02, 0xF0, 0x63, 0xF9, 0x21, 0x25, 0xE8, 0xE7, + 0x7F, 0x23, 0xF3, 0xE7, 0x0C, 0x4B, 0xD3, 0xF8, 0x10, 0x53, 0x2D, 0xB1, 0x99, 0x21, 0x08, 0x48, 0x02, 0xF0, 0x57, 0xF9, 0x02, 0x25, 0xDC, 0xE7, 0x02, 0xF0, 0x26, 0xFD, 0x80, 0x46, 0x3A, 0x46, 0x20, 0x46, 0x31, 0x46, 0x01, 0xF0, 0x44, 0xFC, + 0x40, 0x46, 0x02, 0xF0, 0x18, 0xFD, 0xD0, 0xE7, 0x3C, 0x32, 0x00, 0x08, 0x84, 0x32, 0x00, 0x08, 0x00, 0xC0, 0x03, 0x50, 0x38, 0xB5, 0x04, 0x46, 0x28, 0xB9, 0x12, 0x48, 0xE2, 0x21, 0x02, 0xF0, 0x3C, 0xF9, 0x22, 0x20, 0x38, 0xBD, 0x03, 0x78, + 0x7B, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x0D, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x07, 0xD4, 0x09, 0x48, 0xE6, 0x21, 0x02, 0xF0, 0x2A, 0xF9, 0x21, 0x20, 0xEC, 0xE7, 0x7F, 0x23, 0xF3, 0xE7, 0x02, 0xF0, + 0xF7, 0xFC, 0x05, 0x46, 0x20, 0x46, 0x02, 0xF0, 0x6F, 0xFA, 0x28, 0x46, 0x02, 0xF0, 0xEB, 0xFC, 0x00, 0x20, 0xDF, 0xE7, 0x3C, 0x32, 0x00, 0x08, 0x84, 0x32, 0x00, 0x08, 0x38, 0xB5, 0x04, 0x46, 0x28, 0xB9, 0x12, 0x48, 0xFA, 0x21, 0x02, 0xF0, + 0x10, 0xF9, 0x22, 0x20, 0x38, 0xBD, 0x03, 0x78, 0x7B, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x0D, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x07, 0xD4, 0x09, 0x48, 0xFE, 0x21, 0x02, 0xF0, 0xFE, 0xF8, 0x21, 0x20, + 0xEC, 0xE7, 0x7F, 0x23, 0xF3, 0xE7, 0x02, 0xF0, 0xCB, 0xFC, 0x05, 0x46, 0x20, 0x46, 0x01, 0xF0, 0x61, 0xFB, 0x28, 0x46, 0x02, 0xF0, 0xBF, 0xFC, 0x00, 0x20, 0xDF, 0xE7, 0x3C, 0x32, 0x00, 0x08, 0x84, 0x32, 0x00, 0x08, 0x38, 0xB5, 0x04, 0x46, + 0x30, 0xB9, 0x13, 0x48, 0x4F, 0xF4, 0x89, 0x71, 0x02, 0xF0, 0xE3, 0xF8, 0x22, 0x20, 0x38, 0xBD, 0x03, 0x78, 0x83, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x0D, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x08, 0xD4, + 0x09, 0x48, 0x4F, 0xF4, 0x8B, 0x71, 0x02, 0xF0, 0xD0, 0xF8, 0x21, 0x20, 0xEB, 0xE7, 0x7F, 0x23, 0xF2, 0xE7, 0x02, 0xF0, 0x9D, 0xFC, 0x05, 0x46, 0x20, 0x46, 0x01, 0xF0, 0x89, 0xFB, 0x28, 0x46, 0x02, 0xF0, 0x91, 0xFC, 0x00, 0x20, 0xDE, 0xE7, + 0x3C, 0x32, 0x00, 0x08, 0x84, 0x32, 0x00, 0x08, 0x70, 0xB5, 0x0D, 0x46, 0x04, 0x46, 0x00, 0xB1, 0x31, 0xB9, 0x14, 0x48, 0x40, 0xF2, 0x2B, 0x11, 0x02, 0xF0, 0xB3, 0xF8, 0x22, 0x20, 0x70, 0xBD, 0x03, 0x78, 0x83, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, + 0x02, 0x2B, 0x05, 0xD8, 0x0E, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x08, 0xD4, 0x0A, 0x48, 0x40, 0xF2, 0x2F, 0x11, 0x02, 0xF0, 0xA0, 0xF8, 0x21, 0x20, 0xEB, 0xE7, 0x7F, 0x23, 0xF2, 0xE7, 0x02, 0xF0, 0x6D, 0xFC, 0x06, 0x46, + 0x20, 0x46, 0x01, 0xF0, 0x2D, 0xFB, 0x28, 0x70, 0x30, 0x46, 0x02, 0xF0, 0x60, 0xFC, 0x00, 0x20, 0xDD, 0xE7, 0x00, 0xBF, 0x3C, 0x32, 0x00, 0x08, 0x84, 0x32, 0x00, 0x08, 0x08, 0xB5, 0x01, 0xF0, 0x75, 0xFB, 0x05, 0x4B, 0x00, 0xF0, 0x55, 0x30, + 0x20, 0xF0, 0x50, 0x20, 0xC3, 0xF8, 0x20, 0x04, 0xBD, 0xE8, 0x08, 0x40, 0xFF, 0xF7, 0xB0, 0xBE, 0x00, 0xE0, 0x03, 0x50, 0x08, 0xB5, 0x01, 0xF0, 0x65, 0xFB, 0x05, 0x4B, 0x00, 0xF0, 0xAA, 0x30, 0x20, 0xF0, 0xA0, 0x20, 0xC3, 0xF8, 0x20, 0x04, + 0xBD, 0xE8, 0x08, 0x40, 0xFF, 0xF7, 0xA0, 0xBE, 0x00, 0xE0, 0x03, 0x50, 0x13, 0xB5, 0x04, 0x46, 0x0A, 0x48, 0x02, 0xF0, 0x11, 0xF9, 0xA2, 0x78, 0x04, 0x21, 0xB2, 0xFA, 0x82, 0xF2, 0x23, 0x78, 0x52, 0x09, 0x8D, 0xF8, 0x04, 0x30, 0x63, 0x78, + 0x0D, 0xEB, 0x01, 0x00, 0x8D, 0xF8, 0x05, 0x30, 0xFF, 0xF7, 0xD4, 0xFE, 0x00, 0x20, 0x02, 0xB0, 0x10, 0xBD, 0x00, 0xBF, 0xB4, 0x34, 0x00, 0x08, 0x04, 0x4B, 0xD3, 0xF8, 0x84, 0x20, 0xD2, 0x06, 0xFB, 0xD4, 0xD3, 0xF8, 0x84, 0x00, 0xC0, 0xF3, + 0x81, 0x10, 0x70, 0x47, 0x00, 0x40, 0x00, 0x50, 0x38, 0xB5, 0x10, 0x4B, 0x05, 0x46, 0xD3, 0xF8, 0x00, 0x31, 0x0C, 0x46, 0x03, 0xF0, 0x03, 0x03, 0x02, 0x2B, 0x0B, 0xD0, 0x03, 0x2B, 0x0D, 0xD0, 0x01, 0x2B, 0x0F, 0xD1, 0x02, 0xF0, 0x74, 0xF9, + 0x03, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0x76, 0xF9, 0x08, 0x23, 0xF6, 0xE7, 0x02, 0xF0, 0x6E, 0xF9, 0x07, 0x23, 0xF2, 0xE7, 0x01, 0x23, 0x00, 0x20, 0xEF, 0xE7, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, + 0x38, 0xB5, 0x10, 0x4B, 0x05, 0x46, 0xD3, 0xF8, 0x20, 0x31, 0x0C, 0x46, 0x03, 0xF0, 0x03, 0x03, 0x02, 0x2B, 0x0B, 0xD0, 0x03, 0x2B, 0x0D, 0xD0, 0x01, 0x2B, 0x0F, 0xD1, 0x02, 0xF0, 0x10, 0xF9, 0x05, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, + 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0x48, 0xF9, 0x03, 0x23, 0xF6, 0xE7, 0x02, 0xF0, 0x40, 0xF9, 0x02, 0x23, 0xF2, 0xE7, 0x01, 0x23, 0x00, 0x20, 0xEF, 0xE7, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0x38, 0xB5, 0x10, 0x4B, 0x05, 0x46, 0xD3, 0xF8, + 0x40, 0x31, 0x0C, 0x46, 0x03, 0xF0, 0x03, 0x03, 0x02, 0x2B, 0x0B, 0xD0, 0x03, 0x2B, 0x0D, 0xD0, 0x01, 0x2B, 0x0F, 0xD1, 0x02, 0xF0, 0xC6, 0xFB, 0x09, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0x2E, 0xF9, + 0x08, 0x23, 0xF6, 0xE7, 0x02, 0xF0, 0xBD, 0xFB, 0x0B, 0x23, 0xF2, 0xE7, 0x01, 0x23, 0x00, 0x20, 0xEF, 0xE7, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0x37, 0xB5, 0x0C, 0x46, 0x00, 0x21, 0x12, 0x4B, 0x01, 0x91, 0xD3, 0xF8, 0x84, 0x32, 0x05, 0x46, + 0x03, 0xF0, 0x03, 0x03, 0x02, 0x2B, 0x0E, 0xD0, 0x03, 0x2B, 0x11, 0xD0, 0x01, 0x2B, 0x14, 0xD1, 0x01, 0xA8, 0xFF, 0xF7, 0xA5, 0xFF, 0x0F, 0x23, 0x0D, 0xB1, 0x01, 0x9A, 0x2A, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x03, 0xB0, 0x30, 0xBD, 0x01, 0xA8, + 0xFF, 0xF7, 0xBE, 0xFF, 0x10, 0x23, 0xF3, 0xE7, 0x02, 0xF0, 0xF2, 0xF8, 0x02, 0x23, 0x01, 0x90, 0xEE, 0xE7, 0x01, 0x23, 0xEC, 0xE7, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0x38, 0xB5, 0x10, 0x4B, 0x05, 0x46, 0xD3, 0xF8, 0x60, 0x31, 0x0C, 0x46, + 0x03, 0xF0, 0x03, 0x03, 0x02, 0x2B, 0x0B, 0xD0, 0x03, 0x2B, 0x0D, 0xD0, 0x01, 0x2B, 0x0F, 0xD1, 0x02, 0xF0, 0x78, 0xFB, 0x09, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0xE0, 0xF8, 0x08, 0x23, 0xF6, 0xE7, + 0x02, 0xF0, 0x6F, 0xFB, 0x0B, 0x23, 0xF2, 0xE7, 0x01, 0x23, 0x00, 0x20, 0xEF, 0xE7, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0x38, 0xB5, 0x0F, 0x4B, 0x05, 0x46, 0xD3, 0xF8, 0x80, 0x30, 0x0C, 0x46, 0x03, 0xF0, 0x03, 0x03, 0x01, 0x2B, 0x09, 0xD0, + 0x02, 0x2B, 0x0F, 0xD0, 0x0A, 0x48, 0x41, 0xF2, 0x14, 0x21, 0x01, 0xF0, 0x7A, 0xFF, 0x00, 0x23, 0x18, 0x46, 0x02, 0xE0, 0x02, 0xF0, 0x7A, 0xF8, 0x0D, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0x6C, 0xF8, + 0x06, 0x23, 0xF6, 0xE7, 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, 0x38, 0xB5, 0x1A, 0x4B, 0x05, 0x46, 0xD3, 0xF8, 0x24, 0x01, 0x0C, 0x46, 0x00, 0xF0, 0x07, 0x00, 0x06, 0x28, 0x21, 0xD8, 0xDF, 0xE8, 0x00, 0xF0, 0x28, 0x04, 0x10, 0x18, + 0x1C, 0x0C, 0x14, 0x00, 0x02, 0xF0, 0x54, 0xF8, 0x05, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0x4C, 0xF8, 0x06, 0x23, 0xF6, 0xE7, 0x02, 0xF0, 0x88, 0xF8, 0x03, 0x23, 0xF2, 0xE7, 0x02, 0xF0, 0x84, 0xF8, + 0x04, 0x23, 0xEE, 0xE7, 0x02, 0xF0, 0x7C, 0xF8, 0x02, 0x23, 0xEA, 0xE7, 0x02, 0xF0, 0x82, 0xF8, 0x07, 0x23, 0xE6, 0xE7, 0x05, 0x48, 0x40, 0xF6, 0xDB, 0x71, 0x01, 0xF0, 0x36, 0xFF, 0x00, 0x23, 0x18, 0x46, 0xDE, 0xE7, 0x01, 0x23, 0xDC, 0xE7, + 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, 0x38, 0xB5, 0x12, 0x4B, 0x05, 0x46, 0xD3, 0xF8, 0x28, 0x31, 0x0C, 0x46, 0x03, 0xF0, 0x03, 0x03, 0x02, 0x2B, 0x0B, 0xD0, 0x03, 0x2B, 0x0D, 0xD0, 0x01, 0x2B, 0x0F, 0xD1, 0x02, 0xF0, 0x1C, 0xF8, + 0x05, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0x54, 0xF8, 0x03, 0x23, 0xF6, 0xE7, 0x02, 0xF0, 0x4C, 0xF8, 0x02, 0x23, 0xF2, 0xE7, 0x04, 0x48, 0x41, 0xF2, 0x99, 0x01, 0x01, 0xF0, 0x0A, 0xFF, 0x00, 0x23, + 0x18, 0x46, 0xEA, 0xE7, 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, 0xF7, 0xB5, 0x00, 0x27, 0x11, 0x4B, 0x01, 0x97, 0xD3, 0xF8, 0x80, 0x41, 0x06, 0x46, 0x04, 0xF0, 0x03, 0x04, 0x01, 0x2C, 0x0D, 0x46, 0x08, 0xD0, 0x02, 0x2C, 0x12, 0xD0, + 0x41, 0xF2, 0xE6, 0x31, 0x0B, 0x48, 0x01, 0xF0, 0xF0, 0xFE, 0x3C, 0x46, 0x04, 0xE0, 0x39, 0x46, 0x01, 0xA8, 0xFF, 0xF7, 0xC9, 0xFE, 0x0F, 0x24, 0x0E, 0xB1, 0x01, 0x9B, 0x33, 0x60, 0x05, 0xB1, 0x2C, 0x60, 0x03, 0xB0, 0xF0, 0xBD, 0x02, 0xF0, + 0x1B, 0xF8, 0x01, 0x90, 0xF4, 0xE7, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, 0x38, 0xB5, 0x16, 0x4B, 0x05, 0x46, 0xD3, 0xF8, 0x00, 0x02, 0x0C, 0x46, 0x00, 0xF0, 0x07, 0x00, 0x04, 0x28, 0x19, 0xD8, 0xDF, 0xE8, 0x00, 0xF0, + 0x20, 0x03, 0x0B, 0x0F, 0x13, 0x00, 0x02, 0xF0, 0xA1, 0xFA, 0x09, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, 0x02, 0xF0, 0x09, 0xF8, 0x08, 0x23, 0xF6, 0xE7, 0x02, 0xF0, 0x98, 0xFA, 0x0B, 0x23, 0xF2, 0xE7, 0x01, 0xF0, + 0xDD, 0xFF, 0x0E, 0x23, 0x80, 0x0A, 0xED, 0xE7, 0x05, 0x48, 0x41, 0xF2, 0xA4, 0x41, 0x01, 0xF0, 0xB0, 0xFE, 0x00, 0x23, 0x18, 0x46, 0xE5, 0xE7, 0x01, 0x23, 0xE3, 0xE7, 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, 0x38, 0xB5, 0x12, 0x4B, + 0x05, 0x46, 0xD3, 0xF8, 0x40, 0x32, 0x0C, 0x46, 0x03, 0xF0, 0x03, 0x03, 0x02, 0x2B, 0x0B, 0xD0, 0x03, 0x2B, 0x0D, 0xD0, 0x01, 0x2B, 0x0F, 0xD1, 0x02, 0xF0, 0x70, 0xFA, 0x09, 0x23, 0x05, 0xB1, 0x28, 0x60, 0x04, 0xB1, 0x23, 0x60, 0x38, 0xBD, + 0x01, 0xF0, 0xD8, 0xFF, 0x08, 0x23, 0xF6, 0xE7, 0x02, 0xF0, 0x67, 0xFA, 0x0B, 0x23, 0xF2, 0xE7, 0x04, 0x48, 0x41, 0xF2, 0x2F, 0x41, 0x01, 0xF0, 0x84, 0xFE, 0x00, 0x23, 0x18, 0x46, 0xEA, 0xE7, 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, + 0x08, 0xB5, 0x33, 0x4B, 0x98, 0x42, 0x4F, 0xD0, 0x27, 0xD8, 0x32, 0x4B, 0x98, 0x42, 0x45, 0xD0, 0x17, 0xD8, 0x31, 0x4B, 0x98, 0x42, 0x3E, 0xD0, 0x0A, 0xD8, 0x38, 0xB1, 0x2F, 0x4B, 0x98, 0x42, 0x39, 0xD0, 0x41, 0xF2, 0xBB, 0x31, 0x2E, 0x48, + 0x01, 0xF0, 0x67, 0xFE, 0x00, 0x20, 0x34, 0xE0, 0x2C, 0x4B, 0x98, 0x42, 0x2F, 0xD0, 0x2C, 0x4B, 0x98, 0x42, 0xF2, 0xD1, 0x2B, 0x4B, 0x58, 0x6E, 0x2B, 0xE0, 0x2B, 0x4B, 0x98, 0x42, 0x2C, 0xD0, 0x03, 0xF5, 0x37, 0x13, 0x03, 0xF5, 0xD8, 0x63, + 0x98, 0x42, 0xE6, 0xD1, 0x25, 0x4B, 0x98, 0x6F, 0x1F, 0xE0, 0x26, 0x4B, 0x98, 0x42, 0x2F, 0xD0, 0x0C, 0xD8, 0x25, 0x4B, 0x98, 0x42, 0x23, 0xD0, 0x24, 0x4B, 0x98, 0x42, 0x24, 0xD0, 0x24, 0x4B, 0x98, 0x42, 0xD6, 0xD1, 0x1D, 0x4B, 0xD3, 0xF8, + 0x84, 0x00, 0x0E, 0xE0, 0x21, 0x4B, 0x98, 0x42, 0x22, 0xD0, 0x03, 0xF5, 0x74, 0x03, 0x03, 0xF5, 0x10, 0x53, 0x98, 0x42, 0xC9, 0xD1, 0x17, 0x4B, 0xD3, 0xF8, 0x98, 0x00, 0x01, 0xE0, 0x15, 0x4B, 0x98, 0x6D, 0x08, 0xBD, 0x13, 0x4B, 0x18, 0x6F, + 0xFB, 0xE7, 0x12, 0x4B, 0x58, 0x6F, 0xF8, 0xE7, 0x10, 0x4B, 0xD3, 0xF8, 0x80, 0x00, 0xF4, 0xE7, 0x0E, 0x4B, 0xD3, 0xF8, 0x88, 0x00, 0xF0, 0xE7, 0x0C, 0x4B, 0xD3, 0xF8, 0x8C, 0x00, 0xEC, 0xE7, 0x0A, 0x4B, 0xD3, 0xF8, 0x90, 0x00, 0xE8, 0xE7, + 0x08, 0x4B, 0xD3, 0xF8, 0x94, 0x00, 0xE4, 0xE7, 0x80, 0xBA, 0x8C, 0x01, 0x40, 0x5D, 0xC6, 0x00, 0x80, 0x84, 0x1E, 0x00, 0x40, 0x42, 0x0F, 0x00, 0x87, 0x32, 0x00, 0x08, 0x00, 0x09, 0x3D, 0x00, 0xC0, 0xCF, 0x6A, 0x00, 0x00, 0x80, 0xE0, 0x0F, + 0x00, 0x24, 0xF4, 0x00, 0x00, 0x7E, 0x56, 0x03, 0x80, 0xD5, 0x43, 0x02, 0x00, 0x6C, 0xDC, 0x02, 0x00, 0x48, 0xE8, 0x01, 0x00, 0x90, 0xD0, 0x03, 0xB0, 0xF5, 0x20, 0x7F, 0x10, 0xB5, 0x2E, 0xD0, 0x09, 0xD8, 0xB0, 0xF5, 0x00, 0x7F, 0x24, 0xD0, + 0x03, 0xD8, 0x68, 0xB1, 0xB0, 0xF5, 0xC0, 0x7F, 0x0A, 0xD0, 0x00, 0x24, 0x1B, 0xE0, 0xB0, 0xF5, 0x60, 0x7F, 0xFA, 0xD1, 0x12, 0x4B, 0xD3, 0xF8, 0x80, 0x40, 0xC4, 0xF3, 0x01, 0x14, 0x12, 0xE0, 0x0F, 0x4B, 0x1C, 0x6F, 0x23, 0x0B, 0x13, 0xF0, + 0x0E, 0x0F, 0xC4, 0xF3, 0x03, 0x34, 0x0A, 0xD0, 0x07, 0x2C, 0x08, 0xD0, 0x0F, 0x2C, 0x06, 0xD0, 0x03, 0x2C, 0x04, 0xD0, 0x4F, 0xF4, 0x22, 0x71, 0x08, 0x48, 0x01, 0xF0, 0xCE, 0xFD, 0x60, 0x1C, 0x10, 0xBD, 0x05, 0x4B, 0xD3, 0xF8, 0x90, 0x40, + 0xC4, 0xF3, 0x04, 0x64, 0xF7, 0xE7, 0x02, 0x4B, 0x1C, 0x6F, 0xC4, 0xF3, 0x80, 0x24, 0xF2, 0xE7, 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, 0x4F, 0xF4, 0x00, 0x32, 0x0E, 0x4B, 0x10, 0xB5, 0x04, 0x46, 0x9A, 0x66, 0x00, 0x20, 0xFF, 0xF7, + 0xBB, 0xFF, 0x60, 0x43, 0x41, 0xF6, 0x71, 0x32, 0x0A, 0x4C, 0x0B, 0x4B, 0xA0, 0x42, 0x94, 0xBF, 0x00, 0x20, 0x01, 0x20, 0xD9, 0x69, 0xDA, 0x63, 0x5A, 0x68, 0x22, 0xF4, 0x40, 0x12, 0x42, 0xEA, 0x00, 0x52, 0x5A, 0x60, 0xCA, 0x03, 0x44, 0xBF, + 0x00, 0x22, 0xDA, 0x63, 0x10, 0xBD, 0x00, 0xBF, 0x00, 0x90, 0x00, 0x50, 0x00, 0x5A, 0x62, 0x02, 0x00, 0x00, 0x03, 0x50, 0x38, 0xB5, 0x43, 0x09, 0x04, 0x46, 0x0D, 0x46, 0x0E, 0xD1, 0x40, 0xF2, 0x35, 0x31, 0x0D, 0x48, 0x01, 0xF0, 0x8D, 0xFD, + 0x00, 0x23, 0x04, 0xF0, 0x1F, 0x04, 0x85, 0xB1, 0x03, 0xF5, 0x80, 0x53, 0x01, 0x22, 0xA2, 0x40, 0x1A, 0x60, 0x38, 0xBD, 0x01, 0x2B, 0x04, 0xD0, 0x02, 0x2B, 0x04, 0xD0, 0x40, 0xF2, 0x43, 0x31, 0xEB, 0xE7, 0x04, 0x4B, 0xED, 0xE7, 0x04, 0x4B, + 0xEB, 0xE7, 0x03, 0xF5, 0x00, 0x53, 0xED, 0xE7, 0x87, 0x32, 0x00, 0x08, 0x64, 0x80, 0x00, 0x50, 0x68, 0x80, 0x00, 0x50, 0x00, 0x21, 0x30, 0xB5, 0xB0, 0xF5, 0x80, 0x7F, 0x85, 0xB0, 0x04, 0x46, 0xCD, 0xE9, 0x00, 0x11, 0x00, 0xF0, 0x3D, 0x81, + 0x00, 0xF2, 0xBF, 0x80, 0x3F, 0x28, 0x2D, 0xD9, 0x5C, 0x28, 0x00, 0xF2, 0xB1, 0x80, 0x4E, 0x28, 0x05, 0xD8, 0x40, 0xF2, 0xA4, 0x41, 0xAB, 0x48, 0x01, 0xF0, 0x57, 0xFD, 0xAE, 0xE0, 0x4F, 0x3C, 0x0D, 0x2C, 0xF6, 0xD8, 0x01, 0xA3, 0x53, 0xF8, + 0x24, 0xF0, 0x00, 0xBF, 0x2B, 0x10, 0x00, 0x08, 0x2B, 0x10, 0x00, 0x08, 0x2B, 0x10, 0x00, 0x08, 0xE5, 0x10, 0x00, 0x08, 0x3F, 0x10, 0x00, 0x08, 0xEF, 0x10, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0xF9, 0x10, 0x00, 0x08, + 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0xA7, 0x10, 0x00, 0x08, 0x3F, 0x28, 0xD4, 0xD8, 0x01, 0xA3, 0x53, 0xF8, 0x20, 0xF0, 0x00, 0xBF, 0x2B, 0x10, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, + 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, + 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, + 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, + 0x2B, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0x2B, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0xE5, 0x10, 0x00, 0x08, 0xE5, 0x10, 0x00, 0x08, 0xE5, 0x10, 0x00, 0x08, 0xE5, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, + 0x89, 0x10, 0x00, 0x08, 0x3F, 0x10, 0x00, 0x08, 0x25, 0x11, 0x00, 0x08, 0x2F, 0x11, 0x00, 0x08, 0x3F, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, + 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x9B, 0x0E, 0x00, 0x08, 0x63, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0xA7, 0x10, 0x00, 0x08, + 0x39, 0x11, 0x00, 0x08, 0xC5, 0x10, 0x00, 0x08, 0x80, 0x28, 0x7F, 0xF4, 0x4E, 0xAF, 0x01, 0xF0, 0xAD, 0xFD, 0x00, 0x90, 0x00, 0x98, 0x05, 0xB0, 0x30, 0xBD, 0xB0, 0xF5, 0xA0, 0x6F, 0x6E, 0xD0, 0x2C, 0xD8, 0xB0, 0xF5, 0x60, 0x7F, 0x60, 0xD0, + 0x1C, 0xD8, 0xB0, 0xF5, 0x00, 0x7F, 0x47, 0xD0, 0x06, 0xD8, 0xB0, 0xF5, 0xC0, 0x7F, 0x7F, 0xF4, 0x38, 0xAF, 0x01, 0xF0, 0xB7, 0xFD, 0xE8, 0xE7, 0xB0, 0xF5, 0x20, 0x7F, 0x46, 0xD0, 0xB0, 0xF5, 0x40, 0x7F, 0x7F, 0xF4, 0x2E, 0xAF, 0x01, 0xF0, + 0xAD, 0xFD, 0x04, 0x46, 0x4F, 0xF4, 0x20, 0x70, 0xFF, 0xF7, 0x8A, 0xFE, 0xB4, 0xFB, 0xF0, 0xF4, 0x64, 0x08, 0x40, 0xE0, 0xB0, 0xF5, 0x80, 0x6F, 0x44, 0xD0, 0xB0, 0xF5, 0x90, 0x6F, 0x7F, 0xF4, 0x1C, 0xAF, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, + 0x0D, 0xFD, 0xCB, 0xE7, 0xB0, 0xF5, 0xE0, 0x6F, 0x62, 0xD0, 0x0E, 0xD8, 0xB0, 0xF5, 0xC0, 0x6F, 0x54, 0xD0, 0xB0, 0xF5, 0xD0, 0x6F, 0x56, 0xD0, 0xB0, 0xF5, 0xB0, 0x6F, 0x7F, 0xF4, 0x09, 0xAF, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, 0x5E, 0xFD, + 0xB8, 0xE7, 0xB0, 0xF5, 0x08, 0x6F, 0x54, 0xD0, 0xB0, 0xF5, 0x40, 0x6F, 0x2C, 0xD0, 0xB0, 0xF5, 0xF0, 0x6F, 0x7F, 0xF4, 0xFA, 0xAE, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, 0xA3, 0xFC, 0xA9, 0xE7, 0x01, 0xF0, 0x54, 0xFD, 0x05, 0x46, 0x20, 0x46, + 0xFF, 0xF7, 0x52, 0xFE, 0xB5, 0xFB, 0xF0, 0xF5, 0x00, 0x95, 0x9F, 0xE7, 0x01, 0xF0, 0x6A, 0xFD, 0x04, 0x46, 0x4F, 0xF4, 0x20, 0x70, 0xFF, 0xF7, 0x47, 0xFE, 0xB4, 0xFB, 0xF0, 0xF4, 0x00, 0x94, 0x94, 0xE7, 0x01, 0xA8, 0xFF, 0xF7, 0xAE, 0xFC, + 0x01, 0x9D, 0xE8, 0xE7, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, 0x12, 0xFC, 0x8A, 0xE7, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, 0x55, 0xFC, 0x85, 0xE7, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, 0xFC, 0xFC, 0x80, 0xE7, 0x4F, 0xF0, 0xE0, 0x23, 0x02, 0x91, + 0x1B, 0x69, 0x5B, 0x07, 0x05, 0xD5, 0x01, 0xF0, 0x45, 0xFD, 0x02, 0x90, 0x02, 0x9B, 0x00, 0x93, 0x74, 0xE7, 0x03, 0xA9, 0x02, 0xA8, 0xFF, 0xF7, 0x1B, 0xFC, 0xF7, 0xE7, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, 0x16, 0xFC, 0x6A, 0xE7, 0x00, 0x21, + 0x68, 0x46, 0xFF, 0xF7, 0x35, 0xFD, 0x65, 0xE7, 0x00, 0x21, 0x68, 0x46, 0xFF, 0xF7, 0x62, 0xFD, 0x60, 0xE7, 0x68, 0x46, 0xFF, 0xF7, 0xC0, 0xFB, 0x5C, 0xE7, 0x00, 0xBF, 0x87, 0x32, 0x00, 0x08, 0x08, 0xB5, 0x80, 0x20, 0xFF, 0xF7, 0x8E, 0xFE, + 0x03, 0x4B, 0x98, 0x42, 0x9E, 0xBF, 0x4F, 0xF4, 0x80, 0x32, 0x02, 0x4B, 0x1A, 0x67, 0x08, 0xBD, 0x00, 0x5A, 0x62, 0x02, 0x00, 0xA0, 0x00, 0x50, 0x1F, 0xB5, 0x03, 0x46, 0x00, 0x20, 0xB3, 0xF5, 0x60, 0x7F, 0x01, 0x90, 0x00, 0xF0, 0xCA, 0x80, + 0x5A, 0xD8, 0x5C, 0x2B, 0x47, 0xD8, 0x51, 0x2B, 0x06, 0xD8, 0x2D, 0x2B, 0x3A, 0xD8, 0x23, 0x2B, 0x1E, 0xD8, 0x40, 0xF2, 0x89, 0x51, 0x99, 0xE0, 0x52, 0x3B, 0x0A, 0x2B, 0xF9, 0xD8, 0x01, 0xA2, 0x52, 0xF8, 0x23, 0xF0, 0xE5, 0x12, 0x00, 0x08, + 0x93, 0x11, 0x00, 0x08, 0x1D, 0x13, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0x97, 0x12, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0xF9, 0x12, 0x00, 0x08, + 0x24, 0x3B, 0x09, 0x2B, 0xDD, 0xD8, 0x01, 0xA2, 0x52, 0xF8, 0x23, 0xF0, 0xE5, 0x12, 0x00, 0x08, 0xE5, 0x12, 0x00, 0x08, 0xE5, 0x12, 0x00, 0x08, 0xE5, 0x12, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0x93, 0x11, 0x00, 0x08, 0xD5, 0x12, 0x00, 0x08, + 0x93, 0x11, 0x00, 0x08, 0x6B, 0x12, 0x00, 0x08, 0x03, 0x13, 0x00, 0x08, 0x3D, 0x2B, 0x77, 0xD0, 0x3E, 0x2B, 0xC2, 0xD1, 0x00, 0x20, 0x01, 0xA9, 0xFF, 0xF7, 0xF8, 0xFC, 0x62, 0xE0, 0x80, 0x2B, 0x42, 0xD0, 0xB3, 0xF5, 0x80, 0x7F, 0xB8, 0xD1, + 0x4F, 0xF0, 0xE0, 0x23, 0x02, 0x90, 0x1B, 0x69, 0x5B, 0x07, 0x60, 0xD5, 0x01, 0xF0, 0xB6, 0xFC, 0x0C, 0x23, 0x03, 0x93, 0x03, 0x9B, 0x3F, 0xE0, 0xB3, 0xF5, 0xD0, 0x6F, 0x61, 0xD0, 0x19, 0xD8, 0xB3, 0xF5, 0xA0, 0x6F, 0x6A, 0xD0, 0x0A, 0xD8, + 0xB3, 0xF5, 0x80, 0x6F, 0x4A, 0xD0, 0xB3, 0xF5, 0x90, 0x6F, 0x9E, 0xD1, 0x00, 0x20, 0x01, 0xA9, 0xFF, 0xF7, 0x14, 0xFC, 0x3E, 0xE0, 0xB3, 0xF5, 0xB0, 0x6F, 0x37, 0xD0, 0xB3, 0xF5, 0xC0, 0x6F, 0x93, 0xD1, 0x00, 0x20, 0x01, 0xA9, 0xFF, 0xF7, + 0x73, 0xFB, 0x33, 0xE0, 0xB3, 0xF5, 0x08, 0x6F, 0x48, 0xD0, 0x08, 0xD8, 0xB3, 0xF5, 0xF0, 0x6F, 0x3A, 0xD0, 0xB3, 0xF5, 0x00, 0x6F, 0xE5, 0xD0, 0xB3, 0xF5, 0xE0, 0x6F, 0xBD, 0xE7, 0xB3, 0xF5, 0x40, 0x6F, 0x7F, 0xF4, 0x7E, 0xAF, 0x00, 0x20, + 0x01, 0xA9, 0xFF, 0xF7, 0x2D, 0xFC, 0x1D, 0xE0, 0x21, 0x4B, 0x1B, 0x6F, 0x03, 0xF0, 0x07, 0x03, 0x01, 0x3B, 0x03, 0x2B, 0x0C, 0xD8, 0xDF, 0xE8, 0x03, 0xF0, 0x09, 0x02, 0x05, 0x07, 0x05, 0x23, 0x01, 0x93, 0x0F, 0xE0, 0x03, 0x23, 0xFB, 0xE7, + 0x07, 0x23, 0xF9, 0xE7, 0x02, 0x23, 0xF7, 0xE7, 0x40, 0xF2, 0xD6, 0x41, 0x17, 0x48, 0x01, 0xF0, 0x40, 0xFB, 0x03, 0xE0, 0x00, 0x20, 0x01, 0xA9, 0xFF, 0xF7, 0x38, 0xFC, 0x01, 0x98, 0x05, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, 0x00, 0x20, 0x01, 0xA9, + 0xFF, 0xF7, 0x12, 0xFB, 0xF6, 0xE7, 0x03, 0xA9, 0x02, 0xA8, 0xFF, 0xF7, 0x31, 0xFB, 0x9D, 0xE7, 0x00, 0x20, 0x01, 0xA9, 0xFF, 0xF7, 0x7A, 0xFB, 0xEC, 0xE7, 0x00, 0x20, 0x01, 0xA9, 0xFF, 0xF7, 0x4B, 0xFC, 0xE7, 0xE7, 0x01, 0xA9, 0xFF, 0xF7, + 0xDB, 0xFA, 0xE3, 0xE7, 0x01, 0xA9, 0xFF, 0xF7, 0x91, 0xFB, 0xDF, 0xE7, 0x00, 0x20, 0x01, 0xA9, 0xFF, 0xF7, 0x3E, 0xFB, 0xDA, 0xE7, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0x87, 0x32, 0x00, 0x08, 0x4F, 0xF4, 0x80, 0x32, 0x07, 0x4B, 0x08, 0x49, + 0x58, 0x6E, 0x03, 0xF5, 0x80, 0x53, 0x5A, 0x66, 0x0B, 0x6A, 0x23, 0xF0, 0x01, 0x03, 0x0B, 0x62, 0xC3, 0x03, 0x5C, 0xBF, 0x03, 0x4B, 0x5A, 0x66, 0x70, 0x47, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0x00, 0xC0, 0x07, 0x50, 0x00, 0xA0, 0x00, 0x50, + 0xF8, 0xB5, 0x03, 0x68, 0x04, 0x46, 0x0F, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0x8A, 0x31, 0x6C, 0x48, 0x01, 0xF0, 0xEF, 0xFA, 0x63, 0x68, 0x0F, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0x8D, 0x31, 0x68, 0x48, 0x01, 0xF0, 0xE7, 0xFA, 0xA3, 0x68, 0x0F, 0x2B, + 0x04, 0xD9, 0x4F, 0xF4, 0x39, 0x61, 0x64, 0x48, 0x01, 0xF0, 0xDF, 0xFA, 0x23, 0x7B, 0x0F, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0x93, 0x31, 0x60, 0x48, 0x01, 0xF0, 0xD7, 0xFA, 0x63, 0x7B, 0x0F, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0x96, 0x31, 0x5C, 0x48, + 0x01, 0xF0, 0xCF, 0xFA, 0xA3, 0x7B, 0x3F, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0x99, 0x31, 0x58, 0x48, 0x01, 0xF0, 0xC7, 0xFA, 0xE3, 0x7B, 0x3F, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0x9C, 0x31, 0x54, 0x48, 0x01, 0xF0, 0xBF, 0xFA, 0x23, 0x69, 0x03, 0x2B, + 0x04, 0xD9, 0x40, 0xF6, 0x9F, 0x31, 0x50, 0x48, 0x01, 0xF0, 0xB7, 0xFA, 0x63, 0x69, 0x03, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0xA2, 0x31, 0x4C, 0x48, 0x01, 0xF0, 0xAF, 0xFA, 0xE3, 0x69, 0x01, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0xA5, 0x31, 0x48, 0x48, + 0x01, 0xF0, 0xA7, 0xFA, 0x80, 0x20, 0xFF, 0xF7, 0xB3, 0xFE, 0x03, 0x28, 0x00, 0xF0, 0x87, 0x80, 0x4F, 0xF4, 0x00, 0x22, 0x43, 0x4B, 0x02, 0x21, 0x5A, 0x66, 0x45, 0xF6, 0x0E, 0x03, 0x42, 0x4A, 0xC2, 0xF8, 0x80, 0x30, 0x41, 0x4B, 0x99, 0x62, + 0x01, 0x21, 0x03, 0xF5, 0x80, 0x53, 0x99, 0x62, 0x93, 0x6D, 0xD9, 0x03, 0xFC, 0xD4, 0xD4, 0xE9, 0x00, 0x13, 0x1B, 0x05, 0x43, 0xEA, 0x01, 0x63, 0xE1, 0x7B, 0x94, 0xF8, 0x20, 0x50, 0x0B, 0x43, 0x21, 0x7B, 0xE7, 0x7E, 0x43, 0xEA, 0x01, 0x43, + 0x61, 0x7B, 0x6D, 0x01, 0x43, 0xEA, 0x01, 0x33, 0xA1, 0x7B, 0x43, 0xEA, 0x81, 0x13, 0x13, 0x61, 0x91, 0x69, 0xD4, 0xE9, 0x04, 0x03, 0x1B, 0x06, 0x43, 0xEA, 0x80, 0x63, 0x01, 0xF0, 0x00, 0x41, 0x0B, 0x43, 0xA1, 0x7E, 0x94, 0xF8, 0x23, 0x00, + 0x0B, 0x43, 0x21, 0x7E, 0x43, 0xEA, 0x01, 0x43, 0x61, 0x7E, 0x43, 0xEA, 0x01, 0x23, 0x93, 0x61, 0x13, 0x6A, 0xE6, 0x69, 0x23, 0xF0, 0x0D, 0x03, 0x94, 0xF8, 0x22, 0x10, 0x43, 0xEA, 0x87, 0x03, 0x00, 0x2E, 0x2D, 0xD1, 0x13, 0x62, 0x96, 0x6A, + 0x94, 0xF8, 0x21, 0x30, 0x45, 0xEA, 0x03, 0x13, 0x26, 0xF0, 0x33, 0x05, 0x2B, 0x43, 0x43, 0xF0, 0x01, 0x03, 0x93, 0x62, 0x1E, 0x4D, 0x1C, 0x4B, 0x9A, 0x6D, 0x35, 0xEA, 0x02, 0x02, 0xFB, 0xD1, 0x02, 0x22, 0x1A, 0x4D, 0xAA, 0x62, 0x1A, 0x65, + 0x9A, 0x6D, 0x52, 0x00, 0xFC, 0xD4, 0x1A, 0x69, 0xA5, 0x68, 0x22, 0xF4, 0x70, 0x02, 0x42, 0xEA, 0x05, 0x52, 0x1A, 0x61, 0x4F, 0xF0, 0x00, 0x42, 0x12, 0x4B, 0x9A, 0x61, 0x19, 0xB9, 0x02, 0x22, 0x03, 0xF5, 0x80, 0x53, 0x9A, 0x62, 0x78, 0xB9, + 0x01, 0x22, 0x10, 0x4B, 0x9A, 0x62, 0x0B, 0xE0, 0x33, 0x43, 0x43, 0xF0, 0x08, 0x03, 0x13, 0x62, 0x93, 0x6A, 0x23, 0xF0, 0x33, 0x03, 0x03, 0x43, 0x2B, 0x43, 0x43, 0xEA, 0x41, 0x03, 0x93, 0x62, 0x94, 0xF8, 0x24, 0x30, 0x1B, 0xB1, 0x04, 0x4B, + 0x07, 0x4A, 0xC3, 0xF8, 0x80, 0x20, 0xF8, 0xBD, 0x87, 0x32, 0x00, 0x08, 0x00, 0x90, 0x00, 0x50, 0x00, 0xC0, 0x00, 0x50, 0x00, 0xD0, 0x00, 0x50, 0x03, 0x00, 0x01, 0x40, 0x00, 0xE0, 0x00, 0x50, 0xF1, 0xA7, 0xFF, 0xFF, 0x01, 0x4B, 0x93, 0xF9, + 0x00, 0x00, 0x70, 0x47, 0xBA, 0x11, 0x00, 0x20, 0x43, 0x68, 0x10, 0xB5, 0x07, 0x2B, 0x04, 0x46, 0x04, 0xD9, 0x40, 0xF6, 0xE6, 0x51, 0x2A, 0x48, 0x01, 0xF0, 0xFB, 0xF9, 0xA3, 0x68, 0x03, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0xE8, 0x51, 0x26, 0x48, + 0x01, 0xF0, 0xF3, 0xF9, 0x23, 0x78, 0x03, 0x2B, 0x04, 0xD9, 0x40, 0xF6, 0xEA, 0x51, 0x22, 0x48, 0x01, 0xF0, 0xEB, 0xF9, 0x94, 0xF9, 0x01, 0x30, 0x00, 0x2B, 0x04, 0xDA, 0x40, 0xF6, 0xEC, 0x51, 0x1D, 0x48, 0x01, 0xF0, 0xE2, 0xF9, 0x4F, 0xF4, + 0x80, 0x01, 0x1C, 0x4A, 0x63, 0x78, 0x51, 0x66, 0x4F, 0xF4, 0xD1, 0x51, 0x02, 0x20, 0x02, 0xF5, 0xB8, 0x32, 0x51, 0x62, 0x18, 0x49, 0x4F, 0x2B, 0x48, 0x60, 0x4F, 0xF0, 0x01, 0x00, 0x28, 0xBF, 0x4F, 0x23, 0x01, 0xF5, 0x80, 0x51, 0x48, 0x60, + 0x11, 0x69, 0xC9, 0x03, 0xFC, 0xD4, 0x21, 0x78, 0x43, 0xEA, 0x01, 0x23, 0x53, 0x61, 0xD4, 0xE9, 0x01, 0x13, 0x1B, 0x01, 0x43, 0xEA, 0x01, 0x23, 0x61, 0x7B, 0x0B, 0x43, 0x21, 0x7B, 0x43, 0xEA, 0x41, 0x03, 0x93, 0x60, 0xE3, 0x7B, 0xA1, 0x7B, + 0x1B, 0x01, 0x43, 0xEA, 0x41, 0x13, 0x61, 0x7C, 0x0B, 0x43, 0x21, 0x7C, 0x43, 0xEA, 0x41, 0x03, 0x53, 0x60, 0xA3, 0x7C, 0x13, 0xB1, 0x6F, 0xF4, 0xD1, 0x53, 0x53, 0x62, 0x10, 0xBD, 0x00, 0xBF, 0x87, 0x32, 0x00, 0x08, 0x00, 0x90, 0x00, 0x50, + 0x00, 0x10, 0x02, 0x50, 0x01, 0x4B, 0x18, 0x80, 0x70, 0x47, 0x00, 0xBF, 0xD6, 0x11, 0x00, 0x20, 0x01, 0x4B, 0x18, 0x80, 0x70, 0x47, 0x00, 0xBF, 0xD4, 0x11, 0x00, 0x20, 0x4F, 0xF4, 0x00, 0x12, 0x08, 0xB5, 0x18, 0x4B, 0x5A, 0x66, 0x02, 0x23, + 0x17, 0x4A, 0x53, 0x60, 0x93, 0x68, 0x13, 0xF4, 0x80, 0x33, 0xFB, 0xD1, 0x01, 0x28, 0x22, 0xD1, 0x01, 0xF0, 0xC6, 0xFA, 0x13, 0x4B, 0x98, 0x42, 0x15, 0xD0, 0x03, 0xF5, 0x12, 0x23, 0x03, 0xF5, 0xF8, 0x63, 0x98, 0x42, 0x13, 0xD0, 0x10, 0x4B, + 0x00, 0xEB, 0x80, 0x02, 0x40, 0x0A, 0xB3, 0xFB, 0xF0, 0xF3, 0x52, 0x0A, 0x0A, 0x49, 0xCA, 0x62, 0x0B, 0x63, 0x01, 0x23, 0x4B, 0x62, 0x00, 0x22, 0x07, 0x4B, 0x5A, 0x60, 0x08, 0xBD, 0x45, 0xF6, 0x7A, 0x13, 0x08, 0x4A, 0xF2, 0xE7, 0x45, 0xF6, + 0x1A, 0x03, 0x07, 0x4A, 0xEE, 0xE7, 0x53, 0x62, 0xF1, 0xE7, 0x00, 0xBF, 0x00, 0x90, 0x00, 0x50, 0x00, 0x40, 0x02, 0x50, 0x00, 0xF0, 0x49, 0x02, 0x64, 0x66, 0x66, 0x66, 0xD8, 0xB8, 0x05, 0x00, 0xBB, 0xCF, 0x05, 0x00, 0xB0, 0xF5, 0x20, 0x7F, + 0x38, 0xB5, 0x77, 0xD0, 0x0E, 0xD8, 0xB0, 0xF5, 0x00, 0x7F, 0x61, 0xD0, 0x03, 0xD8, 0x90, 0xB3, 0xB0, 0xF5, 0xC0, 0x7F, 0x2F, 0xD0, 0x4F, 0xF4, 0x46, 0x71, 0xBD, 0xE8, 0x38, 0x40, 0x3D, 0x48, 0x01, 0xF0, 0x43, 0xB9, 0xB0, 0xF5, 0x60, 0x7F, + 0xF5, 0xD1, 0x3B, 0x4A, 0x4C, 0x1E, 0xD2, 0xF8, 0xFC, 0x50, 0x15, 0xF0, 0x80, 0x75, 0x1E, 0xBF, 0xD2, 0xF8, 0xFC, 0x30, 0x23, 0xF0, 0x80, 0x73, 0xC2, 0xF8, 0xFC, 0x30, 0x03, 0x2C, 0x04, 0xD9, 0x40, 0xF2, 0xF7, 0x21, 0x31, 0x48, 0x01, 0xF0, + 0x2C, 0xF9, 0x32, 0x4A, 0xD2, 0xF8, 0x80, 0x30, 0x23, 0xF0, 0x30, 0x03, 0x43, 0xEA, 0x04, 0x13, 0xC2, 0xF8, 0x80, 0x30, 0x35, 0xB1, 0x2C, 0x4A, 0xD2, 0xF8, 0xFC, 0x30, 0x43, 0xF0, 0x80, 0x73, 0xC2, 0xF8, 0xFC, 0x30, 0x38, 0xBD, 0x4C, 0x1E, + 0x01, 0x2C, 0x0A, 0xD9, 0x10, 0x29, 0x03, 0xD8, 0x27, 0x4B, 0xCB, 0x40, 0xDB, 0x07, 0x04, 0xD4, 0x40, 0xF2, 0xCB, 0x21, 0x21, 0x48, 0x01, 0xF0, 0x0C, 0xF9, 0x01, 0xF0, 0x7D, 0xF9, 0x01, 0xF0, 0x89, 0xF9, 0x4F, 0xF4, 0x80, 0x31, 0x21, 0x4B, + 0x1E, 0x4A, 0x19, 0x67, 0x13, 0x6F, 0x23, 0xF4, 0x70, 0x43, 0x43, 0xEA, 0x04, 0x33, 0x13, 0x67, 0x01, 0xF0, 0x20, 0xFA, 0x04, 0x46, 0xFF, 0xF7, 0xA7, 0xF8, 0xC0, 0xF1, 0x02, 0x01, 0x20, 0x46, 0x01, 0xF0, 0x6E, 0xF9, 0x00, 0xF0, 0x48, 0xF8, + 0xBD, 0xE8, 0x38, 0x40, 0xFF, 0xF7, 0xEC, 0xBC, 0x4C, 0x1E, 0x1F, 0x2C, 0x04, 0xD9, 0x4F, 0xF4, 0x43, 0x71, 0x0E, 0x48, 0x01, 0xF0, 0xE5, 0xF8, 0x0E, 0x4A, 0xD2, 0xF8, 0x90, 0x30, 0x23, 0xF0, 0xF8, 0x53, 0x43, 0xEA, 0x04, 0x63, 0xC2, 0xF8, + 0x90, 0x30, 0xBF, 0xE7, 0x4C, 0x1E, 0x01, 0x2C, 0x04, 0xD9, 0x40, 0xF2, 0x12, 0x31, 0x05, 0x48, 0x01, 0xF0, 0xD3, 0xF8, 0x05, 0x4A, 0x13, 0x6F, 0x23, 0xF4, 0x80, 0x63, 0x43, 0xEA, 0x84, 0x23, 0x13, 0x67, 0xAF, 0xE7, 0x87, 0x32, 0x00, 0x08, + 0x00, 0xED, 0x00, 0xE0, 0x00, 0x80, 0x00, 0x50, 0x10, 0x01, 0x01, 0x00, 0x00, 0x90, 0x00, 0x50, 0x08, 0xB5, 0x01, 0x21, 0x02, 0x20, 0x00, 0xF0, 0xE5, 0xF8, 0x4F, 0xF4, 0x20, 0x70, 0xFF, 0xF7, 0xBF, 0xFA, 0x05, 0x4B, 0x18, 0x70, 0x01, 0xF0, + 0x27, 0xF9, 0x01, 0xF0, 0x33, 0xF9, 0x4F, 0xF4, 0x80, 0x32, 0x02, 0x4B, 0x1A, 0x67, 0x08, 0xBD, 0xB9, 0x11, 0x00, 0x20, 0x00, 0x90, 0x00, 0x50, 0x08, 0xB5, 0x4F, 0xF4, 0xC0, 0x70, 0xFF, 0xF7, 0x35, 0xFB, 0xBD, 0xE8, 0x08, 0x40, 0x04, 0x49, + 0x88, 0x42, 0x94, 0xBF, 0x01, 0x21, 0x02, 0x21, 0x4F, 0xF4, 0x20, 0x70, 0xFF, 0xF7, 0x42, 0xBF, 0x80, 0xF0, 0xFA, 0x02, 0x38, 0xB5, 0x04, 0x46, 0x01, 0xF0, 0xB8, 0xF9, 0x05, 0x46, 0xFF, 0xF7, 0x3F, 0xF8, 0xC0, 0xF1, 0x02, 0x01, 0x28, 0x46, + 0x01, 0xF0, 0x06, 0xF9, 0x01, 0x21, 0x00, 0x20, 0x00, 0xF0, 0x04, 0xF9, 0x2C, 0xB1, 0xFF, 0xF7, 0xDB, 0xFF, 0xBD, 0xE8, 0x38, 0x40, 0xFF, 0xF7, 0x7F, 0xBC, 0x03, 0x4B, 0x4F, 0xF4, 0x20, 0x70, 0x19, 0x78, 0xFF, 0xF7, 0x23, 0xFF, 0xF4, 0xE7, + 0xB9, 0x11, 0x00, 0x20, 0x2D, 0xE9, 0xF0, 0x41, 0x05, 0x46, 0xFF, 0xF7, 0xF5, 0xF9, 0x43, 0x1E, 0x03, 0x33, 0x04, 0x46, 0x04, 0xD9, 0x40, 0xF6, 0xE2, 0x11, 0x3B, 0x48, 0x01, 0xF0, 0x69, 0xF8, 0x4F, 0xF4, 0xC0, 0x22, 0x39, 0x4B, 0x5A, 0x66, + 0x03, 0xF5, 0x98, 0x33, 0x5A, 0x68, 0x01, 0x2A, 0x04, 0xD1, 0x37, 0x49, 0x4A, 0x60, 0x5A, 0x68, 0x92, 0x07, 0xFC, 0xD4, 0x80, 0x20, 0xFF, 0xF7, 0x67, 0xFC, 0x05, 0x28, 0x07, 0xD1, 0x01, 0xF0, 0xC7, 0xF8, 0x01, 0xF0, 0xD3, 0xF8, 0x4F, 0xF4, + 0x80, 0x32, 0x2E, 0x4B, 0x1A, 0x67, 0x2F, 0x4B, 0x24, 0xF0, 0x40, 0x74, 0x9D, 0x42, 0x39, 0xD0, 0x2D, 0x4B, 0x9D, 0x42, 0x39, 0xD0, 0x01, 0xF0, 0x43, 0xF9, 0x85, 0x42, 0x06, 0x46, 0x03, 0xD9, 0x01, 0x21, 0x28, 0x46, 0x00, 0xF0, 0xBA, 0xF8, + 0x28, 0x4F, 0xFB, 0x68, 0x13, 0xF0, 0x06, 0x0F, 0xFB, 0xD1, 0xD7, 0xF8, 0x08, 0x80, 0xBC, 0x60, 0xBB, 0x68, 0x63, 0x40, 0x13, 0xF4, 0xF8, 0x1F, 0x26, 0xD1, 0x28, 0x46, 0xFE, 0xF7, 0xE4, 0xFD, 0x80, 0x20, 0xFF, 0xF7, 0x39, 0xFC, 0x05, 0x28, + 0x14, 0xD1, 0x01, 0xF0, 0x4B, 0xF9, 0xA8, 0x42, 0x04, 0x46, 0x04, 0xD9, 0x40, 0xF6, 0x3B, 0x21, 0x15, 0x48, 0x01, 0xF0, 0x1E, 0xF8, 0xFE, 0xF7, 0xCB, 0xFF, 0xC0, 0xF1, 0x02, 0x01, 0x20, 0x46, 0x01, 0xF0, 0x92, 0xF8, 0xFF, 0xF7, 0x6C, 0xFF, + 0xFF, 0xF7, 0x12, 0xFC, 0xAE, 0x42, 0x13, 0xD2, 0xBD, 0xE8, 0xF0, 0x81, 0x44, 0xF0, 0x00, 0x74, 0xC5, 0xE7, 0x44, 0xF0, 0x80, 0x74, 0xC2, 0xE7, 0x40, 0xF6, 0x2A, 0x21, 0x08, 0x48, 0x01, 0xF0, 0x04, 0xF8, 0x80, 0x20, 0xC7, 0xF8, 0x08, 0x80, + 0xFF, 0xF7, 0x0E, 0xFC, 0x05, 0x28, 0x05, 0xD0, 0xBD, 0xE8, 0xF0, 0x41, 0x01, 0x21, 0x00, 0x20, 0x00, 0xF0, 0x74, 0xB8, 0x35, 0x46, 0xCC, 0xE7, 0x87, 0x32, 0x00, 0x08, 0x00, 0x90, 0x00, 0x50, 0x00, 0xE0, 0x01, 0x50, 0x40, 0x42, 0x0F, 0x00, + 0x80, 0x84, 0x1E, 0x00, 0x00, 0x00, 0x01, 0x50, 0x02, 0x4A, 0x13, 0x6C, 0xDB, 0x07, 0xFC, 0xD4, 0x70, 0x47, 0x00, 0xBF, 0x00, 0x40, 0x09, 0x50, 0x03, 0x4A, 0x01, 0x79, 0xD3, 0x6E, 0x23, 0xF0, 0x30, 0x03, 0x0B, 0x43, 0xD3, 0x66, 0x70, 0x47, + 0x00, 0x40, 0x00, 0x50, 0xF8, 0xB5, 0x04, 0x46, 0x24, 0x4B, 0xD3, 0xF8, 0x84, 0x20, 0xD0, 0x06, 0xFB, 0xD4, 0xD3, 0xF8, 0x84, 0x30, 0xC3, 0xF3, 0x81, 0x13, 0x9C, 0x42, 0x3C, 0xD0, 0x01, 0xF0, 0xCD, 0xF8, 0x01, 0x2C, 0x05, 0x46, 0x0B, 0xD1, + 0x1D, 0x4B, 0x98, 0x42, 0x04, 0xD9, 0x4F, 0xF4, 0xF7, 0x61, 0x1C, 0x48, 0x00, 0xF0, 0xBD, 0xFF, 0x01, 0x21, 0x28, 0x46, 0x01, 0xF0, 0x34, 0xF8, 0x01, 0xF0, 0x81, 0xFB, 0x4F, 0xF0, 0x00, 0x72, 0x17, 0x4B, 0x07, 0x46, 0x5A, 0x66, 0x20, 0x46, + 0x01, 0xF0, 0x35, 0xF8, 0x4F, 0xF4, 0x80, 0x63, 0x10, 0x4E, 0x62, 0x1E, 0x93, 0x40, 0x33, 0x67, 0x73, 0x6E, 0x9A, 0x01, 0x03, 0xD4, 0xD6, 0xF8, 0x84, 0x30, 0x9B, 0x06, 0x0A, 0xD5, 0x38, 0x46, 0x01, 0xF0, 0x64, 0xFB, 0x02, 0x2C, 0x0F, 0xD1, + 0x28, 0x46, 0xBD, 0xE8, 0xF8, 0x40, 0x00, 0x21, 0x01, 0xF0, 0x12, 0xB8, 0xD6, 0xF8, 0x84, 0x30, 0x99, 0x06, 0xE9, 0xD5, 0x40, 0xF2, 0xC6, 0x71, 0x04, 0x48, 0x00, 0xF0, 0x8E, 0xFF, 0xE3, 0xE7, 0xF8, 0xBD, 0x00, 0xBF, 0x00, 0x40, 0x00, 0x50, + 0x00, 0x5A, 0x62, 0x02, 0xC8, 0x32, 0x00, 0x08, 0x00, 0x60, 0x00, 0x50, 0x10, 0xB5, 0x0C, 0x46, 0x08, 0xB9, 0x01, 0xF0, 0x83, 0xF8, 0x07, 0x4B, 0x21, 0x46, 0x1B, 0x78, 0x3B, 0xB1, 0x06, 0x4B, 0x98, 0x42, 0x04, 0xD8, 0x01, 0x20, 0xBD, 0xE8, + 0x10, 0x40, 0xFF, 0xF7, 0x9B, 0xBF, 0x02, 0x20, 0xF9, 0xE7, 0x00, 0xBF, 0xBB, 0x11, 0x00, 0x20, 0x00, 0x5A, 0x62, 0x02, 0x01, 0x23, 0x18, 0xB1, 0x03, 0x4A, 0xC2, 0xF8, 0xBC, 0x30, 0x70, 0x47, 0x4F, 0xF0, 0x50, 0x22, 0xF9, 0xE7, 0x00, 0xBF, + 0x00, 0x60, 0x00, 0x50, 0x4F, 0xF0, 0x00, 0x42, 0x38, 0xB5, 0x24, 0x4B, 0x24, 0x49, 0x5A, 0x66, 0x4A, 0xF6, 0xCD, 0x33, 0xD1, 0xF8, 0x94, 0x40, 0xC1, 0xF8, 0x90, 0x30, 0x04, 0xF0, 0x01, 0x04, 0x28, 0xBB, 0xFF, 0xF7, 0x65, 0xFF, 0x4B, 0x68, + 0xDB, 0x07, 0x16, 0xD5, 0x01, 0x22, 0x1D, 0x4B, 0x5A, 0x60, 0x1D, 0x4B, 0xCA, 0x6B, 0xD5, 0x07, 0x0D, 0xD4, 0x98, 0x42, 0x09, 0xD1, 0x07, 0x25, 0x1C, 0xB1, 0x17, 0x4B, 0x19, 0x4A, 0xC3, 0xF8, 0x90, 0x20, 0x00, 0xF0, 0xC1, 0xFF, 0x28, 0x46, + 0x38, 0xBD, 0x01, 0x30, 0xEE, 0xE7, 0x98, 0x42, 0xF1, 0xD0, 0x00, 0x25, 0xF0, 0xE7, 0x01, 0x32, 0xCB, 0x6B, 0x13, 0xF0, 0x08, 0x03, 0x05, 0xD0, 0x82, 0x42, 0xF8, 0xD1, 0xE7, 0xE7, 0x00, 0x22, 0x0D, 0x48, 0xF5, 0xE7, 0x82, 0x42, 0xE2, 0xD0, + 0x20, 0x21, 0x0A, 0x4A, 0x51, 0x63, 0x01, 0x21, 0xA2, 0xF5, 0x80, 0x52, 0x51, 0x60, 0x06, 0x49, 0x07, 0x4A, 0x48, 0x6B, 0x80, 0x06, 0x03, 0xD4, 0x93, 0x42, 0xD4, 0xD0, 0x01, 0x33, 0xF8, 0xE7, 0x93, 0x42, 0xDD, 0xE7, 0x00, 0x90, 0x00, 0x50, + 0x00, 0x40, 0x09, 0x50, 0x00, 0x60, 0x09, 0x50, 0x40, 0x42, 0x0F, 0x00, 0x32, 0x54, 0xFF, 0xFF, 0x4F, 0xF0, 0x00, 0x42, 0xF8, 0xB5, 0x1C, 0x4B, 0x05, 0x46, 0x5A, 0x66, 0x4A, 0xF6, 0xCD, 0x33, 0x1A, 0x4C, 0xD4, 0xF8, 0x94, 0x70, 0xC4, 0xF8, + 0x90, 0x30, 0xFF, 0xF7, 0x11, 0xFF, 0x86, 0x79, 0x01, 0xF0, 0xC1, 0xFA, 0x63, 0x68, 0x36, 0x02, 0x5E, 0x40, 0x06, 0xF4, 0x70, 0x66, 0x5E, 0x40, 0x66, 0x60, 0x01, 0xF0, 0xB3, 0xFA, 0x23, 0x6A, 0x2A, 0x78, 0x23, 0xF0, 0x70, 0x03, 0x43, 0xEA, + 0x02, 0x13, 0x23, 0x62, 0xAA, 0x78, 0x2B, 0x79, 0x68, 0x78, 0x43, 0xEA, 0x02, 0x23, 0xA3, 0x62, 0xEA, 0x78, 0x6B, 0x79, 0x43, 0xEA, 0x02, 0x23, 0xE3, 0x62, 0xFF, 0xF7, 0x6F, 0xFF, 0x01, 0x20, 0xFF, 0xF7, 0x78, 0xFF, 0xFB, 0x07, 0x44, 0xBF, + 0x05, 0x4B, 0xC4, 0xF8, 0x90, 0x30, 0x00, 0xF0, 0x57, 0xFF, 0x01, 0x20, 0xF8, 0xBD, 0x00, 0xBF, 0x00, 0x90, 0x00, 0x50, 0x00, 0x40, 0x09, 0x50, 0x32, 0x54, 0xFF, 0xFF, 0x02, 0x28, 0x38, 0xB5, 0x05, 0x46, 0x0C, 0x46, 0x03, 0xD9, 0x4C, 0x21, + 0x0C, 0x48, 0x00, 0xF0, 0xBE, 0xFE, 0xE3, 0x78, 0x62, 0x78, 0x21, 0x78, 0x5B, 0x01, 0x43, 0xEA, 0x82, 0x03, 0x22, 0x79, 0x0B, 0x43, 0x43, 0xEA, 0x02, 0x13, 0x0C, 0x22, 0x6A, 0x43, 0x02, 0xF1, 0xB0, 0x42, 0x13, 0x63, 0x01, 0x29, 0x02, 0xBF, + 0xA2, 0x78, 0x03, 0x4B, 0x43, 0xF8, 0x25, 0x20, 0x38, 0xBD, 0x00, 0xBF, 0x09, 0x33, 0x00, 0x08, 0xF8, 0x80, 0x03, 0x50, 0x08, 0xB5, 0x4F, 0xF0, 0xB0, 0x43, 0x5A, 0x68, 0x6A, 0xB9, 0x58, 0xB1, 0x5B, 0x68, 0x0B, 0xB1, 0x00, 0xF0, 0x21, 0xFF, + 0x01, 0x21, 0x0D, 0x4B, 0x59, 0x60, 0x00, 0xF0, 0x1C, 0xFF, 0x4F, 0xF0, 0xB0, 0x43, 0xD9, 0x60, 0x08, 0xBD, 0x5B, 0x68, 0x0B, 0xB1, 0x00, 0xF0, 0x14, 0xFF, 0x00, 0x28, 0xF0, 0xD1, 0x00, 0xF0, 0x10, 0xFF, 0x4F, 0xF0, 0xB0, 0x43, 0x02, 0x22, + 0xDA, 0x60, 0x00, 0xF0, 0x0A, 0xFF, 0x01, 0x22, 0x02, 0x4B, 0x5A, 0x60, 0xEC, 0xE7, 0x00, 0xBF, 0x00, 0x10, 0x00, 0x58, 0x00, 0x20, 0x00, 0x58, 0x4F, 0xF0, 0xB0, 0x41, 0x4B, 0x68, 0x10, 0xB5, 0x0B, 0xB1, 0x00, 0xF0, 0xFA, 0xFE, 0x01, 0x22, + 0x0B, 0x4B, 0xC4, 0x78, 0x5A, 0x60, 0x83, 0x78, 0x93, 0x40, 0x43, 0xEA, 0x84, 0x03, 0x44, 0x78, 0x23, 0x43, 0x04, 0x79, 0x43, 0xEA, 0x04, 0x13, 0x44, 0x79, 0x43, 0xEA, 0xC4, 0x03, 0x8B, 0x60, 0x04, 0x4B, 0x5A, 0x60, 0x03, 0x78, 0xC3, 0xF1, + 0x02, 0x03, 0xCB, 0x60, 0x10, 0xBD, 0x00, 0xBF, 0x00, 0x20, 0x00, 0x58, 0x00, 0x10, 0x00, 0x58, 0x70, 0xB5, 0x06, 0x46, 0x0C, 0x46, 0x15, 0x46, 0x22, 0xB9, 0x40, 0xF2, 0x8E, 0x21, 0x0C, 0x48, 0x00, 0xF0, 0x4B, 0xFE, 0x24, 0xB9, 0x4F, 0xF4, + 0x20, 0x70, 0xFF, 0xF7, 0xD7, 0xF8, 0x04, 0x46, 0x6D, 0x00, 0x01, 0x3C, 0xB4, 0xFB, 0xF5, 0xF4, 0x06, 0x4B, 0x25, 0x02, 0x13, 0xEA, 0x04, 0x23, 0x04, 0xD0, 0x40, 0xF2, 0xB3, 0x21, 0x02, 0x48, 0x00, 0xF0, 0x37, 0xFE, 0xF5, 0x61, 0x70, 0xBD, + 0x4B, 0x33, 0x00, 0x08, 0x07, 0x00, 0x80, 0xFF, 0x17, 0x4B, 0x10, 0xB5, 0x98, 0x42, 0x04, 0x46, 0x08, 0xD0, 0x03, 0xF5, 0x80, 0x43, 0x98, 0x42, 0x04, 0xD0, 0x40, 0xF2, 0x42, 0x41, 0x13, 0x48, 0x00, 0xF0, 0x23, 0xFE, 0x01, 0x22, 0x04, 0xF5, + 0x80, 0x53, 0x5A, 0x60, 0x40, 0xF6, 0xAA, 0x63, 0x41, 0xF2, 0x05, 0x02, 0x63, 0x61, 0x00, 0x23, 0x0D, 0x49, 0xA3, 0x60, 0xE3, 0x65, 0xE2, 0x60, 0x04, 0xF5, 0x00, 0x52, 0x23, 0x61, 0xE3, 0x61, 0xE3, 0x64, 0x91, 0x64, 0x06, 0x49, 0xA3, 0x65, + 0x8C, 0x42, 0x03, 0xD1, 0x23, 0x65, 0x00, 0x23, 0x63, 0x65, 0x02, 0xE0, 0x05, 0x49, 0x8C, 0x42, 0xF8, 0xD0, 0x01, 0x23, 0x53, 0x60, 0x10, 0xBD, 0x00, 0xC0, 0x05, 0x50, 0x4B, 0x33, 0x00, 0x08, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x06, 0x50, + 0x38, 0xB5, 0x2F, 0x4B, 0x04, 0x46, 0x98, 0x42, 0x0D, 0x46, 0x08, 0xD0, 0x03, 0xF5, 0x80, 0x43, 0x98, 0x42, 0x04, 0xD0, 0x40, 0xF2, 0x69, 0x31, 0x2A, 0x48, 0x00, 0xF0, 0xEA, 0xFD, 0x20, 0x46, 0xFF, 0xF7, 0xB6, 0xFF, 0x01, 0x22, 0x04, 0xF5, + 0x80, 0x53, 0x5A, 0x60, 0x2B, 0x8A, 0xA2, 0x68, 0x43, 0xF0, 0x01, 0x03, 0x13, 0x43, 0xAA, 0x7B, 0x43, 0xEA, 0x82, 0x23, 0xA3, 0x60, 0xA3, 0x68, 0x2A, 0x7D, 0x43, 0xEA, 0x42, 0x73, 0xA3, 0x60, 0xAB, 0x7C, 0x5B, 0xB1, 0x1C, 0x4A, 0xEB, 0x7C, + 0x94, 0x42, 0x2D, 0xD1, 0xA2, 0xF5, 0x10, 0x32, 0xC2, 0xF8, 0xB4, 0x31, 0xE3, 0x6D, 0x43, 0xF0, 0x80, 0x03, 0xE3, 0x65, 0x2B, 0x7B, 0x20, 0x46, 0xD5, 0xE9, 0x01, 0x12, 0x43, 0xF4, 0x80, 0x53, 0xE3, 0x60, 0xFF, 0xF7, 0x69, 0xFF, 0x6B, 0x7B, + 0x0B, 0xB1, 0x10, 0x23, 0x63, 0x61, 0x6B, 0x7D, 0x1B, 0xB1, 0xA3, 0x68, 0x43, 0xF4, 0x80, 0x33, 0xA3, 0x60, 0xAB, 0x7D, 0x1B, 0xB1, 0xA3, 0x68, 0x43, 0xF4, 0x00, 0x43, 0xA3, 0x60, 0xEB, 0x7D, 0x2A, 0x7E, 0x1B, 0x07, 0x12, 0x05, 0x03, 0xF0, + 0xE0, 0x43, 0x02, 0xF4, 0xE0, 0x02, 0x13, 0x43, 0xA3, 0x65, 0x2B, 0x78, 0x63, 0x61, 0x38, 0xBD, 0x05, 0x4A, 0x94, 0x42, 0x04, 0xBF, 0xA2, 0xF5, 0x20, 0x32, 0xC2, 0xF8, 0xD0, 0x31, 0xCD, 0xE7, 0x00, 0xC0, 0x05, 0x50, 0x4B, 0x33, 0x00, 0x08, + 0x00, 0x00, 0x06, 0x50, 0x10, 0xB5, 0x04, 0x46, 0x20, 0xB9, 0x4F, 0xF4, 0x03, 0x71, 0x0F, 0x48, 0x00, 0xF0, 0x8B, 0xFD, 0x23, 0x78, 0xBB, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x0B, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, + 0xDB, 0x07, 0x04, 0xD4, 0x40, 0xF2, 0x0D, 0x21, 0x06, 0x48, 0x00, 0xF0, 0x7A, 0xFD, 0x01, 0x22, 0x63, 0x78, 0x21, 0x78, 0x9A, 0x40, 0x30, 0x23, 0x59, 0x43, 0x04, 0x4B, 0x5A, 0x50, 0x10, 0xBD, 0x7F, 0x23, 0xEB, 0xE7, 0x8E, 0x33, 0x00, 0x08, + 0x24, 0x34, 0x00, 0x08, 0x40, 0xE0, 0x03, 0x50, 0x10, 0xB5, 0x04, 0x46, 0x20, 0xB9, 0x40, 0xF2, 0x3A, 0x21, 0x11, 0x48, 0x00, 0xF0, 0x61, 0xFD, 0x23, 0x78, 0xDB, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x0D, 0x4A, 0xD3, 0x5C, + 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x04, 0xD4, 0x40, 0xF2, 0x3B, 0x21, 0x08, 0x48, 0x00, 0xF0, 0x50, 0xFD, 0x30, 0x22, 0x23, 0x78, 0x53, 0x43, 0x03, 0xF1, 0xA0, 0x43, 0x03, 0xF5, 0x70, 0x33, 0x18, 0x6C, 0x63, 0x78, 0xD8, 0x40, 0x00, 0xF0, + 0x01, 0x00, 0x10, 0xBD, 0x7F, 0x23, 0xE7, 0xE7, 0x8E, 0x33, 0x00, 0x08, 0x24, 0x34, 0x00, 0x08, 0x10, 0xB5, 0x04, 0x46, 0x20, 0xB9, 0x40, 0xF2, 0x65, 0x21, 0x0F, 0x48, 0x00, 0xF0, 0x35, 0xFD, 0x23, 0x78, 0xBB, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, + 0x02, 0x2B, 0x05, 0xD8, 0x0B, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x04, 0xD4, 0x40, 0xF2, 0x66, 0x21, 0x06, 0x48, 0x00, 0xF0, 0x24, 0xFD, 0x01, 0x22, 0x63, 0x78, 0x21, 0x78, 0x9A, 0x40, 0x30, 0x23, 0x59, 0x43, 0x04, 0x4B, + 0x5A, 0x50, 0x10, 0xBD, 0x7F, 0x23, 0xEB, 0xE7, 0x8E, 0x33, 0x00, 0x08, 0x24, 0x34, 0x00, 0x08, 0x40, 0xF0, 0x03, 0x50, 0x03, 0x4B, 0xD3, 0xF8, 0x24, 0x24, 0xD3, 0xF8, 0x20, 0x04, 0x10, 0x40, 0x70, 0x47, 0x00, 0xBF, 0x00, 0xC0, 0x03, 0x50, + 0x2D, 0xE9, 0xF0, 0x41, 0x03, 0x78, 0x04, 0x46, 0x0D, 0x46, 0x16, 0x46, 0x0B, 0xB3, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x2A, 0x4A, 0xD3, 0x5C, 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x03, 0xD4, 0x59, 0x21, 0x27, 0x48, 0x00, 0xF0, + 0xF4, 0xFC, 0x27, 0x4B, 0xD3, 0xF8, 0x10, 0x33, 0x1B, 0xB1, 0x5A, 0x21, 0x23, 0x48, 0x00, 0xF0, 0xEC, 0xFC, 0x0F, 0x2D, 0x0B, 0xD8, 0xDF, 0xE8, 0x05, 0xF0, 0x36, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, + 0x31, 0x31, 0x7F, 0x23, 0xE1, 0xE7, 0xAE, 0x21, 0x1A, 0x48, 0x00, 0xF0, 0xDA, 0xFC, 0x4F, 0xF0, 0x00, 0x08, 0x20, 0x46, 0x06, 0xB3, 0x00, 0xF0, 0x23, 0xFE, 0x0F, 0x21, 0x67, 0x78, 0x23, 0x78, 0x07, 0x2F, 0x03, 0xEB, 0x43, 0x03, 0x88, 0xBF, + 0x08, 0x3F, 0x4F, 0xEA, 0x03, 0x13, 0x13, 0x48, 0x95, 0xBF, 0xBF, 0x00, 0xBF, 0x00, 0x04, 0x33, 0x0C, 0x33, 0x08, 0xFA, 0x07, 0xF2, 0xB9, 0x40, 0x18, 0x44, 0x00, 0xF0, 0x58, 0xFD, 0x85, 0xB9, 0x20, 0x46, 0x56, 0xB1, 0xBD, 0xE8, 0xF0, 0x41, + 0x00, 0xF0, 0x06, 0xBE, 0xA8, 0x46, 0xDC, 0xE7, 0xFF, 0xF7, 0x20, 0xFF, 0xDD, 0xE7, 0xA8, 0x46, 0xDB, 0xE7, 0xBD, 0xE8, 0xF0, 0x41, 0xFF, 0xF7, 0x19, 0xBF, 0xBD, 0xE8, 0xF0, 0x81, 0x00, 0xBF, 0x24, 0x34, 0x00, 0x08, 0xD9, 0x33, 0x00, 0x08, + 0x00, 0xC0, 0x03, 0x50, 0x30, 0xC0, 0x03, 0x50, 0x70, 0xB5, 0x0D, 0x46, 0xE8, 0xB1, 0x03, 0x68, 0x13, 0xF4, 0xE0, 0x7F, 0x03, 0xF0, 0x3F, 0x06, 0xC3, 0xF3, 0x82, 0x12, 0x10, 0xD0, 0x01, 0x2A, 0x13, 0xD1, 0x0B, 0x4C, 0x9B, 0x06, 0x03, 0xD5, + 0x91, 0x21, 0x0A, 0x48, 0x00, 0xF0, 0x8D, 0xFC, 0x45, 0xB1, 0x04, 0xF5, 0x80, 0x54, 0x01, 0x23, 0x00, 0x20, 0xB3, 0x40, 0x23, 0x60, 0x70, 0xBD, 0x05, 0x4C, 0xEF, 0xE7, 0x04, 0xF5, 0x00, 0x54, 0xF5, 0xE7, 0x0E, 0x20, 0xF7, 0xE7, 0x00, 0xBF, + 0x68, 0x80, 0x00, 0x50, 0x27, 0x34, 0x00, 0x08, 0x64, 0x80, 0x00, 0x50, 0x30, 0xB5, 0x8B, 0xB0, 0x6D, 0x46, 0x68, 0x4C, 0x0F, 0xCC, 0x0F, 0xC5, 0x4F, 0xF0, 0x7E, 0x62, 0x54, 0xF8, 0x04, 0x3B, 0x68, 0x46, 0x2B, 0x60, 0x92, 0xF8, 0x9C, 0x30, + 0x92, 0xF9, 0x9C, 0x20, 0x6D, 0x46, 0x00, 0x2A, 0xB8, 0xBF, 0x3F, 0x23, 0x8D, 0xF8, 0x01, 0x30, 0xFF, 0xF7, 0x5A, 0xFA, 0x32, 0x20, 0xFF, 0xF7, 0xB9, 0xFA, 0x0F, 0xCC, 0x0F, 0xC5, 0x0F, 0xCC, 0x0F, 0xC5, 0x94, 0xE8, 0x03, 0x00, 0x5A, 0x4B, + 0x85, 0xE8, 0x03, 0x00, 0x1C, 0x88, 0xB4, 0xF5, 0x80, 0x7F, 0x28, 0xBF, 0x8C, 0x24, 0x8D, 0xF8, 0x19, 0x40, 0xFF, 0xF7, 0x3F, 0xFA, 0x04, 0x44, 0x84, 0xF3, 0x08, 0x04, 0x53, 0x48, 0x8D, 0xF8, 0x18, 0x40, 0xFE, 0xF7, 0xFF, 0xF9, 0x68, 0x46, + 0xFF, 0xF7, 0x46, 0xF9, 0x32, 0x20, 0xFF, 0xF7, 0x9F, 0xFA, 0x4F, 0x48, 0xFF, 0xF7, 0xC2, 0xFB, 0x4E, 0x4C, 0x01, 0x21, 0x35, 0x20, 0xFE, 0xF7, 0x9D, 0xFE, 0x00, 0x20, 0xFF, 0xF7, 0x9A, 0xFA, 0xFF, 0xF7, 0x6E, 0xFB, 0x23, 0x6F, 0x00, 0x20, + 0x23, 0xF0, 0x07, 0x03, 0x43, 0xF0, 0x03, 0x03, 0x23, 0x67, 0xFF, 0xF7, 0x8F, 0xFB, 0x23, 0x6F, 0x23, 0xF4, 0x74, 0x43, 0x23, 0x67, 0x44, 0x4B, 0xD3, 0xF8, 0xFC, 0x20, 0xD2, 0x01, 0x5F, 0xD4, 0xD4, 0xF8, 0x80, 0x30, 0x23, 0xF0, 0x03, 0x03, + 0x43, 0xF0, 0x01, 0x03, 0xC4, 0xF8, 0x80, 0x30, 0xD4, 0xF8, 0x80, 0x30, 0xC4, 0xF8, 0x80, 0x30, 0x3A, 0x4B, 0xD3, 0xF8, 0x20, 0x21, 0x22, 0xF0, 0x03, 0x02, 0x42, 0xF0, 0x02, 0x02, 0xC3, 0xF8, 0x20, 0x21, 0xD3, 0xF8, 0x24, 0x21, 0x22, 0xF0, + 0x07, 0x02, 0x42, 0xF0, 0x02, 0x02, 0xC3, 0xF8, 0x24, 0x21, 0xD3, 0xF8, 0x28, 0x21, 0x22, 0xF0, 0x03, 0x02, 0x42, 0xF0, 0x02, 0x02, 0xC3, 0xF8, 0x28, 0x21, 0xD3, 0xF8, 0x80, 0x21, 0x22, 0xF0, 0x03, 0x02, 0x42, 0xF0, 0x01, 0x02, 0xC3, 0xF8, + 0x80, 0x21, 0xD3, 0xF8, 0x40, 0x21, 0x22, 0xF0, 0x03, 0x02, 0x42, 0xF0, 0x02, 0x02, 0xC3, 0xF8, 0x40, 0x21, 0xD3, 0xF8, 0x60, 0x21, 0x22, 0xF0, 0x03, 0x02, 0x42, 0xF0, 0x02, 0x02, 0xC3, 0xF8, 0x60, 0x21, 0xD3, 0xF8, 0x40, 0x22, 0x22, 0xF0, + 0x03, 0x02, 0x42, 0xF0, 0x02, 0x02, 0xC3, 0xF8, 0x40, 0x22, 0xD3, 0xF8, 0x00, 0x22, 0x22, 0xF0, 0x07, 0x02, 0x42, 0xF0, 0x02, 0x02, 0xC3, 0xF8, 0x00, 0x22, 0xD3, 0xF8, 0x84, 0x22, 0x22, 0xF0, 0x03, 0x02, 0x42, 0xF0, 0x01, 0x02, 0xC3, 0xF8, + 0x84, 0x22, 0xFF, 0xF7, 0xB5, 0xF8, 0x4F, 0xF0, 0xE0, 0x22, 0x00, 0x20, 0x13, 0x69, 0x43, 0xF0, 0x04, 0x03, 0x13, 0x61, 0x0B, 0xB0, 0x30, 0xBD, 0xD3, 0xF8, 0xFC, 0x20, 0x22, 0xF0, 0x80, 0x72, 0xC3, 0xF8, 0xFC, 0x20, 0xD4, 0xF8, 0x80, 0x20, + 0x22, 0xF0, 0x03, 0x02, 0x42, 0xF0, 0x01, 0x02, 0xC4, 0xF8, 0x80, 0x20, 0xD4, 0xF8, 0x80, 0x20, 0xC4, 0xF8, 0x80, 0x20, 0xD3, 0xF8, 0xFC, 0x20, 0x42, 0xF0, 0x80, 0x72, 0xC3, 0xF8, 0xFC, 0x20, 0x92, 0xE7, 0x00, 0xBF, 0x68, 0x34, 0x00, 0x08, + 0x00, 0x01, 0xE0, 0x0F, 0x00, 0xF0, 0x49, 0x02, 0x00, 0xB4, 0xC4, 0x04, 0x00, 0x80, 0x00, 0x50, 0x00, 0xED, 0x00, 0xE0, 0x07, 0xB5, 0x08, 0x4B, 0x18, 0x68, 0x9A, 0x88, 0x9B, 0x79, 0x00, 0x90, 0x68, 0x46, 0xAD, 0xF8, 0x04, 0x20, 0x8D, 0xF8, + 0x06, 0x30, 0xFF, 0xF7, 0x81, 0xFC, 0x00, 0x20, 0x03, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, 0x00, 0xBF, 0xA4, 0x34, 0x00, 0x08, 0x13, 0xB5, 0x00, 0x24, 0x06, 0x4A, 0x68, 0x46, 0x53, 0x6F, 0x43, 0xF0, 0x01, 0x03, 0x53, 0x67, 0x00, 0x94, 0x8D, 0xF8, + 0x04, 0x40, 0xFF, 0xF7, 0x95, 0xFB, 0x20, 0x46, 0x02, 0xB0, 0x10, 0xBD, 0x00, 0x40, 0x00, 0x50, 0x46, 0x28, 0x10, 0xB5, 0x04, 0x46, 0x08, 0xD8, 0x01, 0x23, 0x61, 0x09, 0x07, 0x4A, 0x04, 0xF0, 0x1F, 0x04, 0xA3, 0x40, 0x42, 0xF8, 0x21, 0x30, + 0x10, 0xBD, 0x4F, 0xF4, 0x95, 0x71, 0x04, 0x48, 0x00, 0xF0, 0x5F, 0xFB, 0x00, 0x2C, 0xF7, 0xDB, 0xEE, 0xE7, 0x00, 0xBF, 0x00, 0xE1, 0x00, 0xE0, 0xC4, 0x34, 0x00, 0x08, 0x45, 0x28, 0x10, 0xB5, 0x04, 0x46, 0x04, 0xD9, 0x40, 0xF2, 0x35, 0x11, + 0x06, 0x48, 0x00, 0xF0, 0x4E, 0xFB, 0x06, 0x4B, 0x62, 0x11, 0x53, 0xF8, 0x22, 0x00, 0x04, 0xF0, 0x1F, 0x04, 0xE0, 0x40, 0xC0, 0x43, 0x00, 0xF0, 0x01, 0x00, 0x10, 0xBD, 0xC4, 0x34, 0x00, 0x08, 0x00, 0xE1, 0x00, 0xE0, 0x00, 0x28, 0x08, 0xDB, + 0x01, 0x22, 0x43, 0x09, 0x03, 0x49, 0x00, 0xF0, 0x1F, 0x00, 0x82, 0x40, 0x60, 0x33, 0x41, 0xF8, 0x23, 0x20, 0x70, 0x47, 0x00, 0xE1, 0x00, 0xE0, 0x38, 0xB5, 0x00, 0xF1, 0x10, 0x03, 0x56, 0x2B, 0x04, 0x46, 0x0D, 0x46, 0x04, 0xD9, 0x4F, 0xF4, + 0xEC, 0x71, 0x0D, 0x48, 0x00, 0xF0, 0x25, 0xFB, 0x0F, 0x2D, 0x04, 0xD9, 0x40, 0xF2, 0xD9, 0x11, 0x09, 0x48, 0x00, 0xF0, 0x1E, 0xFB, 0x00, 0x2C, 0xAC, 0xBF, 0x04, 0xF1, 0x60, 0x44, 0x07, 0x4B, 0x4F, 0xEA, 0x05, 0x15, 0xED, 0xB2, 0xAB, 0xBF, + 0x04, 0xF5, 0x61, 0x44, 0x04, 0xF0, 0x0F, 0x04, 0x84, 0xF8, 0x00, 0x53, 0x1D, 0x55, 0x38, 0xBD, 0xC4, 0x34, 0x00, 0x08, 0x14, 0xED, 0x00, 0xE0, 0x10, 0xB5, 0x00, 0xF0, 0xD9, 0xFE, 0x0A, 0x4B, 0x1A, 0x78, 0x6A, 0xB9, 0x01, 0x22, 0x6F, 0xF0, + 0x04, 0x04, 0x1A, 0x70, 0x00, 0xF0, 0xCB, 0xFE, 0x20, 0x46, 0x05, 0x21, 0x01, 0x34, 0xFF, 0xF7, 0xC7, 0xFF, 0x46, 0x2C, 0xF8, 0xD1, 0x10, 0xBD, 0xBD, 0xE8, 0x10, 0x40, 0x00, 0xF0, 0xBF, 0xBE, 0xBD, 0x11, 0x00, 0x20, 0x70, 0xB5, 0x00, 0xF0, + 0xBF, 0xFE, 0x14, 0x4E, 0x05, 0x46, 0x34, 0x78, 0xFC, 0xB9, 0x13, 0x4B, 0x1C, 0x60, 0x13, 0x4B, 0x1C, 0x60, 0x13, 0x4B, 0x1C, 0x60, 0x00, 0xF0, 0x2B, 0xF8, 0x01, 0x20, 0x00, 0xF0, 0x1F, 0xFF, 0x00, 0xF0, 0x70, 0xFE, 0x0F, 0x4B, 0x02, 0x46, + 0x18, 0x60, 0x20, 0xB9, 0x28, 0x46, 0x00, 0xF0, 0xA2, 0xFE, 0x23, 0x20, 0x70, 0xBD, 0x23, 0x46, 0x40, 0xF2, 0xE7, 0x31, 0x0A, 0x48, 0x00, 0xF0, 0xFB, 0xF8, 0x0A, 0x4B, 0x18, 0x60, 0x01, 0x23, 0x33, 0x70, 0x28, 0x46, 0x00, 0xF0, 0x93, 0xFE, + 0x00, 0x20, 0xEF, 0xE7, 0xC0, 0x11, 0x00, 0x20, 0x88, 0x11, 0x00, 0x20, 0x84, 0x11, 0x00, 0x20, 0x90, 0x11, 0x00, 0x20, 0x8C, 0x11, 0x00, 0x20, 0x18, 0xFC, 0xFF, 0xFF, 0x80, 0x11, 0x00, 0x20, 0x1F, 0xB5, 0x00, 0x24, 0x1C, 0x4B, 0x18, 0x68, + 0x9A, 0x88, 0x02, 0x90, 0xD3, 0xF8, 0x06, 0x00, 0x9B, 0x7A, 0x00, 0x90, 0x19, 0x48, 0xAD, 0xF8, 0x0C, 0x20, 0x8D, 0xF8, 0x04, 0x30, 0x00, 0xF0, 0x4F, 0xFB, 0x8D, 0xF8, 0x08, 0x40, 0x00, 0xF0, 0x55, 0xFB, 0x8D, 0xF8, 0x0C, 0x00, 0x02, 0xA8, + 0xFF, 0xF7, 0x22, 0xFC, 0x69, 0x46, 0x01, 0x20, 0x8D, 0xF8, 0x00, 0x40, 0xFF, 0xF7, 0xCE, 0xFB, 0x4F, 0xF0, 0xB0, 0x42, 0x40, 0xF2, 0xFF, 0x31, 0x93, 0x69, 0x23, 0xF4, 0x7F, 0x73, 0x23, 0xF0, 0x03, 0x03, 0x93, 0x61, 0x0A, 0x4B, 0x59, 0x61, + 0x93, 0x6A, 0x13, 0xF0, 0x08, 0x03, 0xFB, 0xD1, 0x13, 0x62, 0x01, 0x20, 0xFF, 0xF7, 0xDE, 0xFB, 0x0F, 0x20, 0xFF, 0xF7, 0x3F, 0xFF, 0x0F, 0x20, 0xFF, 0xF7, 0x0A, 0xFF, 0x04, 0xB0, 0x10, 0xBD, 0x84, 0x35, 0x00, 0x08, 0xB0, 0x34, 0x00, 0x08, + 0x00, 0x20, 0x00, 0x58, 0x10, 0xB5, 0x00, 0xF0, 0x43, 0xFE, 0x4F, 0xF0, 0xB0, 0x43, 0x04, 0x46, 0x5B, 0x69, 0x5A, 0x06, 0x07, 0x4A, 0x03, 0xF0, 0x01, 0x00, 0x03, 0xF0, 0x51, 0x03, 0x48, 0xBF, 0x40, 0xF0, 0x02, 0x00, 0x53, 0x61, 0x00, 0xF0, + 0x1B, 0xFD, 0x20, 0x46, 0xBD, 0xE8, 0x10, 0x40, 0x00, 0xF0, 0x29, 0xBE, 0x00, 0x20, 0x00, 0x58, 0x10, 0xB5, 0x04, 0x46, 0x00, 0xF0, 0x7A, 0xFB, 0x4F, 0xF4, 0x7A, 0x72, 0x90, 0x42, 0xB0, 0xFB, 0xF2, 0xF1, 0x05, 0xD2, 0x36, 0x21, 0xBD, 0xE8, + 0x10, 0x40, 0x0C, 0x48, 0x00, 0xF0, 0x49, 0xBA, 0x0B, 0x4B, 0xB3, 0xFB, 0xF1, 0xF3, 0x0B, 0x49, 0x88, 0x42, 0x01, 0xD9, 0x3C, 0x21, 0xF2, 0xE7, 0x02, 0xFB, 0x04, 0xF0, 0xB0, 0xFB, 0xF3, 0xF0, 0x02, 0x28, 0x06, 0xD9, 0xBD, 0xE8, 0x10, 0x40, + 0x03, 0x23, 0xB0, 0xFB, 0xF3, 0xF0, 0xFD, 0xF7, 0x3B, 0xBE, 0x10, 0xBD, 0x8F, 0x35, 0x00, 0x08, 0x40, 0x42, 0x0F, 0x00, 0xE7, 0xCD, 0x9A, 0x3B, 0x01, 0x22, 0x01, 0x4B, 0x1A, 0x70, 0x70, 0x47, 0xC1, 0x11, 0x00, 0x20, 0x07, 0xB5, 0x00, 0x23, + 0x01, 0x22, 0x4F, 0xF4, 0xFA, 0x71, 0xCD, 0xE9, 0x00, 0x32, 0x03, 0x48, 0x03, 0x4A, 0x00, 0xF0, 0x9B, 0xFC, 0x03, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, 0x94, 0x11, 0x00, 0x20, 0xF9, 0x24, 0x00, 0x08, 0x10, 0xB5, 0x04, 0x4C, 0x23, 0x78, 0x23, 0xB1, + 0x03, 0x48, 0x00, 0xF0, 0x38, 0xFA, 0x00, 0x23, 0x23, 0x70, 0x10, 0xBD, 0xC1, 0x11, 0x00, 0x20, 0xDC, 0x35, 0x00, 0x08, 0x38, 0xB5, 0x4F, 0xF4, 0x80, 0x32, 0x01, 0x20, 0x4F, 0xF4, 0x80, 0x25, 0x10, 0x4B, 0x11, 0x49, 0x11, 0x4C, 0x9A, 0x66, + 0x48, 0x60, 0xA2, 0x66, 0x5D, 0x66, 0x03, 0xF5, 0xE0, 0x43, 0x9B, 0x68, 0x03, 0xF0, 0x7F, 0x03, 0x7F, 0x2B, 0x02, 0xD1, 0x0C, 0x48, 0xFF, 0xF7, 0x79, 0xF9, 0x65, 0x66, 0xFF, 0xF7, 0xE4, 0xFE, 0xFD, 0xF7, 0x88, 0xFE, 0x00, 0xF0, 0x9C, 0xFA, + 0xFF, 0xF7, 0x50, 0xFE, 0x00, 0xF0, 0x8E, 0xFA, 0xFF, 0xF7, 0x60, 0xFE, 0xBD, 0xE8, 0x38, 0x40, 0xFD, 0xF7, 0x70, 0xBE, 0x00, 0x90, 0x00, 0x50, 0x00, 0x60, 0x03, 0x50, 0x00, 0xA0, 0x00, 0x50, 0xC0, 0xEA, 0x21, 0x01, 0x01, 0x48, 0x00, 0xF0, + 0xFB, 0xB9, 0x00, 0xBF, 0xDC, 0x35, 0x00, 0x08, 0x53, 0xB9, 0x4A, 0xB9, 0x00, 0x29, 0x08, 0xBF, 0x00, 0x28, 0x1C, 0xBF, 0x4F, 0xF0, 0xFF, 0x31, 0x4F, 0xF0, 0xFF, 0x30, 0x00, 0xF0, 0x82, 0xB9, 0xAD, 0xF1, 0x08, 0x0C, 0x6D, 0xE9, 0x04, 0xCE, + 0x00, 0xF0, 0x06, 0xF8, 0xDD, 0xF8, 0x04, 0xE0, 0xDD, 0xE9, 0x02, 0x23, 0x04, 0xB0, 0x70, 0x47, 0x2D, 0xE9, 0xF0, 0x4F, 0x09, 0x9D, 0x0C, 0x46, 0x00, 0x2B, 0x4D, 0xD1, 0x8A, 0x42, 0x0F, 0x46, 0x84, 0x46, 0x96, 0x46, 0xB2, 0xFA, 0x82, 0xF3, + 0x60, 0xD9, 0x4B, 0xB1, 0x02, 0xFA, 0x03, 0xFE, 0xC3, 0xF1, 0x20, 0x02, 0x9F, 0x40, 0x00, 0xFA, 0x03, 0xFC, 0x20, 0xFA, 0x02, 0xF2, 0x17, 0x43, 0x4F, 0xEA, 0x1E, 0x46, 0x1F, 0xFA, 0x8E, 0xF4, 0x4F, 0xEA, 0x1C, 0x42, 0xB7, 0xFB, 0xF6, 0xF1, + 0x06, 0xFB, 0x11, 0x77, 0x01, 0xFB, 0x04, 0xF0, 0x42, 0xEA, 0x07, 0x42, 0x90, 0x42, 0x08, 0xD9, 0x1E, 0xEB, 0x02, 0x02, 0x01, 0xF1, 0xFF, 0x37, 0x02, 0xD2, 0x90, 0x42, 0x00, 0xF2, 0x31, 0x81, 0x39, 0x46, 0x12, 0x1A, 0x1F, 0xFA, 0x8C, 0xFC, + 0xB2, 0xFB, 0xF6, 0xF0, 0x06, 0xFB, 0x10, 0x22, 0x00, 0xFB, 0x04, 0xF4, 0x4C, 0xEA, 0x02, 0x4C, 0x64, 0x45, 0x08, 0xD9, 0x1E, 0xEB, 0x0C, 0x0C, 0x00, 0xF1, 0xFF, 0x32, 0x02, 0xD2, 0x64, 0x45, 0x00, 0xF2, 0x1E, 0x81, 0x10, 0x46, 0x40, 0xEA, + 0x01, 0x40, 0xAC, 0xEB, 0x04, 0x0C, 0x00, 0x21, 0x25, 0xB1, 0x2C, 0xFA, 0x03, 0xF3, 0x00, 0x22, 0xC5, 0xE9, 0x00, 0x32, 0xBD, 0xE8, 0xF0, 0x8F, 0x8B, 0x42, 0x05, 0xD9, 0x0D, 0xB1, 0xC5, 0xE9, 0x00, 0x01, 0x00, 0x21, 0x08, 0x46, 0xF5, 0xE7, + 0xB3, 0xFA, 0x83, 0xF1, 0x00, 0x29, 0x4D, 0xD1, 0xA3, 0x42, 0xC0, 0xF0, 0xF3, 0x80, 0x90, 0x42, 0x80, 0xF0, 0xF0, 0x80, 0x06, 0x46, 0x23, 0x46, 0x08, 0x46, 0x00, 0x2D, 0xE6, 0xD0, 0xC5, 0xE9, 0x00, 0x63, 0xE3, 0xE7, 0x00, 0x2B, 0x40, 0xF0, + 0xA3, 0x80, 0x8A, 0x1A, 0x4F, 0xEA, 0x1E, 0x47, 0x1F, 0xFA, 0x8E, 0xF6, 0x01, 0x21, 0xB2, 0xFB, 0xF7, 0xF4, 0x07, 0xFB, 0x14, 0x20, 0x4F, 0xEA, 0x1C, 0x42, 0x42, 0xEA, 0x00, 0x42, 0x06, 0xFB, 0x04, 0xF0, 0x90, 0x42, 0x0F, 0xD9, 0x1E, 0xEB, + 0x02, 0x02, 0x04, 0xF1, 0xFF, 0x38, 0x2C, 0xBF, 0x4F, 0xF0, 0x01, 0x09, 0x4F, 0xF0, 0x00, 0x09, 0x90, 0x42, 0x03, 0xD9, 0xB9, 0xF1, 0x00, 0x0F, 0x00, 0xF0, 0xCC, 0x80, 0x44, 0x46, 0x12, 0x1A, 0x1F, 0xFA, 0x8C, 0xFC, 0xB2, 0xFB, 0xF7, 0xF0, + 0x07, 0xFB, 0x10, 0x22, 0x00, 0xFB, 0x06, 0xF6, 0x4C, 0xEA, 0x02, 0x4C, 0x66, 0x45, 0x08, 0xD9, 0x1E, 0xEB, 0x0C, 0x0C, 0x00, 0xF1, 0xFF, 0x32, 0x02, 0xD2, 0x66, 0x45, 0x00, 0xF2, 0xB3, 0x80, 0x10, 0x46, 0xAC, 0xEB, 0x06, 0x0C, 0x40, 0xEA, + 0x04, 0x40, 0x9D, 0xE7, 0xC1, 0xF1, 0x20, 0x06, 0x8B, 0x40, 0x04, 0xFA, 0x01, 0xFE, 0x22, 0xFA, 0x06, 0xF7, 0x20, 0xFA, 0x06, 0xFC, 0xF4, 0x40, 0x8A, 0x40, 0x1F, 0x43, 0x4E, 0xEA, 0x0C, 0x03, 0x00, 0xFA, 0x01, 0xFE, 0x4F, 0xEA, 0x17, 0x48, + 0x4F, 0xEA, 0x13, 0x49, 0x1F, 0xFA, 0x87, 0xFC, 0xB4, 0xFB, 0xF8, 0xF0, 0x08, 0xFB, 0x10, 0x44, 0x49, 0xEA, 0x04, 0x44, 0x00, 0xFB, 0x0C, 0xF9, 0xA1, 0x45, 0x0E, 0xD9, 0x3C, 0x19, 0x00, 0xF1, 0xFF, 0x3A, 0x2C, 0xBF, 0x4F, 0xF0, 0x01, 0x0B, + 0x4F, 0xF0, 0x00, 0x0B, 0xA1, 0x45, 0x03, 0xD9, 0xBB, 0xF1, 0x00, 0x0F, 0x00, 0xF0, 0x8B, 0x80, 0x50, 0x46, 0xA4, 0xEB, 0x09, 0x04, 0x1F, 0xFA, 0x83, 0xF9, 0xB4, 0xFB, 0xF8, 0xF3, 0x08, 0xFB, 0x13, 0x44, 0x03, 0xFB, 0x0C, 0xFC, 0x49, 0xEA, + 0x04, 0x44, 0xA4, 0x45, 0x06, 0xD9, 0x3C, 0x19, 0x03, 0xF1, 0xFF, 0x38, 0x01, 0xD2, 0xA4, 0x45, 0x7B, 0xD8, 0x43, 0x46, 0x43, 0xEA, 0x00, 0x40, 0xA4, 0xEB, 0x0C, 0x04, 0xA0, 0xFB, 0x02, 0x98, 0x44, 0x45, 0xCC, 0x46, 0x43, 0x46, 0x02, 0xD3, + 0x06, 0xD1, 0xCE, 0x45, 0x04, 0xD2, 0x01, 0x38, 0xB9, 0xEB, 0x02, 0x0C, 0x68, 0xEB, 0x07, 0x03, 0x00, 0x2D, 0x6C, 0xD0, 0xBE, 0xEB, 0x0C, 0x02, 0x64, 0xEB, 0x03, 0x04, 0x22, 0xFA, 0x01, 0xF3, 0x04, 0xFA, 0x06, 0xF6, 0xCC, 0x40, 0x00, 0x21, + 0x1E, 0x43, 0xC5, 0xE9, 0x00, 0x64, 0x3D, 0xE7, 0x02, 0xFA, 0x03, 0xFE, 0xC3, 0xF1, 0x20, 0x01, 0x04, 0xFA, 0x03, 0xF2, 0x00, 0xFA, 0x03, 0xFC, 0xCC, 0x40, 0x4F, 0xEA, 0x1E, 0x47, 0x20, 0xFA, 0x01, 0xF1, 0x1F, 0xFA, 0x8E, 0xF6, 0xB4, 0xFB, + 0xF7, 0xF0, 0x0A, 0x43, 0x07, 0xFB, 0x10, 0x44, 0x11, 0x0C, 0x41, 0xEA, 0x04, 0x41, 0x00, 0xFB, 0x06, 0xF4, 0x8C, 0x42, 0x0E, 0xD9, 0x1E, 0xEB, 0x01, 0x01, 0x00, 0xF1, 0xFF, 0x38, 0x2C, 0xBF, 0x4F, 0xF0, 0x01, 0x09, 0x4F, 0xF0, 0x00, 0x09, + 0x8C, 0x42, 0x02, 0xD9, 0xB9, 0xF1, 0x00, 0x0F, 0x2C, 0xD0, 0x40, 0x46, 0x09, 0x1B, 0x92, 0xB2, 0xB1, 0xFB, 0xF7, 0xF4, 0x07, 0xFB, 0x14, 0x11, 0x42, 0xEA, 0x01, 0x42, 0x04, 0xFB, 0x06, 0xF1, 0x91, 0x42, 0x07, 0xD9, 0x1E, 0xEB, 0x02, 0x02, + 0x04, 0xF1, 0xFF, 0x38, 0x01, 0xD2, 0x91, 0x42, 0x1E, 0xD8, 0x44, 0x46, 0x52, 0x1A, 0x44, 0xEA, 0x00, 0x41, 0x20, 0xE7, 0x86, 0x1A, 0x64, 0xEB, 0x03, 0x03, 0x01, 0x20, 0x0D, 0xE7, 0xF4, 0x44, 0x02, 0x38, 0x4A, 0xE7, 0x02, 0x3C, 0x72, 0x44, + 0x31, 0xE7, 0x02, 0x39, 0x72, 0x44, 0xCC, 0xE6, 0xF4, 0x44, 0x02, 0x38, 0xDF, 0xE6, 0x02, 0x38, 0x3C, 0x44, 0x72, 0xE7, 0x02, 0x38, 0x71, 0x44, 0xD0, 0xE7, 0x02, 0x3B, 0x3C, 0x44, 0x81, 0xE7, 0x02, 0x3C, 0x72, 0x44, 0xDE, 0xE7, 0x29, 0x46, + 0xDC, 0xE6, 0x00, 0xBF, 0x70, 0x47, 0x00, 0xBF, 0x08, 0xB5, 0x06, 0x4B, 0x04, 0x46, 0x13, 0xB1, 0x00, 0x21, 0xAF, 0xF3, 0x00, 0x80, 0x04, 0x4B, 0x1B, 0x68, 0x03, 0xB1, 0x98, 0x47, 0x20, 0x46, 0x00, 0xF0, 0x34, 0xF8, 0x00, 0x00, 0x00, 0x00, + 0xB4, 0x11, 0x00, 0x20, 0x70, 0xB5, 0x0D, 0x4D, 0x00, 0x26, 0x0D, 0x4C, 0x64, 0x1B, 0xA4, 0x10, 0xA6, 0x42, 0x09, 0xD1, 0x0B, 0x4D, 0x00, 0x26, 0x0B, 0x4C, 0x00, 0xF0, 0x79, 0xFC, 0x64, 0x1B, 0xA4, 0x10, 0xA6, 0x42, 0x05, 0xD1, 0x70, 0xBD, + 0x55, 0xF8, 0x04, 0x3B, 0x01, 0x36, 0x98, 0x47, 0xEE, 0xE7, 0x55, 0xF8, 0x04, 0x3B, 0x01, 0x36, 0x98, 0x47, 0xF2, 0xE7, 0xDC, 0x11, 0x00, 0x20, 0xDC, 0x11, 0x00, 0x20, 0xDC, 0x11, 0x00, 0x20, 0xE0, 0x11, 0x00, 0x20, 0x0F, 0x20, 0x70, 0x47, + 0x08, 0xB5, 0x08, 0x20, 0x00, 0xF0, 0x15, 0xF8, 0xBD, 0xE8, 0x08, 0x40, 0x08, 0x20, 0x00, 0xF0, 0x1B, 0xB8, 0xFE, 0xE7, 0xFE, 0xE7, 0xFE, 0xE7, 0x00, 0x23, 0x9A, 0x42, 0x00, 0xD1, 0x70, 0x47, 0x10, 0xB5, 0x50, 0xF8, 0x23, 0x40, 0x41, 0xF8, + 0x23, 0x40, 0x01, 0x33, 0x9A, 0x42, 0xF8, 0xD1, 0x10, 0xBD, 0x4F, 0xF0, 0x60, 0x42, 0x01, 0x23, 0xD2, 0xF8, 0x00, 0x1E, 0x83, 0x40, 0x0B, 0x43, 0x00, 0x20, 0xC2, 0xF8, 0x00, 0x3E, 0x70, 0x47, 0x4F, 0xF0, 0x60, 0x41, 0x01, 0x22, 0xD1, 0xF8, + 0x00, 0x3E, 0x82, 0x40, 0x23, 0xEA, 0x02, 0x03, 0x00, 0x20, 0xC1, 0xF8, 0x00, 0x3E, 0x70, 0x47, 0xD0, 0xE9, 0x00, 0x03, 0x18, 0x47, 0x03, 0x69, 0x00, 0x68, 0x18, 0x47, 0x07, 0xB5, 0x03, 0x78, 0x8D, 0xF8, 0x04, 0x30, 0x43, 0x78, 0x8D, 0xF8, + 0x05, 0x30, 0x83, 0x78, 0x01, 0xA8, 0x23, 0xB9, 0xFD, 0xF7, 0xB0, 0xFE, 0x03, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, 0xFD, 0xF7, 0x7F, 0xFE, 0xF9, 0xE7, 0x07, 0xB5, 0x03, 0x78, 0x8D, 0xF8, 0x04, 0x30, 0x43, 0x78, 0x8D, 0xF8, 0x05, 0x30, 0x83, 0x78, + 0x01, 0xA8, 0x23, 0xB9, 0xFD, 0xF7, 0x72, 0xFE, 0x03, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, 0xFD, 0xF7, 0x99, 0xFE, 0xF9, 0xE7, 0x07, 0xB5, 0x03, 0x78, 0x8D, 0xF8, 0x04, 0x30, 0x43, 0x78, 0x01, 0xA8, 0x8D, 0xF8, 0x05, 0x30, 0xFD, 0xF7, 0xBA, 0xFE, + 0x03, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, 0x13, 0xB5, 0x04, 0x46, 0x03, 0x78, 0x0D, 0xF1, 0x03, 0x01, 0x8D, 0xF8, 0x04, 0x30, 0x43, 0x78, 0x01, 0xA8, 0x8D, 0xF8, 0x05, 0x30, 0xFD, 0xF7, 0xD8, 0xFE, 0xA3, 0x78, 0x9D, 0xF8, 0x03, 0x00, 0x0B, 0xB9, + 0x80, 0xF0, 0x01, 0x00, 0x02, 0xB0, 0x10, 0xBD, 0x08, 0xB5, 0x00, 0xF0, 0xC1, 0xF8, 0xBD, 0xE8, 0x08, 0x40, 0x00, 0x21, 0xFE, 0xF7, 0xC8, 0xB9, 0x00, 0x29, 0xCC, 0xBF, 0x01, 0x21, 0x00, 0x21, 0xFE, 0xF7, 0xC2, 0xB9, 0x02, 0x21, 0x4F, 0xF4, + 0x20, 0x70, 0xFE, 0xF7, 0x23, 0xBE, 0x70, 0x47, 0x70, 0x47, 0x4F, 0xF0, 0xB0, 0x43, 0x5A, 0x68, 0x12, 0xB1, 0x9A, 0x6A, 0x00, 0x2A, 0xFA, 0xD1, 0x70, 0x47, 0x83, 0x69, 0x5A, 0x06, 0xFC, 0xD5, 0xC1, 0x63, 0x83, 0x69, 0x9B, 0x06, 0xFC, 0xD5, + 0x40, 0x6A, 0xC0, 0xB2, 0x70, 0x47, 0x70, 0xB5, 0x05, 0x46, 0x14, 0x46, 0x0E, 0x46, 0x00, 0xF0, 0x2A, 0xFB, 0x2B, 0x68, 0x5C, 0x40, 0x34, 0x40, 0x5C, 0x40, 0x2C, 0x60, 0xBD, 0xE8, 0x70, 0x40, 0x00, 0xF0, 0x1C, 0xBB, 0x00, 0xF0, 0x06, 0xB8, + 0x01, 0x21, 0xFF, 0xF7, 0xB1, 0xBA, 0x00, 0x21, 0xFF, 0xF7, 0xAE, 0xBA, 0x00, 0x20, 0x70, 0x47, 0xFF, 0xF7, 0xD4, 0xBA, 0x00, 0x20, 0x70, 0x47, 0x08, 0xB5, 0xFF, 0xF7, 0x3F, 0xFD, 0x00, 0xF0, 0x22, 0xF8, 0x00, 0xF0, 0x2B, 0xF8, 0x00, 0xF0, + 0x30, 0xF8, 0xBD, 0xE8, 0x08, 0x40, 0x00, 0xF0, 0x2D, 0xB8, 0x08, 0xB5, 0x00, 0xF0, 0x2B, 0xF8, 0x00, 0xF0, 0x2A, 0xF8, 0x00, 0xF0, 0x29, 0xF8, 0xBD, 0xE8, 0x08, 0x40, 0x00, 0xF0, 0x26, 0xB8, 0xFF, 0xF7, 0x08, 0xBD, 0xFF, 0xF7, 0x18, 0xBD, + 0x08, 0xB5, 0xFF, 0xF7, 0xE1, 0xFF, 0xFF, 0xF7, 0xF7, 0xFF, 0xFF, 0xF7, 0xEA, 0xFF, 0xFF, 0xF7, 0xF5, 0xFF, 0xFA, 0xE7, 0x70, 0x47, 0x08, 0xB5, 0xFD, 0xF7, 0xEC, 0xFC, 0xFD, 0xF7, 0x7E, 0xFD, 0xFF, 0xF7, 0x44, 0xFD, 0xBD, 0xE8, 0x08, 0x40, + 0xFF, 0xF7, 0x0E, 0xBF, 0x08, 0xB5, 0xFF, 0xF7, 0x09, 0xFF, 0xBD, 0xE8, 0x08, 0x40, 0xFF, 0xF7, 0x21, 0xBC, 0x70, 0x47, 0x70, 0x47, 0x70, 0x47, 0x70, 0x47, 0x70, 0x47, 0x70, 0x47, 0x02, 0x44, 0x03, 0x46, 0x93, 0x42, 0x00, 0xD1, 0x70, 0x47, + 0x03, 0xF8, 0x01, 0x1B, 0xF9, 0xE7, 0x00, 0x00, 0x01, 0x4B, 0x18, 0x68, 0x70, 0x47, 0x00, 0xBF, 0xC8, 0x11, 0x00, 0x20, 0x0A, 0x4B, 0x1B, 0x6F, 0x03, 0xF0, 0x07, 0x03, 0x01, 0x3B, 0x03, 0x2B, 0x03, 0xD8, 0xDF, 0xE8, 0x03, 0xF0, 0x0A, 0x03, + 0x06, 0x08, 0xFE, 0xE7, 0x05, 0x4B, 0x18, 0x68, 0x70, 0x47, 0x05, 0x4B, 0xFB, 0xE7, 0x05, 0x48, 0x70, 0x47, 0x05, 0x48, 0x70, 0x47, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0xC8, 0x11, 0x00, 0x20, 0xD0, 0x11, 0x00, 0x20, 0x80, 0xD5, 0x43, 0x02, + 0x00, 0x2D, 0x31, 0x01, 0x08, 0xB5, 0xFF, 0xF7, 0xDD, 0xFF, 0x05, 0x4B, 0x1B, 0x6F, 0xC3, 0xF3, 0x03, 0x33, 0x01, 0x33, 0xB0, 0xFB, 0xF3, 0xF0, 0x02, 0x4B, 0x18, 0x60, 0x08, 0xBD, 0x00, 0xBF, 0x00, 0x80, 0x00, 0x50, 0xC4, 0x11, 0x00, 0x20, + 0x00, 0x48, 0x70, 0x47, 0x00, 0xB4, 0xC4, 0x04, 0x00, 0x48, 0x70, 0x47, 0x00, 0x2D, 0x31, 0x01, 0x01, 0x4B, 0x18, 0x68, 0x70, 0x47, 0x00, 0xBF, 0xD0, 0x11, 0x00, 0x20, 0x00, 0x48, 0x70, 0x47, 0x80, 0xD5, 0x43, 0x02, 0x01, 0x4B, 0x18, 0x68, + 0x70, 0x47, 0x00, 0xBF, 0xCC, 0x11, 0x00, 0x20, 0x10, 0xB5, 0x04, 0x46, 0x20, 0xB9, 0x40, 0xF2, 0xA3, 0x11, 0x0F, 0x48, 0xFF, 0xF7, 0xA9, 0xFE, 0x23, 0x78, 0xBB, 0xB1, 0x01, 0x3B, 0xDB, 0xB2, 0x02, 0x2B, 0x05, 0xD8, 0x0B, 0x4A, 0xD3, 0x5C, + 0x62, 0x78, 0xD3, 0x40, 0xDB, 0x07, 0x04, 0xD4, 0x4F, 0xF4, 0xD2, 0x71, 0x06, 0x48, 0xFF, 0xF7, 0x98, 0xFE, 0x01, 0x22, 0x63, 0x78, 0x21, 0x78, 0x9A, 0x40, 0x30, 0x23, 0x59, 0x43, 0x04, 0x4B, 0x5A, 0x50, 0x10, 0xBD, 0x7F, 0x23, 0xEB, 0xE7, + 0x8E, 0x33, 0x00, 0x08, 0x24, 0x34, 0x00, 0x08, 0x40, 0xD0, 0x03, 0x50, 0x30, 0xB5, 0x0E, 0x4C, 0x41, 0x61, 0x23, 0x68, 0x8B, 0xB9, 0x20, 0x60, 0x83, 0x60, 0x0D, 0xE0, 0x89, 0x1A, 0x9A, 0x68, 0x1D, 0x46, 0x41, 0x61, 0x6A, 0xB1, 0x13, 0x46, + 0x5A, 0x69, 0x8A, 0x42, 0xF6, 0xD9, 0x35, 0xB1, 0xA8, 0x60, 0x52, 0x1A, 0x83, 0x60, 0x5A, 0x61, 0x30, 0xBD, 0x00, 0x25, 0xF4, 0xE7, 0x20, 0x60, 0xF7, 0xE7, 0x98, 0x60, 0x82, 0x60, 0xF7, 0xE7, 0x88, 0x11, 0x00, 0x20, 0x0D, 0x49, 0x0B, 0x68, + 0xA0, 0xB1, 0x00, 0x22, 0xA3, 0xB1, 0x83, 0x42, 0x03, 0xD1, 0x83, 0x68, 0x22, 0xB9, 0x0B, 0x60, 0x03, 0xE0, 0x1A, 0x46, 0x9B, 0x68, 0xF5, 0xE7, 0x93, 0x60, 0x83, 0x68, 0x0B, 0xB9, 0x00, 0x20, 0x70, 0x47, 0x5A, 0x69, 0x41, 0x69, 0x0A, 0x44, + 0x5A, 0x61, 0xF8, 0xE7, 0x22, 0x20, 0x70, 0x47, 0x02, 0x20, 0x70, 0x47, 0x88, 0x11, 0x00, 0x20, 0x38, 0xB5, 0x00, 0xF0, 0x81, 0xFA, 0x00, 0x25, 0x08, 0x4B, 0x09, 0x4C, 0x1A, 0x68, 0x23, 0x68, 0xC3, 0x1A, 0x2A, 0xB1, 0x23, 0xB1, 0x51, 0x69, + 0x99, 0x42, 0x03, 0xD3, 0xC9, 0x1A, 0x51, 0x61, 0x20, 0x60, 0x38, 0xBD, 0x55, 0x61, 0x5B, 0x1A, 0x92, 0x68, 0xF2, 0xE7, 0x88, 0x11, 0x00, 0x20, 0x84, 0x11, 0x00, 0x20, 0x38, 0xB5, 0x13, 0x4D, 0x2B, 0x68, 0x5B, 0x69, 0x9B, 0xB1, 0x12, 0x4A, + 0x02, 0x20, 0x14, 0x68, 0x1C, 0x44, 0x00, 0xF0, 0x66, 0xFA, 0x20, 0x46, 0x00, 0xF0, 0x84, 0xF9, 0x00, 0x23, 0x0E, 0x49, 0x2A, 0x68, 0x0B, 0x70, 0x22, 0xB1, 0xD0, 0x88, 0x80, 0x07, 0x09, 0xD5, 0x01, 0x23, 0x0B, 0x70, 0x38, 0xBD, 0x02, 0x20, + 0x00, 0xF0, 0x55, 0xFA, 0x02, 0x20, 0x00, 0xF0, 0xCD, 0xF9, 0xED, 0xE7, 0x92, 0x68, 0x00, 0x2A, 0xF4, 0xD0, 0x50, 0x69, 0x03, 0x44, 0x01, 0x2B, 0xEB, 0xD9, 0xEF, 0xE7, 0x88, 0x11, 0x00, 0x20, 0x84, 0x11, 0x00, 0x20, 0xBF, 0x11, 0x00, 0x20, + 0x70, 0xB5, 0x16, 0x46, 0x9D, 0xF8, 0x14, 0x20, 0xC0, 0xE9, 0x03, 0x36, 0x02, 0x71, 0x04, 0x9A, 0xBD, 0xF8, 0x18, 0x30, 0x02, 0x60, 0x00, 0x22, 0x04, 0x46, 0x0D, 0x46, 0x82, 0x60, 0xC3, 0x80, 0xEE, 0xB9, 0x00, 0xF0, 0x29, 0xFA, 0x28, 0x44, + 0xA0, 0x61, 0x9D, 0xB1, 0x2E, 0x46, 0x00, 0xF0, 0xB2, 0xF9, 0x05, 0x46, 0xFF, 0xF7, 0x9C, 0xFF, 0x31, 0x46, 0x20, 0x46, 0xFF, 0xF7, 0x5A, 0xFF, 0x10, 0x4B, 0x1B, 0x68, 0xA3, 0x42, 0x01, 0xD1, 0xFF, 0xF7, 0xAC, 0xFF, 0x28, 0x46, 0x00, 0xF0, + 0x9D, 0xF9, 0x02, 0xE0, 0xE3, 0x68, 0x65, 0x61, 0x7B, 0xB9, 0x00, 0x20, 0x70, 0xBD, 0x00, 0xF0, 0x0B, 0xFA, 0x30, 0x44, 0xA0, 0x61, 0x00, 0x2D, 0xE0, 0xD1, 0xE3, 0x68, 0x65, 0x61, 0x00, 0x2B, 0xDD, 0xD0, 0x20, 0x46, 0x21, 0x68, 0x98, 0x47, + 0xD9, 0xE7, 0x20, 0x46, 0x21, 0x68, 0x98, 0x47, 0xEB, 0xE7, 0x00, 0xBF, 0x88, 0x11, 0x00, 0x20, 0x38, 0xB5, 0x0C, 0x46, 0x05, 0x46, 0xA8, 0xB1, 0xA1, 0xB1, 0x00, 0x23, 0x0B, 0x70, 0x00, 0xF0, 0x87, 0xF9, 0x01, 0x21, 0x08, 0x4B, 0x1B, 0x68, + 0x33, 0xB9, 0x00, 0xF0, 0x7C, 0xF9, 0x00, 0x20, 0x38, 0xBD, 0x9D, 0x42, 0x04, 0xD1, 0x21, 0x70, 0x22, 0x78, 0x00, 0x2A, 0xF9, 0xD0, 0xF4, 0xE7, 0x9B, 0x68, 0xF1, 0xE7, 0x22, 0x20, 0xF3, 0xE7, 0x88, 0x11, 0x00, 0x20, 0xF8, 0xB5, 0x0C, 0x4B, + 0x05, 0x46, 0x1B, 0x68, 0x0E, 0x46, 0x83, 0x42, 0x0F, 0xD3, 0x00, 0x24, 0x40, 0xF2, 0xE7, 0x30, 0x21, 0x46, 0x08, 0x4B, 0x4F, 0xF4, 0x7A, 0x72, 0x1F, 0x68, 0x00, 0x23, 0xE5, 0xFB, 0x07, 0x01, 0xFF, 0xF7, 0xBA, 0xFB, 0x30, 0x60, 0x20, 0x46, + 0xF8, 0xBD, 0x21, 0x20, 0xFC, 0xE7, 0x00, 0xBF, 0x80, 0x11, 0x00, 0x20, 0x8C, 0x11, 0x00, 0x20, 0xF0, 0xB5, 0x1F, 0x46, 0x00, 0x23, 0x87, 0xB0, 0x0C, 0x46, 0x16, 0x46, 0x05, 0x46, 0x8D, 0xF8, 0x13, 0x30, 0x50, 0xB3, 0x0D, 0xF1, 0x13, 0x01, + 0xFF, 0xF7, 0xB6, 0xFF, 0x9D, 0xF8, 0x13, 0x30, 0x2B, 0xBB, 0x20, 0x46, 0x05, 0xA9, 0xFF, 0xF7, 0xCD, 0xFF, 0xE0, 0xB9, 0x11, 0x4B, 0xE8, 0x83, 0x1B, 0x68, 0x28, 0x46, 0x5C, 0x43, 0x4F, 0xF4, 0x7A, 0x73, 0xB4, 0xFB, 0xF3, 0xF2, 0x03, 0xFB, + 0x12, 0x44, 0x19, 0x1B, 0x89, 0xB2, 0x99, 0x42, 0x08, 0xBF, 0x00, 0x21, 0xBD, 0xF8, 0x34, 0x30, 0xA9, 0x83, 0x05, 0x9A, 0x02, 0x93, 0x9D, 0xF8, 0x30, 0x30, 0x11, 0x46, 0xCD, 0xE9, 0x00, 0x73, 0x33, 0x46, 0xFF, 0xF7, 0x4D, 0xFF, 0x07, 0xB0, + 0xF0, 0xBD, 0x22, 0x20, 0xFB, 0xE7, 0x02, 0x20, 0xF9, 0xE7, 0x00, 0xBF, 0x8C, 0x11, 0x00, 0x20, 0xC2, 0x07, 0x2D, 0xE9, 0xF8, 0x43, 0x04, 0x46, 0x0A, 0xD5, 0x4D, 0x4A, 0x13, 0x68, 0x01, 0x33, 0x13, 0x60, 0xFF, 0xF7, 0xF1, 0xFE, 0x4B, 0x4B, + 0x1B, 0x68, 0x0B, 0xB1, 0xFF, 0xF7, 0x06, 0xFF, 0xA3, 0x07, 0x40, 0xF1, 0x8B, 0x80, 0x00, 0xF0, 0x03, 0xF9, 0x4F, 0xF0, 0x00, 0x08, 0x05, 0x46, 0x46, 0x46, 0xFF, 0xF7, 0xE1, 0xFE, 0x43, 0x4F, 0x3C, 0x68, 0x0C, 0xB1, 0x63, 0x69, 0x8B, 0xB1, + 0x00, 0x22, 0x41, 0x4B, 0x01, 0x2E, 0x1A, 0x70, 0x03, 0xD1, 0x18, 0xF0, 0x02, 0x0F, 0x18, 0xBF, 0x1E, 0x70, 0x00, 0x2C, 0x6E, 0xD0, 0xFF, 0xF7, 0xE9, 0xFE, 0x28, 0x46, 0xBD, 0xE8, 0xF8, 0x43, 0x00, 0xF0, 0xE1, 0xB8, 0x23, 0x46, 0x5A, 0x69, + 0x3A, 0xB9, 0x1A, 0x79, 0x21, 0x79, 0x91, 0x42, 0x88, 0xBF, 0x1C, 0x46, 0x9B, 0x68, 0x00, 0x2B, 0xF5, 0xD1, 0x28, 0x46, 0x00, 0xF0, 0xD3, 0xF8, 0x25, 0x69, 0xDD, 0xB1, 0x00, 0xF0, 0x3C, 0xF9, 0xA2, 0x69, 0xA0, 0xEB, 0x02, 0x08, 0x4F, 0xEA, + 0xE8, 0x73, 0xA8, 0x45, 0x73, 0xF1, 0x00, 0x03, 0x11, 0xDB, 0x23, 0x69, 0x13, 0x44, 0xA3, 0x61, 0xE3, 0x68, 0x13, 0xB1, 0x20, 0x46, 0x21, 0x68, 0x98, 0x47, 0xB4, 0xF8, 0x06, 0x80, 0x00, 0xF0, 0xBF, 0xF8, 0x01, 0x36, 0x05, 0x46, 0xFF, 0xF7, + 0x9F, 0xFE, 0xBD, 0xE7, 0xA8, 0x46, 0x00, 0xF0, 0xB7, 0xF8, 0x81, 0x46, 0x20, 0x46, 0xFF, 0xF7, 0x79, 0xFE, 0x48, 0x46, 0x00, 0xF0, 0xAB, 0xF8, 0x23, 0x69, 0x00, 0x2B, 0xE4, 0xD0, 0xB5, 0xEB, 0x08, 0x05, 0x4F, 0xEA, 0xE8, 0x73, 0x63, 0xEB, + 0x43, 0x03, 0x01, 0x2D, 0x73, 0xF1, 0x00, 0x03, 0x04, 0xDA, 0x40, 0xF2, 0x47, 0x61, 0x17, 0x48, 0xFF, 0xF7, 0xCB, 0xFC, 0xA3, 0x8B, 0x33, 0xB1, 0xE2, 0x8B, 0x13, 0x44, 0x9B, 0xB2, 0xB3, 0xF5, 0x7A, 0x7F, 0x0F, 0xD2, 0xE3, 0x83, 0x00, 0xF0, + 0x93, 0xF8, 0x80, 0x46, 0x29, 0x46, 0x20, 0x46, 0xFF, 0xF7, 0x34, 0xFE, 0xA3, 0x69, 0x22, 0x69, 0x40, 0x46, 0x13, 0x44, 0xA3, 0x61, 0x00, 0xF0, 0x82, 0xF8, 0xBD, 0xE7, 0xA3, 0xF5, 0x7A, 0x73, 0xE3, 0x83, 0xA3, 0x69, 0x01, 0x3D, 0x01, 0x3B, + 0xA3, 0x61, 0xE8, 0xE7, 0x02, 0x20, 0x00, 0xF0, 0x4D, 0xF8, 0x8E, 0xE7, 0xBD, 0xE8, 0xF8, 0x83, 0x90, 0x11, 0x00, 0x20, 0x88, 0x11, 0x00, 0x20, 0xBE, 0x11, 0x00, 0x20, 0x2F, 0x35, 0x00, 0x08, 0x10, 0xB5, 0x04, 0x46, 0x00, 0xF0, 0x63, 0xF8, + 0x4F, 0xF0, 0xB0, 0x42, 0x93, 0x6A, 0x19, 0x07, 0xFC, 0xD4, 0x13, 0x6A, 0x11, 0x6C, 0x52, 0x69, 0x52, 0x06, 0x04, 0xD4, 0xCA, 0x1A, 0x03, 0x2A, 0x01, 0xD8, 0x8B, 0x42, 0x0E, 0xD1, 0xE2, 0x1A, 0x02, 0x2A, 0x98, 0xBF, 0xDC, 0x1C, 0xB4, 0xF1, + 0xFF, 0x3F, 0x38, 0xBF, 0x01, 0x3C, 0x4F, 0xF0, 0xB0, 0x43, 0x1C, 0x64, 0x9A, 0x69, 0x42, 0xF0, 0x40, 0x02, 0x9A, 0x61, 0x00, 0xF0, 0x3E, 0xF8, 0x05, 0x4A, 0x13, 0x78, 0x3B, 0xB1, 0x4F, 0xF0, 0xB0, 0x41, 0xCB, 0x6B, 0x43, 0xF0, 0x02, 0x03, + 0xCB, 0x63, 0x00, 0x23, 0x13, 0x70, 0x10, 0xBD, 0xD8, 0x11, 0x00, 0x20, 0x07, 0xB5, 0x06, 0x4B, 0x01, 0xA9, 0x18, 0x79, 0x00, 0xF0, 0x44, 0xF8, 0xFF, 0xF7, 0x18, 0xFD, 0x01, 0x9B, 0x23, 0xFA, 0x00, 0xF0, 0x03, 0xB0, 0x5D, 0xF8, 0x04, 0xFB, + 0xB8, 0x34, 0x00, 0x08, 0x82, 0x07, 0x00, 0xF0, 0x01, 0x03, 0x0A, 0xD5, 0x01, 0x21, 0x08, 0x4A, 0x43, 0xF0, 0x40, 0x03, 0x11, 0x70, 0x4F, 0xF0, 0xB0, 0x41, 0xCA, 0x6B, 0x22, 0xF0, 0x03, 0x02, 0xCA, 0x63, 0x4F, 0xF0, 0xB0, 0x41, 0x8A, 0x69, + 0x22, 0xEA, 0x03, 0x03, 0x8B, 0x61, 0x70, 0x47, 0xD8, 0x11, 0x00, 0x20, 0x83, 0x07, 0x42, 0xBF, 0x40, 0x22, 0x01, 0x4B, 0x5A, 0x61, 0x70, 0x47, 0x00, 0x10, 0x00, 0x58, 0x10, 0xB9, 0x62, 0xB6, 0xBF, 0xF3, 0x6F, 0x8F, 0x70, 0x47, 0xEF, 0xF3, + 0x10, 0x80, 0x72, 0xB6, 0x70, 0x47, 0x80, 0xF3, 0x11, 0x88, 0xBF, 0xF3, 0x6F, 0x8F, 0x70, 0x47, 0xEF, 0xF3, 0x11, 0x80, 0x30, 0x23, 0x83, 0xF3, 0x11, 0x88, 0x70, 0x47, 0x4F, 0xF4, 0x00, 0x40, 0x70, 0x47, 0x4F, 0xF4, 0x7A, 0x70, 0x70, 0x47, + 0x09, 0xB1, 0x00, 0xF0, 0x02, 0xB8, 0x22, 0x20, 0x70, 0x47, 0x70, 0xB5, 0x06, 0x46, 0x0D, 0x46, 0xFF, 0xF7, 0xEA, 0xFF, 0x04, 0x46, 0x1C, 0x2E, 0x4B, 0xD8, 0xDF, 0xE8, 0x06, 0xF0, 0x0F, 0x18, 0x4A, 0x1D, 0x20, 0x23, 0x4A, 0x26, 0x29, 0x2C, + 0x2F, 0x4A, 0x32, 0x35, 0x4A, 0x38, 0x3B, 0x4A, 0x3E, 0x4A, 0x4A, 0x41, 0x47, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x44, 0x00, 0xFF, 0xF7, 0x06, 0xFD, 0x00, 0x26, 0x28, 0x60, 0x20, 0x46, 0xFF, 0xF7, 0xCA, 0xFF, 0x30, 0x46, 0x70, 0xBD, 0x4F, 0xF4, + 0xC0, 0x70, 0xFD, 0xF7, 0x87, 0xFE, 0xF3, 0xE7, 0x4F, 0xF4, 0x20, 0x70, 0xF9, 0xE7, 0x4F, 0xF4, 0x40, 0x70, 0xF6, 0xE7, 0x4F, 0xF4, 0x60, 0x70, 0xF3, 0xE7, 0x4F, 0xF4, 0x00, 0x70, 0xF0, 0xE7, 0x4F, 0xF4, 0x80, 0x60, 0xED, 0xE7, 0x4F, 0xF4, + 0x90, 0x60, 0xEA, 0xE7, 0x4F, 0xF4, 0x40, 0x60, 0xE7, 0xE7, 0x4F, 0xF4, 0xC0, 0x60, 0xE4, 0xE7, 0x4F, 0xF4, 0xF0, 0x60, 0xE1, 0xE7, 0x4F, 0xF4, 0xB0, 0x60, 0xDE, 0xE7, 0x4F, 0xF4, 0xD0, 0x60, 0xDB, 0xE7, 0x4F, 0xF4, 0xE0, 0x60, 0xD8, 0xE7, + 0x4F, 0xF4, 0xA0, 0x60, 0xD5, 0xE7, 0x4F, 0xF4, 0x80, 0x70, 0xD2, 0xE7, 0x4F, 0xF4, 0x08, 0x60, 0xCF, 0xE7, 0x00, 0x20, 0x21, 0x26, 0xC4, 0xE7, 0x4F, 0xF0, 0xB0, 0x43, 0x9A, 0x6A, 0x12, 0x07, 0xFC, 0xD4, 0x18, 0x6A, 0x70, 0x47, 0x82, 0x07, + 0x4F, 0xF0, 0xB0, 0x42, 0x00, 0xF0, 0x01, 0x03, 0x91, 0x69, 0x48, 0xBF, 0x43, 0xF0, 0x40, 0x03, 0x0B, 0x43, 0x93, 0x61, 0x70, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xF8, 0xB5, 0x00, 0xBF, 0xF8, 0xBC, 0x08, 0xBC, 0x9E, 0x46, 0x70, 0x47, 0xF8, 0xB5, 0x00, 0xBF, 0xF8, 0xBC, 0x08, 0xBC, 0x9E, 0x46, 0x70, 0x47, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x42, 0x0F, 0x00, 0x05, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x02, 0x03, 0x02, 0x02, 0x02, 0x04, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, + 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x64, 0x72, 0x69, 0x76, 0x65, 0x72, 0x2F, 0x67, 0x70, 0x69, 0x6F, 0x2F, 0x73, 0x72, + 0x63, 0x2F, 0x73, 0x6C, 0x5F, 0x67, 0x70, 0x69, 0x6F, 0x2E, 0x63, 0x00, 0x07, 0x7F, 0x03, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, + 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x65, 0x6D, 0x6C, 0x69, 0x62, 0x2F, 0x73, 0x72, 0x63, 0x2F, 0x65, 0x6D, 0x5F, 0x63, 0x6D, 0x75, 0x2E, 0x63, 0x00, + 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, + 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x65, 0x6D, 0x6C, 0x69, 0x62, 0x2F, 0x73, 0x72, 0x63, 0x2F, 0x65, 0x6D, 0x5F, 0x65, 0x6D, 0x75, 0x2E, 0x63, 0x00, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, + 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x65, 0x6D, 0x6C, 0x69, 0x62, 0x2F, 0x73, 0x72, 0x63, + 0x2F, 0x65, 0x6D, 0x5F, 0x72, 0x74, 0x63, 0x63, 0x2E, 0x63, 0x00, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, + 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x65, 0x6D, 0x6C, 0x69, 0x62, 0x2F, 0x73, 0x72, 0x63, 0x2F, 0x65, 0x6D, 0x5F, 0x75, 0x73, 0x61, 0x72, 0x74, 0x2E, 0x63, 0x00, 0x43, 0x3A, + 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, + 0x6F, 0x72, 0x6D, 0x2F, 0x70, 0x65, 0x72, 0x69, 0x70, 0x68, 0x65, 0x72, 0x61, 0x6C, 0x2F, 0x69, 0x6E, 0x63, 0x2F, 0x73, 0x6C, 0x5F, 0x68, 0x61, 0x6C, 0x5F, 0x67, 0x70, 0x69, 0x6F, 0x2E, 0x68, 0x00, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, + 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x70, + 0x65, 0x72, 0x69, 0x70, 0x68, 0x65, 0x72, 0x61, 0x6C, 0x2F, 0x73, 0x72, 0x63, 0x2F, 0x73, 0x6C, 0x5F, 0x68, 0x61, 0x6C, 0x5F, 0x67, 0x70, 0x69, 0x6F, 0x2E, 0x63, 0x00, 0x07, 0x7F, 0x03, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, + 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x65, 0x6D, 0x6C, + 0x69, 0x62, 0x2F, 0x69, 0x6E, 0x63, 0x2F, 0x65, 0x6D, 0x5F, 0x62, 0x75, 0x73, 0x2E, 0x68, 0x00, 0x01, 0x26, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x0B, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x8C, 0x8C, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x01, 0x01, 0x01, + 0x0C, 0x0A, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x12, 0x00, 0x00, 0x00, 0xB0, 0x34, 0x00, 0x08, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, + 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x73, 0x65, 0x72, 0x76, 0x69, 0x63, + 0x65, 0x2F, 0x69, 0x6E, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x5F, 0x6D, 0x61, 0x6E, 0x61, 0x67, 0x65, 0x72, 0x2F, 0x73, 0x72, 0x63, 0x2F, 0x73, 0x6C, 0x5F, 0x69, 0x6E, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x5F, 0x6D, 0x61, 0x6E, + 0x61, 0x67, 0x65, 0x72, 0x5F, 0x63, 0x6F, 0x72, 0x74, 0x65, 0x78, 0x6D, 0x2E, 0x63, 0x00, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, + 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x73, 0x65, 0x72, 0x76, 0x69, 0x63, 0x65, 0x2F, 0x73, 0x6C, 0x65, 0x65, 0x70, 0x74, 0x69, 0x6D, 0x65, 0x72, 0x2F, + 0x73, 0x72, 0x63, 0x2F, 0x73, 0x6C, 0x5F, 0x73, 0x6C, 0x65, 0x65, 0x70, 0x74, 0x69, 0x6D, 0x65, 0x72, 0x2E, 0x63, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x43, 0x3A, 0x2F, 0x67, 0x73, 0x64, 0x6B, 0x73, 0x2F, + 0x73, 0x69, 0x73, 0x64, 0x6B, 0x2D, 0x32, 0x30, 0x32, 0x34, 0x2E, 0x31, 0x32, 0x5F, 0x31, 0x32, 0x30, 0x2F, 0x67, 0x65, 0x63, 0x6B, 0x6F, 0x2D, 0x73, 0x64, 0x6B, 0x2F, 0x70, 0x6C, 0x61, 0x74, 0x66, 0x6F, 0x72, 0x6D, 0x2F, 0x73, 0x65, 0x72, + 0x76, 0x69, 0x63, 0x65, 0x2F, 0x75, 0x64, 0x65, 0x6C, 0x61, 0x79, 0x2F, 0x73, 0x72, 0x63, 0x2F, 0x73, 0x6C, 0x5F, 0x75, 0x64, 0x65, 0x6C, 0x61, 0x79, 0x2E, 0x63, 0x00, 0xD9, 0x11, 0x00, 0x20, 0x7D, 0x08, 0x00, 0x08, 0xAD, 0x29, 0x00, 0x08, + 0xD1, 0x29, 0x00, 0x08, 0xF5, 0x29, 0x00, 0x08, 0x0F, 0x2A, 0x00, 0x08, 0x04, 0xCC, 0xFF, 0x7F, 0x01, 0x00, 0x00, 0x00, 0x08, 0x36, 0x00, 0x08, 0xC4, 0x11, 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0xC0, 0xEA, 0x21, 0x01, 0xC0, 0xEA, 0x21, 0x01, + 0x00, 0x80, 0x00, 0x00, 0x00, 0xF0, 0x49, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x01, 0x02, 0x00, 0xD5, 0x01, 0x00, 0x08, 0xAD, 0x01, 0x00, 0x08 #elif (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) 0x3A, 0x30, 0x32, 0x30, 0x30, 0x30, 0x30, 0x30, 0x34, 0x30, 0x31, 0x30, 0x30, 0x46, 0x39, 0x0D, 0x0A, 0x3A, 0x31, 0x30, 0x38, 0x30, 0x30, 0x30, 0x30, 0x30, 0x38, 0x38, 0x31, 0x46, 0x30, 0x30, 0x32, 0x30, 0x45, 0x44, 0x39, 0x32, 0x30, 0x30, 0x30, 0x31, 0x31, 0x37, 0x41, 0x36, 0x30, 0x30, 0x30, 0x31, 0x31, 0x37, 0x41, 0x36, 0x30, 0x30, 0x30, 0x31, 0x41, 0x44, 0x0D, 0x0A, 0x3A, 0x31, 0x30, 0x38, 0x30, 0x31, 0x30, 0x30, 0x30, 0x31, 0x37, 0x41, 0x36, 0x30, 0x30, 0x30, 0x31, 0x31, diff --git a/app/common/example/se_manager_tamper/app_se_manager_tamper.c b/app/common/example/se_manager_tamper/app_se_manager_tamper.c index bbf9bc8a32..07a8cae4c6 100644 --- a/app/common/example/se_manager_tamper/app_se_manager_tamper.c +++ b/app/common/example/se_manager_tamper/app_se_manager_tamper.c @@ -219,8 +219,6 @@ void init_tamper_prs(void) PRS_ConnectConsumer(SW_RST_TAMPER_PRS_CH, prsTypeAsync, offsetof(PRS_TypeDef, CONSUMER_SETAMPER_TAMPERSRC31)); #elif defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) - sl_hal_prs_connect_channel_consumer(TAMPER_CNT_PRS_CH, SL_HAL_PRS_TYPE_ASYNC, - offsetof(PRS_TypeDef, CONSUMER_SETAMPER_TAMPERSRC28)); sl_hal_prs_connect_channel_consumer(TAMPER_INT_PRS_CH, SL_HAL_PRS_TYPE_ASYNC, offsetof(PRS_TypeDef, CONSUMER_SETAMPER_TAMPERSRC29)); sl_hal_prs_connect_channel_consumer(HW_RST_TAMPER_PRS_CH, SL_HAL_PRS_TYPE_ASYNC, diff --git a/app/common/example/segment_lcd_tempsensor/segment_lcd_tempsensor.slcp b/app/common/example/segment_lcd_tempsensor/segment_lcd_tempsensor.slcp index b8bf55d0fa..3e0620ddb9 100644 --- a/app/common/example/segment_lcd_tempsensor/segment_lcd_tempsensor.slcp +++ b/app/common/example/segment_lcd_tempsensor/segment_lcd_tempsensor.slcp @@ -35,7 +35,8 @@ readme: ui_hints: highlight: readme.md tag: - - hardware:component:segment_lcd_driver:cl010-1087-04 + - hardware:component:segment_lcd_driver:cl010-1087-04 + - hardware:component:sensor:si7021 configuration: - name: SL_BOARD_ENABLE_VCOM value: 1 diff --git a/app/common/platform_production_demos.xml b/app/common/platform_production_demos.xml index 9e06da65ff..cbd21b1649 100644 --- a/app/common/platform_production_demos.xml +++ b/app/common/platform_production_demos.xml @@ -6,7 +6,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -28,7 +28,7 @@ - + @@ -39,7 +39,29 @@ - + + + + + + + This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + + + + + This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + @@ -50,7 +72,7 @@ - + @@ -61,7 +83,7 @@ - + @@ -72,7 +94,7 @@ - + @@ -83,7 +105,7 @@ - + @@ -94,7 +116,7 @@ - + @@ -105,7 +127,7 @@ - + @@ -116,7 +138,7 @@ - + @@ -127,7 +149,7 @@ - + @@ -138,7 +160,7 @@ - + @@ -149,7 +171,7 @@ - + @@ -160,7 +182,7 @@ - + @@ -171,7 +193,7 @@ - + @@ -182,7 +204,7 @@ - + @@ -193,7 +215,7 @@ - + @@ -204,7 +226,7 @@ - + @@ -215,7 +237,7 @@ - + @@ -226,7 +248,7 @@ - + @@ -237,7 +259,7 @@ - + @@ -248,7 +270,7 @@ - + @@ -259,7 +281,7 @@ - + @@ -270,7 +292,7 @@ - + @@ -281,7 +303,7 @@ - + @@ -292,7 +314,7 @@ - + @@ -303,7 +325,7 @@ - + @@ -314,7 +336,7 @@ - + @@ -325,7 +347,7 @@ - + @@ -336,7 +358,7 @@ - + @@ -347,7 +369,7 @@ - + @@ -358,7 +380,7 @@ - + @@ -369,7 +391,7 @@ - + @@ -380,7 +402,7 @@ - + @@ -391,7 +413,7 @@ - + @@ -402,7 +424,7 @@ - + @@ -413,7 +435,7 @@ - + @@ -424,7 +446,7 @@ - + @@ -435,7 +457,7 @@ - + @@ -446,7 +468,7 @@ - + @@ -457,7 +479,7 @@ - + @@ -468,7 +490,7 @@ - + @@ -479,7 +501,7 @@ - + @@ -490,7 +512,7 @@ - + @@ -501,7 +523,7 @@ - + @@ -512,7 +534,7 @@ - + @@ -523,7 +545,7 @@ - + @@ -534,7 +556,7 @@ - + @@ -545,7 +567,7 @@ - + @@ -556,7 +578,7 @@ - + @@ -567,7 +589,7 @@ - + @@ -578,7 +600,7 @@ - + @@ -589,7 +611,7 @@ - + @@ -600,7 +622,7 @@ - + @@ -611,7 +633,7 @@ - + @@ -622,7 +644,7 @@ - + @@ -633,7 +655,7 @@ - + @@ -644,7 +666,7 @@ - + @@ -655,7 +677,7 @@ - + @@ -666,7 +688,7 @@ - + @@ -677,7 +699,7 @@ - + @@ -688,7 +710,7 @@ - + @@ -697,9 +719,9 @@ This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). - + - + @@ -708,9 +730,9 @@ This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). - + - + @@ -721,7 +743,7 @@ - + @@ -732,7 +754,7 @@ - + @@ -743,7 +765,7 @@ - + @@ -754,7 +776,7 @@ - + @@ -765,7 +787,7 @@ - + @@ -776,7 +798,7 @@ - + @@ -787,7 +809,7 @@ - + @@ -798,7 +820,18 @@ - + + + + + + + This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + @@ -809,7 +842,7 @@ - + @@ -820,7 +853,7 @@ - + @@ -831,7 +864,7 @@ - + @@ -842,7 +875,7 @@ - + diff --git a/app/common/platform_production_templates.xml b/app/common/platform_production_templates.xml index 081bb1d4ac..20de3e0821 100644 --- a/app/common/platform_production_templates.xml +++ b/app/common/platform_production_templates.xml @@ -6,7 +6,7 @@ - + @@ -22,7 +22,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -53,7 +53,7 @@ - + @@ -68,7 +68,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -98,7 +98,7 @@ - + @@ -113,7 +113,7 @@ - + @@ -128,7 +128,7 @@ - + @@ -173,7 +173,7 @@ - + @@ -188,7 +188,7 @@ - + @@ -203,7 +203,7 @@ - + @@ -218,7 +218,7 @@ - + @@ -248,7 +248,7 @@ - + @@ -263,7 +263,7 @@ - + @@ -278,7 +278,7 @@ - + @@ -293,7 +293,7 @@ - + @@ -308,7 +308,7 @@ - + @@ -323,7 +323,7 @@ - + @@ -338,7 +338,7 @@ - + @@ -353,7 +353,7 @@ - + @@ -368,7 +368,7 @@ - + @@ -383,7 +383,7 @@ - + @@ -398,7 +398,7 @@ - + @@ -413,7 +413,7 @@ - + @@ -443,7 +443,7 @@ - + @@ -458,7 +458,7 @@ - + @@ -473,7 +473,7 @@ - + @@ -488,7 +488,7 @@ - + @@ -503,7 +503,7 @@ - + @@ -518,7 +518,7 @@ - + @@ -533,7 +533,7 @@ - + @@ -548,7 +548,7 @@ - + @@ -563,7 +563,7 @@ - + @@ -578,7 +578,7 @@ - + @@ -593,7 +593,7 @@ - + @@ -608,7 +608,7 @@ - + @@ -623,7 +623,7 @@ - + @@ -638,7 +638,7 @@ - + @@ -653,7 +653,7 @@ - + @@ -668,7 +668,7 @@ - + @@ -683,7 +683,7 @@ - + @@ -698,7 +698,7 @@ - + @@ -713,7 +713,7 @@ - + @@ -728,7 +728,7 @@ - + @@ -743,7 +743,7 @@ - + @@ -758,7 +758,7 @@ - + @@ -773,7 +773,7 @@ - + @@ -788,7 +788,7 @@ - + @@ -803,7 +803,7 @@ - + @@ -818,7 +818,7 @@ - + @@ -848,7 +848,7 @@ - + @@ -863,7 +863,7 @@ - + @@ -878,7 +878,7 @@ - + @@ -893,7 +893,7 @@ - + @@ -908,7 +908,7 @@ - + @@ -923,7 +923,7 @@ - + @@ -938,7 +938,7 @@ - + @@ -953,7 +953,7 @@ - + @@ -983,8 +983,8 @@ - - + + @@ -1013,8 +1013,8 @@ - - + + @@ -1028,7 +1028,7 @@ - + @@ -1043,7 +1043,7 @@ - + @@ -1058,7 +1058,7 @@ - + @@ -1073,7 +1073,7 @@ - + @@ -1088,8 +1088,8 @@ - - + + @@ -1103,8 +1103,8 @@ - - + + @@ -1118,8 +1118,8 @@ - - + + @@ -1133,8 +1133,8 @@ - - + + @@ -1148,8 +1148,8 @@ - - + + @@ -1163,8 +1163,8 @@ - - + + @@ -1178,8 +1178,8 @@ - - + + @@ -1193,8 +1193,8 @@ - - + + @@ -1208,8 +1208,8 @@ - - + + diff --git a/app/connect/connect_production_templates.xml b/app/connect/connect_production_templates.xml index 505a4157b7..57ce038e7d 100755 --- a/app/connect/connect_production_templates.xml +++ b/app/connect/connect_production_templates.xml @@ -6,7 +6,7 @@ - + @@ -21,7 +21,7 @@ - + @@ -36,7 +36,7 @@ - + @@ -51,7 +51,7 @@ - + @@ -66,7 +66,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -96,7 +96,7 @@ - + @@ -111,7 +111,7 @@ - + @@ -126,7 +126,7 @@ - + @@ -141,7 +141,7 @@ - + diff --git a/app/connect/documentation/release-highlights.txt b/app/connect/documentation/release-highlights.txt index 12892c399e..728b75e61c 100644 --- a/app/connect/documentation/release-highlights.txt +++ b/app/connect/documentation/release-highlights.txt @@ -1,4 +1,4 @@ -Connect SDK 4.0.0.0 +Connect SDK 4.0.1.0 - Connect Apps and Stack - - PSA Crypto hardware acceleration for payload encryption enabled in Connect Stack on Series-2 parts - - Connect stack and Connect SDK enabled on BRD4276A radio board with EFR32FG25 and SKY66122-11 frontend module for high TX power applications + - Underlying platform changes only. + \ No newline at end of file diff --git a/app/connect/esf.properties b/app/connect/esf.properties index e5223f284c..5dbb22496d 100644 --- a/app/connect/esf.properties +++ b/app/connect/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.connect label=Connect SDK description=Connect Software Development Kit -version=4.0.0.0 -prop.subLabel=Connect\\ 4.0.0.0 +version=4.0.1.0 +prop.subLabel=Connect\\ 4.0.1.0 # General properties are prepended with "prop." prop.file.templatesFile=connect_production_templates.xml connect_demos_only_templates.xml connect_internal_templates.xml connect_evaluation_templates.xml diff --git a/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.c b/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.c index 28c43dbc0f..a2be8131ea 100644 --- a/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.c +++ b/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.c @@ -784,6 +784,73 @@ uint8_t *sl_rail_sdk_802154_packet_unpack_sidewalk_data_frame(const RAIL_RxPacke return tmp; } +int16_t sl_rail_sdk_802154_packet_pack_longrange_data_frame(uint16_t payload_size, + const uint8_t *payload, + uint16_t *frame_size, + uint8_t *frame_buffer) +{ + uint16_t frameLength = 0; + uint8_t fcsSizeByte = 2; + uint32_t phr = 0; + uint8_t phr_size = 1; + + // Checking input parameters + if ((payload_size == 0) + || (payload == NULL) + || (frame_size == NULL) + || (frame_buffer == NULL) + || (payload_size > 127)) { +#if defined(SL_CATALOG_APP_LOG_PRESENT) + app_log_warning("sl_rail_sdk_802154_packet_pack_longrange_data_frame ERR: parameter\r\n"); +#endif + return SL_RAIL_SDK_802154_PACKET_ERROR; + } + + *frame_size = payload_size + phr_size; + frameLength = (*frame_size - phr_size + fcsSizeByte) & 0x7F; + phr = frameLength & 0x7F; + + *frame_size = payload_size + phr_size; + + // Write the phr in the payload + for (uint8_t index = 0; index < phr_size; index++) { + frame_buffer[index] = (uint8_t)((phr & (0xFF << index * 8)) >> index * 8); + } + + for (uint8_t index = phr_size; index < *frame_size; index++) { + frame_buffer[index] = payload[index - phr_size]; + } + + // return SL_RAIL_SDK_802154_PACKET_OK if the frame is ready + return SL_RAIL_SDK_802154_PACKET_OK; +} + +uint8_t *sl_rail_sdk_802154_packet_unpack_longrange_data_frame(const RAIL_RxPacketInfo_t *packet_information, + uint16_t *payload_size, + uint8_t *frame_buffer) +{ + uint32_t phr = 0U; + uint8_t *tmp = frame_buffer; + uint8_t phr_size = 1U; + uint8_t fcsSizeByte = 2U; + + if ((packet_information == NULL) || (frame_buffer == NULL) || (payload_size == NULL)) { +#if defined(SL_CATALOG_APP_LOG_PRESENT) + app_log_warning("sl_rail_sdk_802154_packet_unpack_longrange_data_frame ERR: parameter\r\n"); +#endif + return NULL; + } + + for (uint8_t index = 0; index < phr_size; index++) { + phr |= frame_buffer[index] << (index * 8); + } + + *payload_size = (phr & 0x7F) - fcsSizeByte; + tmp += phr_size; + + return tmp; +} + // ----------------------------------------------------------------------------- // Static Function Definitions // ----------------------------------------------------------------------------- diff --git a/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.h b/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.h index 966d6a7f31..ec9b38119c 100644 --- a/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.h +++ b/app/rail/component/sl_rail_sdk_packet_asm/sl_rail_sdk_packet_asm.h @@ -575,6 +575,36 @@ uint8_t *sl_rail_sdk_802154_packet_unpack_sidewalk_data_frame(const RAIL_RxPacke uint16_t *payload_size, uint8_t *frame_buffer); +/**************************************************************************//** + * This function packs the IEEE 802.15.4 Long Range with 1byte PHR frame. + * + * @param[in] payload_size payload size + * @param[in] *payload payload + * @param[out] *frame_size frame_size that is calculated + * @param[out] *frame_buffer buffer of packed frame + * + * @retval SL_RAIL_SDK_802154_PACKET_OK if the process has been successful. + * @retval SL_RAIL_SDK_802154_PACKET_ERROR if the process has been failed. + *****************************************************************************/ +int16_t sl_rail_sdk_802154_packet_pack_longrange_data_frame(uint16_t payload_size, + const uint8_t *payload, + uint16_t *frame_size, + uint8_t *frame_buffer); + +/**************************************************************************//** + * This function unpacks the received packet to get IEEE 802.15.4 Long Range with 1byte PHR frame. + * + * @param[in] *packet_information packet information + * @param[out] *payload_size payload size + * @param[in] *frame_buffer buffer of packed frame + * + * @return pointer of the payload + * @return NULL on error + *****************************************************************************/ +uint8_t *sl_rail_sdk_802154_packet_unpack_longrange_data_frame(const RAIL_RxPacketInfo_t *packet_information, + uint16_t *payload_size, + uint8_t *frame_buffer); + /**************************************************************************//** * Get Payload pointer * diff --git a/app/rail/component/sl_rail_sdk_packet_assistant/sl_rail_sdk_packet_assistant.c b/app/rail/component/sl_rail_sdk_packet_assistant/sl_rail_sdk_packet_assistant.c index 76c8fcd591..27efac5ee0 100644 --- a/app/rail/component/sl_rail_sdk_packet_assistant/sl_rail_sdk_packet_assistant.c +++ b/app/rail/component/sl_rail_sdk_packet_assistant/sl_rail_sdk_packet_assistant.c @@ -50,6 +50,8 @@ uint16_t unpack_packet_sun_oqpsk(uint8_t *rx_destination, const RAIL_RxPacketInf void prepare_packet_sun_oqpsk(RAIL_Handle_t rail_handle, uint8_t *out_data, uint16_t length); uint16_t unpack_packet_sidewalk(uint8_t *rx_destination, const RAIL_RxPacketInfo_t *packet_information, uint8_t **start_of_payload); void prepare_packet_sidewalk(RAIL_Handle_t rail_handle, uint8_t *out_data, uint16_t length); +uint16_t unpack_packet_longrange(uint8_t *rx_destination, const RAIL_RxPacketInfo_t *packet_information, uint8_t **start_of_payload); +void prepare_packet_longrange(RAIL_Handle_t rail_handle, uint8_t *out_data, uint16_t length); uint16_t unpack_packet_base(uint8_t *rx_destination, const RAIL_RxPacketInfo_t *packet_information, uint8_t **start_of_payload); void prepare_packet_base(RAIL_Handle_t rail_handle, uint8_t *out_data, uint16_t length); @@ -148,6 +150,10 @@ void update_assistant_pointers(uint8_t new_phy_index) prepare_packet_fnc = &prepare_packet_base; } break; + case LONGRANGE: + unpack_packet_fnc = &unpack_packet_longrange; + prepare_packet_fnc = &prepare_packet_longrange; + break; default: unpack_packet_fnc = &unpack_packet_base; prepare_packet_fnc = &prepare_packet_base; @@ -488,6 +494,53 @@ void prepare_packet_sidewalk(RAIL_Handle_t rail_handle, uint8_t *out_data, uint1 } } +/****************************************************************************** + * The API helps to unpack the received packet, point to the payload and returns the length. + *****************************************************************************/ +uint16_t unpack_packet_longrange(uint8_t *rx_destination, const RAIL_RxPacketInfo_t *packet_information, uint8_t **start_of_payload) +{ + uint16_t payload_size = 0; + + RAIL_CopyRxPacket(rx_destination, packet_information); + *start_of_payload + = sl_rail_sdk_802154_packet_unpack_longrange_data_frame(packet_information, + &payload_size, + rx_destination); + if (print_packet_info) { + #if defined(SL_CATALOG_APP_LOG_PRESENT) + app_log_info("Long Range Packet is ready, %d bytes payload read\n ", payload_size); + #endif + } + return payload_size; +} + +/****************************************************************************** + * The API prepares the packet for sending and load it in the RAIL TX FIFO + *****************************************************************************/ +void prepare_packet_longrange(RAIL_Handle_t rail_handle, uint8_t *out_data, uint16_t length) +{ + // Check if write fifo has written all bytes + uint16_t bytes_written_in_fifo = 0; + uint16_t packet_size = 0U; + uint8_t tx_frame_buffer[256]; + sl_rail_sdk_802154_packet_pack_longrange_data_frame(length, + out_data, + &packet_size, + tx_frame_buffer); + bytes_written_in_fifo = RAIL_WriteTxFifo(rail_handle, tx_frame_buffer, packet_size, true); + #if defined(SL_CATALOG_APP_ASSERT_PRESENT) + app_assert(bytes_written_in_fifo == packet_size, + "RAIL_WriteTxFifo() failed to write in fifo (%d bytes instead of %d bytes)\n", + bytes_written_in_fifo, + packet_size); + #endif + if (print_packet_info) { + #if defined(SL_CATALOG_APP_LOG_PRESENT) + app_log_info("Long Range Packet is ready, %d bytes written\n ", bytes_written_in_fifo); + #endif + } +} + /****************************************************************************** * The API helps to unpack the received packet, point to the payload and returns the length. *****************************************************************************/ diff --git a/app/rail/component/sl_rail_sdk_range_test_core/app_measurement.c b/app/rail/component/sl_rail_sdk_range_test_core/app_measurement.c index 1a9e52e0cf..67182879e1 100644 --- a/app/rail/component/sl_rail_sdk_range_test_core/app_measurement.c +++ b/app/rail/component/sl_rail_sdk_range_test_core/app_measurement.c @@ -592,6 +592,14 @@ void set_power_level_to_max(bool init) tx_power_config_original.mode = SL_RAIL_UTIL_PA_SELECTION_SUBGHZ; tx_power_needs_reinit = true; } +#if RAIL_SUPPORTS_OFDM_PA + if (channelConfigs[range_test_settings.current_phy]->configs[0].stackInfo[0] == CONNECT + || channelConfigs[range_test_settings.current_phy]->configs[0].stackInfo[0] == WISUN) { + if (channelConfigs[range_test_settings.current_phy]->configs[0].stackInfo[1] >= 0x20) { + tx_power_config_original.mode = SL_RAIL_UTIL_PA_SELECTION_OFDM; + } + } +#endif } else { if (tx_power_config_original.mode != SL_RAIL_UTIL_PA_SELECTION_2P4GHZ) { tx_power_config_original.mode = SL_RAIL_UTIL_PA_SELECTION_2P4GHZ; diff --git a/app/rail/documentation/release-highlights.txt b/app/rail/documentation/release-highlights.txt index b31a95b14a..83110ad761 100644 --- a/app/rail/documentation/release-highlights.txt +++ b/app/rail/documentation/release-highlights.txt @@ -1,8 +1,5 @@ -RAIL SDK 2.18.0.0 +RAIL SDK 2.18.1.0 - RAIL Apps and Library - - RAIL Tutorial moved to docs.silabs.com: https://docs.silabs.com/rail/latest/rail-start/rail-training - - RAIL SDK supported on BRD4276A radio board with EFR32FG25 and SKY66122-11 frontend module for high TX power applications - - Improved RangeTest Sample Application to fully support multi-PHY configurations and added new feature to control measurements on RX side – in alpha quality - - Sigfox TX PHYs and RX PHYs supported on EFR32FG23 and EFR32FG28 parts for EU and NA region + - Targeted quality improvements and bug fixes. diff --git a/app/rail/esf.properties b/app/rail/esf.properties index 29ae6802d5..5150b5f3b3 100644 --- a/app/rail/esf.properties +++ b/app/rail/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.rail label=RAIL SDK description=RAIL Software Development Kit -version=2.18.0.0 -prop.subLabel=RAIL\\ 2.18.0.0 +version=2.18.1.0 +prop.subLabel=RAIL\\ 2.18.1.0 # General properties are prepended with "prop." prop.file.templatesFile=rail_production_templates.xml rail_demos_only_templates.xml rail_internal_templates.xml rail_evaluation_templates.xml diff --git a/app/rail/example/soc/rail_soc_burst_duty_cycle/app_init.c b/app/rail/example/soc/rail_soc_burst_duty_cycle/app_init.c index 7d04e452ab..9437603273 100644 --- a/app/rail/example/soc/rail_soc_burst_duty_cycle/app_init.c +++ b/app/rail/example/soc/rail_soc_burst_duty_cycle/app_init.c @@ -94,11 +94,19 @@ SL_WEAK void print_sample_app_name(const char* app_name) *****************************************************************************/ RAIL_Handle_t app_init(void) { + // For handling error codes + RAIL_Status_t rail_status = RAIL_STATUS_NO_ERROR; + // To calculate proper preamble uint32_t bit_rate = 0UL; // Get RAIL handle, used later by the application RAIL_Handle_t rail_handle = sl_rail_util_get_handle(SL_RAIL_UTIL_HANDLE_INST0); + // Set to IDLE (channel select automatically start RX) + rail_status = RAIL_Idle(rail_handle, RAIL_IDLE, true); + if (rail_status != RAIL_STATUS_NO_ERROR) { + app_log_warning("Couldn't enter into IDLE, error code %lu\n", rail_status); + } set_up_tx_fifo(rail_handle); diff --git a/app/rail/example/soc/rail_soc_long_preamble_duty_cycle/app_init.c b/app/rail/example/soc/rail_soc_long_preamble_duty_cycle/app_init.c index 04dada58a4..6bea026e69 100644 --- a/app/rail/example/soc/rail_soc_long_preamble_duty_cycle/app_init.c +++ b/app/rail/example/soc/rail_soc_long_preamble_duty_cycle/app_init.c @@ -102,6 +102,11 @@ RAIL_Handle_t app_init(void) // Get RAIL handle, used later by the application RAIL_Handle_t rail_handle = sl_rail_util_get_handle(SL_RAIL_UTIL_HANDLE_INST0); + // Set to IDLE (channel select automatically start RX) + rail_status = RAIL_Idle(rail_handle, RAIL_IDLE, true); + if (rail_status != RAIL_STATUS_NO_ERROR) { + app_log_warning("Couldn't enter into IDLE, error code %lu\n", rail_status); + } set_up_tx_fifo(rail_handle); diff --git a/app/rail/rail_demos_only_demos.xml b/app/rail/rail_demos_only_demos.xml index ff04accdae..edf273983b 100644 --- a/app/rail/rail_demos_only_demos.xml +++ b/app/rail/rail_demos_only_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + diff --git a/app/rail/rail_production_demos.xml b/app/rail/rail_production_demos.xml index f3ed27e7e7..7912747e78 100644 --- a/app/rail/rail_production_demos.xml +++ b/app/rail/rail_production_demos.xml @@ -6,7 +6,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -28,7 +28,7 @@ - + @@ -39,7 +39,7 @@ - + @@ -50,7 +50,7 @@ - + @@ -61,7 +61,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -116,7 +116,7 @@ - + @@ -127,7 +127,7 @@ - + @@ -138,7 +138,7 @@ - + @@ -149,7 +149,29 @@ - + + + + + + + The purpose of the application is to demonstrate simple wireless communication between two or more boards. In combination with the Light sample application, it creates basic switch functionality, where the light can be toggled in the Light node. After power-up, the node is in SCAN state. It means the broadcast messages of the light modules can be captured. After pushing PB1 button, the closest Light module will be connected. This is called the LINK state. If the Light module has done the same procedure, light can be toggled from all the boards by pushing BP0 button. + + + + + + + + + + + The purpose of the application is to demonstrate simple wireless communication between two or more boards. In combination with the Light sample application, it creates basic switch functionality, where the light can be toggled in the Light node. After power-up, the node is in SCAN state. It means the broadcast messages of the light modules can be captured. After pushing PB1 button, the closest Light module will be connected. This is called the LINK state. If the Light module has done the same procedure, light can be toggled from all the boards by pushing BP0 button. + + + + + @@ -160,7 +182,7 @@ - + @@ -171,7 +193,7 @@ - + @@ -182,7 +204,7 @@ - + @@ -193,7 +215,7 @@ - + @@ -204,7 +226,7 @@ - + @@ -215,7 +237,7 @@ - + @@ -226,7 +248,7 @@ - + @@ -237,7 +259,7 @@ - + @@ -248,7 +270,7 @@ - + @@ -259,7 +281,7 @@ - + @@ -270,7 +292,7 @@ - + @@ -281,7 +303,7 @@ - + @@ -292,7 +314,7 @@ - + @@ -303,7 +325,7 @@ - + @@ -314,7 +336,7 @@ - + @@ -325,7 +347,7 @@ - + @@ -336,7 +358,7 @@ - + @@ -347,7 +369,7 @@ - + @@ -358,7 +380,7 @@ - + @@ -369,7 +391,7 @@ - + @@ -380,7 +402,7 @@ - + @@ -391,7 +413,7 @@ - + @@ -402,7 +424,7 @@ - + @@ -413,7 +435,7 @@ - + @@ -424,7 +446,7 @@ - + @@ -435,7 +457,7 @@ - + @@ -446,7 +468,7 @@ - + @@ -457,7 +479,7 @@ - + @@ -468,7 +490,7 @@ - + @@ -479,7 +501,7 @@ - + @@ -490,7 +512,7 @@ - + @@ -501,7 +523,7 @@ - + @@ -512,7 +534,7 @@ - + @@ -523,7 +545,7 @@ - + @@ -534,7 +556,7 @@ - + @@ -545,7 +567,7 @@ - + @@ -556,7 +578,7 @@ - + @@ -567,7 +589,7 @@ - + @@ -578,7 +600,18 @@ - + + + + + + + The purpose of the application is to demonstrate simple wireless communication between two or more boards. In combination with the Light sample application, it creates basic switch functionality, where the light can be toggled in the Light node. After power-up, the node is in SCAN state. It means the broadcast messages of the light modules can be captured. After pushing PB1 button, the closest Light module will be connected. This is called the LINK state. If the Light module has done the same procedure, light can be toggled from all the boards by pushing BP0 button. + + + + + @@ -589,7 +622,7 @@ - + @@ -600,7 +633,7 @@ - + @@ -611,7 +644,7 @@ - + @@ -622,7 +655,7 @@ - + @@ -633,7 +666,7 @@ - + @@ -644,7 +677,7 @@ - + @@ -655,7 +688,7 @@ - + @@ -666,7 +699,7 @@ - + @@ -677,7 +710,7 @@ - + @@ -688,7 +721,7 @@ - + @@ -699,7 +732,7 @@ - + @@ -710,7 +743,7 @@ - + @@ -721,7 +754,7 @@ - + @@ -732,7 +765,7 @@ - + @@ -743,7 +776,7 @@ - + @@ -754,7 +787,7 @@ - + @@ -765,7 +798,7 @@ - + @@ -776,7 +809,7 @@ - + @@ -787,7 +820,7 @@ - + @@ -798,7 +831,7 @@ - + @@ -809,7 +842,7 @@ - + @@ -820,7 +853,7 @@ - + @@ -831,7 +864,7 @@ - + @@ -842,7 +875,7 @@ - + @@ -853,7 +886,7 @@ - + @@ -864,7 +897,7 @@ - + @@ -875,7 +908,7 @@ - + @@ -886,7 +919,7 @@ - + @@ -897,7 +930,29 @@ - + + + + + + + The Range Test application, running on Micrium OS RTOS and multiprotocol RAIL, demonstrates the over-the-air range of the EFR32. It serves as both a transmitter and a receiver, with adjustable packet length and transmission options. Output power can be set from -15 dBm to +20 dBm. In Rx Mode, it inspects received packets based on device IDs, displaying Packet Error Rate, Bit Error Rate, and RSSI. The CLI can also be used for configuration. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Note: Avoid powering the boards from a coin cell due to higher current consumption during continuous radio usage, particularly in Rx Mode. For portability, consider using a USB power bank instead. + + + + + + + + + + + The Range Test application, running on Micrium OS RTOS and multiprotocol RAIL, demonstrates the over-the-air range of the EFR32. It serves as both a transmitter and a receiver, with adjustable packet length and transmission options. Output power can be set from -15 dBm to +20 dBm. In Rx Mode, it inspects received packets based on device IDs, displaying Packet Error Rate, Bit Error Rate, and RSSI. The CLI can also be used for configuration. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Note: Avoid powering the boards from a coin cell due to higher current consumption during continuous radio usage, particularly in Rx Mode. For portability, consider using a USB power bank instead. + + + + + @@ -908,7 +963,7 @@ - + @@ -919,7 +974,7 @@ - + @@ -930,7 +985,7 @@ - + @@ -941,7 +996,7 @@ - + @@ -952,7 +1007,7 @@ - + @@ -963,7 +1018,7 @@ - + @@ -974,7 +1029,7 @@ - + @@ -985,7 +1040,7 @@ - + @@ -996,7 +1051,7 @@ - + @@ -1007,7 +1062,7 @@ - + @@ -1018,7 +1073,7 @@ - + @@ -1029,7 +1084,7 @@ - + @@ -1040,7 +1095,7 @@ - + @@ -1051,7 +1106,7 @@ - + @@ -1062,7 +1117,7 @@ - + @@ -1073,7 +1128,7 @@ - + @@ -1084,7 +1139,7 @@ - + @@ -1095,7 +1150,7 @@ - + @@ -1106,7 +1161,7 @@ - + @@ -1117,7 +1172,7 @@ - + @@ -1128,7 +1183,7 @@ - + @@ -1139,7 +1194,7 @@ - + @@ -1150,7 +1205,7 @@ - + @@ -1161,7 +1216,7 @@ - + diff --git a/app/rail/rail_production_templates.xml b/app/rail/rail_production_templates.xml index d94cf6eb29..b3f81e6cdf 100755 --- a/app/rail/rail_production_templates.xml +++ b/app/rail/rail_production_templates.xml @@ -6,7 +6,7 @@ - + @@ -21,7 +21,7 @@ - + @@ -36,7 +36,7 @@ - + @@ -51,7 +51,7 @@ - + @@ -66,7 +66,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -96,7 +96,7 @@ - + @@ -126,7 +126,7 @@ - + @@ -141,7 +141,7 @@ - + @@ -156,7 +156,7 @@ - + @@ -171,7 +171,7 @@ - + @@ -186,7 +186,7 @@ - + @@ -216,7 +216,7 @@ - + @@ -231,7 +231,7 @@ - + @@ -246,7 +246,7 @@ - + @@ -261,7 +261,7 @@ - + diff --git a/app/wisun/component/app_core/sl_wisun_app_core.c b/app/wisun/component/app_core/sl_wisun_app_core.c index d476b21fd3..ad5d7179fc 100644 --- a/app/wisun/component/app_core/sl_wisun_app_core.c +++ b/app/wisun/component/app_core/sl_wisun_app_core.c @@ -80,10 +80,10 @@ /// Synthetize app settings if it is not available #if !defined(SL_CATALOG_WISUN_APP_SETTING_PRESENT) -typedef struct app_setting_wisun{ +typedef struct app_setting_wisun { char network_name[SL_WISUN_NETWORK_NAME_SIZE + 1]; uint8_t network_size; - int16_t tx_power; + int16_t tx_power_ddbm; uint8_t device_type; uint8_t lfn_profile; bool is_default_phy; @@ -188,9 +188,9 @@ static const app_setting_wisun_t _app_default_settings = { .network_size = SL_WISUN_NETWORK_SIZE_SMALL, #endif #if defined(WISUN_CONFIG_TX_POWER) - .tx_power = WISUN_CONFIG_TX_POWER, + .tx_power_ddbm = WISUN_CONFIG_TX_POWER, #else - .tx_power = 200, + .tx_power_ddbm = 200, #endif .is_default_phy = true, #if defined(WISUN_CONFIG_DEVICE_TYPE) @@ -406,6 +406,31 @@ void sl_wisun_multicast_reg_finish_hnd(sl_wisun_evt_t *evt) __CHECK_FOR_STATUS(evt->evt.error.status); } +void sl_wisun_dhcp_vendor_data_hnd(sl_wisun_evt_t *evt) +{ + __CHECK_FOR_STATUS(evt->evt.error.status); +} + +void sl_wisun_pan_defect_hnd(sl_wisun_evt_t *evt) +{ + __CHECK_FOR_STATUS(evt->evt.error.status); +} + +void sl_wisun_direct_connect_link_available_hnd(sl_wisun_evt_t *evt) +{ + __CHECK_FOR_STATUS(evt->evt.error.status); +} + +void sl_wisun_direct_connect_status_hnd(sl_wisun_evt_t *evt) +{ + __CHECK_FOR_STATUS(evt->evt.error.status); +} + +void sl_wisun_br_stopped_hnd(sl_wisun_evt_t *evt) +{ + __CHECK_FOR_STATUS(evt->evt.error.status); +} + /* Wisun app core init */ void sl_wisun_app_core_init(void) { @@ -699,7 +724,7 @@ static sl_status_t _app_wisun_application_setting(const app_setting_wisun_t * co #endif // set the TX power - ret = sl_wisun_set_tx_power_ddbm(setting->tx_power); + ret = sl_wisun_set_tx_power_ddbm(setting->tx_power_ddbm); if (ret != SL_STATUS_OK) { printf("[Failed: unable to set TX power: %lu]\n", ret); _app_wisun_core_set_state(SL_WISUN_APP_CORE_STATE_SET_TX_POWER_ERROR); diff --git a/app/wisun/component/app_setting/sl_wisun_app_setting.c b/app/wisun/component/app_setting/sl_wisun_app_setting.c index 1f3e58c32a..67be775f43 100644 --- a/app/wisun/component/app_setting/sl_wisun_app_setting.c +++ b/app/wisun/component/app_setting/sl_wisun_app_setting.c @@ -149,9 +149,9 @@ static const app_setting_wisun_t wisun_app_settings_default = { .network_size = SL_WISUN_NETWORK_SIZE_SMALL, #endif #if defined(WISUN_CONFIG_TX_POWER) - .tx_power = WISUN_CONFIG_TX_POWER, + .tx_power_ddbm = WISUN_CONFIG_TX_POWER, #else - .tx_power = 200, + .tx_power_ddbm = 200, #endif .is_default_phy = true, #if defined(WISUN_CONFIG_DEVICE_TYPE) @@ -315,7 +315,7 @@ sl_status_t app_wisun_setting_set_tx_power(const int16_t * const tx_power) _app_wisun_mutex_acquire(); - _wisun_app_settings.tx_power = *tx_power; + _wisun_app_settings.tx_power_ddbm = *tx_power; stat = _setting_notify(APP_SETTING_NOTIFICATION_SET_TX_POWER); @@ -391,7 +391,7 @@ sl_status_t app_wisun_setting_get_tx_power(int16_t * const tx_power) } _app_wisun_mutex_acquire(); - *tx_power = _wisun_app_settings.tx_power; + *tx_power = _wisun_app_settings.tx_power_ddbm; _app_wisun_mutex_release(); return SL_STATUS_OK; diff --git a/app/wisun/component/app_setting/sl_wisun_app_setting.h b/app/wisun/component/app_setting/sl_wisun_app_setting.h index edab795e9e..b09cfd6104 100644 --- a/app/wisun/component/app_setting/sl_wisun_app_setting.h +++ b/app/wisun/component/app_setting/sl_wisun_app_setting.h @@ -81,7 +81,7 @@ typedef struct app_setting_wisun{ /// Network size uint8_t network_size; /// TX Power - int16_t tx_power; + int16_t tx_power_ddbm; /// Device type uint8_t device_type; /// LFN profile diff --git a/app/wisun/component/cli/sl_wisun_cli.c b/app/wisun/component/cli/sl_wisun_cli.c index 09a816ce63..1a6ce2e433 100644 --- a/app/wisun/component/cli/sl_wisun_cli.c +++ b/app/wisun/component/cli/sl_wisun_cli.c @@ -1067,6 +1067,19 @@ const app_cli_entry_t app_settings_entries[] = { .key = "tx_power", .domain = APP_CLI_WISUN_DOMAIN_ID, + .value_size = APP_CLI_VALUE_SIZE_UINT8, + .input = APP_CLI_INPUT_FLAG_DEFAULT | APP_CLI_INPUT_FLAG_SIGNED, + .output = APP_CLI_OUTPUT_FLAG_DEFAULT | APP_CLI_OUTPUT_FLAG_SIGNED, + .value = NULL, + .input_enum_list = NULL, + .output_enum_list = NULL, + .set_handler = _app_cli_set_tx_power, + .get_handler = _app_cli_get_tx_power, + .description = "TX power in dBm [int8]" + }, + { + .key = "tx_power_ddbm", + .domain = APP_CLI_WISUN_DOMAIN_ID, .value_size = APP_CLI_VALUE_SIZE_UINT16, .input = APP_CLI_INPUT_FLAG_DEFAULT | APP_CLI_INPUT_FLAG_SIGNED, .output = APP_CLI_OUTPUT_FLAG_DEFAULT | APP_CLI_OUTPUT_FLAG_SIGNED, @@ -1075,7 +1088,7 @@ const app_cli_entry_t app_settings_entries[] = .output_enum_list = NULL, .set_handler = _app_cli_set_tx_power, .get_handler = _app_cli_get_tx_power, - .description = "TX power in ddBm [uint16]" + .description = "TX power in ddBm [int16]" }, { .key = APP_CLI_PHY_PARAM_REG_DOMAIN_STR, @@ -1775,21 +1788,24 @@ static sl_status_t _app_cli_set_tx_power(const char *value_str, const char *key_str, const app_cli_entry_t *entry) { - sl_status_t res = SL_STATUS_FAIL; - int32_t value = 0U; + sl_status_t ret = SL_STATUS_FAIL; + uint32_t value = 0U; (void)key_str; - (void)entry; - res = app_util_get_integer((uint32_t *)&value, + ret = app_util_get_integer(&value, value_str, entry->input_enum_list, entry->input & APP_CLI_INPUT_FLAG_SIGNED); - if (res == SL_STATUS_OK) { - // sets the tx power - res = app_wisun_setting_set_tx_power((int16_t *)&value); + if (ret == SL_STATUS_OK) { + // If entry is in dBm, multiply by 10 to have ddBm + if (entry->value_size == APP_SETTINGS_VALUE_SIZE_UINT8) { + value = value * 10U; + } + // Set the tx power + ret = app_wisun_setting_set_tx_power((int16_t *)&value); } - return res; + return ret; } /* App CLI setting network name */ @@ -1849,19 +1865,26 @@ static sl_status_t _app_cli_get_tx_power(char *value_str, const char *key_str, const app_cli_entry_t *entry) { - sl_status_t res = SL_STATUS_FAIL; - int16_t value = 0; + sl_status_t ret = SL_STATUS_FAIL; + int16_t tx_power_ddbm = 0; (void)key_str; - (void)entry; - res = app_wisun_setting_get_tx_power(&value); - if (res == SL_STATUS_OK) { - snprintf(value_str, APP_CLI_STR_VALUE_LENGTH, "%d ddBm", value); + ret = app_wisun_setting_get_tx_power(&tx_power_ddbm); + if (ret == SL_STATUS_OK) { + if (entry->value_size == APP_SETTINGS_VALUE_SIZE_UINT8) { + // If entry is in dBm, print in float format + snprintf(value_str, APP_CLI_STR_VALUE_LENGTH, "%d.%d", tx_power_ddbm / 10, abs(tx_power_ddbm % 10)); + } else if (entry->value_size == APP_SETTINGS_VALUE_SIZE_UINT16) { + snprintf(value_str, APP_CLI_STR_VALUE_LENGTH, "%d", tx_power_ddbm); + } else { + ret = SL_STATUS_FAIL; + snprintf(value_str, APP_CLI_STR_VALUE_LENGTH, "N/A"); + } } else { snprintf(value_str, APP_CLI_STR_VALUE_LENGTH, "N/A"); } - return res; + return ret; } static bool _is_param_used(const char *param_str) diff --git a/app/wisun/component/event_manager/sl_wisun_event_mgr.c b/app/wisun/component/event_manager/sl_wisun_event_mgr.c index 25968b0597..760f86dbbb 100644 --- a/app/wisun/component/event_manager/sl_wisun_event_mgr.c +++ b/app/wisun/component/event_manager/sl_wisun_event_mgr.c @@ -61,7 +61,12 @@ typedef enum { EVENT_IDX_JOIN_STATE, EVENT_IDX_REGULATION_TX_LEVEL, EVENT_IDX_LFN_WAKE_UP, - EVENT_IDX_MULTICAST_REG_FINISH + EVENT_IDX_MULTICAST_REG_FINISH, + EVENT_IDX_DHCP_VENDOR_DATA, + EVENT_IDX_PAN_DEFECT, + EVENT_IDX_DIRECT_CONNECT_LINK_AVAILABLE, + EVENT_IDX_DIRECT_CONNECT_LINK_STATUS, + EVENT_IDX_BR_STOPPED } app_wisun_event_id_t; /// Wi-SUN application callback type. @@ -200,6 +205,31 @@ static event_handler_t _wisun_events[] = { .id = SL_WISUN_MSG_LFN_MULTICAST_REG_IND_ID, .callback = sl_wisun_multicast_reg_finish_hnd, .custom_callback = NULL + }, + { + .id = SL_WISUN_MSG_DHCP_VENDOR_DATA_IND_ID, + .callback = sl_wisun_dhcp_vendor_data_hnd, + .custom_callback = NULL + }, + { + .id = SL_WISUN_MSG_PAN_DEFECT_IND_ID, + .callback = sl_wisun_pan_defect_hnd, + .custom_callback = NULL + }, + { + .id = SL_WISUN_MSG_DIRECT_CONNECT_LINK_AVAILABLE_IND_ID, + .callback = sl_wisun_direct_connect_link_available_hnd, + .custom_callback = NULL + }, + { + .id = SL_WISUN_MSG_DIRECT_CONNECT_LINK_STATUS_IND_ID, + .callback = sl_wisun_direct_connect_status_hnd, + .custom_callback = NULL + }, + { + .id = SL_WISUN_BR_MSG_STOPPED_IND_ID, + .callback = sl_wisun_br_stopped_hnd, + .custom_callback = NULL } }; @@ -404,7 +434,13 @@ __STATIC_INLINE app_wisun_event_id_t _decode_ind(const sl_wisun_msg_ind_id_t ind case SL_WISUN_MSG_REGULATION_TX_LEVEL_IND_ID: return EVENT_IDX_REGULATION_TX_LEVEL; case SL_WISUN_MSG_LFN_WAKE_UP_IND_ID: return EVENT_IDX_LFN_WAKE_UP; case SL_WISUN_MSG_LFN_MULTICAST_REG_IND_ID: return EVENT_IDX_MULTICAST_REG_FINISH; + case SL_WISUN_MSG_DHCP_VENDOR_DATA_IND_ID: return EVENT_IDX_DHCP_VENDOR_DATA; + case SL_WISUN_MSG_PAN_DEFECT_IND_ID: return EVENT_IDX_PAN_DEFECT; + case SL_WISUN_MSG_DIRECT_CONNECT_LINK_AVAILABLE_IND_ID: return EVENT_IDX_DIRECT_CONNECT_LINK_AVAILABLE; + case SL_WISUN_MSG_DIRECT_CONNECT_LINK_STATUS_IND_ID: return EVENT_IDX_DIRECT_CONNECT_LINK_STATUS; + case SL_WISUN_BR_MSG_STOPPED_IND_ID: return EVENT_IDX_BR_STOPPED; default: return EVENT_IDX_NOTVALID; + } } @@ -568,3 +604,58 @@ SL_WEAK void sl_wisun_multicast_reg_finish_hnd(sl_wisun_evt_t *evt) (void) evt; assert(false); } + +/**************************************************************************//** + * @brief Wi-SUN DHCP vendor data event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +SL_WEAK void sl_wisun_dhcp_vendor_data_hnd(sl_wisun_evt_t *evt) +{ + (void) evt; + assert(false); +} + +/**************************************************************************//** + * @brief Wi-SUN PAN defect event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +SL_WEAK void sl_wisun_pan_defect_hnd(sl_wisun_evt_t *evt) +{ + (void) evt; + assert(false); +} + +/**************************************************************************//** + * @brief Wi-SUN Direct Connect link available event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +SL_WEAK void sl_wisun_direct_connect_link_available_hnd(sl_wisun_evt_t *evt) +{ + (void) evt; + assert(false); +} + +/**************************************************************************//** + * @brief Wi-SUN Direct Connect status event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +SL_WEAK void sl_wisun_direct_connect_status_hnd(sl_wisun_evt_t *evt) +{ + (void) evt; + assert(false); +} + +/**************************************************************************//** + * @brief Wi-SUN Border Router stopped event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +SL_WEAK void sl_wisun_br_stopped_hnd(sl_wisun_evt_t *evt) +{ + (void) evt; + assert(false); +} \ No newline at end of file diff --git a/app/wisun/component/event_manager/sl_wisun_event_mgr.h b/app/wisun/component/event_manager/sl_wisun_event_mgr.h index cab2e7d05e..96159cb2a0 100644 --- a/app/wisun/component/event_manager/sl_wisun_event_mgr.h +++ b/app/wisun/component/event_manager/sl_wisun_event_mgr.h @@ -218,6 +218,41 @@ void sl_wisun_lfn_wake_up_hnd(sl_wisun_evt_t *evt); *****************************************************************************/ void sl_wisun_multicast_reg_finish_hnd(sl_wisun_evt_t *evt); +/**************************************************************************//** + * @brief Wi-SUN DHCP vendor data event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +void sl_wisun_dhcp_vendor_data_hnd(sl_wisun_evt_t *evt); + +/**************************************************************************//** + * @brief Wi-SUN PAN defect event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +void sl_wisun_pan_defect_hnd(sl_wisun_evt_t *evt); + +/**************************************************************************//** + * @brief Wi-SUN Direct Connect link available event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +void sl_wisun_direct_connect_link_available_hnd(sl_wisun_evt_t *evt); + +/**************************************************************************//** + * @brief Wi-SUN Direct Connect status event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +void sl_wisun_direct_connect_status_hnd(sl_wisun_evt_t *evt); + +/**************************************************************************//** + * @brief Wi-SUN Border Router stopped event handler + * @details + * @param[in] evt event ptr + *****************************************************************************/ +void sl_wisun_br_stopped_hnd(sl_wisun_evt_t *evt); + #ifdef __cplusplus } #endif diff --git a/app/wisun/component/network_measurement/sl_wisun_network_measurement_gui.c b/app/wisun/component/network_measurement/sl_wisun_network_measurement_gui.c index ce554dd896..ac3459f664 100644 --- a/app/wisun/component/network_measurement/sl_wisun_network_measurement_gui.c +++ b/app/wisun/component/network_measurement/sl_wisun_network_measurement_gui.c @@ -411,7 +411,7 @@ static void _node_info_form(void *args) node_info.settings.network_name, app_wisun_trace_util_nw_size_to_str(node_info.settings.network_size), node_info.settings.network_size, - node_info.settings.tx_power, + node_info.settings.tx_power_ddbm, app_wisun_trace_util_phy_cfg_type_to_str(node_info.settings.phy.type), app_wisun_trace_util_reg_domain_to_str(node_info.settings.phy.config.fan10.reg_domain), node_info.settings.phy.config.fan10.reg_domain, @@ -429,7 +429,7 @@ static void _node_info_form(void *args) node_info.settings.network_name, app_wisun_trace_util_nw_size_to_str(node_info.settings.network_size), node_info.settings.network_size, - node_info.settings.tx_power, + node_info.settings.tx_power_ddbm, app_wisun_trace_util_phy_cfg_type_to_str(node_info.settings.phy.type), app_wisun_trace_util_reg_domain_to_str(node_info.settings.phy.config.fan11.reg_domain), node_info.settings.phy.config.fan11.reg_domain, diff --git a/app/wisun/component/sl_ftp.slcc b/app/wisun/component/sl_ftp.slcc index dd22e4e720..8b34090aa8 100644 --- a/app/wisun/component/sl_ftp.slcc +++ b/app/wisun/component/sl_ftp.slcc @@ -15,7 +15,7 @@ description: > To ensure proper functionality, a TFTP server, such as tftpd-hpa, must be prepared on the remote host. category: "Wi-SUN|Wi-SUN Services" -quality: "production" +quality: "evaluation" metadata: sbom: license: Zlib diff --git a/app/wisun/component/sl_wisun_ota_dfu.slcc b/app/wisun/component/sl_wisun_ota_dfu.slcc index c055a5b430..297ce7ebf0 100644 --- a/app/wisun/component/sl_wisun_ota_dfu.slcc +++ b/app/wisun/component/sl_wisun_ota_dfu.slcc @@ -21,7 +21,7 @@ description: > To save on download time, we recommend applying compression on both the bootloader and device projects. category: "Wi-SUN|Wi-SUN Services" -quality: "production" +quality: "evaluation" metadata: sbom: license: Zlib diff --git a/app/wisun/documentation/release-highlights.txt b/app/wisun/documentation/release-highlights.txt index f957b494b6..5cfaeb1e14 100644 --- a/app/wisun/documentation/release-highlights.txt +++ b/app/wisun/documentation/release-highlights.txt @@ -1,9 +1,8 @@ -Wi-SUN SDK 2.3.0 +Wi-SUN SDK 2.4.0 - Wi-SUN Stack - - Direct Connect - - PAN Defect + - Introducted a new API to select a preferred PAN + - Targeted quality improvements and bug fixes. - Wi-SUN Applications - - Border Router CLI source code - - Border Router CLI with Wi-Fi Backhaul + - Targeted quality improvements and bug fixes. diff --git a/app/wisun/documentation/slWi-SUN_docContent.xml b/app/wisun/documentation/slWi-SUN_docContent.xml index e5b0dd32db..8b15708270 100644 --- a/app/wisun/documentation/slWi-SUN_docContent.xml +++ b/app/wisun/documentation/slWi-SUN_docContent.xml @@ -1,6 +1,6 @@ - - + + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -8,7 +8,7 @@ - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -16,7 +16,7 @@ - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -24,70 +24,70 @@ - + Describes the test environment and methods for testing Wi-SUN network performance. The results are intended to provide guidance on design practices and principles as well as expected field performance results. - + Describes how to use the Silicon Labs Wi-SUN Linux border router or the EFR32 standalone border router demonstration. Covers the associated configuration and debugging tools. - + Describes how to use the Wi-SUN Network Performance Measurement Application from either the LCD output or the CLI, and includes suggestions for improving ping latency in a Wi-SUN network. - + Provides an introduction to the Wi-SUN PHY Mode Switch feature using the RAILtest example application. - + Explains how to program EFR32FG25 devices to enable the Wi-SUN concurrent detection feature. - + Provides an overview and hyperlinks to all packaged documentation. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Wi-SUN stack. - + Reference for those developing applications using the Silicon Labs Wi-SUN SDK. The guide covers guidelines to develop an application on top of Silicon Labs Wi-SUN stack . The purpose of this document is to fill in the gaps between the Silicon Labs Wi-SUN Field Area Network (FAN) API reference, Gecko Platform references, and documentation for the target EFR32xG part. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the SiliconLabs Wi-SUN SDK, including added/deleted/deprecated features/API. Reviews fixed and known issues. - + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. @@ -95,7 +95,7 @@ - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -103,7 +103,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. @@ -111,7 +111,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: PS Store and NVM3. @@ -119,7 +119,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface. @@ -127,7 +127,7 @@ - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/app/wisun/esf.properties b/app/wisun/esf.properties index 2f561fbec9..ec3983f39b 100644 --- a/app/wisun/esf.properties +++ b/app/wisun/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.wisun label=Wi-SUN description=Silicon Labs Wi-SUN SDK -version=2.3.0.0 -prop.subLabel=Wi-SUN\\ 2.3.0.0 +version=2.4.0.0 +prop.subLabel=Wi-SUN\\ 2.4.0.0 # General properties are prepended with "prop." prop.file.templatesFile=wisun_production_templates.xml wisun_br_demos_templates.xml wisun_evaluation_templates.xml diff --git a/app/wisun/wisun_evaluation_demos.xml b/app/wisun/wisun_evaluation_demos.xml index 5fd2afd65c..fefbe2d6ef 100644 --- a/app/wisun/wisun_evaluation_demos.xml +++ b/app/wisun/wisun_evaluation_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + @@ -25,7 +25,7 @@ - + @@ -35,7 +35,7 @@ - + @@ -45,7 +45,7 @@ - + @@ -55,7 +55,7 @@ - + @@ -65,7 +65,7 @@ - + @@ -75,7 +75,7 @@ - + @@ -85,7 +85,7 @@ - + @@ -95,7 +95,7 @@ - + @@ -105,7 +105,7 @@ - + diff --git a/app/wisun/wisun_production_demos.xml b/app/wisun/wisun_production_demos.xml index f886f2d4dc..0703a24e15 100644 --- a/app/wisun/wisun_production_demos.xml +++ b/app/wisun/wisun_production_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + @@ -25,7 +25,7 @@ - + @@ -35,7 +35,7 @@ - + @@ -45,7 +45,7 @@ - + @@ -55,7 +55,7 @@ - + @@ -65,7 +65,7 @@ - + @@ -75,7 +75,7 @@ - + @@ -85,7 +85,7 @@ - + @@ -95,7 +95,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -115,7 +115,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -135,7 +135,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -185,7 +185,7 @@ - + @@ -195,7 +195,7 @@ - + @@ -205,7 +205,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -225,7 +225,7 @@ - + @@ -235,7 +235,7 @@ - + @@ -245,7 +245,7 @@ - + @@ -255,7 +255,7 @@ - + @@ -265,7 +265,7 @@ - + @@ -275,7 +275,7 @@ - + @@ -285,7 +285,7 @@ - + @@ -295,7 +295,7 @@ - + @@ -305,7 +305,7 @@ - + @@ -315,7 +315,7 @@ - + @@ -325,7 +325,7 @@ - + @@ -335,7 +335,7 @@ - + @@ -345,7 +345,7 @@ - + @@ -355,7 +355,7 @@ - + @@ -365,7 +365,7 @@ - + @@ -375,7 +375,7 @@ - + @@ -385,7 +385,7 @@ - + @@ -395,7 +395,7 @@ - + @@ -405,7 +405,7 @@ - + @@ -415,7 +415,7 @@ - + @@ -425,7 +425,7 @@ - + @@ -435,7 +435,7 @@ - + @@ -445,7 +445,7 @@ - + @@ -455,7 +455,7 @@ - + @@ -465,7 +465,7 @@ - + @@ -475,7 +475,7 @@ - + @@ -485,7 +485,7 @@ - + @@ -495,7 +495,7 @@ - + @@ -505,7 +505,7 @@ - + @@ -515,7 +515,7 @@ - + @@ -525,7 +525,7 @@ - + @@ -535,7 +535,7 @@ - + @@ -545,7 +545,7 @@ - + @@ -555,7 +555,7 @@ - + @@ -565,7 +565,7 @@ - + @@ -575,7 +575,7 @@ - + diff --git a/hardware/board/component/bg22-rb4402c.slcc b/hardware/board/component/bg22-rb4402c.slcc new file mode 100644 index 0000000000..fad16bf9c3 --- /dev/null +++ b/hardware/board/component/bg22-rb4402c.slcc @@ -0,0 +1,26 @@ +!!omap +- id: bg22_rb4402c +- label: BG22-RB4402C +- package: platform +- description: Kit BSP support for the EFR32BG22 Bluetooth LE 6 dBm QFN40 Rev F Radio + Board. +- category: Platform|Board|Kit|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_bg22-rb4402c +- provides: + - name: hardware_kit + - name: hardware_kit_rb +- define: + - name: SL_KIT_NAME + value: '"BG22-RB4402C"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:BG22-RB4402C + - kit:pn:RB4402 + - kit:variant:C + - kit:revision:A00 diff --git a/hardware/board/component/bg22-rb4403c.slcc b/hardware/board/component/bg22-rb4403c.slcc new file mode 100644 index 0000000000..258e155644 --- /dev/null +++ b/hardware/board/component/bg22-rb4403c.slcc @@ -0,0 +1,26 @@ +!!omap +- id: bg22_rb4403c +- label: BG22-RB4403C +- package: platform +- description: Kit BSP support for the EFR32BG22 Bluetooth LE 6 dBm QFN32 Rev F Radio + Board. +- category: Platform|Board|Kit|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_bg22-rb4403c +- provides: + - name: hardware_kit + - name: hardware_kit_rb +- define: + - name: SL_KIT_NAME + value: '"BG22-RB4403C"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:BG22-RB4403C + - kit:pn:RB4403 + - kit:variant:C + - kit:revision:A00 diff --git a/hardware/board/component/bg29-rb4414a.slcc b/hardware/board/component/bg29-rb4414a.slcc index 16d3d6c332..2eaa10b645 100644 --- a/hardware/board/component/bg29-rb4414a.slcc +++ b/hardware/board/component/bg29-rb4414a.slcc @@ -18,9 +18,9 @@ - name: SL_KIT_NAME value: '"BG29-RB4414A"' - name: SL_KIT_REV - value: '"A00"' + value: '"A01"' - tag: - kit:opn:BG29-RB4414A - kit:pn:RB4414 - kit:variant:A - - kit:revision:A00 + - kit:revision:A01 diff --git a/hardware/board/component/brd1021a.slcc b/hardware/board/component/brd1021a.slcc index 36068ef7da..7bc7a174e8 100644 --- a/hardware/board/component/brd1021a.slcc +++ b/hardware/board/component/brd1021a.slcc @@ -19,6 +19,7 @@ - name: hardware_board_from_stk - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_16 - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz - name: hardware_board_has_hfxo @@ -42,7 +43,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd2503a.slcc b/hardware/board/component/brd2503a.slcc index b9d5013570..01f4093b34 100644 --- a/hardware/board/component/brd2503a.slcc +++ b/hardware/board/component/brd2503a.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd2503b.slcc b/hardware/board/component/brd2503b.slcc index d739b44ac9..0971b23e31 100644 --- a/hardware/board/component/brd2503b.slcc +++ b/hardware/board/component/brd2503b.slcc @@ -20,6 +20,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd2504a.slcc b/hardware/board/component/brd2504a.slcc index 89f6b2117a..336727e914 100644 --- a/hardware/board/component/brd2504a.slcc +++ b/hardware/board/component/brd2504a.slcc @@ -20,6 +20,14 @@ - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_3 - name: hardware_board_has_uart - name: hardware_board_has_i2c - name: board_config_clock_manager diff --git a/hardware/board/component/brd2505a.slcc b/hardware/board/component/brd2505a.slcc new file mode 100644 index 0000000000..0713f4002a --- /dev/null +++ b/hardware/board/component/brd2505a.slcc @@ -0,0 +1,84 @@ +!!omap +- id: brd2505a +- label: BRD2505A +- package: platform +- description: Board support for BRD2505A. +- category: Platform|Board|Starter Kit +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: efm32pg26b500f3200il136 + - name: brd2505a_config +- provides: + - name: brd2505a + - name: hardware_board + - name: hardware_board_stk + - name: hardware_board_from_stk + - name: hardware_board_from_pg26-pk2505a + - name: hardware_board_has_sht4x + - name: hardware_board_has_tempsensor + - name: hardware_board_has_vcom + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_17 + - name: hardware_board_has_exp_19 + - name: hardware_board_has_spi + - name: hardware_board_has_uart + - name: hardware_board_has_i2c + - name: board_config_clock_manager + - name: hardware_board_has_hfxo_freq_39mhz + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_has_segment_lcd +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2505A"' + - name: SL_BOARD_REV + value: '"A02"' + - name: HFXO_FREQ + value: 39000000 +- tag: + - board:pn:BRD2505 + - board:variant:A + - board:revision:A02 + - board:device:efm32pg26b500f3200il136 + - hardware:has:vcom + - hardware:has:sensor:sht40-ad1f-r2 + - hardware:has:led:2 + - hardware:has:button:2 + - hardware:has:segment_lcd_driver:cl010-1087-04 + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/brd2506a.slcc b/hardware/board/component/brd2506a.slcc index b55340d928..d16ecb211c 100644 --- a/hardware/board/component/brd2506a.slcc +++ b/hardware/board/component/brd2506a.slcc @@ -20,6 +20,22 @@ - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_17 + - name: hardware_board_has_exp_19 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd2601a.slcc b/hardware/board/component/brd2601a.slcc index d3d353d242..4c3fcfecaf 100644 --- a/hardware/board/component/brd2601a.slcc +++ b/hardware/board/component/brd2601a.slcc @@ -22,6 +22,26 @@ - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_1 + - name: hardware_board_has_exp_2 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_17 + - name: hardware_board_has_exp_18 + - name: hardware_board_has_exp_19 + - name: hardware_board_has_exp_20 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -52,7 +72,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - id: imu_driver_icm20689 diff --git a/hardware/board/component/brd2601b.slcc b/hardware/board/component/brd2601b.slcc index 261fc55746..4041e3b005 100644 --- a/hardware/board/component/brd2601b.slcc +++ b/hardware/board/component/brd2601b.slcc @@ -22,6 +22,26 @@ - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_1 + - name: hardware_board_has_exp_2 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_17 + - name: hardware_board_has_exp_18 + - name: hardware_board_has_exp_19 + - name: hardware_board_has_exp_20 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -52,7 +72,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - id: imu_driver_icm20689 diff --git a/hardware/board/component/brd2602a.slcc b/hardware/board/component/brd2602a.slcc index 23ca59f5f1..6bcf40bff8 100644 --- a/hardware/board/component/brd2602a.slcc +++ b/hardware/board/component/brd2602a.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -47,7 +61,7 @@ - id: simple_button instance: - btn0 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - id: imu_driver_icm20689 diff --git a/hardware/board/component/brd2603a.slcc b/hardware/board/component/brd2603a.slcc index 4829428bd2..2e04c8633e 100644 --- a/hardware/board/component/brd2603a.slcc +++ b/hardware/board/component/brd2603a.slcc @@ -24,6 +24,26 @@ - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_1 + - name: hardware_board_has_exp_2 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_17 + - name: hardware_board_has_exp_18 + - name: hardware_board_has_exp_19 + - name: hardware_board_has_exp_20 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -49,7 +69,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - id: imu_driver_icm20689 diff --git a/hardware/board/component/brd2606a.slcc b/hardware/board/component/brd2606a.slcc index 14264aa511..ad9d6b8435 100644 --- a/hardware/board/component/brd2606a.slcc +++ b/hardware/board/component/brd2606a.slcc @@ -42,7 +42,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: imu_driver_icm40627 - template_contribution: [] diff --git a/hardware/board/component/brd2608a.slcc b/hardware/board/component/brd2608a.slcc index ad7cef93d1..28628b3eee 100644 --- a/hardware/board/component/brd2608a.slcc +++ b/hardware/board/component/brd2608a.slcc @@ -16,6 +16,7 @@ - name: hardware_board - name: hardware_board_stk - name: hardware_board_from_stk + - name: hardware_board_from_xg26-dk2608a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom @@ -47,7 +48,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: imu_driver_icm40627 - template_contribution: [] @@ -55,7 +56,7 @@ - name: SL_BOARD_NAME value: '"BRD2608A"' - name: SL_BOARD_REV - value: '"A03"' + value: '"A04"' - name: HFXO_FREQ value: 39000000 - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 @@ -64,7 +65,7 @@ - tag: - board:pn:BRD2608 - board:variant:A - - board:revision:A03 + - board:revision:A04 - board:device:efr32mg26b510f3200im68 - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd2709a.slcc b/hardware/board/component/brd2709a.slcc index 9c42d67f89..5a303b840a 100644 --- a/hardware/board/component/brd2709a.slcc +++ b/hardware/board/component/brd2709a.slcc @@ -3,7 +3,7 @@ - label: BRD2709A - package: platform - description: Board support for BRD2709A. -- category: Platform|Board|Starter Kit +- category: Platform|Board|Thunderboard - quality: production - metadata: sbom: @@ -14,8 +14,9 @@ - provides: - name: brd2709a - name: hardware_board - - name: hardware_board_stk - - name: hardware_board_from_stk + - name: hardware_board_tb + - name: hardware_board_from_tb + - name: hardware_board_from_xg26-ek2709a - name: hardware_board_has_vcom - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_39mhz @@ -43,7 +44,7 @@ - name: SL_BOARD_NAME value: '"BRD2709A"' - name: SL_BOARD_REV - value: '"A02"' + value: '"A03"' - name: HFXO_FREQ value: 39000000 - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 @@ -52,7 +53,7 @@ - tag: - board:pn:BRD2709 - board:variant:A - - board:revision:A02 + - board:revision:A03 - board:device:efr32mg26b510f3200im48 - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd2711a.slcc b/hardware/board/component/brd2711a.slcc index 889fbaf01a..04de8d1b7a 100644 --- a/hardware/board/component/brd2711a.slcc +++ b/hardware/board/component/brd2711a.slcc @@ -3,7 +3,7 @@ - label: BRD2711A - package: platform - description: Board support for BRD2711A. -- category: Platform|Board|Starter Kit +- category: Platform|Board|Thunderboard - quality: production - metadata: sbom: @@ -14,8 +14,9 @@ - provides: - name: brd2711a - name: hardware_board - - name: hardware_board_stk - - name: hardware_board_from_stk + - name: hardware_board_tb + - name: hardware_board_from_tb + - name: hardware_board_from_pg26-ek2711a - name: hardware_board_has_vcom - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_39mhz @@ -39,13 +40,13 @@ - name: SL_BOARD_NAME value: '"BRD2711A"' - name: SL_BOARD_REV - value: '"A01"' + value: '"A02"' - name: HFXO_FREQ value: 39000000 - tag: - board:pn:BRD2711 - board:variant:A - - board:revision:A01 + - board:revision:A02 - board:device:efm32pg26b500f3200im68 - hardware:has:vcom - hardware:has:led:2 diff --git a/hardware/board/component/brd2713a.slcc b/hardware/board/component/brd2713a.slcc new file mode 100644 index 0000000000..ccd23063b0 --- /dev/null +++ b/hardware/board/component/brd2713a.slcc @@ -0,0 +1,20 @@ +!!omap +- id: brd2713a +- label: BRD2713A +- package: platform +- description: Board support for BRD2713A. +- category: Platform|Board|Thunderboard +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: brd2713a_revision +- provides: + - name: brd2713a + - name: hardware_board_from_tb + - name: hardware_board_from_mgm260p-ek2713a +- recommends: + - id: brd2713a_a04 +- ui_hints: + visibility: never diff --git a/hardware/board/component/brd2713a_a01.slcc b/hardware/board/component/brd2713a_a01.slcc new file mode 100644 index 0000000000..8aec3029db --- /dev/null +++ b/hardware/board/component/brd2713a_a01.slcc @@ -0,0 +1,56 @@ +!!omap +- id: brd2713a_a01 +- label: BRD2713A rev A01 +- package: platform +- description: Board support for BRD2713A. +- category: Platform|Board|Thunderboard +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: mgm260pb32vna + - name: brd2713a_config +- provides: + - name: brd2713a_revision + - name: brd2713a_a01 + - name: hardware_board + - name: hardware_board_tb + - name: hardware_board_has_vcom + - name: board_config_clock_manager + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2713A"' + - name: SL_BOARD_REV + value: '"A01"' + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD2713 + - board:variant:A + - board:revision:A01 + - board:device:mgm260pb32vna + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:2 + - hardware:has:button:2 diff --git a/hardware/board/component/brd2713a_a02.slcc b/hardware/board/component/brd2713a_a02.slcc new file mode 100644 index 0000000000..f748d0d7fb --- /dev/null +++ b/hardware/board/component/brd2713a_a02.slcc @@ -0,0 +1,56 @@ +!!omap +- id: brd2713a_a02 +- label: BRD2713A rev A02 +- package: platform +- description: Board support for BRD2713A. +- category: Platform|Board|Thunderboard +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: mgm260pb32vna + - name: brd2713a_config +- provides: + - name: brd2713a_revision + - name: brd2713a_a02 + - name: hardware_board + - name: hardware_board_tb + - name: hardware_board_has_vcom + - name: board_config_clock_manager + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2713A"' + - name: SL_BOARD_REV + value: '"A02"' + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD2713 + - board:variant:A + - board:revision:A02 + - board:device:mgm260pb32vna + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:2 + - hardware:has:button:2 diff --git a/hardware/board/component/brd2713a_a03.slcc b/hardware/board/component/brd2713a_a03.slcc new file mode 100644 index 0000000000..c71a655589 --- /dev/null +++ b/hardware/board/component/brd2713a_a03.slcc @@ -0,0 +1,56 @@ +!!omap +- id: brd2713a_a03 +- label: BRD2713A rev A03 +- package: platform +- description: Board support for BRD2713A. +- category: Platform|Board|Thunderboard +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: mgm260pb32vna + - name: brd2713a_config +- provides: + - name: brd2713a_revision + - name: brd2713a_a03 + - name: hardware_board + - name: hardware_board_tb + - name: hardware_board_has_vcom + - name: board_config_clock_manager + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2713A"' + - name: SL_BOARD_REV + value: '"A03"' + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD2713 + - board:variant:A + - board:revision:A03 + - board:device:mgm260pb32vna + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:2 + - hardware:has:button:2 diff --git a/hardware/board/component/brd2713a_a04.slcc b/hardware/board/component/brd2713a_a04.slcc new file mode 100644 index 0000000000..ac55fd6872 --- /dev/null +++ b/hardware/board/component/brd2713a_a04.slcc @@ -0,0 +1,56 @@ +!!omap +- id: brd2713a_a04 +- label: BRD2713A rev A04 +- package: platform +- description: Board support for BRD2713A. +- category: Platform|Board|Thunderboard +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: mgm260pd32vna + - name: brd2713a_config +- provides: + - name: brd2713a_revision + - name: brd2713a_a04 + - name: hardware_board + - name: hardware_board_tb + - name: hardware_board_has_vcom + - name: board_config_clock_manager + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2713A"' + - name: SL_BOARD_REV + value: '"A04"' + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD2713 + - board:variant:A + - board:revision:A04 + - board:device:mgm260pd32vna + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:2 + - hardware:has:button:2 diff --git a/hardware/board/component/brd4109a.slcc b/hardware/board/component/brd4109a.slcc index 66d4975df9..993d04cb94 100644 --- a/hardware/board/component/brd4109a.slcc +++ b/hardware/board/component/brd4109a.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +63,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4110a.slcc b/hardware/board/component/brd4110a.slcc index 616d222fce..f89d119e88 100644 --- a/hardware/board/component/brd4110a.slcc +++ b/hardware/board/component/brd4110a.slcc @@ -20,6 +20,13 @@ - name: hardware_board_from_bg27-rb4110a - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_7 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz @@ -44,7 +51,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4110b.slcc b/hardware/board/component/brd4110b.slcc index 71064d834e..119415a9ef 100644 --- a/hardware/board/component/brd4110b.slcc +++ b/hardware/board/component/brd4110b.slcc @@ -21,6 +21,16 @@ - name: hardware_board_from_xg27-pk6018a - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager @@ -45,7 +55,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4111a.slcc b/hardware/board/component/brd4111a.slcc index f892d51729..61dc4943bc 100644 --- a/hardware/board/component/brd4111a.slcc +++ b/hardware/board/component/brd4111a.slcc @@ -20,6 +20,13 @@ - name: hardware_board_from_bg27-rb4111a - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_7 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz @@ -44,7 +51,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4111b.slcc b/hardware/board/component/brd4111b.slcc index cba0c8b27d..2a01047391 100644 --- a/hardware/board/component/brd4111b.slcc +++ b/hardware/board/component/brd4111b.slcc @@ -21,6 +21,16 @@ - name: hardware_board_from_xg27-pk6019a - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager @@ -45,7 +55,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4113a.slcc b/hardware/board/component/brd4113a.slcc index 6a64c2993c..6c0b2b8595 100644 --- a/hardware/board/component/brd4113a.slcc +++ b/hardware/board/component/brd4113a.slcc @@ -19,6 +19,10 @@ - name: hardware_board_from_stk - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_7 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz @@ -43,7 +47,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4115a.slcc b/hardware/board/component/brd4115a.slcc index a4a4021a20..0b81eb6e40 100644 --- a/hardware/board/component/brd4115a.slcc +++ b/hardware/board/component/brd4115a.slcc @@ -20,6 +20,16 @@ - name: hardware_board_from_xg24-rb4115a - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager @@ -44,7 +54,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4115b.slcc b/hardware/board/component/brd4115b.slcc index ed45f2427a..fa50422011 100644 --- a/hardware/board/component/brd4115b.slcc +++ b/hardware/board/component/brd4115b.slcc @@ -20,6 +20,16 @@ - name: hardware_board_from_xg24-rb4115b - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager @@ -44,7 +54,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4116a.slcc b/hardware/board/component/brd4116a.slcc index 6bcb64c536..8a2b888b9b 100644 --- a/hardware/board/component/brd4116a.slcc +++ b/hardware/board/component/brd4116a.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4117a.slcc b/hardware/board/component/brd4117a.slcc index c6f8463b6d..ec0923ee87 100644 --- a/hardware/board/component/brd4117a.slcc +++ b/hardware/board/component/brd4117a.slcc @@ -24,6 +24,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4118a.slcc b/hardware/board/component/brd4118a.slcc index 29bc99e9bb..d21c881d95 100644 --- a/hardware/board/component/brd4118a.slcc +++ b/hardware/board/component/brd4118a.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4120a.slcc b/hardware/board/component/brd4120a.slcc new file mode 100644 index 0000000000..22919b62dd --- /dev/null +++ b/hardware/board/component/brd4120a.slcc @@ -0,0 +1,103 @@ +!!omap +- id: brd4120a +- label: BRD4120A +- package: platform +- description: Board support for BRD4120A. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: efr32mg26b410f3200im68 + - name: brd4120a_config + - name: hardware_board_mainboard +- provides: + - name: brd4120a + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_from_stk + - name: hardware_board_from_xg26-pk6028a + - name: hardware_board_from_xg26-rb4120a + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_supports_wstk_lcd + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_spi + - name: hardware_board_has_uart + - name: hardware_board_has_i2c + - name: board_config_clock_manager + - name: hardware_board_has_hfxo_freq_39mhz + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - id: joystick + - id: simple_button + instance: + - btn0 + - btn1 + - id: mx25_flash_shutdown_eusart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: + - name: board_default_init + value: sl_board_disable_vcom() +- define: + - name: SL_BOARD_NAME + value: '"BRD4120A"' + - name: SL_BOARD_REV + value: '"A05"' + - name: HFXO_FREQ + value: 39000000 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4120 + - board:variant:A + - board:revision:A05 + - board:device:efr32mg26b410f3200im68 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:joystick:skrhaae010 + - hardware:has:button:2 + - hardware:has:memory:spi:mx25r8035f + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/brd4121a.slcc b/hardware/board/component/brd4121a.slcc new file mode 100644 index 0000000000..36e789cfde --- /dev/null +++ b/hardware/board/component/brd4121a.slcc @@ -0,0 +1,102 @@ +!!omap +- id: brd4121a +- label: BRD4121A +- package: platform +- description: Board support for BRD4121A. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: efr32mg26b420f3200im68 + - name: brd4121a_config + - name: hardware_board_mainboard +- provides: + - name: brd4121a + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_from_stk + - name: hardware_board_from_xg26-rb4121a + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_supports_wstk_lcd + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_spi + - name: hardware_board_has_uart + - name: hardware_board_has_i2c + - name: board_config_clock_manager + - name: hardware_board_has_hfxo_freq_39mhz + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - id: joystick + - id: simple_button + instance: + - btn0 + - btn1 + - id: mx25_flash_shutdown_eusart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: + - name: board_default_init + value: sl_board_disable_vcom() +- define: + - name: SL_BOARD_NAME + value: '"BRD4121A"' + - name: SL_BOARD_REV + value: '"A05"' + - name: HFXO_FREQ + value: 39000000 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4121 + - board:variant:A + - board:revision:A05 + - board:device:efr32mg26b420f3200im68 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:joystick:skrhaae010 + - hardware:has:button:2 + - hardware:has:memory:spi:mx25r8035f + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/brd4171a.slcc b/hardware/board/component/brd4171a.slcc index c01faa9332..db64b5d3dd 100644 --- a/hardware/board/component/brd4171a.slcc +++ b/hardware/board/component/brd4171a.slcc @@ -21,6 +21,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4176a.slcc b/hardware/board/component/brd4176a.slcc index b13632e5c0..7134c57322 100644 --- a/hardware/board/component/brd4176a.slcc +++ b/hardware/board/component/brd4176a.slcc @@ -19,6 +19,20 @@ - name: hardware_board_from_stk - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4179b.slcc b/hardware/board/component/brd4179b.slcc index 0ab4655d5b..5a5685b7de 100644 --- a/hardware/board/component/brd4179b.slcc +++ b/hardware/board/component/brd4179b.slcc @@ -20,6 +20,12 @@ - name: hardware_board_from_slwrb4179b - name: hardware_board_has_efp - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4180a.slcc b/hardware/board/component/brd4180a.slcc index b9f95f1d8d..6f8d06c697 100644 --- a/hardware/board/component/brd4180a.slcc +++ b/hardware/board/component/brd4180a.slcc @@ -21,6 +21,16 @@ - name: hardware_board_from_slwstk6006a - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4180b.slcc b/hardware/board/component/brd4180b.slcc index 9cf27701ee..50cbd8da18 100644 --- a/hardware/board/component/brd4180b.slcc +++ b/hardware/board/component/brd4180b.slcc @@ -21,6 +21,16 @@ - name: hardware_board_from_slwstk6006a - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4181a.slcc b/hardware/board/component/brd4181a.slcc index b6e5cf0da6..418ab1cf55 100644 --- a/hardware/board/component/brd4181a.slcc +++ b/hardware/board/component/brd4181a.slcc @@ -21,6 +21,16 @@ - name: hardware_board_from_slwstk6006a - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4181b.slcc b/hardware/board/component/brd4181b.slcc index aac3572263..81183b1368 100644 --- a/hardware/board/component/brd4181b.slcc +++ b/hardware/board/component/brd4181b.slcc @@ -22,6 +22,16 @@ - name: hardware_board_from_slwstk6023a - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4181c.slcc b/hardware/board/component/brd4181c.slcc index 0c14573f74..543939b607 100644 --- a/hardware/board/component/brd4181c.slcc +++ b/hardware/board/component/brd4181c.slcc @@ -20,6 +20,16 @@ - name: hardware_board_from_slwrb4181c - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4182a_a00.slcc b/hardware/board/component/brd4182a_a00.slcc index 7c126513b8..32e517f018 100644 --- a/hardware/board/component/brd4182a_a00.slcc +++ b/hardware/board/component/brd4182a_a00.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_a01.slcc b/hardware/board/component/brd4182a_a01.slcc index 5777f0b0d7..737dd47d85 100644 --- a/hardware/board/component/brd4182a_a01.slcc +++ b/hardware/board/component/brd4182a_a01.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_a02.slcc b/hardware/board/component/brd4182a_a02.slcc index 4bac40ea04..4ae906a574 100644 --- a/hardware/board/component/brd4182a_a02.slcc +++ b/hardware/board/component/brd4182a_a02.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_b00.slcc b/hardware/board/component/brd4182a_b00.slcc index 0b0c9abcc5..757accb0b6 100644 --- a/hardware/board/component/brd4182a_b00.slcc +++ b/hardware/board/component/brd4182a_b00.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_b01.slcc b/hardware/board/component/brd4182a_b01.slcc index c880d372e1..71fe0bc501 100644 --- a/hardware/board/component/brd4182a_b01.slcc +++ b/hardware/board/component/brd4182a_b01.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_b02.slcc b/hardware/board/component/brd4182a_b02.slcc index 53ede0d32f..0c09509bfe 100644 --- a/hardware/board/component/brd4182a_b02.slcc +++ b/hardware/board/component/brd4182a_b02.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_b03.slcc b/hardware/board/component/brd4182a_b03.slcc index e8d87f6ff8..d224a7a64b 100644 --- a/hardware/board/component/brd4182a_b03.slcc +++ b/hardware/board/component/brd4182a_b03.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_b04.slcc b/hardware/board/component/brd4182a_b04.slcc index c316c8d604..ae24336ab8 100644 --- a/hardware/board/component/brd4182a_b04.slcc +++ b/hardware/board/component/brd4182a_b04.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_b05.slcc b/hardware/board/component/brd4182a_b05.slcc index 37308a601a..673f35689f 100644 --- a/hardware/board/component/brd4182a_b05.slcc +++ b/hardware/board/component/brd4182a_b05.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4182a_b06.slcc b/hardware/board/component/brd4182a_b06.slcc index ffad29138f..f42c8f36bc 100644 --- a/hardware/board/component/brd4182a_b06.slcc +++ b/hardware/board/component/brd4182a_b06.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4183a.slcc b/hardware/board/component/brd4183a.slcc index 9ad1f138b6..88cdf2ef8d 100644 --- a/hardware/board/component/brd4183a.slcc +++ b/hardware/board/component/brd4183a.slcc @@ -21,6 +21,10 @@ - name: hardware_board_from_slwstk6021a - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4183b.slcc b/hardware/board/component/brd4183b.slcc index d512986f05..e00fea8139 100644 --- a/hardware/board/component/brd4183b.slcc +++ b/hardware/board/component/brd4183b.slcc @@ -19,6 +19,10 @@ - name: hardware_board_from_stk - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4183c.slcc b/hardware/board/component/brd4183c.slcc index 709d3c27ce..5ae48c8c54 100644 --- a/hardware/board/component/brd4183c.slcc +++ b/hardware/board/component/brd4183c.slcc @@ -19,6 +19,10 @@ - name: hardware_board_from_stk - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_7 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4184a_a00.slcc b/hardware/board/component/brd4184a_a00.slcc index 916b0379f3..053bda683c 100644 --- a/hardware/board/component/brd4184a_a00.slcc +++ b/hardware/board/component/brd4184a_a00.slcc @@ -20,6 +20,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4184a_a01.slcc b/hardware/board/component/brd4184a_a01.slcc index 8b2c80c755..7def0dc041 100644 --- a/hardware/board/component/brd4184a_a01.slcc +++ b/hardware/board/component/brd4184a_a01.slcc @@ -20,6 +20,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4184a_a02.slcc b/hardware/board/component/brd4184a_a02.slcc index 932ab789a7..8b657e0906 100644 --- a/hardware/board/component/brd4184a_a02.slcc +++ b/hardware/board/component/brd4184a_a02.slcc @@ -20,6 +20,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4184b.slcc b/hardware/board/component/brd4184b.slcc index 879ab03b82..f3001f76b0 100644 --- a/hardware/board/component/brd4184b.slcc +++ b/hardware/board/component/brd4184b.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4185a.slcc b/hardware/board/component/brd4185a.slcc index a30ca21999..d7405ba73e 100644 --- a/hardware/board/component/brd4185a.slcc +++ b/hardware/board/component/brd4185a.slcc @@ -23,6 +23,18 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4186a.slcc b/hardware/board/component/brd4186a.slcc index d5a62886fc..8f8a7d114a 100644 --- a/hardware/board/component/brd4186a.slcc +++ b/hardware/board/component/brd4186a.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4186b.slcc b/hardware/board/component/brd4186b.slcc index e8cae6a23f..092d428bf3 100644 --- a/hardware/board/component/brd4186b.slcc +++ b/hardware/board/component/brd4186b.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4186c.slcc b/hardware/board/component/brd4186c.slcc index 5c20a0fe8a..6988c1ab90 100644 --- a/hardware/board/component/brd4186c.slcc +++ b/hardware/board/component/brd4186c.slcc @@ -24,6 +24,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4187a.slcc b/hardware/board/component/brd4187a.slcc index 22b9996d63..b53d396fdc 100644 --- a/hardware/board/component/brd4187a.slcc +++ b/hardware/board/component/brd4187a.slcc @@ -24,6 +24,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4187b.slcc b/hardware/board/component/brd4187b.slcc index c40da0c318..a48fb9738c 100644 --- a/hardware/board/component/brd4187b.slcc +++ b/hardware/board/component/brd4187b.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -52,7 +66,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4187c.slcc b/hardware/board/component/brd4187c.slcc index 3dd374e10e..afa3ec8ebc 100644 --- a/hardware/board/component/brd4187c.slcc +++ b/hardware/board/component/brd4187c.slcc @@ -25,6 +25,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -55,7 +69,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4188a_a00.slcc b/hardware/board/component/brd4188a_a00.slcc index 1acbf4ad79..f08b64bc07 100644 --- a/hardware/board/component/brd4188a_a00.slcc +++ b/hardware/board/component/brd4188a_a00.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4188a_a01.slcc b/hardware/board/component/brd4188a_a01.slcc index 3f059d33ff..3f0532c789 100644 --- a/hardware/board/component/brd4188a_a01.slcc +++ b/hardware/board/component/brd4188a_a01.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4188a_a02.slcc b/hardware/board/component/brd4188a_a02.slcc index 87a8d17604..743b370613 100644 --- a/hardware/board/component/brd4188a_a02.slcc +++ b/hardware/board/component/brd4188a_a02.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4188b.slcc b/hardware/board/component/brd4188b.slcc index 2b1d3d7d4a..bfbee9dd6c 100644 --- a/hardware/board/component/brd4188b.slcc +++ b/hardware/board/component/brd4188b.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4194a.slcc b/hardware/board/component/brd4194a.slcc index 569371cec7..2fa4d15e1b 100644 --- a/hardware/board/component/brd4194a.slcc +++ b/hardware/board/component/brd4194a.slcc @@ -24,6 +24,17 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -55,7 +66,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4195a.slcc b/hardware/board/component/brd4195a.slcc index 5119722f8c..f080f9355a 100644 --- a/hardware/board/component/brd4195a.slcc +++ b/hardware/board/component/brd4195a.slcc @@ -20,6 +20,16 @@ - name: hardware_board_from_xg21-rb4195a - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4195b.slcc b/hardware/board/component/brd4195b.slcc index 5158674d2b..f28cd125eb 100644 --- a/hardware/board/component/brd4195b.slcc +++ b/hardware/board/component/brd4195b.slcc @@ -21,6 +21,16 @@ - name: hardware_board_from_xg21-rb4195b - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a00.slcc b/hardware/board/component/brd4196a_a00.slcc index 5178567886..774b495dc1 100644 --- a/hardware/board/component/brd4196a_a00.slcc +++ b/hardware/board/component/brd4196a_a00.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a01.slcc b/hardware/board/component/brd4196a_a01.slcc index 576d5f00b2..215d05a9c4 100644 --- a/hardware/board/component/brd4196a_a01.slcc +++ b/hardware/board/component/brd4196a_a01.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a02.slcc b/hardware/board/component/brd4196a_a02.slcc index 3592d8c1a6..c8eb153586 100644 --- a/hardware/board/component/brd4196a_a02.slcc +++ b/hardware/board/component/brd4196a_a02.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a03.slcc b/hardware/board/component/brd4196a_a03.slcc index ec0530a4b0..9082f0fc35 100644 --- a/hardware/board/component/brd4196a_a03.slcc +++ b/hardware/board/component/brd4196a_a03.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a04.slcc b/hardware/board/component/brd4196a_a04.slcc index d2ba990dc8..59fc4e4bd4 100644 --- a/hardware/board/component/brd4196a_a04.slcc +++ b/hardware/board/component/brd4196a_a04.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a05.slcc b/hardware/board/component/brd4196a_a05.slcc index dd6e98bfc6..a0464a421e 100644 --- a/hardware/board/component/brd4196a_a05.slcc +++ b/hardware/board/component/brd4196a_a05.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a06.slcc b/hardware/board/component/brd4196a_a06.slcc index 2f5b4caaa8..ff28b16e2d 100644 --- a/hardware/board/component/brd4196a_a06.slcc +++ b/hardware/board/component/brd4196a_a06.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a07.slcc b/hardware/board/component/brd4196a_a07.slcc index 60b41f1df2..af31697794 100644 --- a/hardware/board/component/brd4196a_a07.slcc +++ b/hardware/board/component/brd4196a_a07.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196a_a08.slcc b/hardware/board/component/brd4196a_a08.slcc index 57fb4014fd..41c2b99ab2 100644 --- a/hardware/board/component/brd4196a_a08.slcc +++ b/hardware/board/component/brd4196a_a08.slcc @@ -19,6 +19,16 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4196b.slcc b/hardware/board/component/brd4196b.slcc index 72c6dcaadd..965a35df9d 100644 --- a/hardware/board/component/brd4196b.slcc +++ b/hardware/board/component/brd4196b.slcc @@ -21,6 +21,16 @@ - name: hardware_board_from_xg21-rb4196b - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4197a_a00.slcc b/hardware/board/component/brd4197a_a00.slcc index 6c9e35cfc9..333651d603 100644 --- a/hardware/board/component/brd4197a_a00.slcc +++ b/hardware/board/component/brd4197a_a00.slcc @@ -22,6 +22,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_si446x_radio + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4197a_a01.slcc b/hardware/board/component/brd4197a_a01.slcc index 8a2dcaf313..66f5fcc5dc 100644 --- a/hardware/board/component/brd4197a_a01.slcc +++ b/hardware/board/component/brd4197a_a01.slcc @@ -22,6 +22,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_si446x_radio + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4198a.slcc b/hardware/board/component/brd4198a.slcc index 9f9913df2b..df8c0ca285 100644 --- a/hardware/board/component/brd4198a.slcc +++ b/hardware/board/component/brd4198a.slcc @@ -25,6 +25,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -56,7 +70,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4198b.slcc b/hardware/board/component/brd4198b.slcc index 8ba54025dc..9d38e7d951 100644 --- a/hardware/board/component/brd4198b.slcc +++ b/hardware/board/component/brd4198b.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4199b.slcc b/hardware/board/component/brd4199b.slcc index 8496b462e2..fa891e3ab0 100644 --- a/hardware/board/component/brd4199b.slcc +++ b/hardware/board/component/brd4199b.slcc @@ -36,7 +36,7 @@ instance: - vcom - id: bootloader_uart_driver - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - template_contribution: - name: board_default_init diff --git a/hardware/board/component/brd4204a.slcc b/hardware/board/component/brd4204a.slcc index 80b76890e4..89cd9e95af 100644 --- a/hardware/board/component/brd4204a.slcc +++ b/hardware/board/component/brd4204a.slcc @@ -22,6 +22,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4204b.slcc b/hardware/board/component/brd4204b.slcc index e648196780..7ea1638a02 100644 --- a/hardware/board/component/brd4204b.slcc +++ b/hardware/board/component/brd4204b.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4204c.slcc b/hardware/board/component/brd4204c.slcc index 098959a14c..eaf7c46cd5 100644 --- a/hardware/board/component/brd4204c.slcc +++ b/hardware/board/component/brd4204c.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4204d.slcc b/hardware/board/component/brd4204d.slcc index 01ae157c43..ec1e43b4ac 100644 --- a/hardware/board/component/brd4204d.slcc +++ b/hardware/board/component/brd4204d.slcc @@ -26,6 +26,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -57,7 +71,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4205a.slcc b/hardware/board/component/brd4205a.slcc index 1b49c153d3..5d26c1b394 100644 --- a/hardware/board/component/brd4205a.slcc +++ b/hardware/board/component/brd4205a.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4205b.slcc b/hardware/board/component/brd4205b.slcc index 1ab048a80f..f155c79cd4 100644 --- a/hardware/board/component/brd4205b.slcc +++ b/hardware/board/component/brd4205b.slcc @@ -26,6 +26,20 @@ - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -57,7 +71,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4210a.slcc b/hardware/board/component/brd4210a.slcc index 2254eee306..9501d861ce 100644 --- a/hardware/board/component/brd4210a.slcc +++ b/hardware/board/component/brd4210a.slcc @@ -24,6 +24,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -55,7 +69,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4263a.slcc b/hardware/board/component/brd4263a.slcc index d243fbf044..593574e866 100644 --- a/hardware/board/component/brd4263a.slcc +++ b/hardware/board/component/brd4263a.slcc @@ -22,6 +22,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +66,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4263b.slcc b/hardware/board/component/brd4263b.slcc index 33e5a2bf1d..ce31c66dcc 100644 --- a/hardware/board/component/brd4263b.slcc +++ b/hardware/board/component/brd4263b.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4263c.slcc b/hardware/board/component/brd4263c.slcc index c7ba967805..6a31658cac 100644 --- a/hardware/board/component/brd4263c.slcc +++ b/hardware/board/component/brd4263c.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4264a.slcc b/hardware/board/component/brd4264a.slcc index 565b8927fb..da068f4650 100644 --- a/hardware/board/component/brd4264a.slcc +++ b/hardware/board/component/brd4264a.slcc @@ -22,6 +22,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +66,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4264b.slcc b/hardware/board/component/brd4264b.slcc index 2565a7534b..ebb81c49ca 100644 --- a/hardware/board/component/brd4264b.slcc +++ b/hardware/board/component/brd4264b.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4264c.slcc b/hardware/board/component/brd4264c.slcc index 113db491a0..a24985db2d 100644 --- a/hardware/board/component/brd4264c.slcc +++ b/hardware/board/component/brd4264c.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -54,7 +68,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4264v.slcc b/hardware/board/component/brd4264v.slcc index 468e11d6a0..bccc5c8265 100644 --- a/hardware/board/component/brd4264v.slcc +++ b/hardware/board/component/brd4264v.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4265a.slcc b/hardware/board/component/brd4265a.slcc index f8edc60ddc..961088f81c 100644 --- a/hardware/board/component/brd4265a.slcc +++ b/hardware/board/component/brd4265a.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4265b.slcc b/hardware/board/component/brd4265b.slcc index cb2138a778..2574b8d0b0 100644 --- a/hardware/board/component/brd4265b.slcc +++ b/hardware/board/component/brd4265b.slcc @@ -23,6 +23,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4270a_a00.slcc b/hardware/board/component/brd4270a_a00.slcc index d4c23c2a3d..79e2073369 100644 --- a/hardware/board/component/brd4270a_a00.slcc +++ b/hardware/board/component/brd4270a_a00.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4270a_a01.slcc b/hardware/board/component/brd4270a_a01.slcc index e0c1c36bfd..4a25f69c4e 100644 --- a/hardware/board/component/brd4270a_a01.slcc +++ b/hardware/board/component/brd4270a_a01.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4270a_a02.slcc b/hardware/board/component/brd4270a_a02.slcc index 8a9d424812..c98cb31eea 100644 --- a/hardware/board/component/brd4270a_a02.slcc +++ b/hardware/board/component/brd4270a_a02.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4270a_a03.slcc b/hardware/board/component/brd4270a_a03.slcc index 90465c3955..8a73f017d9 100644 --- a/hardware/board/component/brd4270a_a03.slcc +++ b/hardware/board/component/brd4270a_a03.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4270a_a04.slcc b/hardware/board/component/brd4270a_a04.slcc index 4da53f0a98..dde0e6ab42 100644 --- a/hardware/board/component/brd4270a_a04.slcc +++ b/hardware/board/component/brd4270a_a04.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4270b.slcc b/hardware/board/component/brd4270b.slcc index e42fda1cc4..8c75476af9 100644 --- a/hardware/board/component/brd4270b.slcc +++ b/hardware/board/component/brd4270b.slcc @@ -23,6 +23,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4271a.slcc b/hardware/board/component/brd4271a.slcc index 61c560552e..eed04b757e 100644 --- a/hardware/board/component/brd4271a.slcc +++ b/hardware/board/component/brd4271a.slcc @@ -23,6 +23,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4272a.slcc b/hardware/board/component/brd4272a.slcc index fb4c162c3a..f743bcef6c 100644 --- a/hardware/board/component/brd4272a.slcc +++ b/hardware/board/component/brd4272a.slcc @@ -21,6 +21,19 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4276a.slcc b/hardware/board/component/brd4276a.slcc index 2c66cfaf42..4449559454 100644 --- a/hardware/board/component/brd4276a.slcc +++ b/hardware/board/component/brd4276a.slcc @@ -21,6 +21,16 @@ - name: hardware_board_has_fem - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4308a_a00.slcc b/hardware/board/component/brd4308a_a00.slcc index b5edbb716d..c24a49735c 100644 --- a/hardware/board/component/brd4308a_a00.slcc +++ b/hardware/board/component/brd4308a_a00.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308a_a01.slcc b/hardware/board/component/brd4308a_a01.slcc index 24b74fba58..494bdfbb3b 100644 --- a/hardware/board/component/brd4308a_a01.slcc +++ b/hardware/board/component/brd4308a_a01.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308a_a02.slcc b/hardware/board/component/brd4308a_a02.slcc index d76b377c63..13e748205c 100644 --- a/hardware/board/component/brd4308a_a02.slcc +++ b/hardware/board/component/brd4308a_a02.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308a_a03.slcc b/hardware/board/component/brd4308a_a03.slcc index 9d80150365..7735443bce 100644 --- a/hardware/board/component/brd4308a_a03.slcc +++ b/hardware/board/component/brd4308a_a03.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308b_a00.slcc b/hardware/board/component/brd4308b_a00.slcc index d48b7de83e..7d1f7f5962 100644 --- a/hardware/board/component/brd4308b_a00.slcc +++ b/hardware/board/component/brd4308b_a00.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308b_a01.slcc b/hardware/board/component/brd4308b_a01.slcc index 6f1ebe8228..25d45ec1c1 100644 --- a/hardware/board/component/brd4308b_a01.slcc +++ b/hardware/board/component/brd4308b_a01.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308b_a02.slcc b/hardware/board/component/brd4308b_a02.slcc index de1df0753b..e4c42f9692 100644 --- a/hardware/board/component/brd4308b_a02.slcc +++ b/hardware/board/component/brd4308b_a02.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308b_a03.slcc b/hardware/board/component/brd4308b_a03.slcc index 0c69fbc09f..adbb428e12 100644 --- a/hardware/board/component/brd4308b_a03.slcc +++ b/hardware/board/component/brd4308b_a03.slcc @@ -19,6 +19,14 @@ - name: hardware_board_rb - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308c.slcc b/hardware/board/component/brd4308c.slcc index f125d2f9f6..605f91995c 100644 --- a/hardware/board/component/brd4308c.slcc +++ b/hardware/board/component/brd4308c.slcc @@ -21,6 +21,14 @@ - name: hardware_board_from_slwstk6102a - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4308d.slcc b/hardware/board/component/brd4308d.slcc index 97da1fa2ec..135d4c81bb 100644 --- a/hardware/board/component/brd4308d.slcc +++ b/hardware/board/component/brd4308d.slcc @@ -21,6 +21,14 @@ - name: hardware_board_from_slwstk6102a - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: board_config_clock_manager diff --git a/hardware/board/component/brd4309a.slcc b/hardware/board/component/brd4309a.slcc index 1b86c0b8e1..4d9c1e2c87 100644 --- a/hardware/board/component/brd4309a.slcc +++ b/hardware/board/component/brd4309a.slcc @@ -19,6 +19,10 @@ - name: hardware_board_from_stk - name: hardware_board_from_slwrb4309a - name: hardware_board_has_vcom + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_9 - name: hardware_board_has_uart - name: hardware_board_supports_rf_band_2400 - name: hardware_board_supports_1_rf_band diff --git a/hardware/board/component/brd4309b.slcc b/hardware/board/component/brd4309b.slcc index 49c3a6f0e8..73bf180675 100644 --- a/hardware/board/component/brd4309b.slcc +++ b/hardware/board/component/brd4309b.slcc @@ -19,6 +19,10 @@ - name: hardware_board_from_stk - name: hardware_board_from_slwrb4309b - name: hardware_board_has_vcom + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_9 - name: hardware_board_has_uart - name: hardware_board_supports_rf_band_2400 - name: hardware_board_supports_1_rf_band diff --git a/hardware/board/component/brd4310a.slcc b/hardware/board/component/brd4310a.slcc index b72dab4825..63c5f63963 100644 --- a/hardware/board/component/brd4310a.slcc +++ b/hardware/board/component/brd4310a.slcc @@ -24,6 +24,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4311a_a00.slcc b/hardware/board/component/brd4311a_a00.slcc index f594689449..f119bd44ed 100644 --- a/hardware/board/component/brd4311a_a00.slcc +++ b/hardware/board/component/brd4311a_a00.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4311a_a01.slcc b/hardware/board/component/brd4311a_a01.slcc index cd779a1a92..0497c3e42c 100644 --- a/hardware/board/component/brd4311a_a01.slcc +++ b/hardware/board/component/brd4311a_a01.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4311a_a02.slcc b/hardware/board/component/brd4311a_a02.slcc index 687264d32e..f540089a35 100644 --- a/hardware/board/component/brd4311a_a02.slcc +++ b/hardware/board/component/brd4311a_a02.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4311a_a03.slcc b/hardware/board/component/brd4311a_a03.slcc index 25c337e6cc..e4c6e262db 100644 --- a/hardware/board/component/brd4311a_a03.slcc +++ b/hardware/board/component/brd4311a_a03.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4311a_a04.slcc b/hardware/board/component/brd4311a_a04.slcc index 58f02736dc..8f2152f93e 100644 --- a/hardware/board/component/brd4311a_a04.slcc +++ b/hardware/board/component/brd4311a_a04.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4311a_a05.slcc b/hardware/board/component/brd4311a_a05.slcc index 1ce90ad8a3..8daab74699 100644 --- a/hardware/board/component/brd4311a_a05.slcc +++ b/hardware/board/component/brd4311a_a05.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4311b.slcc b/hardware/board/component/brd4311b.slcc index 6b4e9bc1c4..ad24584fb3 100644 --- a/hardware/board/component/brd4311b.slcc +++ b/hardware/board/component/brd4311b.slcc @@ -24,6 +24,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4312a.slcc b/hardware/board/component/brd4312a.slcc index 374c319474..c709e29066 100644 --- a/hardware/board/component/brd4312a.slcc +++ b/hardware/board/component/brd4312a.slcc @@ -23,6 +23,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4316a.slcc b/hardware/board/component/brd4316a.slcc index dcaf9b1c8c..7ac222c805 100644 --- a/hardware/board/component/brd4316a.slcc +++ b/hardware/board/component/brd4316a.slcc @@ -23,6 +23,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -51,7 +61,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4317a.slcc b/hardware/board/component/brd4317a.slcc index 7df75db418..376b99ee66 100644 --- a/hardware/board/component/brd4317a.slcc +++ b/hardware/board/component/brd4317a.slcc @@ -23,6 +23,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -51,7 +61,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4318a_a00.slcc b/hardware/board/component/brd4318a_a00.slcc index 9329048624..3a6f0f6fd3 100644 --- a/hardware/board/component/brd4318a_a00.slcc +++ b/hardware/board/component/brd4318a_a00.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -50,7 +64,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4318a_a01.slcc b/hardware/board/component/brd4318a_a01.slcc index 3aa54c08de..3f6e543aca 100644 --- a/hardware/board/component/brd4318a_a01.slcc +++ b/hardware/board/component/brd4318a_a01.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -50,7 +64,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4318a_a02.slcc b/hardware/board/component/brd4318a_a02.slcc index d182db02c5..bb1aa3999c 100644 --- a/hardware/board/component/brd4318a_a02.slcc +++ b/hardware/board/component/brd4318a_a02.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -50,7 +64,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4318a_a03.slcc b/hardware/board/component/brd4318a_a03.slcc index 8012dfdd34..8a91e30b9c 100644 --- a/hardware/board/component/brd4318a_a03.slcc +++ b/hardware/board/component/brd4318a_a03.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -50,7 +64,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4318a_a04.slcc b/hardware/board/component/brd4318a_a04.slcc index 975d4fa0c7..446aae08b3 100644 --- a/hardware/board/component/brd4318a_a04.slcc +++ b/hardware/board/component/brd4318a_a04.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -50,7 +64,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4319a_a00.slcc b/hardware/board/component/brd4319a_a00.slcc index e6df55dc23..26be606ff1 100644 --- a/hardware/board/component/brd4319a_a00.slcc +++ b/hardware/board/component/brd4319a_a00.slcc @@ -18,6 +18,10 @@ - name: hardware_board - name: hardware_board_rb - name: hardware_board_has_vcom + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_12 - name: hardware_board_has_uart - name: hardware_board_supports_rf_band_2400 - name: hardware_board_supports_1_rf_band diff --git a/hardware/board/component/brd4319a_a01.slcc b/hardware/board/component/brd4319a_a01.slcc index 6eb4f40c3c..d1585d7ece 100644 --- a/hardware/board/component/brd4319a_a01.slcc +++ b/hardware/board/component/brd4319a_a01.slcc @@ -18,6 +18,10 @@ - name: hardware_board - name: hardware_board_rb - name: hardware_board_has_vcom + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_12 - name: hardware_board_has_uart - name: hardware_board_supports_rf_band_2400 - name: hardware_board_supports_1_rf_band diff --git a/hardware/board/component/brd4328a.slcc b/hardware/board/component/brd4328a.slcc index 4bf3a91bfe..19fbf1ce98 100644 --- a/hardware/board/component/brd4328a.slcc +++ b/hardware/board/component/brd4328a.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -55,7 +69,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4328b.slcc b/hardware/board/component/brd4328b.slcc index 476690d3aa..657fb8446b 100644 --- a/hardware/board/component/brd4328b.slcc +++ b/hardware/board/component/brd4328b.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -55,7 +69,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4329a.slcc b/hardware/board/component/brd4329a.slcc index aa8365344e..ca8563499b 100644 --- a/hardware/board/component/brd4329a.slcc +++ b/hardware/board/component/brd4329a.slcc @@ -19,6 +19,10 @@ - name: hardware_board_from_stk - name: hardware_board_from_xgm210-rb4329a - name: hardware_board_has_vcom + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_9 - name: hardware_board_has_uart - name: hardware_board_supports_rf_band_2400 - name: hardware_board_supports_1_rf_band diff --git a/hardware/board/component/brd4332a.slcc b/hardware/board/component/brd4332a.slcc index 96e6708582..fd32a50335 100644 --- a/hardware/board/component/brd4332a.slcc +++ b/hardware/board/component/brd4332a.slcc @@ -20,6 +20,8 @@ - name: hardware_board_from_kg100s-pk6130a - name: hardware_board_from_kg100s-rb4332a - name: hardware_board_has_vcom + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_15 - name: hardware_board_has_i2c - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4335a.slcc b/hardware/board/component/brd4335a.slcc index 673acc6151..1ef19dd46c 100644 --- a/hardware/board/component/brd4335a.slcc +++ b/hardware/board/component/brd4335a.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -51,7 +65,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: diff --git a/hardware/board/component/brd4337a.slcc b/hardware/board/component/brd4337a.slcc index e5881f16fb..82675fe253 100644 --- a/hardware/board/component/brd4337a.slcc +++ b/hardware/board/component/brd4337a.slcc @@ -19,6 +19,10 @@ - name: hardware_board_from_stk - name: hardware_board_from_xgm240-rb4337a - name: hardware_board_has_vcom + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_12 - name: hardware_board_has_uart - name: hardware_board_supports_rf_band_2400 - name: hardware_board_supports_1_rf_band diff --git a/hardware/board/component/brd4350a.slcc b/hardware/board/component/brd4350a.slcc index eaede92daf..265ad099de 100644 --- a/hardware/board/component/brd4350a.slcc +++ b/hardware/board/component/brd4350a.slcc @@ -15,6 +15,6 @@ - name: hardware_board_from_stk - name: hardware_board_from_mgm260p-rb4350a - recommends: - - id: brd4350a_a03 + - id: brd4350a_a05 - ui_hints: visibility: never diff --git a/hardware/board/component/brd4350a_a01.slcc b/hardware/board/component/brd4350a_a01.slcc index 75fe57ee7a..466b18e499 100644 --- a/hardware/board/component/brd4350a_a01.slcc +++ b/hardware/board/component/brd4350a_a01.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -31,11 +45,16 @@ - name: hardware_board_default_rf_band - name: hardware_board_default_rf_band_2400 - recommends: - - id: brd4001a + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver - id: i2cspm instance: - sensor - id: ls013b7dh03 + - id: memlcd_usart - id: simple_led instance: - led0 @@ -45,6 +64,7 @@ instance: - btn0 - btn1 + - id: bootloader_spi_peripheral_usart_driver - template_contribution: - name: board_default_init value: sl_board_disable_vcom() diff --git a/hardware/board/component/brd4350a_a02.slcc b/hardware/board/component/brd4350a_a02.slcc index 83101c40ba..7a1e36bc9b 100644 --- a/hardware/board/component/brd4350a_a02.slcc +++ b/hardware/board/component/brd4350a_a02.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4350a_a03.slcc b/hardware/board/component/brd4350a_a03.slcc index 94248eb74e..629ad1aabe 100644 --- a/hardware/board/component/brd4350a_a03.slcc +++ b/hardware/board/component/brd4350a_a03.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4350a_a04.slcc b/hardware/board/component/brd4350a_a04.slcc index 84626b7a68..d7ec44f79d 100644 --- a/hardware/board/component/brd4350a_a04.slcc +++ b/hardware/board/component/brd4350a_a04.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4350a_a05.slcc b/hardware/board/component/brd4350a_a05.slcc new file mode 100644 index 0000000000..fe1dadced6 --- /dev/null +++ b/hardware/board/component/brd4350a_a05.slcc @@ -0,0 +1,93 @@ +!!omap +- id: brd4350a_a05 +- label: BRD4350A rev A05 +- package: platform +- description: Board support for BRD4350A. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: mgm260pd22vna + - name: brd4350a_config + - name: hardware_board_mainboard +- provides: + - name: brd4350a_revision + - name: brd4350a_a05 + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_supports_wstk_lcd + - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_spi + - name: hardware_board_has_uart + - name: hardware_board_has_i2c + - name: board_config_clock_manager + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - id: joystick + - id: simple_button + instance: + - btn0 + - btn1 + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: + - name: board_default_init + value: sl_board_disable_vcom() +- define: + - name: SL_BOARD_NAME + value: '"BRD4350A"' + - name: SL_BOARD_REV + value: '"A05"' + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4350 + - board:variant:A + - board:revision:A05 + - board:device:mgm260pd22vna + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:joystick:skrhaae010 + - hardware:has:button:2 + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/brd4351a.slcc b/hardware/board/component/brd4351a.slcc index 5406017b8f..334e6819f9 100644 --- a/hardware/board/component/brd4351a.slcc +++ b/hardware/board/component/brd4351a.slcc @@ -15,6 +15,6 @@ - name: hardware_board_from_stk - name: hardware_board_from_mgm260p-rb4351a - recommends: - - id: brd4351a_a03 + - id: brd4351a_a05 - ui_hints: visibility: never diff --git a/hardware/board/component/brd4351a_a01.slcc b/hardware/board/component/brd4351a_a01.slcc index 76f0374184..f5c58403a9 100644 --- a/hardware/board/component/brd4351a_a01.slcc +++ b/hardware/board/component/brd4351a_a01.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -31,11 +45,16 @@ - name: hardware_board_default_rf_band - name: hardware_board_default_rf_band_2400 - recommends: - - id: brd4001a + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver - id: i2cspm instance: - sensor - id: ls013b7dh03 + - id: memlcd_usart - id: simple_led instance: - led0 @@ -45,6 +64,7 @@ instance: - btn0 - btn1 + - id: bootloader_spi_peripheral_usart_driver - template_contribution: - name: board_default_init value: sl_board_disable_vcom() diff --git a/hardware/board/component/brd4351a_a02.slcc b/hardware/board/component/brd4351a_a02.slcc index 63047b5d3b..3760b7495b 100644 --- a/hardware/board/component/brd4351a_a02.slcc +++ b/hardware/board/component/brd4351a_a02.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4351a_a03.slcc b/hardware/board/component/brd4351a_a03.slcc index db856b26de..8fe6447fd6 100644 --- a/hardware/board/component/brd4351a_a03.slcc +++ b/hardware/board/component/brd4351a_a03.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4351a_a04.slcc b/hardware/board/component/brd4351a_a04.slcc index 941a2613dd..8a7457910e 100644 --- a/hardware/board/component/brd4351a_a04.slcc +++ b/hardware/board/component/brd4351a_a04.slcc @@ -21,6 +21,20 @@ - name: hardware_board_has_tempsensor - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4351a_a05.slcc b/hardware/board/component/brd4351a_a05.slcc new file mode 100644 index 0000000000..94fe4cf413 --- /dev/null +++ b/hardware/board/component/brd4351a_a05.slcc @@ -0,0 +1,93 @@ +!!omap +- id: brd4351a_a05 +- label: BRD4351A rev A05 +- package: platform +- description: Board support for BRD4351A. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: mgm260pd32vna + - name: brd4351a_config + - name: hardware_board_mainboard +- provides: + - name: brd4351a_revision + - name: brd4351a_a05 + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_supports_wstk_lcd + - name: hardware_board_has_vcom + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_spi + - name: hardware_board_has_uart + - name: hardware_board_has_i2c + - name: board_config_clock_manager + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - id: joystick + - id: simple_button + instance: + - btn0 + - btn1 + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: + - name: board_default_init + value: sl_board_disable_vcom() +- define: + - name: SL_BOARD_NAME + value: '"BRD4351A"' + - name: SL_BOARD_REV + value: '"A05"' + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4351 + - board:variant:A + - board:revision:A05 + - board:device:mgm260pd32vna + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:joystick:skrhaae010 + - hardware:has:button:2 + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/brd4400a_a00.slcc b/hardware/board/component/brd4400a_a00.slcc index 268979025c..3e61dcd3ce 100644 --- a/hardware/board/component/brd4400a_a00.slcc +++ b/hardware/board/component/brd4400a_a00.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4400a_a01.slcc b/hardware/board/component/brd4400a_a01.slcc index 29dc29d2b5..c823dc74b3 100644 --- a/hardware/board/component/brd4400a_a01.slcc +++ b/hardware/board/component/brd4400a_a01.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -57,7 +71,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4400a_a02.slcc b/hardware/board/component/brd4400a_a02.slcc index d5d452b283..b29fd4354c 100644 --- a/hardware/board/component/brd4400a_a02.slcc +++ b/hardware/board/component/brd4400a_a02.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -57,7 +71,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4400b.slcc b/hardware/board/component/brd4400b.slcc index ed92e98370..cd53163a79 100644 --- a/hardware/board/component/brd4400b.slcc +++ b/hardware/board/component/brd4400b.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -58,7 +72,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4400c.slcc b/hardware/board/component/brd4400c.slcc index 509f07ddbe..e5f637ea49 100644 --- a/hardware/board/component/brd4400c.slcc +++ b/hardware/board/component/brd4400c.slcc @@ -25,6 +25,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -59,7 +73,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4401a_a00.slcc b/hardware/board/component/brd4401a_a00.slcc index b3b7229b48..99f9b1fda9 100644 --- a/hardware/board/component/brd4401a_a00.slcc +++ b/hardware/board/component/brd4401a_a00.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4401a_a01.slcc b/hardware/board/component/brd4401a_a01.slcc index 15f5ad5266..31650fe691 100644 --- a/hardware/board/component/brd4401a_a01.slcc +++ b/hardware/board/component/brd4401a_a01.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -57,7 +71,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4401a_a02.slcc b/hardware/board/component/brd4401a_a02.slcc index b832dd1d14..bc36a530ab 100644 --- a/hardware/board/component/brd4401a_a02.slcc +++ b/hardware/board/component/brd4401a_a02.slcc @@ -23,6 +23,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -57,7 +71,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4401b.slcc b/hardware/board/component/brd4401b.slcc index 91420e433c..aaf93cc0fb 100644 --- a/hardware/board/component/brd4401b.slcc +++ b/hardware/board/component/brd4401b.slcc @@ -24,6 +24,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -58,7 +72,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4401c.slcc b/hardware/board/component/brd4401c.slcc index fb406c0919..02c467e65f 100644 --- a/hardware/board/component/brd4401c.slcc +++ b/hardware/board/component/brd4401c.slcc @@ -25,6 +25,20 @@ - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_rfswitch + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -59,7 +73,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4402a_a00.slcc b/hardware/board/component/brd4402a_a00.slcc index e47170c673..f3a30278d9 100644 --- a/hardware/board/component/brd4402a_a00.slcc +++ b/hardware/board/component/brd4402a_a00.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4402a_a01.slcc b/hardware/board/component/brd4402a_a01.slcc index 9f110d6e3d..4d56041c76 100644 --- a/hardware/board/component/brd4402a_a01.slcc +++ b/hardware/board/component/brd4402a_a01.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4402a_a02.slcc b/hardware/board/component/brd4402a_a02.slcc index 4f2fdc79e3..1d09b6d0eb 100644 --- a/hardware/board/component/brd4402a_a02.slcc +++ b/hardware/board/component/brd4402a_a02.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4402b.slcc b/hardware/board/component/brd4402b.slcc index 43707590ea..e66a63d1bb 100644 --- a/hardware/board/component/brd4402b.slcc +++ b/hardware/board/component/brd4402b.slcc @@ -23,6 +23,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4402c.slcc b/hardware/board/component/brd4402c.slcc new file mode 100644 index 0000000000..d60045c912 --- /dev/null +++ b/hardware/board/component/brd4402c.slcc @@ -0,0 +1,20 @@ +!!omap +- id: brd4402c +- label: BRD4402C +- package: platform +- description: Board support for BRD4402C. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: brd4402c_revision +- provides: + - name: brd4402c + - name: hardware_board_from_stk + - name: hardware_board_from_bg22-rb4402c +- recommends: + - id: brd4402c_a01 +- ui_hints: + visibility: never diff --git a/hardware/board/component/brd4402c_a00.slcc b/hardware/board/component/brd4402c_a00.slcc new file mode 100644 index 0000000000..adaeeb902c --- /dev/null +++ b/hardware/board/component/brd4402c_a00.slcc @@ -0,0 +1,95 @@ +!!omap +- id: brd4402c_a00 +- label: BRD4402C rev A00 +- package: platform +- description: Board support for BRD4402C. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: efr32bg22c224f512gm40 + - name: brd4402c_config + - name: hardware_board_mainboard +- provides: + - name: brd4402c_revision + - name: brd4402c_a00 + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_supports_wstk_lcd + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_spi + - name: hardware_board_has_uart + - name: hardware_board_has_i2c + - name: board_config_clock_manager + - name: hardware_board_has_hfxo_freq_38.4mhz + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4001a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 + - id: mx25_flash_shutdown_usart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD4402C"' + - name: SL_BOARD_REV + value: '"A00"' + - name: HFXO_FREQ + value: 38400000 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4402 + - board:variant:C + - board:revision:A00 + - board:device:efr32bg22c224f512gm40 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:button:2 + - hardware:has:memory:spi:mx25r8035f + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/brd4402c_a01.slcc b/hardware/board/component/brd4402c_a01.slcc new file mode 100644 index 0000000000..b46096dd73 --- /dev/null +++ b/hardware/board/component/brd4402c_a01.slcc @@ -0,0 +1,95 @@ +!!omap +- id: brd4402c_a01 +- label: BRD4402C rev A01 +- package: platform +- description: Board support for BRD4402C. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: efr32bg22c224f512im40 + - name: brd4402c_config + - name: hardware_board_mainboard +- provides: + - name: brd4402c_revision + - name: brd4402c_a01 + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_supports_wstk_lcd + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_spi + - name: hardware_board_has_uart + - name: hardware_board_has_i2c + - name: board_config_clock_manager + - name: hardware_board_has_hfxo_freq_38.4mhz + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4001a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 + - id: mx25_flash_shutdown_usart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD4402C"' + - name: SL_BOARD_REV + value: '"A01"' + - name: HFXO_FREQ + value: 38400000 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4402 + - board:variant:C + - board:revision:A01 + - board:device:efr32bg22c224f512im40 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:button:2 + - hardware:has:memory:spi:mx25r8035f + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/brd4403a_a00.slcc b/hardware/board/component/brd4403a_a00.slcc index d9f24718c7..47e3318dd8 100644 --- a/hardware/board/component/brd4403a_a00.slcc +++ b/hardware/board/component/brd4403a_a00.slcc @@ -19,6 +19,10 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_7 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4403a_a01.slcc b/hardware/board/component/brd4403a_a01.slcc index 431348265a..f8710076c2 100644 --- a/hardware/board/component/brd4403a_a01.slcc +++ b/hardware/board/component/brd4403a_a01.slcc @@ -19,6 +19,10 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_7 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4403a_a02.slcc b/hardware/board/component/brd4403a_a02.slcc index fe734b8e41..375c4a611e 100644 --- a/hardware/board/component/brd4403a_a02.slcc +++ b/hardware/board/component/brd4403a_a02.slcc @@ -19,6 +19,10 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_7 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4403b.slcc b/hardware/board/component/brd4403b.slcc index 931989a573..ef1ee624ff 100644 --- a/hardware/board/component/brd4403b.slcc +++ b/hardware/board/component/brd4403b.slcc @@ -20,6 +20,12 @@ - name: hardware_board_from_bg22-rb4403b - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 - name: hardware_board_has_uart - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz diff --git a/hardware/board/component/brd4403c.slcc b/hardware/board/component/brd4403c.slcc new file mode 100644 index 0000000000..2deafbc22e --- /dev/null +++ b/hardware/board/component/brd4403c.slcc @@ -0,0 +1,20 @@ +!!omap +- id: brd4403c +- label: BRD4403C +- package: platform +- description: Board support for BRD4403C. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: brd4403c_revision +- provides: + - name: brd4403c + - name: hardware_board_from_stk + - name: hardware_board_from_bg22-rb4403c +- recommends: + - id: brd4403c_a01 +- ui_hints: + visibility: never diff --git a/hardware/board/component/brd4403c_a00.slcc b/hardware/board/component/brd4403c_a00.slcc new file mode 100644 index 0000000000..1808a6cfa5 --- /dev/null +++ b/hardware/board/component/brd4403c_a00.slcc @@ -0,0 +1,73 @@ +!!omap +- id: brd4403c_a00 +- label: BRD4403C rev A00 +- package: platform +- description: Board support for BRD4403C. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: efr32bg22c224f512gm32 + - name: brd4403c_config + - name: hardware_board_mainboard +- provides: + - name: brd4403c_revision + - name: brd4403c_a00 + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_uart + - name: board_config_clock_manager + - name: hardware_board_has_hfxo_freq_38.4mhz + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4001a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - id: simple_button + instance: + - btn0 + - id: mx25_flash_shutdown_usart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD4403C"' + - name: SL_BOARD_REV + value: '"A00"' + - name: HFXO_FREQ + value: 38400000 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4403 + - board:variant:C + - board:revision:A00 + - board:device:efr32bg22c224f512gm32 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:1 + - hardware:has:button:1 + - hardware:has:memory:spi:mx25r8035f + - hardware:has:exp_header:uart diff --git a/hardware/board/component/brd4403c_a01.slcc b/hardware/board/component/brd4403c_a01.slcc new file mode 100644 index 0000000000..5f59254afc --- /dev/null +++ b/hardware/board/component/brd4403c_a01.slcc @@ -0,0 +1,73 @@ +!!omap +- id: brd4403c_a01 +- label: BRD4403C rev A01 +- package: platform +- description: Board support for BRD4403C. +- category: Platform|Board|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: efr32bg22c224f512im32 + - name: brd4403c_config + - name: hardware_board_mainboard +- provides: + - name: brd4403c_revision + - name: brd4403c_a01 + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_uart + - name: board_config_clock_manager + - name: hardware_board_has_hfxo_freq_38.4mhz + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4001a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - id: simple_button + instance: + - btn0 + - id: mx25_flash_shutdown_usart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD4403C"' + - name: SL_BOARD_REV + value: '"A01"' + - name: HFXO_FREQ + value: 38400000 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_2400 + - name: HARDWARE_BOARD_SUPPORTS_1_RF_BAND + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_2400 +- tag: + - board:pn:BRD4403 + - board:variant:C + - board:revision:A01 + - board:device:efr32bg22c224f512im32 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:1 + - hardware:has:button:1 + - hardware:has:memory:spi:mx25r8035f + - hardware:has:exp_header:uart diff --git a/hardware/board/component/brd4406a.slcc b/hardware/board/component/brd4406a.slcc index 2d115c61d7..65d4c3707a 100644 --- a/hardware/board/component/brd4406a.slcc +++ b/hardware/board/component/brd4406a.slcc @@ -36,7 +36,7 @@ instance: - vcom - id: bootloader_uart_driver - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - template_contribution: [] - define: diff --git a/hardware/board/component/brd4411a.slcc b/hardware/board/component/brd4411a.slcc index 82f2926c69..3cfb2bdce8 100644 --- a/hardware/board/component/brd4411a.slcc +++ b/hardware/board/component/brd4411a.slcc @@ -22,6 +22,20 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_5 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_3 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_9 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +67,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4412a.slcc b/hardware/board/component/brd4412a.slcc index 37c9361631..149eab601a 100644 --- a/hardware/board/component/brd4412a.slcc +++ b/hardware/board/component/brd4412a.slcc @@ -22,6 +22,17 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_13 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +64,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4413a.slcc b/hardware/board/component/brd4413a.slcc index b1b6bc9903..93ecc618a2 100644 --- a/hardware/board/component/brd4413a.slcc +++ b/hardware/board/component/brd4413a.slcc @@ -22,6 +22,16 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c @@ -53,7 +63,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4414a.slcc b/hardware/board/component/brd4414a.slcc index 399d2938e1..cd4f6fe051 100644 --- a/hardware/board/component/brd4414a.slcc +++ b/hardware/board/component/brd4414a.slcc @@ -15,6 +15,6 @@ - name: hardware_board_from_stk - name: hardware_board_from_bg29-rb4414a - recommends: - - id: brd4414a_a04 + - id: brd4414a_a06 - ui_hints: visibility: never diff --git a/hardware/board/component/brd4414a_a01.slcc b/hardware/board/component/brd4414a_a01.slcc index 3ec00a4c4d..fed49f294c 100644 --- a/hardware/board/component/brd4414a_a01.slcc +++ b/hardware/board/component/brd4414a_a01.slcc @@ -19,6 +19,7 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_16 - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz - name: hardware_board_has_hfxo @@ -41,7 +42,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4414a_a02.slcc b/hardware/board/component/brd4414a_a02.slcc index 49826c941d..94d6400c51 100644 --- a/hardware/board/component/brd4414a_a02.slcc +++ b/hardware/board/component/brd4414a_a02.slcc @@ -19,6 +19,7 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_16 - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz - name: hardware_board_has_hfxo @@ -41,7 +42,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4414a_a03.slcc b/hardware/board/component/brd4414a_a03.slcc index afb00512be..cfc0efaeda 100644 --- a/hardware/board/component/brd4414a_a03.slcc +++ b/hardware/board/component/brd4414a_a03.slcc @@ -19,6 +19,7 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_16 - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz - name: hardware_board_has_hfxo diff --git a/hardware/board/component/brd4414a_a04.slcc b/hardware/board/component/brd4414a_a04.slcc index d405428ade..1c06428e41 100644 --- a/hardware/board/component/brd4414a_a04.slcc +++ b/hardware/board/component/brd4414a_a04.slcc @@ -19,6 +19,7 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_16 - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz - name: hardware_board_has_hfxo @@ -41,7 +42,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4414a_a05.slcc b/hardware/board/component/brd4414a_a05.slcc index 5203edd235..e32cfcb469 100644 --- a/hardware/board/component/brd4414a_a05.slcc +++ b/hardware/board/component/brd4414a_a05.slcc @@ -19,6 +19,7 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_16 - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz - name: hardware_board_has_hfxo @@ -41,7 +42,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4414a_a06.slcc b/hardware/board/component/brd4414a_a06.slcc index e07024a022..a230c538ab 100644 --- a/hardware/board/component/brd4414a_a06.slcc +++ b/hardware/board/component/brd4414a_a06.slcc @@ -19,6 +19,7 @@ - name: hardware_board_rb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_16 - name: board_config_clock_manager - name: hardware_board_has_hfxo_freq_38.4mhz - name: hardware_board_has_hfxo @@ -41,7 +42,7 @@ instance: - btn0 - btn1 - - id: mx25_flash_shutdown_usart + - id: mx25_flash_shutdown_eusart - id: bootloader_spi_controller_usart_driver - id: bootloader_spi_peripheral_usart_driver - template_contribution: [] diff --git a/hardware/board/component/brd4415a_a00.slcc b/hardware/board/component/brd4415a_a00.slcc index 7f8f27ceac..e96eb7acfa 100644 --- a/hardware/board/component/brd4415a_a00.slcc +++ b/hardware/board/component/brd4415a_a00.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/brd4415a_a01.slcc b/hardware/board/component/brd4415a_a01.slcc index 5954e43450..121dfdc7e6 100644 --- a/hardware/board/component/brd4415a_a01.slcc +++ b/hardware/board/component/brd4415a_a01.slcc @@ -22,6 +22,18 @@ - name: hardware_board_supports_wstk_lcd - name: hardware_board_has_vcom - name: hardware_board_has_spiflash + - name: hardware_board_has_exp_12 + - name: hardware_board_has_exp_14 + - name: hardware_board_has_exp_7 + - name: hardware_board_has_exp_9 + - name: hardware_board_has_exp_15 + - name: hardware_board_has_exp_16 + - name: hardware_board_has_exp_4 + - name: hardware_board_has_exp_6 + - name: hardware_board_has_exp_8 + - name: hardware_board_has_exp_10 + - name: hardware_board_has_exp_11 + - name: hardware_board_has_exp_13 - name: hardware_board_has_spi - name: hardware_board_has_uart - name: hardware_board_has_i2c diff --git a/hardware/board/component/mgm260p-ek2713a.slcc b/hardware/board/component/mgm260p-ek2713a.slcc new file mode 100644 index 0000000000..27176138ed --- /dev/null +++ b/hardware/board/component/mgm260p-ek2713a.slcc @@ -0,0 +1,25 @@ +!!omap +- id: mgm260p_ek2713a +- label: MGM260P-EK2713A +- package: platform +- description: Kit BSP support for the MGM260P Module Explorer Kit. +- category: Platform|Board|Kit|Explorer Kit +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_mgm260p-ek2713a +- provides: + - name: hardware_kit + - name: hardware_kit_ek +- define: + - name: SL_KIT_NAME + value: '"MGM260P-EK2713A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:MGM260P-EK2713A + - kit:pn:EK2713 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/mgm260p-rb4350a.slcc b/hardware/board/component/mgm260p-rb4350a.slcc index 05b2c3e50e..ad3fc6965c 100644 --- a/hardware/board/component/mgm260p-rb4350a.slcc +++ b/hardware/board/component/mgm260p-rb4350a.slcc @@ -17,9 +17,9 @@ - name: SL_KIT_NAME value: '"MGM260P-RB4350A"' - name: SL_KIT_REV - value: '"A00"' + value: '"A01"' - tag: - kit:opn:MGM260P-RB4350A - kit:pn:RB4350 - kit:variant:A - - kit:revision:A00 + - kit:revision:A01 diff --git a/hardware/board/component/mgm260p-rb4351a.slcc b/hardware/board/component/mgm260p-rb4351a.slcc index e4d291a3a4..9288c894f7 100644 --- a/hardware/board/component/mgm260p-rb4351a.slcc +++ b/hardware/board/component/mgm260p-rb4351a.slcc @@ -17,9 +17,9 @@ - name: SL_KIT_NAME value: '"MGM260P-RB4351A"' - name: SL_KIT_REV - value: '"A00"' + value: '"A01"' - tag: - kit:opn:MGM260P-RB4351A - kit:pn:RB4351 - kit:variant:A - - kit:revision:A00 + - kit:revision:A01 diff --git a/hardware/board/component/pg26-ek2711a.slcc b/hardware/board/component/pg26-ek2711a.slcc new file mode 100644 index 0000000000..cc9f465342 --- /dev/null +++ b/hardware/board/component/pg26-ek2711a.slcc @@ -0,0 +1,25 @@ +!!omap +- id: pg26_ek2711a +- label: PG26-EK2711A +- package: platform +- description: Kit BSP support for the EFM32PG26 Explorer Kit. +- category: Platform|Board|Kit|Explorer Kit +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_pg26-ek2711a +- provides: + - name: hardware_kit + - name: hardware_kit_ek +- define: + - name: SL_KIT_NAME + value: '"PG26-EK2711A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:PG26-EK2711A + - kit:pn:EK2711 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/pg26-pk2505a.slcc b/hardware/board/component/pg26-pk2505a.slcc new file mode 100644 index 0000000000..1c6dd3d719 --- /dev/null +++ b/hardware/board/component/pg26-pk2505a.slcc @@ -0,0 +1,25 @@ +!!omap +- id: pg26_pk2505a +- label: PG26-PK2505A +- package: platform +- description: Kit BSP support for the PG26 Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_pg26-pk2505a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"PG26-PK2505A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:PG26-PK2505A + - kit:pn:PK2505 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/xg26-dk2608a.slcc b/hardware/board/component/xg26-dk2608a.slcc new file mode 100644 index 0000000000..6db9514c76 --- /dev/null +++ b/hardware/board/component/xg26-dk2608a.slcc @@ -0,0 +1,25 @@ +!!omap +- id: xg26_dk2608a +- label: XG26-DK2608A +- package: platform +- description: Kit BSP support for the xG26 Dev Kit. +- category: Platform|Board|Kit|Development Kit +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_xg26-dk2608a +- provides: + - name: hardware_kit + - name: hardware_kit_dk +- define: + - name: SL_KIT_NAME + value: '"XG26-DK2608A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:xG26-DK2608A + - kit:pn:DK2608 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/xg26-ek2709a.slcc b/hardware/board/component/xg26-ek2709a.slcc new file mode 100644 index 0000000000..4abaf29da4 --- /dev/null +++ b/hardware/board/component/xg26-ek2709a.slcc @@ -0,0 +1,25 @@ +!!omap +- id: xg26_ek2709a +- label: XG26-EK2709A +- package: platform +- description: Kit BSP support for the xG26 Explorer Kit. +- category: Platform|Board|Kit|Explorer Kit +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_xg26-ek2709a +- provides: + - name: hardware_kit + - name: hardware_kit_ek +- define: + - name: SL_KIT_NAME + value: '"XG26-EK2709A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:xG26-EK2709A + - kit:pn:EK2709 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/xg26-rb4120a.slcc b/hardware/board/component/xg26-rb4120a.slcc new file mode 100644 index 0000000000..717b71ad6a --- /dev/null +++ b/hardware/board/component/xg26-rb4120a.slcc @@ -0,0 +1,25 @@ +!!omap +- id: xg26_rb4120a +- label: XG26-RB4120A +- package: platform +- description: Kit BSP support for the EFR32xG26 Wireless 2.4 GHz 10 dBm Radio Board. +- category: Platform|Board|Kit|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_xg26-rb4120a +- provides: + - name: hardware_kit + - name: hardware_kit_rb +- define: + - name: SL_KIT_NAME + value: '"XG26-RB4120A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:xG26-RB4120A + - kit:pn:RB4120 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/xg26-rb4121a.slcc b/hardware/board/component/xg26-rb4121a.slcc new file mode 100644 index 0000000000..6007852c9e --- /dev/null +++ b/hardware/board/component/xg26-rb4121a.slcc @@ -0,0 +1,25 @@ +!!omap +- id: xg26_rb4121a +- label: XG26-RB4121A +- package: platform +- description: Kit BSP support for the EFR32xG26 Wireless 2.4 GHz 20 dBm Radio Board. +- category: Platform|Board|Kit|Radio Board +- quality: production +- metadata: + sbom: + license: Zlib +- requires: + - name: hardware_board_from_xg26-rb4121a +- provides: + - name: hardware_kit + - name: hardware_kit_rb +- define: + - name: SL_KIT_NAME + value: '"XG26-RB4121A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:xG26-RB4121A + - kit:pn:RB4121 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/zwave-pk800a.slcc b/hardware/board/component/zwave-pk800a.slcc index 7412ecced6..87dfb41881 100644 --- a/hardware/board/component/zwave-pk800a.slcc +++ b/hardware/board/component/zwave-pk800a.slcc @@ -2,7 +2,7 @@ - id: zwave_pk800a - label: ZWAVE-PK800A - package: platform -- description: Kit BSP support for the ZWAVE-PK800A. +- description: Kit BSP support for the Z-Wave 800 Pro Kit. - category: Platform|Board|Kit|Pro Kit - quality: production - metadata: diff --git a/hardware/board/component/zwave-pk800b.slcc b/hardware/board/component/zwave-pk800b.slcc index e5444b1429..0b4ad9e2f4 100644 --- a/hardware/board/component/zwave-pk800b.slcc +++ b/hardware/board/component/zwave-pk800b.slcc @@ -2,7 +2,7 @@ - id: zwave_pk800b - label: ZWAVE-PK800B - package: platform -- description: Kit BSP support for the ZWAVE-PK800B. +- description: Kit BSP support for the Z-Wave 800 Pro Kit. - category: Platform|Board|Kit|Pro Kit - quality: production - metadata: diff --git a/hardware/board/config/brd1021a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd1021a_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd1021a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd1021a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd1021a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd1021a_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd1021a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd1021a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2503a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2503a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd2503a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2503a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_2_config.h index 4f94714657..30e113000b 100644 --- a/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_config.h index 7f6f55277f..6266efab4d 100644 --- a/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd2503a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2503a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2503a/sl_uartdrv_usart_exp_config.h index fd1930c706..d1b876c155 100644 --- a/hardware/board/config/brd2503a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd2503a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 8 +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2503b/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2503b/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd2503b/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2503b/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_2_config.h index 4f94714657..30e113000b 100644 --- a/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_config.h index 7f6f55277f..6266efab4d 100644 --- a/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd2503b/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2503b/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2503b/sl_uartdrv_usart_exp_config.h index fd1930c706..d1b876c155 100644 --- a/hardware/board/config/brd2503b/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd2503b/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 8 +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2504a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2504a/sl_clock_manager_oscillator_config.h index b83702a14b..44ed893d5f 100644 --- a/hardware/board/config/brd2504a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2504a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2505a/btl_euart_driver_cfg.h b/hardware/board/config/brd2505a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..2c24ccd7f6 --- /dev/null +++ b/hardware/board/config/brd2505a/btl_euart_driver_cfg.h @@ -0,0 +1,80 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART2 +#define SL_SERIAL_EUART_PERIPHERAL_NO 2 + +// EUSART2 TX on PC12 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_EUART_TX_PIN 12 + +// EUSART2 RX on PC13 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_EUART_RX_PIN 13 + + + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 14 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd2505a/btl_gpio_activation_cfg.h b/hardware/board/config/brd2505a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..323a11c825 --- /dev/null +++ b/hardware/board/config/brd2505a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd2505a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd2505a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..126ba0397b --- /dev/null +++ b/hardware/board/config/brd2505a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD12 +#define SL_EUSART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_TX_PIN 12 + +// EUSART1 RX on PD13 +#define SL_EUSART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_RX_PIN 13 + +// EUSART1 CS on PD15 +#define SL_EUSART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_CS_PIN 15 + +// EUSART1 SCLK on PD14 +#define SL_EUSART_SPINCP_SCLK_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_SCLK_PIN 14 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd2505a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd2505a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..01bcd841e5 --- /dev/null +++ b/hardware/board/config/brd2505a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define SL_USART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_TX_PIN 12 + +// USART0 RX on PD13 +#define SL_USART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_RX_PIN 13 + +// USART0 CS on PD15 +#define SL_USART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CS_PIN 15 + +// USART0 CLK on PD14 +#define SL_USART_SPINCP_CLK_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CLK_PIN 14 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd2505a/btl_uart_driver_cfg.h b/hardware/board/config/brd2505a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..0b374420b0 --- /dev/null +++ b/hardware/board/config/brd2505a/btl_uart_driver_cfg.h @@ -0,0 +1,80 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_UART_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_UART_RX_PIN 13 + + + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 14 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd2505a/iot_flash_cfg_exp.h b/hardware/board/config/brd2505a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..9079b213d0 --- /dev/null +++ b/hardware/board/config/brd2505a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 12 + +// USART0 RX on PD13 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 13 + +// USART0 CLK on PD14 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 14 + +// USART0 CS on PD15 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 15 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd2505a/iot_flash_cfg_msc.h b/hardware/board/config/brd2505a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd2505a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd2505a/iot_i2c_cfg_exp.h b/hardware/board/config/brd2505a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..55184d04b4 --- /dev/null +++ b/hardware/board/config/brd2505a/iot_i2c_cfg_exp.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C1 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 1 + +// I2C1 SCL on PC15 +#define IOT_I2C_CFG_EXP_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SCL_PIN 15 + +// I2C1 SDA on PC14 +#define IOT_I2C_CFG_EXP_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SDA_PIN 14 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd2505a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd2505a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..6da7388ccd --- /dev/null +++ b/hardware/board/config/brd2505a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC15 +#define IOT_I2C_CFG_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SCL_PIN 15 + +// I2C1 SDA on PC14 +#define IOT_I2C_CFG_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SDA_PIN 14 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd2505a/iot_i2c_cfg_test.h b/hardware/board/config/brd2505a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..40b54506aa --- /dev/null +++ b/hardware/board/config/brd2505a/iot_i2c_cfg_test.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C1 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 1 + +// I2C1 SCL on PC15 +#define IOT_I2C_CFG_TEST_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SCL_PIN 15 + +// I2C1 SDA on PC14 +#define IOT_I2C_CFG_TEST_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SDA_PIN 14 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd2505a/iot_pwm_cfg_led0.h b/hardware/board/config/brd2505a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..f66e1202c6 --- /dev/null +++ b/hardware/board/config/brd2505a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PC10 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_C +#define IOT_PWM_CFG_LED0_CC0_PIN 10 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd2505a/iot_pwm_cfg_led1.h b/hardware/board/config/brd2505a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..6ab68bdd2c --- /dev/null +++ b/hardware/board/config/brd2505a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PC11 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_C +#define IOT_PWM_CFG_LED1_CC0_PIN 11 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd2505a/iot_spi_cfg_exp.h b/hardware/board/config/brd2505a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..6a60ceb030 --- /dev/null +++ b/hardware/board/config/brd2505a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define IOT_SPI_CFG_EXP_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_TX_PIN 12 + +// USART0 RX on PD13 +#define IOT_SPI_CFG_EXP_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_RX_PIN 13 + +// USART0 CLK on PD14 +#define IOT_SPI_CFG_EXP_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CLK_PIN 14 + +// USART0 CS on PD15 +#define IOT_SPI_CFG_EXP_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CS_PIN 15 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd2505a/iot_spi_cfg_loopback.h b/hardware/board/config/brd2505a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..4049b86904 --- /dev/null +++ b/hardware/board/config/brd2505a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 12 + +// USART0 RX on PD13 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 13 + +// USART0 CLK on PD14 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 14 + +// USART0 CS on PD15 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 15 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd2505a/iot_uart_cfg_exp.h b/hardware/board/config/brd2505a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..4971f118c8 --- /dev/null +++ b/hardware/board/config/brd2505a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_RX_PIN 13 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd2505a/iot_uart_cfg_loopback.h b/hardware/board/config/brd2505a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..08132e2ecd --- /dev/null +++ b/hardware/board/config/brd2505a/iot_uart_cfg_loopback.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_LOOPBACK_TX_PIN 12 + +// USART0 RX on PC13 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_LOOPBACK_RX_PIN 13 + + + + + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd2505a/iot_uart_cfg_vcom.h b/hardware/board/config/brd2505a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..ee1c1584ef --- /dev/null +++ b/hardware/board/config/brd2505a/iot_uart_cfg_vcom.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_VCOM_TX_PIN 12 + +// USART0 RX on PC13 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_VCOM_RX_PIN 13 + + + + + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd2505a/sl_board_control_config.h b/hardware/board/config/brd2505a/sl_board_control_config.h new file mode 100644 index 0000000000..dca7426945 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_board_control_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_B +#define SL_BOARD_ENABLE_VCOM_PIN 14 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT SL_GPIO_PORT_A +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 15 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2505a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..5b46882186 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 96 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 35 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_clock_manager_tree_config.h b/hardware/board/config/brd2505a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..c87be3c16f --- /dev/null +++ b/hardware/board/config/brd2505a/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd2505a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd2505a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..fbd47c8004 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_IRQ] +#define SL_CPC_DRV_SPI_EXP_IRQ_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_IRQ_PIN 15 + +// [GPIO_SL_CPC_DRV_SPI_EXP_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define SL_CPC_DRV_SPI_EXP_COPI_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_COPI_PIN 12 + +// USART0 RX on PD13 +#define SL_CPC_DRV_SPI_EXP_CIPO_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CIPO_PIN 13 + +// USART0 CLK on PD14 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 14 + +// USART0 CS on PD15 +#define SL_CPC_DRV_SPI_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CS_PIN 15 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd2505a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..6873a141ac --- /dev/null +++ b/hardware/board/config/brd2505a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD12 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 12 + +// EUSART1 RX on PD13 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 13 + +// EUSART1 CTS on PD14 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 14 + +// EUSART1 RTS on PD15 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 15 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd2505a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..c2bd44c411 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,96 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART2 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 2 + +// EUSART2 TX on PC12 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_TX_PIN 12 + +// EUSART2 RX on PC13 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_RX_PIN 13 + + + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd2505a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..a907149a80 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 12 + +// USART0 RX on PD13 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 13 + +// USART0 CTS on PD14 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 14 + +// USART0 RTS on PD15 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 15 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd2505a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..13ecc4e624 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,96 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_RX_PIN 13 + + + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd2505a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..f78564792b --- /dev/null +++ b/hardware/board/config/brd2505a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd2505a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..978ab69f1c --- /dev/null +++ b/hardware/board/config/brd2505a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 12 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_device_init_hfxo_config.h b/hardware/board/config/brd2505a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..fa02144986 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 96 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_device_init_lfxo_config.h b/hardware/board/config/brd2505a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..aff0a45ed7 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 35 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_10_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_10_config.h new file mode 100644 index 0000000000..16d718da1d --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_10_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_10_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_10_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_10 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_10] +#define SL_EMLIB_GPIO_INIT_EXP_10_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_10_PIN 15 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_10]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..bb209aedb5 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 12 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..0910e978d0 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 13 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_15_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_15_config.h new file mode 100644 index 0000000000..37c26e7482 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_15_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_15_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_15_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_15 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_15] +#define SL_EMLIB_GPIO_INIT_EXP_15_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_15_PIN 15 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_15]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_16_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_16_config.h new file mode 100644 index 0000000000..0bafe56e99 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_16_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_16_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_16_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_16 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_16] +#define SL_EMLIB_GPIO_INIT_EXP_16_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_16_PIN 14 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_16]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_4_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_4_config.h new file mode 100644 index 0000000000..7738012003 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_4_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_4_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_4_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_4 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_4] +#define SL_EMLIB_GPIO_INIT_EXP_4_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_4_PIN 12 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_6_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_6_config.h new file mode 100644 index 0000000000..68ccab956a --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_6_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_6_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_6_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_6 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_6] +#define SL_EMLIB_GPIO_INIT_EXP_6_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_6_PIN 13 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_6]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_8_config.h b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_8_config.h new file mode 100644 index 0000000000..48164bc4b1 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_emlib_gpio_init_exp_8_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_8_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_8_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_8 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_8] +#define SL_EMLIB_GPIO_INIT_EXP_8_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_8_PIN 14 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_8]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd2505a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..4980ce1e86 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC15 +#define SL_I2CSPM_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SCL_PIN 15 + +// I2C1 SDA on PC14 +#define SL_I2CSPM_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SDA_PIN 14 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd2505a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..a32ea6b45b --- /dev/null +++ b/hardware/board/config/brd2505a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 13 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2505a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd2505a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..dd5c587c35 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART2 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 2 + +// EUSART2 TX on PC12 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 12 + +// EUSART2 RX on PC13 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 13 + + + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2505a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd2505a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..5358b1fb6b --- /dev/null +++ b/hardware/board/config/brd2505a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_RX_PIN 13 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2505a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd2505a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..7b9ecadea3 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_VCOM_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_VCOM_RX_PIN 13 + + + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2505a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd2505a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..9ccfc81511 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * @file + * @brief OpenThread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 12 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 13 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 15 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define SL_NCP_SPIDRV_USART_TX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_TX_PIN 12 + +// USART0 RX on PD13 +#define SL_NCP_SPIDRV_USART_RX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_RX_PIN 13 + +// USART0 CLK on PD14 +#define SL_NCP_SPIDRV_USART_CLK_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CLK_PIN 14 + +// USART0 CS on PD15 +#define SL_NCP_SPIDRV_USART_CS_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CS_PIN 15 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd2505a/sl_pwm_init_led0_config.h b/hardware/board/config/brd2505a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..9723ddef7a --- /dev/null +++ b/hardware/board/config/brd2505a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PC10 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_C +#define SL_PWM_LED0_OUTPUT_PIN 10 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_pwm_init_led1_config.h b/hardware/board/config/brd2505a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..f218754352 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PC11 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_C +#define SL_PWM_LED1_OUTPUT_PIN 11 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_simple_button_btn0_config.h b/hardware/board/config/brd2505a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..23e27379c4 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_simple_button_btn1_config.h b/hardware/board/config/brd2505a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..b1add33661 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 12 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_simple_led_led0_config.h b/hardware/board/config/brd2505a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..66c3384b95 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_C +#define SL_SIMPLE_LED_LED0_PIN 10 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_simple_led_led1_config.h b/hardware/board/config/brd2505a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..8528f19571 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_C +#define SL_SIMPLE_LED_LED1_PIN 11 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd2505a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..d9dc012c68 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD12 +#define SL_SPIDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PD13 +#define SL_SPIDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_RX_PIN 13 + +// EUSART1 SCLK on PD14 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 14 + +// EUSART1 CS on PD15 +#define SL_SPIDRV_EUSART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_CS_PIN 15 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd2505a/sl_spidrv_exp_config.h b/hardware/board/config/brd2505a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..736172ff16 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define SL_SPIDRV_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_TX_PIN 12 + +// USART0 RX on PD13 +#define SL_SPIDRV_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_RX_PIN 13 + +// USART0 CLK on PD14 +#define SL_SPIDRV_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CLK_PIN 14 + +// USART0 CS on PD15 +#define SL_SPIDRV_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CS_PIN 15 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd2505a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..88d3902f8d --- /dev/null +++ b/hardware/board/config/brd2505a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD12 +#define SL_SPIDRV_USART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_TX_PIN 12 + +// USART0 RX on PD13 +#define SL_SPIDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_RX_PIN 13 + +// USART0 CLK on PD14 +#define SL_SPIDRV_USART_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CLK_PIN 14 + +// USART0 CS on PD15 +#define SL_SPIDRV_USART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CS_PIN 15 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd2505a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..881e7a753b --- /dev/null +++ b/hardware/board/config/brd2505a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_RX_PIN 13 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd2505a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..2bdf03db16 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART2 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 2 + +// EUSART2 TX on PC12 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 12 + +// EUSART2 RX on PC13 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 13 + + + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2505a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..a8134f4585 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RX_PIN 13 + + + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd2505a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd2505a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..3844658ae5 --- /dev/null +++ b/hardware/board/config/brd2505a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_RX_PIN 13 + + + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd2506a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2506a/sl_clock_manager_oscillator_config.h index 497deb8f81..43de9ff567 100644 --- a/hardware/board/config/brd2506a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2506a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2506a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2506a/sl_uartdrv_usart_exp_config.h index 8d826e1af3..2ba2385c54 100644 --- a/hardware/board/config/brd2506a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd2506a/sl_uartdrv_usart_exp_config.h @@ -101,6 +101,9 @@ #define SL_UARTDRV_USART_EXP_RX_PIN 8 +// USART0 RTS on PB00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2506a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd2506a/sl_uartdrv_usart_vcom_config.h index b66abe54ae..85c00353ee 100644 --- a/hardware/board/config/brd2506a/sl_uartdrv_usart_vcom_config.h +++ b/hardware/board/config/brd2506a/sl_uartdrv_usart_vcom_config.h @@ -101,6 +101,9 @@ #define SL_UARTDRV_USART_VCOM_RX_PIN 8 +// USART0 RTS on PB00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 // [USART_SL_UARTDRV_USART_VCOM]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2600a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2600a/sl_clock_manager_oscillator_config.h index c308c50aac..a97fad0d05 100644 --- a/hardware/board/config/brd2600a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2600a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2601a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2601a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2601a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2601a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2601a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd2601a/sl_uartdrv_eusart_exp_config.h index 01d786b521..0316239713 100644 --- a/hardware/board/config/brd2601a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd2601a/sl_uartdrv_eusart_exp_config.h @@ -106,6 +106,9 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PB02 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 2 // [EUSART_SL_UARTDRV_EUSART_EXP]$ diff --git a/hardware/board/config/brd2601a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd2601a/sl_uartdrv_eusart_vcom_config.h index 882099f5df..b3293e07f5 100644 --- a/hardware/board/config/brd2601a/sl_uartdrv_eusart_vcom_config.h +++ b/hardware/board/config/brd2601a/sl_uartdrv_eusart_vcom_config.h @@ -106,6 +106,9 @@ #define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 +// EUSART0 CTS on PB02 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 2 // [EUSART_SL_UARTDRV_EUSART_VCOM]$ diff --git a/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_2_config.h index fd2526c015..ee7564f7cf 100644 --- a/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_2_config.h @@ -100,6 +100,9 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 2 +// USART0 CTS on PB02 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 2 // [USART_SL_UARTDRV_USART_EXP_2]$ diff --git a/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_config.h index d44463bec2..687f96324a 100644 --- a/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd2601a/sl_uartdrv_usart_exp_config.h @@ -100,6 +100,9 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB02 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 2 // [USART_SL_UARTDRV_USART_EXP]$ diff --git a/hardware/board/config/brd2601a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd2601a/sl_uartdrv_usart_vcom_config.h index d1e372ff55..125a421595 100644 --- a/hardware/board/config/brd2601a/sl_uartdrv_usart_vcom_config.h +++ b/hardware/board/config/brd2601a/sl_uartdrv_usart_vcom_config.h @@ -100,6 +100,9 @@ #define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_VCOM_RX_PIN 6 +// USART0 CTS on PB02 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_CTS_PIN 2 // [USART_SL_UARTDRV_USART_VCOM]$ diff --git a/hardware/board/config/brd2601b/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2601b/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2601b/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2601b/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2601b/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd2601b/sl_uartdrv_eusart_exp_config.h index 01d786b521..0316239713 100644 --- a/hardware/board/config/brd2601b/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd2601b/sl_uartdrv_eusart_exp_config.h @@ -106,6 +106,9 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PB02 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 2 // [EUSART_SL_UARTDRV_EUSART_EXP]$ diff --git a/hardware/board/config/brd2601b/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd2601b/sl_uartdrv_eusart_vcom_config.h index 882099f5df..b3293e07f5 100644 --- a/hardware/board/config/brd2601b/sl_uartdrv_eusart_vcom_config.h +++ b/hardware/board/config/brd2601b/sl_uartdrv_eusart_vcom_config.h @@ -106,6 +106,9 @@ #define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 +// EUSART0 CTS on PB02 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 2 // [EUSART_SL_UARTDRV_EUSART_VCOM]$ diff --git a/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_2_config.h index fd2526c015..ee7564f7cf 100644 --- a/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_2_config.h @@ -100,6 +100,9 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 2 +// USART0 CTS on PB02 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 2 // [USART_SL_UARTDRV_USART_EXP_2]$ diff --git a/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_config.h index d44463bec2..687f96324a 100644 --- a/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd2601b/sl_uartdrv_usart_exp_config.h @@ -100,6 +100,9 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB02 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 2 // [USART_SL_UARTDRV_USART_EXP]$ diff --git a/hardware/board/config/brd2601b/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd2601b/sl_uartdrv_usart_vcom_config.h index d1e372ff55..125a421595 100644 --- a/hardware/board/config/brd2601b/sl_uartdrv_usart_vcom_config.h +++ b/hardware/board/config/brd2601b/sl_uartdrv_usart_vcom_config.h @@ -100,6 +100,9 @@ #define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_VCOM_RX_PIN 6 +// USART0 CTS on PB02 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_CTS_PIN 2 // [USART_SL_UARTDRV_USART_VCOM]$ diff --git a/hardware/board/config/brd2602a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2602a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd2602a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2602a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_2_config.h index 02ad536a96..b6756566da 100644 --- a/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUSART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 8 +// EUSART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_config.h index 01d786b521..82107a6a3f 100644 --- a/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd2602a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 8 +// EUSART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2602a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2602a/sl_uartdrv_usart_exp_config.h index fd1930c706..d1b876c155 100644 --- a/hardware/board/config/brd2602a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd2602a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 8 +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2603a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2603a/sl_clock_manager_oscillator_config.h index b83702a14b..44ed893d5f 100644 --- a/hardware/board/config/brd2603a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2603a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2603a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd2603a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..58e6c17898 100644 --- a/hardware/board/config/brd2603a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd2603a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB03 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 3 +// EUSART0 RTS on PB02 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 2 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_2_config.h index de425acca8..bc94ed8917 100644 --- a/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 4 +// USART0 CTS on PB03 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 3 +// USART0 RTS on PB02 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 2 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_config.h index f7e3837efe..8b39f36b1b 100644 --- a/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd2603a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB03 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 3 +// USART0 RTS on PB02 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 2 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd2606a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2606a/sl_clock_manager_oscillator_config.h index ee20501462..fcda1c4c85 100644 --- a/hardware/board/config/brd2606a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2606a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2608a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2608a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2608a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2608a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2703a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2703a/sl_clock_manager_oscillator_config.h index 0e0eb4ba78..1544140002 100644 --- a/hardware/board/config/brd2703a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2703a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2704a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2704a/sl_clock_manager_oscillator_config.h index 8b8740fd42..87c85741c9 100644 --- a/hardware/board/config/brd2704a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2704a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2705a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2705a/sl_clock_manager_oscillator_config.h index 8ff06b607b..77d12d1291 100644 --- a/hardware/board/config/brd2705a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2705a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2709a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2709a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2709a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2709a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2710a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2710a/sl_clock_manager_oscillator_config.h index 72c256c3cd..cf3c80c0bf 100644 --- a/hardware/board/config/brd2710a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2710a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2711a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2711a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2711a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2711a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2713a/btl_euart_driver_cfg.h b/hardware/board/config/brd2713a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..60da9a7afd --- /dev/null +++ b/hardware/board/config/brd2713a/btl_euart_driver_cfg.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PB02 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_B +#define SL_SERIAL_EUART_TX_PIN 2 + +// EUSART0 RX on PB03 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_B +#define SL_SERIAL_EUART_RX_PIN 3 + +// EUSART0 CTS on PA06 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 6 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd2713a/btl_gpio_activation_cfg.h b/hardware/board/config/brd2713a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..e3a5417677 --- /dev/null +++ b/hardware/board/config/brd2713a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY HIGH + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd2713a/btl_uart_driver_cfg.h b/hardware/board/config/brd2713a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..c2d822a359 --- /dev/null +++ b/hardware/board/config/brd2713a/btl_uart_driver_cfg.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PB02 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_B +#define SL_SERIAL_UART_TX_PIN 2 + +// USART0 RX on PB03 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_B +#define SL_SERIAL_UART_RX_PIN 3 + +// USART0 CTS on PA06 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 6 + +// USART0 RTS on PA00 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 0 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd2713a/iot_flash_cfg_mikroe.h b/hardware/board/config/brd2713a/iot_flash_cfg_mikroe.h new file mode 100644 index 0000000000..062d47708a --- /dev/null +++ b/hardware/board/config/brd2713a/iot_flash_cfg_mikroe.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MIKROE_H_ +#define _IOT_FLASH_CFG_MIKROE_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MIKROE_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MIKROE_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MIKROE_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MIKROE_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MIKROE_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MIKROE_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MIKROE_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MIKROE_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MIKROE_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MIKROE_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MIKROE_SPI +// $[USART_IOT_FLASH_CFG_MIKROE_SPI] +#define IOT_FLASH_CFG_MIKROE_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_MIKROE_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_FLASH_CFG_MIKROE_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_MIKROE_SPI_TX_PIN 2 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_MIKROE_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_MIKROE_SPI_RX_PIN 1 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_MIKROE_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_MIKROE_SPI_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_MIKROE_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_MIKROE_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_MIKROE_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2713a/iot_flash_cfg_msc.h b/hardware/board/config/brd2713a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd2713a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd2713a/iot_i2c_cfg_mikroe.h b/hardware/board/config/brd2713a/iot_i2c_cfg_mikroe.h new file mode 100644 index 0000000000..9ce900b35d --- /dev/null +++ b/hardware/board/config/brd2713a/iot_i2c_cfg_mikroe.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_MIKROE_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_MIKROE_H_ +#define _IOT_I2C_CFG_MIKROE_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_MIKROE_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_MIKROE_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_MIKROE_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_MIKROE_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_MIKROE_ENABLE +// $[GPIO_IOT_I2C_CFG_MIKROE_ENABLE] + +// [GPIO_IOT_I2C_CFG_MIKROE_ENABLE]$ + +// IOT_I2C_CFG_MIKROE +// $[I2C_IOT_I2C_CFG_MIKROE] +#define IOT_I2C_CFG_MIKROE_PERIPHERAL I2C1 +#define IOT_I2C_CFG_MIKROE_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_MIKROE_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_MIKROE_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_MIKROE_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_MIKROE_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_MIKROE]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2713a/iot_i2c_cfg_qwiic.h b/hardware/board/config/brd2713a/iot_i2c_cfg_qwiic.h new file mode 100644 index 0000000000..bd3dabc99b --- /dev/null +++ b/hardware/board/config/brd2713a/iot_i2c_cfg_qwiic.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_QWIIC_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_QWIIC_H_ +#define _IOT_I2C_CFG_QWIIC_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_QWIIC_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_QWIIC_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_QWIIC_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_QWIIC_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_QWIIC_ENABLE +// $[GPIO_IOT_I2C_CFG_QWIIC_ENABLE] + +// [GPIO_IOT_I2C_CFG_QWIIC_ENABLE]$ + +// IOT_I2C_CFG_QWIIC +// $[I2C_IOT_I2C_CFG_QWIIC] +#define IOT_I2C_CFG_QWIIC_PERIPHERAL I2C1 +#define IOT_I2C_CFG_QWIIC_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_QWIIC_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_QWIIC_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_QWIIC_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_QWIIC_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_QWIIC]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_QWIIC_H_ */ diff --git a/hardware/board/config/brd2713a/iot_pwm_cfg_led0.h b/hardware/board/config/brd2713a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..40d37d759f --- /dev/null +++ b/hardware/board/config/brd2713a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PA09 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_A +#define IOT_PWM_CFG_LED0_CC0_PIN 9 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd2713a/iot_pwm_cfg_led1.h b/hardware/board/config/brd2713a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..b82fa23f9d --- /dev/null +++ b/hardware/board/config/brd2713a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PC09 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_C +#define IOT_PWM_CFG_LED1_CC0_PIN 9 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd2713a/iot_pwm_cfg_mikroe.h b/hardware/board/config/brd2713a/iot_pwm_cfg_mikroe.h new file mode 100644 index 0000000000..f13b20c80f --- /dev/null +++ b/hardware/board/config/brd2713a/iot_pwm_cfg_mikroe.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_MIKROE_H_ +#define _IOT_PWM_CFG_MIKROE_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_MIKROE_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_MIKROE +// $[TIMER_IOT_PWM_CFG_MIKROE] +#define IOT_PWM_CFG_MIKROE_PERIPHERAL TIMER9 +#define IOT_PWM_CFG_MIKROE_PERIPHERAL_NO 9 + +// TIMER9 CC0 on PA07 +#define IOT_PWM_CFG_MIKROE_CC0_PORT SL_GPIO_PORT_A +#define IOT_PWM_CFG_MIKROE_CC0_PIN 7 + + + +// [TIMER_IOT_PWM_CFG_MIKROE]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2713a/iot_spi_cfg_mikroe.h b/hardware/board/config/brd2713a/iot_spi_cfg_mikroe.h new file mode 100644 index 0000000000..c0a8fbfebb --- /dev/null +++ b/hardware/board/config/brd2713a/iot_spi_cfg_mikroe.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_MIKROE_H_ +#define _IOT_SPI_CFG_MIKROE_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_MIKROE_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_MIKROE_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_MIKROE_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_MIKROE_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_MIKROE_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_MIKROE_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_MIKROE_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_MIKROE_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_MIKROE_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_MIKROE +// $[USART_IOT_SPI_CFG_MIKROE] +#define IOT_SPI_CFG_MIKROE_PERIPHERAL USART0 +#define IOT_SPI_CFG_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_SPI_CFG_MIKROE_TX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_MIKROE_TX_PIN 2 + +// USART0 RX on PC01 +#define IOT_SPI_CFG_MIKROE_RX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_MIKROE_RX_PIN 1 + +// USART0 CLK on PC03 +#define IOT_SPI_CFG_MIKROE_CLK_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_MIKROE_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_SPI_CFG_MIKROE_CS_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_MIKROE_CS_PIN 4 + +// [USART_IOT_SPI_CFG_MIKROE]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2713a/iot_uart_cfg_loopback.h b/hardware/board/config/brd2713a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..6e06046d35 --- /dev/null +++ b/hardware/board/config/brd2713a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PB02 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_B +#define IOT_UART_CFG_LOOPBACK_TX_PIN 2 + +// USART0 RX on PB03 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_B +#define IOT_UART_CFG_LOOPBACK_RX_PIN 3 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 + +// USART0 CTS on PA06 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 6 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd2713a/iot_uart_cfg_mikroe.h b/hardware/board/config/brd2713a/iot_uart_cfg_mikroe.h new file mode 100644 index 0000000000..8fc269fd45 --- /dev/null +++ b/hardware/board/config/brd2713a/iot_uart_cfg_mikroe.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_MIKROE_H_ +#define _IOT_UART_CFG_MIKROE_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_MIKROE_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_MIKROE_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_MIKROE_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_MIKROE_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_MIKROE_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_MIKROE_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_MIKROE_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_MIKROE +// $[USART_IOT_UART_CFG_MIKROE] +#define IOT_UART_CFG_MIKROE_PERIPHERAL USART0 +#define IOT_UART_CFG_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PA04 +#define IOT_UART_CFG_MIKROE_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_MIKROE_TX_PIN 4 + +// USART0 RX on PA05 +#define IOT_UART_CFG_MIKROE_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_MIKROE_RX_PIN 5 + + + + + +// [USART_IOT_UART_CFG_MIKROE]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2713a/iot_uart_cfg_vcom.h b/hardware/board/config/brd2713a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..e04af53dbd --- /dev/null +++ b/hardware/board/config/brd2713a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PB02 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_B +#define IOT_UART_CFG_VCOM_TX_PIN 2 + +// USART0 RX on PB03 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_B +#define IOT_UART_CFG_VCOM_RX_PIN 3 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 0 + +// USART0 CTS on PA06 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 6 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd2713a/sl_board_control_config.h b/hardware/board/config/brd2713a/sl_board_control_config.h new file mode 100644 index 0000000000..ad7793aa7e --- /dev/null +++ b/hardware/board/config/brd2713a/sl_board_control_config.h @@ -0,0 +1,42 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2713a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..1e32569794 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 40000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_clock_manager_tree_config.h b/hardware/board/config/brd2713a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..c87be3c16f --- /dev/null +++ b/hardware/board/config/brd2713a/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd2713a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h b/hardware/board/config/brd2713a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h new file mode 100644 index 0000000000..98b946bd16 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h @@ -0,0 +1,138 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_EUSART_MIKROE_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_EUSART_MIKROE_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_MIKROE_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_MIKROE_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_MIKROE_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_MIKROE_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_MIKROE_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_MIKROE_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_MIKROE_TXC_SYNCTRIG_PRS_CH 4 +// + +// Chip Select PRS Routing +// The Chip Select input to EXTernal Interrupt number <0-7> +// The CS input needs to be routed to a PRS channel in order to manipulate its LDMA SYNCTRIG bit. +// Modify this value to avoid collisions if any specific EXTI number needs to be used elsewhere in the project. +// Note that only EXTI0..7 can be used as input for a PRS channel, and only pins Px0..7 can be routed to those. +// Default : 0 (pin0..4 of any port) +// 0 +#define SL_CPC_DRV_SPI_MIKROE_CS_EXTI_NUMBER 4 +// + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_MIKROE_IRQ +// $[GPIO_SL_CPC_DRV_SPI_MIKROE_IRQ] +#define SL_CPC_DRV_SPI_MIKROE_IRQ_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_IRQ_PIN 0 + +// [GPIO_SL_CPC_DRV_SPI_MIKROE_IRQ]$ + +// SL_CPC_DRV_SPI_MIKROE +// $[EUSART_SL_CPC_DRV_SPI_MIKROE] +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL EUSART1 +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_CPC_DRV_SPI_MIKROE_COPI_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_COPI_PIN 2 + +// EUSART1 RX on PC01 +#define SL_CPC_DRV_SPI_MIKROE_CIPO_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_CIPO_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_CPC_DRV_SPI_MIKROE_SCLK_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_CPC_DRV_SPI_MIKROE_CS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_CS_PIN 4 + +// [EUSART_SL_CPC_DRV_SPI_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_MIKROE_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h b/hardware/board/config/brd2713a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h new file mode 100644 index 0000000000..8ba2842638 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_MIKROE_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_MIKROE_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_MIKROE_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_MIKROE_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_MIKROE_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_MIKROE_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_MIKROE_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_MIKROE_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_MIKROE_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_MIKROE_IRQ +// $[GPIO_SL_CPC_DRV_SPI_MIKROE_IRQ] +#define SL_CPC_DRV_SPI_MIKROE_IRQ_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_IRQ_PIN 0 + +// [GPIO_SL_CPC_DRV_SPI_MIKROE_IRQ]$ + +// SL_CPC_DRV_SPI_MIKROE +// $[USART_SL_CPC_DRV_SPI_MIKROE] +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_CPC_DRV_SPI_MIKROE_COPI_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_COPI_PIN 2 + +// USART0 RX on PC01 +#define SL_CPC_DRV_SPI_MIKROE_CIPO_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_CIPO_PIN 1 + +// USART0 CLK on PC03 +#define SL_CPC_DRV_SPI_MIKROE_CLK_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_CPC_DRV_SPI_MIKROE_CS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_MIKROE_CS_PIN 4 + +// [USART_SL_CPC_DRV_SPI_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_MIKROE_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_cpc_drv_uart_eusart_mikroe_config.h b/hardware/board/config/brd2713a/sl_cpc_drv_uart_eusart_mikroe_config.h new file mode 100644 index 0000000000..582943a9d1 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_drv_uart_eusart_mikroe_config.h @@ -0,0 +1,96 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_MIKROE_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_MIKROE_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_MIKROE_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_MIKROE_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_MIKROE_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_MIKROE_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_MIKROE_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_MIKROE +// $[EUSART_SL_CPC_DRV_UART_MIKROE] +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PA04 +#define SL_CPC_DRV_UART_MIKROE_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_MIKROE_TX_PIN 4 + +// EUSART1 RX on PA05 +#define SL_CPC_DRV_UART_MIKROE_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_MIKROE_RX_PIN 5 + + + +// [EUSART_SL_CPC_DRV_UART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_MIKROE_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd2713a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..97f4b23eca --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PB02 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_UART_VCOM_TX_PIN 2 + +// EUSART0 RX on PB03 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_UART_VCOM_RX_PIN 3 + +// EUSART0 CTS on PA06 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 6 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_cpc_drv_uart_usart_mikroe_config.h b/hardware/board/config/brd2713a/sl_cpc_drv_uart_usart_mikroe_config.h new file mode 100644 index 0000000000..a399a41bf7 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_drv_uart_usart_mikroe_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_MIKROE_CONFIG_H +#define SL_CPC_DRV_UART_USART_MIKROE_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_MIKROE_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_MIKROE_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_MIKROE_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_MIKROE_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_MIKROE_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_MIKROE +// $[USART_SL_CPC_DRV_UART_MIKROE] +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PA04 +#define SL_CPC_DRV_UART_MIKROE_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_MIKROE_TX_PIN 4 + +// USART0 RX on PA05 +#define SL_CPC_DRV_UART_MIKROE_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_MIKROE_RX_PIN 5 + +// USART0 CTS on PA06 +#define SL_CPC_DRV_UART_MIKROE_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_MIKROE_CTS_PIN 6 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_MIKROE_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_MIKROE_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_MIKROE_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd2713a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..9c9484f698 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PB02 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_UART_VCOM_TX_PIN 2 + +// USART0 RX on PB03 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_UART_VCOM_RX_PIN 3 + +// USART0 CTS on PA06 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 6 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd2713a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..f78564792b --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd2713a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..d8327b6c6a --- /dev/null +++ b/hardware/board/config/brd2713a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 0 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd2713a/sl_device_init_dpll_config.h b/hardware/board/config/brd2713a/sl_device_init_dpll_config.h new file mode 100644 index 0000000000..d640c6ea05 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_device_init_dpll_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DPLL Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H +#define SL_DEVICE_INIT_DPLL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// Default: 78000000 +#define SL_DEVICE_INIT_DPLL_FREQ 80000000 + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 3839 +#define SL_DEVICE_INIT_DPLL_N 3839 + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 1919 +#define SL_DEVICE_INIT_DPLL_M 1919 + +// Reference Clock +// Reference clock source for DPLL +// HFXO +// LFXO +// CLKIN0 +// Default: cmuSelect_HFXO +#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// Default: cmuDPLLEdgeSel_Fall +#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// Default: cmuDPLLLockMode_Freq +#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase + +// Automatic Lock Recovery +// Default: 1 +#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 + +// Enable Dither +// Default: 0 +#define SL_DEVICE_INIT_DPLL_DITHER 0 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_device_init_hfxo_config.h b/hardware/board/config/brd2713a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..5c118546ba --- /dev/null +++ b/hardware/board/config/brd2713a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 40000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_device_init_lfxo_config.h b/hardware/board/config/brd2713a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..e331b00d8e --- /dev/null +++ b/hardware/board/config/brd2713a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_i2cspm_mikroe_config.h b/hardware/board/config/brd2713a/sl_i2cspm_mikroe_config.h new file mode 100644 index 0000000000..f2b2ae772f --- /dev/null +++ b/hardware/board/config/brd2713a/sl_i2cspm_mikroe_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_MIKROE_CONFIG_H +#define SL_I2CSPM_MIKROE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_MIKROE_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_MIKROE_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_MIKROE +// $[I2C_SL_I2CSPM_MIKROE] +#define SL_I2CSPM_MIKROE_PERIPHERAL I2C1 +#define SL_I2CSPM_MIKROE_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_MIKROE_SCL_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_MIKROE_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_MIKROE_SDA_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_MIKROE_SDA_PIN 7 + +// [I2C_SL_I2CSPM_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_i2cspm_qwiic_config.h b/hardware/board/config/brd2713a/sl_i2cspm_qwiic_config.h new file mode 100644 index 0000000000..a45973d76f --- /dev/null +++ b/hardware/board/config/brd2713a/sl_i2cspm_qwiic_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_QWIIC_CONFIG_H +#define SL_I2CSPM_QWIIC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_QWIIC_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_QWIIC_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_QWIIC +// $[I2C_SL_I2CSPM_QWIIC] +#define SL_I2CSPM_QWIIC_PERIPHERAL I2C1 +#define SL_I2CSPM_QWIIC_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_QWIIC_SCL_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_QWIIC_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_QWIIC_SDA_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_QWIIC_SDA_PIN 7 + +// [I2C_SL_I2CSPM_QWIIC]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_QWIIC_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_iostream_eusart_mikroe_config.h b/hardware/board/config/brd2713a/sl_iostream_eusart_mikroe_config.h new file mode 100644 index 0000000000..b99fa277bb --- /dev/null +++ b/hardware/board/config/brd2713a/sl_iostream_eusart_mikroe_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_MIKROE_CONFIG_H +#define SL_IOSTREAM_EUSART_MIKROE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_MIKROE_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_MIKROE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_MIKROE_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_MIKROE_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_MIKROE_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_MIKROE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_MIKROE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_MIKROE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_MIKROE +// $[EUSART_SL_IOSTREAM_EUSART_MIKROE] +#define SL_IOSTREAM_EUSART_MIKROE_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PA04 +#define SL_IOSTREAM_EUSART_MIKROE_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_MIKROE_TX_PIN 4 + +// EUSART1 RX on PA05 +#define SL_IOSTREAM_EUSART_MIKROE_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_MIKROE_RX_PIN 5 + + + +// [EUSART_SL_IOSTREAM_EUSART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2713a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd2713a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..6f094b06fb --- /dev/null +++ b/hardware/board/config/brd2713a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PB02 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_B +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 2 + +// EUSART0 RX on PB03 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_B +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 3 + +// EUSART0 CTS on PA06 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 6 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2713a/sl_iostream_usart_mikroe_config.h b/hardware/board/config/brd2713a/sl_iostream_usart_mikroe_config.h new file mode 100644 index 0000000000..92cef39f4b --- /dev/null +++ b/hardware/board/config/brd2713a/sl_iostream_usart_mikroe_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_MIKROE_CONFIG_H +#define SL_IOSTREAM_USART_MIKROE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_MIKROE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_MIKROE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_MIKROE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_MIKROE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_MIKROE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_MIKROE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_MIKROE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_MIKROE +// $[USART_SL_IOSTREAM_USART_MIKROE] +#define SL_IOSTREAM_USART_MIKROE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PA04 +#define SL_IOSTREAM_USART_MIKROE_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_MIKROE_TX_PIN 4 + +// USART0 RX on PA05 +#define SL_IOSTREAM_USART_MIKROE_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_MIKROE_RX_PIN 5 + + + +// [USART_SL_IOSTREAM_USART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2713a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd2713a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..03236eea14 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PB02 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_B +#define SL_IOSTREAM_USART_VCOM_TX_PIN 2 + +// USART0 RX on PB03 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_B +#define SL_IOSTREAM_USART_VCOM_RX_PIN 3 + +// USART0 CTS on PA06 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 6 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2713a/sl_pwm_init_led0_config.h b/hardware/board/config/brd2713a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..1809a97f2f --- /dev/null +++ b/hardware/board/config/brd2713a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PA09 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_A +#define SL_PWM_LED0_OUTPUT_PIN 9 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_pwm_init_led1_config.h b/hardware/board/config/brd2713a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..15d016e589 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PC09 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_C +#define SL_PWM_LED1_OUTPUT_PIN 9 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_pwm_init_mikroe_config.h b/hardware/board/config/brd2713a/sl_pwm_init_mikroe_config.h new file mode 100644 index 0000000000..f468592cfd --- /dev/null +++ b/hardware/board/config/brd2713a/sl_pwm_init_mikroe_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_MIKROE_CONFIG_H +#define SL_PWM_INIT_MIKROE_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_MIKROE_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_MIKROE_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_MIKROE +// $[TIMER_SL_PWM_MIKROE] +#define SL_PWM_MIKROE_PERIPHERAL TIMER9 +#define SL_PWM_MIKROE_PERIPHERAL_NO 9 + +#define SL_PWM_MIKROE_OUTPUT_CHANNEL 0 +// TIMER9 CC0 on PA07 +#define SL_PWM_MIKROE_OUTPUT_PORT SL_GPIO_PORT_A +#define SL_PWM_MIKROE_OUTPUT_PIN 7 + +// [TIMER_SL_PWM_MIKROE]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_rail_util_pti_config.h b/hardware/board/config/brd2713a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..5b05d35a25 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PD05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_simple_button_btn0_config.h b/hardware/board/config/brd2713a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..23e27379c4 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_simple_button_btn1_config.h b/hardware/board/config/brd2713a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..c5980aa392 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 0 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_simple_led_led0_config.h b/hardware/board/config/brd2713a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..8d462d86e6 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_A +#define SL_SIMPLE_LED_LED0_PIN 9 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_simple_led_led1_config.h b/hardware/board/config/brd2713a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..bad67bba22 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_C +#define SL_SIMPLE_LED_LED1_PIN 9 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_spidrv_eusart_mikroe_config.h b/hardware/board/config/brd2713a/sl_spidrv_eusart_mikroe_config.h new file mode 100644 index 0000000000..093b2c6e23 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_spidrv_eusart_mikroe_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_MIKROE_CONFIG_H +#define SL_SPIDRV_EUSART_MIKROE_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_MIKROE_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_MIKROE_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_MIKROE_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_MIKROE_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_MIKROE_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_MIKROE_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_MIKROE_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_MIKROE +// $[EUSART_SL_SPIDRV_EUSART_MIKROE] +#define SL_SPIDRV_EUSART_MIKROE_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_SPIDRV_EUSART_MIKROE_TX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EUSART_MIKROE_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_SPIDRV_EUSART_MIKROE_RX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EUSART_MIKROE_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_SPIDRV_EUSART_MIKROE_SCLK_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EUSART_MIKROE_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_SPIDRV_EUSART_MIKROE_CS_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EUSART_MIKROE_CS_PIN 4 + +// [EUSART_SL_SPIDRV_EUSART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_MIKROE_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd2713a/sl_spidrv_mikroe_config.h b/hardware/board/config/brd2713a/sl_spidrv_mikroe_config.h new file mode 100644 index 0000000000..60c5e68135 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_spidrv_mikroe_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_MIKROE_CONFIG_H +#define SL_SPIDRV_MIKROE_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_MIKROE_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_MIKROE_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_MIKROE_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_MIKROE_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_MIKROE_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_MIKROE_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_MIKROE_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_MIKROE +// $[USART_SL_SPIDRV_MIKROE] +#define SL_SPIDRV_MIKROE_PERIPHERAL USART0 +#define SL_SPIDRV_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_SPIDRV_MIKROE_TX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_MIKROE_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_SPIDRV_MIKROE_RX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_MIKROE_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_SPIDRV_MIKROE_CLK_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_MIKROE_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_SPIDRV_MIKROE_CS_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_MIKROE_CS_PIN 4 + +// [USART_SL_SPIDRV_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_spidrv_usart_mikroe_config.h b/hardware/board/config/brd2713a/sl_spidrv_usart_mikroe_config.h new file mode 100644 index 0000000000..926efffb73 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_spidrv_usart_mikroe_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_MIKROE_CONFIG_H +#define SL_SPIDRV_USART_MIKROE_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_MIKROE_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_MIKROE_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_MIKROE_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_MIKROE_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_MIKROE_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_MIKROE_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_MIKROE_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_MIKROE +// $[USART_SL_SPIDRV_USART_MIKROE] +#define SL_SPIDRV_USART_MIKROE_PERIPHERAL USART0 +#define SL_SPIDRV_USART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_SPIDRV_USART_MIKROE_TX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_MIKROE_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_SPIDRV_USART_MIKROE_RX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_MIKROE_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_SPIDRV_USART_MIKROE_CLK_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_MIKROE_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_SPIDRV_USART_MIKROE_CS_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_MIKROE_CS_PIN 4 + +// [USART_SL_SPIDRV_USART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_uartdrv_eusart_mikroe_config.h b/hardware/board/config/brd2713a/sl_uartdrv_eusart_mikroe_config.h new file mode 100644 index 0000000000..dafa920aec --- /dev/null +++ b/hardware/board/config/brd2713a/sl_uartdrv_eusart_mikroe_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_MIKROE_CONFIG_H +#define SL_UARTDRV_EUSART_MIKROE_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_MIKROE_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_MIKROE_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_MIKROE_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_MIKROE_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_MIKROE_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_MIKROE_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_MIKROE_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_MIKROE_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_MIKROE_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_MIKROE +// $[EUSART_SL_UARTDRV_EUSART_MIKROE] +#define SL_UARTDRV_EUSART_MIKROE_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PA04 +#define SL_UARTDRV_EUSART_MIKROE_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_MIKROE_TX_PIN 4 + +// EUSART1 RX on PA05 +#define SL_UARTDRV_EUSART_MIKROE_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_MIKROE_RX_PIN 5 + + + +// [EUSART_SL_UARTDRV_EUSART_MIKROE]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd2713a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..b38cea08d0 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PB02 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 2 + +// EUSART0 RX on PB03 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 3 + +// EUSART0 CTS on PA06 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 6 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_uartdrv_usart_mikroe_config.h b/hardware/board/config/brd2713a/sl_uartdrv_usart_mikroe_config.h new file mode 100644 index 0000000000..461182469f --- /dev/null +++ b/hardware/board/config/brd2713a/sl_uartdrv_usart_mikroe_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_MIKROE_CONFIG_H +#define SL_UARTDRV_USART_MIKROE_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_MIKROE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_MIKROE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_MIKROE_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_MIKROE_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_MIKROE_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_MIKROE_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_MIKROE_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_MIKROE_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_MIKROE +// $[USART_SL_UARTDRV_USART_MIKROE] +#define SL_UARTDRV_USART_MIKROE_PERIPHERAL USART0 +#define SL_UARTDRV_USART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PA04 +#define SL_UARTDRV_USART_MIKROE_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_MIKROE_TX_PIN 4 + +// USART0 RX on PA05 +#define SL_UARTDRV_USART_MIKROE_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_MIKROE_RX_PIN 5 + + + +// [USART_SL_UARTDRV_USART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2713a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd2713a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..6b3daef9f9 --- /dev/null +++ b/hardware/board/config/brd2713a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PB02 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_TX_PIN 2 + +// USART0 RX on PB03 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_RX_PIN 3 + +// USART0 CTS on PA06 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 6 + +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd2902a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2902a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2902a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2902a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2903a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2903a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2903a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2903a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2904a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2904a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2904a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2904a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd2905a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd2905a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd2905a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd2905a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4108a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4108a/sl_clock_manager_oscillator_config.h index 72c256c3cd..cf3c80c0bf 100644 --- a/hardware/board/config/brd4108a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4108a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4109a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4109a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4109a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4109a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4109a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4109a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4109a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4109a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4110a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4110a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4110a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4110a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4110a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4110a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4110a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4110a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4110b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4110b_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4110b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4110b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_eusart_exp_config.h index 01d786b521..ebee77e994 100644 --- a/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_usart_exp_config.h index fd1930c706..050572650c 100644 --- a/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4110b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART1 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4110b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4110b_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4110b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4110b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_eusart_exp_config.h index 01d786b521..ebee77e994 100644 --- a/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_usart_exp_config.h index fd1930c706..050572650c 100644 --- a/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4110b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART1 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4111a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4111a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4111a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4111a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4111a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4111a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4111a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4111a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4111b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4111b_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4111b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4111b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_eusart_exp_config.h index 01d786b521..ebee77e994 100644 --- a/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_usart_exp_config.h index fd1930c706..050572650c 100644 --- a/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4111b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART1 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4111b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4111b_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4111b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4111b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_eusart_exp_config.h index 01d786b521..ebee77e994 100644 --- a/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_usart_exp_config.h index fd1930c706..050572650c 100644 --- a/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4111b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART1 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4113a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4113a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4113a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4113a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4113a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4113a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4113a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4113a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4115a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4115a_brd4001a/sl_clock_manager_oscillator_config.h index 99aa3461f1..d3e3eeb419 100644 --- a/hardware/board/config/brd4115a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4115a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_eusart_exp_config.h index 01d786b521..63c439b5a6 100644 --- a/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PB00 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 0 +// EUSART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..b2fc1735b2 100644 --- a/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4115a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4115a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4115a_brd4002a/sl_clock_manager_oscillator_config.h index 99aa3461f1..d3e3eeb419 100644 --- a/hardware/board/config/brd4115a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4115a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_eusart_exp_config.h index 01d786b521..63c439b5a6 100644 --- a/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PB00 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 0 +// EUSART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..b2fc1735b2 100644 --- a/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4115a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4115b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4115b_brd4001a/sl_clock_manager_oscillator_config.h index ea810fad52..c6acb3ad93 100644 --- a/hardware/board/config/brd4115b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4115b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_eusart_exp_config.h index 01d786b521..63c439b5a6 100644 --- a/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PB00 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 0 +// EUSART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..b2fc1735b2 100644 --- a/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4115b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4115b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4115b_brd4002a/sl_clock_manager_oscillator_config.h index ea810fad52..c6acb3ad93 100644 --- a/hardware/board/config/brd4115b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4115b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_eusart_exp_config.h index 01d786b521..63c439b5a6 100644 --- a/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PB00 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 0 +// EUSART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..b2fc1735b2 100644 --- a/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4115b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4116a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4116a_brd4001a/sl_clock_manager_oscillator_config.h index 1442c3c4af..418ddfd88a 100644 --- a/hardware/board/config/brd4116a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4116a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4116a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4116a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4116a_brd4002a/sl_clock_manager_oscillator_config.h index 1442c3c4af..418ddfd88a 100644 --- a/hardware/board/config/brd4116a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4116a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4116a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4117a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4117a_brd4001a/sl_clock_manager_oscillator_config.h index 7f2462bf13..6b22cf07df 100644 --- a/hardware/board/config/brd4117a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4117a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4117a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4117a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4117a_brd4002a/sl_clock_manager_oscillator_config.h index 7f2462bf13..6b22cf07df 100644 --- a/hardware/board/config/brd4117a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4117a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4117a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4118a_brd4001a/sl_clock_manager_oscillator_config.h index 7ddc7d46d4..dfd6823540 100644 --- a/hardware/board/config/brd4118a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4118a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_2_config.h index d07927f8ef..3c78dac7fb 100644 --- a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 5 +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_config.h index 881e7a753b..bad894da17 100644 --- a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_EUSART_EXP_RX_PIN 13 +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_2_config.h index 5366cb13e7..7f3438ddd7 100644 --- a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 3 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_config.h index a8134f4585..e356682540 100644 --- a/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4118a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_USART_EXP_RX_PIN 13 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4118a_brd4002a/sl_clock_manager_oscillator_config.h index 7ddc7d46d4..dfd6823540 100644 --- a/hardware/board/config/brd4118a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4118a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_2_config.h index d07927f8ef..3c78dac7fb 100644 --- a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 5 +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_config.h index 881e7a753b..bad894da17 100644 --- a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_EUSART_EXP_RX_PIN 13 +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_2_config.h index 5366cb13e7..7f3438ddd7 100644 --- a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 3 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_config.h index a8134f4585..e356682540 100644 --- a/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4118a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_USART_EXP_RX_PIN 13 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4120a_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..d2d228ce98 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..a687cd1990 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_HOST_INT_PIN 6 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_WAKE_INT_PIN 8 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..323a11c825 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..b4aa816694 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_EUSART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_EUSART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_EXTFLASH_SCLK_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_EUSART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..5ef0b3e933 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..b7275b332d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_EUSART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_EUSART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_RX_PIN 8 + +// EUSART1 CS on PD10 +#define SL_EUSART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_CS_PIN 10 + +// EUSART1 SCLK on PD09 +#define SL_EUSART_SPINCP_SCLK_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_SCLK_PIN 9 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..58f58b3e9b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_USART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_USART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_RX_PIN 8 + +// USART0 CS on PD10 +#define SL_USART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CS_PIN 10 + +// USART0 CLK on PD09 +#define SL_USART_SPINCP_CLK_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CLK_PIN 9 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4120a_brd4001a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..b7d67dfaea --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 0 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_exp.h b/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..aa53eb6930 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 10 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_msc.h b/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..a1d7c4c6b5 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 2 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..8dbfbb4936 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C1 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_EXP_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_EXP_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..2164561334 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_test.h b/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..19af9af4c2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C1 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_TEST_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_TEST_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..c146bb4418 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER9 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 9 + +// TIMER9 CC0 on PB06 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_EXP_CC0_PIN 6 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..dad3db254d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PB02 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..400f7ec1df --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PB04 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED1_CC0_PIN 4 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_spi_cfg_exp.h b/hardware/board/config/brd4120a_brd4001a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..e9619fcda8 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_EXP_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_EXP_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_EXP_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_EXP_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CS_PIN 10 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4120a_brd4001a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..93a3cd124d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 10 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..4971f118c8 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_RX_PIN 13 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..055d076c14 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 10 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..f676da0cf9 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 10 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4120a_brd4001a/legacy_ncp_spi_config.h b/hardware/board/config/brd4120a_brd4001a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..95e855a406 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define LEGACY_NCP_SPI_TX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define LEGACY_NCP_SPI_RX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define LEGACY_NCP_SPI_CLK_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define LEGACY_NCP_SPI_CS_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CS_PIN 10 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_HOST_INT_PIN 6 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_WAKE_INT_PIN 8 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4120a_brd4001a/sl_board_control_config.h new file mode 100644 index 0000000000..94607f2fa6 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_B +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 10 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4120a_brd4001a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..9373231ce6 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 101 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 42 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4120a_brd4001a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..af7f806567 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..dfa8317a75 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_IRQ] +#define SL_CPC_DRV_SPI_EXP_IRQ_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_SPI_EXP_IRQ_PIN 6 + +// [GPIO_SL_CPC_DRV_SPI_EXP_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_SPI_EXP_COPI_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_COPI_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_SPI_EXP_CIPO_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CIPO_PIN 8 + +// USART0 CLK on PD09 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_CPC_DRV_SPI_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CS_PIN 10 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..b4cc679105 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// EUSART1 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// EUSART1 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..0b203e8ec4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..6f1cc4a2fe --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// USART0 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// USART0 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..df33041b0b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..f78564792b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..3db2acad8b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 3 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4120a_brd4001a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..34af287d3d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 101 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4120a_brd4001a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..24254558f2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 42 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_10_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_10_config.h new file mode 100644 index 0000000000..413641b16c --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_10_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_10_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_10_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_10 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_10] +#define SL_EMLIB_GPIO_INIT_EXP_10_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_10_PIN 10 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_10]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7e29751d91 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..bb209aedb5 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 12 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_13_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_13_config.h new file mode 100644 index 0000000000..9bca6524d8 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_13_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_13_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_13_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_13 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_13] +#define SL_EMLIB_GPIO_INIT_EXP_13_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_13_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_13]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..0910e978d0 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 13 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_15_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_15_config.h new file mode 100644 index 0000000000..b0323c7ee7 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_15_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_15_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_15_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_15 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_15] +#define SL_EMLIB_GPIO_INIT_EXP_15_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_15_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_15]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_16_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_16_config.h new file mode 100644 index 0000000000..7375b226b2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_16_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_16_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_16_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_16 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_16] +#define SL_EMLIB_GPIO_INIT_EXP_16_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_16_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_16]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_3_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_3_config.h new file mode 100644 index 0000000000..09639f3d57 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_3_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_3_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_3_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_3 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_3] +#define SL_EMLIB_GPIO_INIT_EXP_3_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_3_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_4_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_4_config.h new file mode 100644 index 0000000000..c1d73c8670 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_4_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_4_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_4_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_4 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_4] +#define SL_EMLIB_GPIO_INIT_EXP_4_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_4_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_5_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_5_config.h new file mode 100644 index 0000000000..7f1ec558ec --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_5_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_5_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_5_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_5 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_5] +#define SL_EMLIB_GPIO_INIT_EXP_5_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_5_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_5]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_6_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_6_config.h new file mode 100644 index 0000000000..7779fdb870 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_6_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_6_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_6_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_6 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_6] +#define SL_EMLIB_GPIO_INIT_EXP_6_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_6_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_6]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..bfe34381a4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_8_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_8_config.h new file mode 100644 index 0000000000..2e54b376fe --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_8_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_8_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_8_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_8 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_8] +#define SL_EMLIB_GPIO_INIT_EXP_8_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_8_PIN 9 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_8]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_9_config.h b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_9_config.h new file mode 100644 index 0000000000..564af0afd7 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_emlib_gpio_init_exp_9_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_9_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_9_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_9 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_9] +#define SL_EMLIB_GPIO_INIT_EXP_9_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_9_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_9]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4120a_brd4001a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..03c4886d4c --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SDA_PIN 7 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_exp_2_config.h b/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_exp_2_config.h new file mode 100644 index 0000000000..1c8cec4fe4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_exp_2_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_2_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_2_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_2_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_2_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_2_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP_2 +// $[EUSART_SL_IOSTREAM_EUSART_EXP_2] +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_IOSTREAM_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_IOSTREAM_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..a32ea6b45b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 13 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..b55733e631 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_exp_2_config.h b/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_exp_2_config.h new file mode 100644 index 0000000000..7f917483d5 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_exp_2_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_2_CONFIG_H +#define SL_IOSTREAM_USART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_2_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP_2 +// $[USART_SL_IOSTREAM_USART_EXP_2] +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_IOSTREAM_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_IOSTREAM_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..5358b1fb6b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_RX_PIN 13 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..53e4d5ea1b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4120a_brd4001a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..00915c9463 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_memlcd_eusart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_MEMLCD_SPI_SCLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_SCLK_PIN 3 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_memlcd_usart_config.h b/hardware/board/config/brd4120a_brd4001a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..78e5f242db --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MEMLCD_SPI_CLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CLK_PIN 3 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4120a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..fcc02c0871 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 3 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4120a_brd4001a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..881e505b88 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4120a_brd4001a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..222bc24e40 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * @file + * @brief OpenThread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 8 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 9 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 6 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_NCP_SPIDRV_USART_TX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_NCP_SPIDRV_USART_RX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_NCP_SPIDRV_USART_CLK_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_NCP_SPIDRV_USART_CS_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CS_PIN 10 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4120a_brd4001a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..0a3361dca2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PB02 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4120a_brd4001a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..ece13eeb73 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PB04 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED1_OUTPUT_PIN 4 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4120a_brd4001a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..7271c8bf05 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4120a_brd4001a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..5b05d35a25 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PD05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4120a_brd4001a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..23e27379c4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4120a_brd4001a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..928a4d5c21 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 3 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4120a_brd4001a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..5de7869377 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_simple_led_led1_config.h b/hardware/board/config/brd4120a_brd4001a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..80a6b55413 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED1_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..707a99a372 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_SPIDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_SPIDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_RX_PIN 8 + +// EUSART1 SCLK on PD09 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 9 + +// EUSART1 CS on PD10 +#define SL_SPIDRV_EUSART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_CS_PIN 10 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4120a_brd4001a/sl_spidrv_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..c3a598114c --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..516ca5fc79 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_USART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_USART_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_USART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_exp_2_config.h new file mode 100644 index 0000000000..3c78dac7fb --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_exp_2_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_2_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_2_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_2_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_2_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_2_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_2_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_2_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_2_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP_2 +// $[EUSART_SL_UARTDRV_EUSART_EXP_2] +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_UARTDRV_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..bad894da17 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_RX_PIN 13 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..f909028771 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_exp_2_config.h new file mode 100644 index 0000000000..7f3438ddd7 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_2_CONFIG_H +#define SL_UARTDRV_USART_EXP_2_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_2_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_2_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP_2 +// $[USART_SL_UARTDRV_USART_EXP_2] +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_UARTDRV_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_RX_PIN 3 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..e356682540 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RX_PIN 13 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..7c85ac0495 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4001a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..d2d228ce98 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..a687cd1990 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_HOST_INT_PIN 6 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_WAKE_INT_PIN 8 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..323a11c825 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..b4aa816694 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_EUSART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_EUSART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_EXTFLASH_SCLK_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_EUSART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..5ef0b3e933 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..b7275b332d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_EUSART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_EUSART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_RX_PIN 8 + +// EUSART1 CS on PD10 +#define SL_EUSART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_CS_PIN 10 + +// EUSART1 SCLK on PD09 +#define SL_EUSART_SPINCP_SCLK_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_SCLK_PIN 9 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..58f58b3e9b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_USART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_USART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_RX_PIN 8 + +// USART0 CS on PD10 +#define SL_USART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CS_PIN 10 + +// USART0 CLK on PD09 +#define SL_USART_SPINCP_CLK_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CLK_PIN 9 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4120a_brd4002a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..b7d67dfaea --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 0 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_exp.h b/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..aa53eb6930 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 10 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_msc.h b/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..a1d7c4c6b5 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 2 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..8dbfbb4936 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C1 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_EXP_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_EXP_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..2164561334 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_test.h b/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..19af9af4c2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C1 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_TEST_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_TEST_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..c146bb4418 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER9 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 9 + +// TIMER9 CC0 on PB06 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_EXP_CC0_PIN 6 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..dad3db254d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PB02 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..400f7ec1df --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PB04 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED1_CC0_PIN 4 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_spi_cfg_exp.h b/hardware/board/config/brd4120a_brd4002a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..e9619fcda8 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_EXP_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_EXP_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_EXP_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_EXP_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CS_PIN 10 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4120a_brd4002a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..93a3cd124d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 10 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..4971f118c8 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_RX_PIN 13 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..055d076c14 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 10 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..f676da0cf9 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 10 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4120a_brd4002a/legacy_ncp_spi_config.h b/hardware/board/config/brd4120a_brd4002a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..95e855a406 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define LEGACY_NCP_SPI_TX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define LEGACY_NCP_SPI_RX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define LEGACY_NCP_SPI_CLK_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define LEGACY_NCP_SPI_CS_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CS_PIN 10 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_HOST_INT_PIN 6 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_WAKE_INT_PIN 8 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4120a_brd4002a/sl_board_control_config.h new file mode 100644 index 0000000000..94607f2fa6 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_B +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 10 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4120a_brd4002a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..9373231ce6 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 101 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 42 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4120a_brd4002a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..af7f806567 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..dfa8317a75 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_IRQ] +#define SL_CPC_DRV_SPI_EXP_IRQ_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_SPI_EXP_IRQ_PIN 6 + +// [GPIO_SL_CPC_DRV_SPI_EXP_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_SPI_EXP_COPI_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_COPI_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_SPI_EXP_CIPO_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CIPO_PIN 8 + +// USART0 CLK on PD09 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_CPC_DRV_SPI_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CS_PIN 10 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..b4cc679105 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// EUSART1 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// EUSART1 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..0b203e8ec4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..6f1cc4a2fe --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// USART0 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// USART0 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..df33041b0b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..f78564792b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..3db2acad8b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 3 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4120a_brd4002a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..34af287d3d --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 101 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4120a_brd4002a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..24254558f2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 42 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_10_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_10_config.h new file mode 100644 index 0000000000..413641b16c --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_10_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_10_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_10_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_10 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_10] +#define SL_EMLIB_GPIO_INIT_EXP_10_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_10_PIN 10 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_10]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7e29751d91 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..bb209aedb5 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 12 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_13_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_13_config.h new file mode 100644 index 0000000000..9bca6524d8 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_13_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_13_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_13_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_13 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_13] +#define SL_EMLIB_GPIO_INIT_EXP_13_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_13_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_13]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..0910e978d0 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 13 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_15_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_15_config.h new file mode 100644 index 0000000000..b0323c7ee7 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_15_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_15_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_15_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_15 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_15] +#define SL_EMLIB_GPIO_INIT_EXP_15_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_15_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_15]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_16_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_16_config.h new file mode 100644 index 0000000000..7375b226b2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_16_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_16_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_16_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_16 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_16] +#define SL_EMLIB_GPIO_INIT_EXP_16_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_16_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_16]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_3_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_3_config.h new file mode 100644 index 0000000000..09639f3d57 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_3_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_3_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_3_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_3 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_3] +#define SL_EMLIB_GPIO_INIT_EXP_3_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_3_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_4_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_4_config.h new file mode 100644 index 0000000000..c1d73c8670 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_4_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_4_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_4_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_4 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_4] +#define SL_EMLIB_GPIO_INIT_EXP_4_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_4_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_5_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_5_config.h new file mode 100644 index 0000000000..7f1ec558ec --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_5_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_5_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_5_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_5 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_5] +#define SL_EMLIB_GPIO_INIT_EXP_5_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_5_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_5]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_6_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_6_config.h new file mode 100644 index 0000000000..7779fdb870 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_6_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_6_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_6_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_6 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_6] +#define SL_EMLIB_GPIO_INIT_EXP_6_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_6_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_6]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..bfe34381a4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_8_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_8_config.h new file mode 100644 index 0000000000..2e54b376fe --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_8_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_8_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_8_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_8 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_8] +#define SL_EMLIB_GPIO_INIT_EXP_8_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_8_PIN 9 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_8]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_9_config.h b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_9_config.h new file mode 100644 index 0000000000..564af0afd7 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_emlib_gpio_init_exp_9_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_9_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_9_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_9 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_9] +#define SL_EMLIB_GPIO_INIT_EXP_9_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_9_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_9]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4120a_brd4002a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..03c4886d4c --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SDA_PIN 7 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_exp_2_config.h b/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_exp_2_config.h new file mode 100644 index 0000000000..1c8cec4fe4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_exp_2_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_2_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_2_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_2_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_2_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_2_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP_2 +// $[EUSART_SL_IOSTREAM_EUSART_EXP_2] +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_IOSTREAM_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_IOSTREAM_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..a32ea6b45b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 13 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..b55733e631 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_exp_2_config.h b/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_exp_2_config.h new file mode 100644 index 0000000000..7f917483d5 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_exp_2_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_2_CONFIG_H +#define SL_IOSTREAM_USART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_2_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP_2 +// $[USART_SL_IOSTREAM_USART_EXP_2] +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_IOSTREAM_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_IOSTREAM_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..5358b1fb6b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_RX_PIN 13 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..53e4d5ea1b --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_joystick_config.h b/hardware/board/config/brd4120a_brd4002a/sl_joystick_config.h new file mode 100644 index 0000000000..2a179fc2ef --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_joystick_config.h @@ -0,0 +1,127 @@ +/***************************************************************************//** + * @file + * @brief Joystick Driver User Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_JOYSTICK_CONFIG_H +#define SL_JOYSTICK_CONFIG_H + +#include "sl_gpio.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Joystick Voltage value Configuration + +// Reference voltage value for analog Joystick signal +// Vref magnitude expressed in millivolts. As per Joystick Hardware on Wireless Pro Kit, Vref = AVDD = 3300 mV +// Default: 3300 +#define REFERENCE_VOLTAGE 3300 + +// Center position mV value +// Default: 3 +#define JOYSTICK_MV_C 3 + +// North position mV value +// Default: 2831 +#define JOYSTICK_MV_N 2831 + +// East position mV value +// Default: 2533 +#define JOYSTICK_MV_E 2533 + +// South position mV value +// Default: 1650 +#define JOYSTICK_MV_S 1650 + +// West position mV value +// Default: 1980 +#define JOYSTICK_MV_W 1980 + +// Joystick error mV value when enabled for Cardinal Directions only +// This value will not be used when joystick is enabled for secondary directions +// Default: 150 +#define JOYSTICK_MV_ERR_CARDINAL_ONLY 150 + +// Enable secondary directions +// Enables secondary directions (NW, NE, SW, SE) +// Note: Joystick Hardware on Wireless Pro Kit does not support Secondary directions +#ifndef ENABLE_SECONDARY_DIRECTIONS +#define ENABLE_SECONDARY_DIRECTIONS 1 +#endif +// Northeast position mV value +// Default: 2247 +#define JOYSTICK_MV_NE 2247 + +// Northwest position mV value +// Default: 1801 +#define JOYSTICK_MV_NW 1801 + +// Southeast position mV value +// Default: 1433 +#define JOYSTICK_MV_SE 1433 + +// Southwest position mV value +// Default: 1238 +#define JOYSTICK_MV_SW 1238 + +// Joystick error mV value when enabled for Cardinal and Secondary Directions +// Default: 75 +#define JOYSTICK_MV_ERR_CARDINAL_AND_SECONDARY 75 + +// end Joystick direction secondary directions selection + +// end Joystick Voltage value Configuration + +// Joystick signal sampling rate Configuration + +// Joystick signal sampling rate [samples/second] +// Sets the sampling rate for Joystick signal +// <50000=> 100 samples/second +// <5000=> 1000 samples/second +// <1000=> 5000 samples/second +// <500=> 10000 samples/second +// <200=> 25000 samples/second +// Default: 50000 +#define TIMER_CYCLES 50000 + +// end Joystick signal sampling rate Configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_JOYSTICK +// $[GPIO_SL_JOYSTICK] +#define SL_JOYSTICK_PORT SL_GPIO_PORT_C +#define SL_JOYSTICK_PIN 11 + +// [GPIO_SL_JOYSTICK]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_JOYSTICK_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4120a_brd4002a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..00915c9463 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_memlcd_eusart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_MEMLCD_SPI_SCLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_SCLK_PIN 3 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_memlcd_usart_config.h b/hardware/board/config/brd4120a_brd4002a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..78e5f242db --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MEMLCD_SPI_CLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CLK_PIN 3 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4120a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4120a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..fcc02c0871 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 3 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4120a_brd4002a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..881e505b88 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4120a_brd4002a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..222bc24e40 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * @file + * @brief OpenThread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 8 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 9 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 6 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_NCP_SPIDRV_USART_TX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_NCP_SPIDRV_USART_RX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_NCP_SPIDRV_USART_CLK_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_NCP_SPIDRV_USART_CS_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CS_PIN 10 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4120a_brd4002a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..0a3361dca2 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PB02 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4120a_brd4002a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..ece13eeb73 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PB04 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED1_OUTPUT_PIN 4 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4120a_brd4002a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..7271c8bf05 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4120a_brd4002a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..5b05d35a25 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PD05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4120a_brd4002a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..23e27379c4 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4120a_brd4002a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..928a4d5c21 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 3 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4120a_brd4002a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..5de7869377 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_simple_led_led1_config.h b/hardware/board/config/brd4120a_brd4002a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..80a6b55413 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED1_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..707a99a372 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_SPIDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_SPIDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_RX_PIN 8 + +// EUSART1 SCLK on PD09 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 9 + +// EUSART1 CS on PD10 +#define SL_SPIDRV_EUSART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_CS_PIN 10 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4120a_brd4002a/sl_spidrv_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..c3a598114c --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..516ca5fc79 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_USART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_USART_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_USART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_exp_2_config.h new file mode 100644 index 0000000000..3c78dac7fb --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_exp_2_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_2_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_2_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_2_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_2_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_2_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_2_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_2_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_2_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP_2 +// $[EUSART_SL_UARTDRV_EUSART_EXP_2] +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_UARTDRV_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..bad894da17 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_RX_PIN 13 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..f909028771 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_exp_2_config.h new file mode 100644 index 0000000000..7f3438ddd7 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_2_CONFIG_H +#define SL_UARTDRV_USART_EXP_2_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_2_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_2_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP_2 +// $[USART_SL_UARTDRV_USART_EXP_2] +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_UARTDRV_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_RX_PIN 3 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..e356682540 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RX_PIN 13 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..7c85ac0495 --- /dev/null +++ b/hardware/board/config/brd4120a_brd4002a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..d2d228ce98 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..a687cd1990 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_HOST_INT_PIN 6 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_WAKE_INT_PIN 8 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..323a11c825 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..b4aa816694 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_EUSART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_EUSART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_EXTFLASH_SCLK_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_EUSART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..5ef0b3e933 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..b7275b332d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_EUSART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_EUSART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_RX_PIN 8 + +// EUSART1 CS on PD10 +#define SL_EUSART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_CS_PIN 10 + +// EUSART1 SCLK on PD09 +#define SL_EUSART_SPINCP_SCLK_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_SCLK_PIN 9 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..58f58b3e9b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_USART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_USART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_RX_PIN 8 + +// USART0 CS on PD10 +#define SL_USART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CS_PIN 10 + +// USART0 CLK on PD09 +#define SL_USART_SPINCP_CLK_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CLK_PIN 9 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4121a_brd4001a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..b7d67dfaea --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 0 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_exp.h b/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..aa53eb6930 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 10 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_msc.h b/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..a1d7c4c6b5 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 2 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..8dbfbb4936 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C1 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_EXP_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_EXP_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..2164561334 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_test.h b/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..19af9af4c2 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C1 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_TEST_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_TEST_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..c146bb4418 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER9 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 9 + +// TIMER9 CC0 on PB06 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_EXP_CC0_PIN 6 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..dad3db254d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PB02 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..400f7ec1df --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PB04 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED1_CC0_PIN 4 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_spi_cfg_exp.h b/hardware/board/config/brd4121a_brd4001a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..e9619fcda8 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_EXP_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_EXP_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_EXP_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_EXP_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CS_PIN 10 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4121a_brd4001a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..93a3cd124d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 10 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..4971f118c8 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_RX_PIN 13 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..055d076c14 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 10 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..f676da0cf9 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 10 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4121a_brd4001a/legacy_ncp_spi_config.h b/hardware/board/config/brd4121a_brd4001a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..95e855a406 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define LEGACY_NCP_SPI_TX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define LEGACY_NCP_SPI_RX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define LEGACY_NCP_SPI_CLK_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define LEGACY_NCP_SPI_CS_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CS_PIN 10 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_HOST_INT_PIN 6 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_WAKE_INT_PIN 8 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4121a_brd4001a/sl_board_control_config.h new file mode 100644 index 0000000000..94607f2fa6 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_B +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 10 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4121a_brd4001a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..6a5ef1d910 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4121a_brd4001a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..af7f806567 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..dfa8317a75 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_IRQ] +#define SL_CPC_DRV_SPI_EXP_IRQ_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_SPI_EXP_IRQ_PIN 6 + +// [GPIO_SL_CPC_DRV_SPI_EXP_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_SPI_EXP_COPI_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_COPI_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_SPI_EXP_CIPO_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CIPO_PIN 8 + +// USART0 CLK on PD09 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_CPC_DRV_SPI_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CS_PIN 10 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..b4cc679105 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// EUSART1 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// EUSART1 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..0b203e8ec4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..6f1cc4a2fe --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// USART0 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// USART0 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..df33041b0b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..f78564792b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..3db2acad8b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 3 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4121a_brd4001a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..e331b00d8e --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_10_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_10_config.h new file mode 100644 index 0000000000..413641b16c --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_10_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_10_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_10_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_10 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_10] +#define SL_EMLIB_GPIO_INIT_EXP_10_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_10_PIN 10 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_10]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7e29751d91 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..bb209aedb5 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 12 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_13_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_13_config.h new file mode 100644 index 0000000000..9bca6524d8 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_13_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_13_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_13_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_13 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_13] +#define SL_EMLIB_GPIO_INIT_EXP_13_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_13_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_13]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..0910e978d0 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 13 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_15_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_15_config.h new file mode 100644 index 0000000000..b0323c7ee7 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_15_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_15_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_15_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_15 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_15] +#define SL_EMLIB_GPIO_INIT_EXP_15_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_15_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_15]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_16_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_16_config.h new file mode 100644 index 0000000000..7375b226b2 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_16_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_16_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_16_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_16 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_16] +#define SL_EMLIB_GPIO_INIT_EXP_16_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_16_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_16]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_3_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_3_config.h new file mode 100644 index 0000000000..09639f3d57 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_3_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_3_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_3_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_3 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_3] +#define SL_EMLIB_GPIO_INIT_EXP_3_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_3_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_4_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_4_config.h new file mode 100644 index 0000000000..c1d73c8670 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_4_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_4_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_4_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_4 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_4] +#define SL_EMLIB_GPIO_INIT_EXP_4_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_4_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_5_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_5_config.h new file mode 100644 index 0000000000..7f1ec558ec --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_5_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_5_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_5_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_5 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_5] +#define SL_EMLIB_GPIO_INIT_EXP_5_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_5_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_5]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_6_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_6_config.h new file mode 100644 index 0000000000..7779fdb870 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_6_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_6_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_6_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_6 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_6] +#define SL_EMLIB_GPIO_INIT_EXP_6_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_6_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_6]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..bfe34381a4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_8_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_8_config.h new file mode 100644 index 0000000000..2e54b376fe --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_8_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_8_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_8_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_8 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_8] +#define SL_EMLIB_GPIO_INIT_EXP_8_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_8_PIN 9 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_8]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_9_config.h b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_9_config.h new file mode 100644 index 0000000000..564af0afd7 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_emlib_gpio_init_exp_9_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_9_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_9_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_9 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_9] +#define SL_EMLIB_GPIO_INIT_EXP_9_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_9_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_9]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4121a_brd4001a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..03c4886d4c --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SDA_PIN 7 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_exp_2_config.h b/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_exp_2_config.h new file mode 100644 index 0000000000..1c8cec4fe4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_exp_2_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_2_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_2_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_2_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_2_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_2_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP_2 +// $[EUSART_SL_IOSTREAM_EUSART_EXP_2] +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_IOSTREAM_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_IOSTREAM_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..a32ea6b45b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 13 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..b55733e631 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_exp_2_config.h b/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_exp_2_config.h new file mode 100644 index 0000000000..7f917483d5 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_exp_2_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_2_CONFIG_H +#define SL_IOSTREAM_USART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_2_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP_2 +// $[USART_SL_IOSTREAM_USART_EXP_2] +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_IOSTREAM_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_IOSTREAM_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..5358b1fb6b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_RX_PIN 13 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..53e4d5ea1b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4121a_brd4001a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..00915c9463 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_memlcd_eusart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_MEMLCD_SPI_SCLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_SCLK_PIN 3 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_memlcd_usart_config.h b/hardware/board/config/brd4121a_brd4001a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..78e5f242db --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MEMLCD_SPI_CLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CLK_PIN 3 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4121a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..fcc02c0871 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 3 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4121a_brd4001a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..881e505b88 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4121a_brd4001a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..222bc24e40 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * @file + * @brief OpenThread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 8 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 9 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 6 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_NCP_SPIDRV_USART_TX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_NCP_SPIDRV_USART_RX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_NCP_SPIDRV_USART_CLK_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_NCP_SPIDRV_USART_CS_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CS_PIN 10 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4121a_brd4001a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..0a3361dca2 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PB02 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4121a_brd4001a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..ece13eeb73 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PB04 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED1_OUTPUT_PIN 4 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4121a_brd4001a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..38a3b20fcc --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4121a_brd4001a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..5b05d35a25 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PD05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4121a_brd4001a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..23e27379c4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4121a_brd4001a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..928a4d5c21 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 3 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4121a_brd4001a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..5de7869377 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_simple_led_led1_config.h b/hardware/board/config/brd4121a_brd4001a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..80a6b55413 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED1_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..707a99a372 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_SPIDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_SPIDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_RX_PIN 8 + +// EUSART1 SCLK on PD09 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 9 + +// EUSART1 CS on PD10 +#define SL_SPIDRV_EUSART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_CS_PIN 10 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4121a_brd4001a/sl_spidrv_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..c3a598114c --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..516ca5fc79 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_USART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_USART_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_USART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_exp_2_config.h new file mode 100644 index 0000000000..3c78dac7fb --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_exp_2_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_2_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_2_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_2_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_2_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_2_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_2_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_2_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_2_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP_2 +// $[EUSART_SL_UARTDRV_EUSART_EXP_2] +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_UARTDRV_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..bad894da17 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_RX_PIN 13 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..f909028771 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_exp_2_config.h new file mode 100644 index 0000000000..7f3438ddd7 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_2_CONFIG_H +#define SL_UARTDRV_USART_EXP_2_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_2_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_2_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP_2 +// $[USART_SL_UARTDRV_USART_EXP_2] +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_UARTDRV_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_RX_PIN 3 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..e356682540 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RX_PIN 13 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..7c85ac0495 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4001a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..d2d228ce98 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..a687cd1990 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_HOST_INT_PIN 6 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_WAKE_INT_PIN 8 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..323a11c825 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..b4aa816694 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_EUSART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_EUSART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_EXTFLASH_SCLK_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_EUSART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..5ef0b3e933 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..b7275b332d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_EUSART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_EUSART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_RX_PIN 8 + +// EUSART1 CS on PD10 +#define SL_EUSART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_CS_PIN 10 + +// EUSART1 SCLK on PD09 +#define SL_EUSART_SPINCP_SCLK_PORT SL_GPIO_PORT_D +#define SL_EUSART_SPINCP_SCLK_PIN 9 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..58f58b3e9b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_USART_SPINCP_TX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_USART_SPINCP_RX_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_RX_PIN 8 + +// USART0 CS on PD10 +#define SL_USART_SPINCP_CS_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CS_PIN 10 + +// USART0 CLK on PD09 +#define SL_USART_SPINCP_CLK_PORT SL_GPIO_PORT_D +#define SL_USART_SPINCP_CLK_PIN 9 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4121a_brd4002a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..b7d67dfaea --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 0 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_exp.h b/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..aa53eb6930 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT SL_GPIO_PORT_D +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 10 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_msc.h b/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..a1d7c4c6b5 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 2 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..8dbfbb4936 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C1 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_EXP_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_EXP_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_EXP_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..2164561334 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_SENSOR_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_test.h b/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..19af9af4c2 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C1 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_TEST_SCL_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_TEST_SDA_PORT SL_GPIO_PORT_C +#define IOT_I2C_CFG_TEST_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..c146bb4418 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER9 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 9 + +// TIMER9 CC0 on PB06 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_EXP_CC0_PIN 6 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..dad3db254d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PB02 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..400f7ec1df --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PB04 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_LED1_CC0_PIN 4 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_spi_cfg_exp.h b/hardware/board/config/brd4121a_brd4002a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..e9619fcda8 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_EXP_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_EXP_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_EXP_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_EXP_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_EXP_CS_PIN 10 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4121a_brd4002a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..93a3cd124d --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 7 + +// USART0 RX on PD08 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 8 + +// USART0 CLK on PD09 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 9 + +// USART0 CS on PD10 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT SL_GPIO_PORT_D +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 10 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..4971f118c8 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_RX_PIN 13 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..055d076c14 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 10 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..f676da0cf9 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 10 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4121a_brd4002a/legacy_ncp_spi_config.h b/hardware/board/config/brd4121a_brd4002a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..95e855a406 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define LEGACY_NCP_SPI_TX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_TX_PIN 7 + +// USART0 RX on PD08 +#define LEGACY_NCP_SPI_RX_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_RX_PIN 8 + +// USART0 CLK on PD09 +#define LEGACY_NCP_SPI_CLK_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CLK_PIN 9 + +// USART0 CS on PD10 +#define LEGACY_NCP_SPI_CS_PORT SL_GPIO_PORT_D +#define LEGACY_NCP_SPI_CS_PIN 10 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_HOST_INT_PIN 6 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_WAKE_INT_PIN 8 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4121a_brd4002a/sl_board_control_config.h new file mode 100644 index 0000000000..94607f2fa6 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_B +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 10 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4121a_brd4002a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..6a5ef1d910 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4121a_brd4002a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..af7f806567 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..dfa8317a75 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_IRQ] +#define SL_CPC_DRV_SPI_EXP_IRQ_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_SPI_EXP_IRQ_PIN 6 + +// [GPIO_SL_CPC_DRV_SPI_EXP_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_SPI_EXP_COPI_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_COPI_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_SPI_EXP_CIPO_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CIPO_PIN 8 + +// USART0 CLK on PD09 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_CPC_DRV_SPI_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_SPI_EXP_CS_PIN 10 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..b4cc679105 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// EUSART1 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// EUSART1 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..0b203e8ec4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..6f1cc4a2fe --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RX_PIN 8 + +// USART0 CTS on PD09 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_CTS_PIN 9 + +// USART0 RTS on PD10 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_CPC_DRV_UART_EXP_RTS_PIN 10 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..df33041b0b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..f78564792b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..3db2acad8b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 3 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4121a_brd4002a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..e331b00d8e --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_10_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_10_config.h new file mode 100644 index 0000000000..413641b16c --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_10_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_10_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_10_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_10 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_10] +#define SL_EMLIB_GPIO_INIT_EXP_10_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_10_PIN 10 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_10]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7e29751d91 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..bb209aedb5 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 12 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_13_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_13_config.h new file mode 100644 index 0000000000..9bca6524d8 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_13_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_13_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_13_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_13 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_13] +#define SL_EMLIB_GPIO_INIT_EXP_13_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_13_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_13]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..0910e978d0 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 13 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_15_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_15_config.h new file mode 100644 index 0000000000..b0323c7ee7 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_15_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_15_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_15_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_15 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_15] +#define SL_EMLIB_GPIO_INIT_EXP_15_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_15_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_15]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_16_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_16_config.h new file mode 100644 index 0000000000..7375b226b2 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_16_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_16_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_16_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_16 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_16] +#define SL_EMLIB_GPIO_INIT_EXP_16_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_16_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_16]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_3_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_3_config.h new file mode 100644 index 0000000000..09639f3d57 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_3_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_3_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_3_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_3 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_3] +#define SL_EMLIB_GPIO_INIT_EXP_3_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_3_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_4_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_4_config.h new file mode 100644 index 0000000000..c1d73c8670 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_4_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_4_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_4_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_4 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_4] +#define SL_EMLIB_GPIO_INIT_EXP_4_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_4_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_5_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_5_config.h new file mode 100644 index 0000000000..7f1ec558ec --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_5_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_5_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_5_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_5 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_5] +#define SL_EMLIB_GPIO_INIT_EXP_5_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_5_PIN 7 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_5]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_6_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_6_config.h new file mode 100644 index 0000000000..7779fdb870 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_6_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_6_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_6_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_6 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_6] +#define SL_EMLIB_GPIO_INIT_EXP_6_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_6_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_6]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..bfe34381a4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_8_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_8_config.h new file mode 100644 index 0000000000..2e54b376fe --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_8_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_8_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_8_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_8 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_8] +#define SL_EMLIB_GPIO_INIT_EXP_8_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_8_PIN 9 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_8]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_9_config.h b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_9_config.h new file mode 100644 index 0000000000..564af0afd7 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_emlib_gpio_init_exp_9_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_9_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_9_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_9 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_9] +#define SL_EMLIB_GPIO_INIT_EXP_9_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_9_PIN 8 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_9]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4121a_brd4002a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..03c4886d4c --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_SENSOR_SCL_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_SENSOR_SDA_PORT SL_GPIO_PORT_C +#define SL_I2CSPM_SENSOR_SDA_PIN 7 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_exp_2_config.h b/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_exp_2_config.h new file mode 100644 index 0000000000..1c8cec4fe4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_exp_2_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_2_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_2_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_2_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_2_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_2_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP_2 +// $[EUSART_SL_IOSTREAM_EUSART_EXP_2] +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_IOSTREAM_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_IOSTREAM_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..a32ea6b45b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 13 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..b55733e631 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_exp_2_config.h b/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_exp_2_config.h new file mode 100644 index 0000000000..7f917483d5 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_exp_2_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_2_CONFIG_H +#define SL_IOSTREAM_USART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_2_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP_2 +// $[USART_SL_IOSTREAM_USART_EXP_2] +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_IOSTREAM_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_IOSTREAM_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..5358b1fb6b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_RX_PIN 13 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..53e4d5ea1b --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_joystick_config.h b/hardware/board/config/brd4121a_brd4002a/sl_joystick_config.h new file mode 100644 index 0000000000..2a179fc2ef --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_joystick_config.h @@ -0,0 +1,127 @@ +/***************************************************************************//** + * @file + * @brief Joystick Driver User Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_JOYSTICK_CONFIG_H +#define SL_JOYSTICK_CONFIG_H + +#include "sl_gpio.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Joystick Voltage value Configuration + +// Reference voltage value for analog Joystick signal +// Vref magnitude expressed in millivolts. As per Joystick Hardware on Wireless Pro Kit, Vref = AVDD = 3300 mV +// Default: 3300 +#define REFERENCE_VOLTAGE 3300 + +// Center position mV value +// Default: 3 +#define JOYSTICK_MV_C 3 + +// North position mV value +// Default: 2831 +#define JOYSTICK_MV_N 2831 + +// East position mV value +// Default: 2533 +#define JOYSTICK_MV_E 2533 + +// South position mV value +// Default: 1650 +#define JOYSTICK_MV_S 1650 + +// West position mV value +// Default: 1980 +#define JOYSTICK_MV_W 1980 + +// Joystick error mV value when enabled for Cardinal Directions only +// This value will not be used when joystick is enabled for secondary directions +// Default: 150 +#define JOYSTICK_MV_ERR_CARDINAL_ONLY 150 + +// Enable secondary directions +// Enables secondary directions (NW, NE, SW, SE) +// Note: Joystick Hardware on Wireless Pro Kit does not support Secondary directions +#ifndef ENABLE_SECONDARY_DIRECTIONS +#define ENABLE_SECONDARY_DIRECTIONS 1 +#endif +// Northeast position mV value +// Default: 2247 +#define JOYSTICK_MV_NE 2247 + +// Northwest position mV value +// Default: 1801 +#define JOYSTICK_MV_NW 1801 + +// Southeast position mV value +// Default: 1433 +#define JOYSTICK_MV_SE 1433 + +// Southwest position mV value +// Default: 1238 +#define JOYSTICK_MV_SW 1238 + +// Joystick error mV value when enabled for Cardinal and Secondary Directions +// Default: 75 +#define JOYSTICK_MV_ERR_CARDINAL_AND_SECONDARY 75 + +// end Joystick direction secondary directions selection + +// end Joystick Voltage value Configuration + +// Joystick signal sampling rate Configuration + +// Joystick signal sampling rate [samples/second] +// Sets the sampling rate for Joystick signal +// <50000=> 100 samples/second +// <5000=> 1000 samples/second +// <1000=> 5000 samples/second +// <500=> 10000 samples/second +// <200=> 25000 samples/second +// Default: 50000 +#define TIMER_CYCLES 50000 + +// end Joystick signal sampling rate Configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_JOYSTICK +// $[GPIO_SL_JOYSTICK] +#define SL_JOYSTICK_PORT SL_GPIO_PORT_C +#define SL_JOYSTICK_PIN 11 + +// [GPIO_SL_JOYSTICK]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_JOYSTICK_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4121a_brd4002a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..00915c9463 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_memlcd_eusart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_MEMLCD_SPI_SCLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_SCLK_PIN 3 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_memlcd_usart_config.h b/hardware/board/config/brd4121a_brd4002a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..78e5f242db --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MEMLCD_SPI_CLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CLK_PIN 3 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4121a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4121a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..fcc02c0871 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// EUSART1 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 3 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4121a_brd4002a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..881e505b88 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 2 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4121a_brd4002a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..222bc24e40 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * @file + * @brief OpenThread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 8 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 9 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 6 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_NCP_SPIDRV_USART_TX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_NCP_SPIDRV_USART_RX_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_NCP_SPIDRV_USART_CLK_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_NCP_SPIDRV_USART_CS_PORT SL_GPIO_PORT_D +#define SL_NCP_SPIDRV_USART_CS_PIN 10 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4121a_brd4002a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..0a3361dca2 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PB02 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4121a_brd4002a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..ece13eeb73 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PB04 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_B +#define SL_PWM_LED1_OUTPUT_PIN 4 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4121a_brd4002a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..38a3b20fcc --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4121a_brd4002a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..5b05d35a25 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PD05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_D +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4121a_brd4002a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..23e27379c4 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4121a_brd4002a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..928a4d5c21 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 3 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4121a_brd4002a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..5de7869377 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_simple_led_led1_config.h b/hardware/board/config/brd4121a_brd4002a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..80a6b55413 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_LED_LED1_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..707a99a372 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PD07 +#define SL_SPIDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_TX_PIN 7 + +// EUSART1 RX on PD08 +#define SL_SPIDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_RX_PIN 8 + +// EUSART1 SCLK on PD09 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 9 + +// EUSART1 CS on PD10 +#define SL_SPIDRV_EUSART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EUSART_EXP_CS_PIN 10 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4121a_brd4002a/sl_spidrv_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..c3a598114c --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..516ca5fc79 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PD07 +#define SL_SPIDRV_USART_EXP_TX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_TX_PIN 7 + +// USART0 RX on PD08 +#define SL_SPIDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_RX_PIN 8 + +// USART0 CLK on PD09 +#define SL_SPIDRV_USART_EXP_CLK_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CLK_PIN 9 + +// USART0 CS on PD10 +#define SL_SPIDRV_USART_EXP_CS_PORT SL_GPIO_PORT_D +#define SL_SPIDRV_USART_EXP_CS_PIN 10 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_exp_2_config.h new file mode 100644 index 0000000000..3c78dac7fb --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_exp_2_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_2_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_2_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_2_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_2_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_2_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_2_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_2_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_2_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP_2 +// $[EUSART_SL_UARTDRV_EUSART_EXP_2] +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL_NO 1 + +// EUSART1 TX on PD02 +#define SL_UARTDRV_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_TX_PIN 2 + +// EUSART1 RX on PD03 +#define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..bad894da17 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC12 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_TX_PIN 12 + +// EUSART1 RX on PC13 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_RX_PIN 13 + +// EUSART1 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 + +// EUSART1 RTS on PB07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..f909028771 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_exp_2_config.h new file mode 100644 index 0000000000..7f3438ddd7 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_2_CONFIG_H +#define SL_UARTDRV_USART_EXP_2_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_2_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_2_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP_2 +// $[USART_SL_UARTDRV_USART_EXP_2] +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_UARTDRV_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_RX_PIN 3 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..e356682540 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC12 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_TX_PIN 12 + +// USART0 RX on PC13 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RX_PIN 13 + +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 + +// USART0 RTS on PB07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..7c85ac0495 --- /dev/null +++ b/hardware/board/config/brd4121a_brd4002a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4171a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4171a_brd4001a/sl_clock_manager_oscillator_config.h index 4c5ba6defd..153a8733e8 100644 --- a/hardware/board/config/brd4171a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4171a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_2_config.h index 0c2be734b7..efe534613b 100644 --- a/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 4 +// USART0 CTS on PC00 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 0 +// USART0 RTS on PC01 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..b25d0df921 100644 --- a/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PC00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PC01 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_vcom_config.h index d1e372ff55..bedd6f7b1f 100644 --- a/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_vcom_config.h +++ b/hardware/board/config/brd4171a_brd4001a/sl_uartdrv_usart_vcom_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_VCOM_RX_PIN 6 +// USART0 CTS on PC00 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +// USART0 RTS on PC01 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_RTS_PIN 1 // [USART_SL_UARTDRV_USART_VCOM]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4171a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4171a_brd4002a/sl_clock_manager_oscillator_config.h index 4c5ba6defd..153a8733e8 100644 --- a/hardware/board/config/brd4171a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4171a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_2_config.h index 0c2be734b7..efe534613b 100644 --- a/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 4 +// USART0 CTS on PC00 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 0 +// USART0 RTS on PC01 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..b25d0df921 100644 --- a/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PC00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PC01 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_vcom_config.h index d1e372ff55..bedd6f7b1f 100644 --- a/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_vcom_config.h +++ b/hardware/board/config/brd4171a_brd4002a/sl_uartdrv_usart_vcom_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_VCOM_RX_PIN 6 +// USART0 CTS on PC00 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +// USART0 RTS on PC01 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_RTS_PIN 1 // [USART_SL_UARTDRV_USART_VCOM]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4176a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4176a_brd4001a/sl_clock_manager_oscillator_config.h index b33ef903d7..3bd61d2ed4 100644 --- a/hardware/board/config/brd4176a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4176a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_2_config.h index ac3e408282..def7bcb8e8 100644 --- a/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 4 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 0 +// USART0 RTS on PB01 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..3f88e267e3 100644 --- a/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PB01 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_vcom_config.h index d1e372ff55..e5bd9dc0eb 100644 --- a/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_vcom_config.h +++ b/hardware/board/config/brd4176a_brd4001a/sl_uartdrv_usart_vcom_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_VCOM_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +// USART0 RTS on PB01 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_RTS_PIN 1 // [USART_SL_UARTDRV_USART_VCOM]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4176a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4176a_brd4002a/sl_clock_manager_oscillator_config.h index b33ef903d7..3bd61d2ed4 100644 --- a/hardware/board/config/brd4176a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4176a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_2_config.h index ac3e408282..def7bcb8e8 100644 --- a/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 4 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 0 +// USART0 RTS on PB01 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..3f88e267e3 100644 --- a/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +// USART0 RTS on PB01 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 1 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_vcom_config.h index d1e372ff55..e5bd9dc0eb 100644 --- a/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_vcom_config.h +++ b/hardware/board/config/brd4176a_brd4002a/sl_uartdrv_usart_vcom_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_VCOM_RX_PIN 6 +// USART0 CTS on PB00 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +// USART0 RTS on PB01 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_VCOM_RTS_PIN 1 // [USART_SL_UARTDRV_USART_VCOM]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4179b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4179b_brd4001a/sl_clock_manager_oscillator_config.h index 030ab9829b..1021f98f19 100644 --- a/hardware/board/config/brd4179b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4179b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4179b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4179b_brd4002a/sl_clock_manager_oscillator_config.h index 030ab9829b..1021f98f19 100644 --- a/hardware/board/config/brd4179b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4179b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4180a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4180a_brd4001a/sl_clock_manager_oscillator_config.h index 610ec6a37a..779a61cc65 100644 --- a/hardware/board/config/brd4180a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4180a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_2_config.h index 0f918d98c2..00a0e5f265 100644 --- a/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 1 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..c0b4db52e0 100644 --- a/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4180a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4180a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4180a_brd4002a/sl_clock_manager_oscillator_config.h index 610ec6a37a..779a61cc65 100644 --- a/hardware/board/config/brd4180a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4180a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_2_config.h index 0f918d98c2..00a0e5f265 100644 --- a/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 1 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..c0b4db52e0 100644 --- a/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4180a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4180b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4180b_brd4001a/sl_clock_manager_oscillator_config.h index c783d6e06e..7431a9380c 100644 --- a/hardware/board/config/brd4180b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4180b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_2_config.h index 5366cb13e7..f1aa3306e0 100644 --- a/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 3 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..c0b4db52e0 100644 --- a/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4180b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4180b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4180b_brd4002a/sl_clock_manager_oscillator_config.h index c783d6e06e..7431a9380c 100644 --- a/hardware/board/config/brd4180b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4180b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_2_config.h index 5366cb13e7..f1aa3306e0 100644 --- a/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 3 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..c0b4db52e0 100644 --- a/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4180b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PC02 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_CTS_PIN 2 +// USART0 RTS on PC03 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RTS_PIN 3 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4181a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4181a_brd4001a/sl_clock_manager_oscillator_config.h index 030ab9829b..1021f98f19 100644 --- a/hardware/board/config/brd4181a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4181a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4181a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4181a_brd4002a/sl_clock_manager_oscillator_config.h index 030ab9829b..1021f98f19 100644 --- a/hardware/board/config/brd4181a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4181a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4181b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4181b_brd4001a/sl_clock_manager_oscillator_config.h index e7f3cc66f9..11c8dbd1f2 100644 --- a/hardware/board/config/brd4181b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4181b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4181b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4181b_brd4002a/sl_clock_manager_oscillator_config.h index e7f3cc66f9..11c8dbd1f2 100644 --- a/hardware/board/config/brd4181b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4181b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4181c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4181c_brd4001a/sl_clock_manager_oscillator_config.h index a19b1d90fa..bf81f408f7 100644 --- a/hardware/board/config/brd4181c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4181c_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4181c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4181c_brd4002a/sl_clock_manager_oscillator_config.h index a19b1d90fa..bf81f408f7 100644 --- a/hardware/board/config/brd4181c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4181c_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4182a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4182a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4182a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4182a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4182a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4182a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4182a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4182a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4183a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4183a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4183a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4183a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4183a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4183a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4183a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4183a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4183b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4183b_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4183b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4183b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4183b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4183b_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4183b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4183b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4183c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4183c_brd4001a/sl_clock_manager_oscillator_config.h index 6e91d57c4b..37cd2cd803 100644 --- a/hardware/board/config/brd4183c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4183c_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4183c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4183c_brd4002a/sl_clock_manager_oscillator_config.h index 6e91d57c4b..37cd2cd803 100644 --- a/hardware/board/config/brd4183c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4183c_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4184a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4184a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4184a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4184a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_2_config.h index 4692c79813..4e41a27065 100644 --- a/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 1 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_config.h index 7f6f55277f..6266efab4d 100644 --- a/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4184a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4184a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4184a/sl_uartdrv_usart_exp_config.h index fd1930c706..d1b876c155 100644 --- a/hardware/board/config/brd4184a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4184a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 8 +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4184b/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4184b/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4184b/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4184b/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_2_config.h index 4f94714657..30e113000b 100644 --- a/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_config.h index 7f6f55277f..6266efab4d 100644 --- a/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4184b/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4184b/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4184b/sl_uartdrv_usart_exp_config.h index fd1930c706..d1b876c155 100644 --- a/hardware/board/config/brd4184b/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4184b/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 8 +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4185a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4185a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4185a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4185a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_2_config.h index 7bafb1a671..78d443e615 100644 --- a/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_config.h index 7f6f55277f..6266efab4d 100644 --- a/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_usart_exp_config.h index fd1930c706..d1b876c155 100644 --- a/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4185a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 8 +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4185a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4185a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4185a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4185a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_2_config.h index 7bafb1a671..78d443e615 100644 --- a/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_2_config.h +++ b/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_2_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_2_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_config.h index 7f6f55277f..6266efab4d 100644 --- a/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 8 +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 7 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_usart_exp_config.h index fd1930c706..d1b876c155 100644 --- a/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4185a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 8 +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 7 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4186a_brd4001a/sl_clock_manager_oscillator_config.h index 742b201507..4d86c24f08 100644 --- a/hardware/board/config/brd4186a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4186a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4186a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4186a_brd4002a/sl_clock_manager_oscillator_config.h index 742b201507..4d86c24f08 100644 --- a/hardware/board/config/brd4186a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4186a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4186a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4186b_brd4001a/sl_clock_manager_oscillator_config.h index 742b201507..4d86c24f08 100644 --- a/hardware/board/config/brd4186b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4186b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4186b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4186b_brd4002a/sl_clock_manager_oscillator_config.h index 742b201507..4d86c24f08 100644 --- a/hardware/board/config/brd4186b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4186b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4186b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4186c_brd4001a/sl_clock_manager_oscillator_config.h index 742b201507..4d86c24f08 100644 --- a/hardware/board/config/brd4186c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4186c_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4186c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4186c_brd4002a/sl_clock_manager_oscillator_config.h index 742b201507..4d86c24f08 100644 --- a/hardware/board/config/brd4186c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4186c_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4186c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4187a_brd4001a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4187a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4187a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4187a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4187a_brd4002a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4187a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4187a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4187a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4187b_brd4001a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4187b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4187b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4187b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4187b_brd4002a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4187b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4187b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4187b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4187c_brd4001a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4187c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4187c_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4187c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4187c_brd4002a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4187c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4187c_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4187c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4188a_brd4001a/sl_clock_manager_oscillator_config.h index 347ed89e59..b4f4da95e8 100644 --- a/hardware/board/config/brd4188a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4188a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4188a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4188a_brd4002a/sl_clock_manager_oscillator_config.h index 347ed89e59..b4f4da95e8 100644 --- a/hardware/board/config/brd4188a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4188a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4188a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4188b_brd4001a/sl_clock_manager_oscillator_config.h index 347ed89e59..b4f4da95e8 100644 --- a/hardware/board/config/brd4188b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4188b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4188b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4188b_brd4002a/sl_clock_manager_oscillator_config.h index 347ed89e59..b4f4da95e8 100644 --- a/hardware/board/config/brd4188b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4188b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4188b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4191a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4191a_brd4001a/sl_clock_manager_oscillator_config.h index 984a00b33f..356568554b 100644 --- a/hardware/board/config/brd4191a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4191a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4191a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4191a_brd4002a/sl_clock_manager_oscillator_config.h index 984a00b33f..356568554b 100644 --- a/hardware/board/config/brd4191a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4191a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4194a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4194a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4194a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4194a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4194a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4194a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4194a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4194a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4195a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4195a_brd4001a/sl_clock_manager_oscillator_config.h index a19b1d90fa..bf81f408f7 100644 --- a/hardware/board/config/brd4195a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4195a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4195a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4195a_brd4002a/sl_clock_manager_oscillator_config.h index a19b1d90fa..bf81f408f7 100644 --- a/hardware/board/config/brd4195a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4195a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4195b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4195b_brd4001a/sl_clock_manager_oscillator_config.h index b6a23153e4..38fa33abda 100644 --- a/hardware/board/config/brd4195b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4195b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4195b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4195b_brd4002a/sl_clock_manager_oscillator_config.h index b6a23153e4..38fa33abda 100644 --- a/hardware/board/config/brd4195b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4195b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4196a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4196a_brd4001a/sl_clock_manager_oscillator_config.h index a19b1d90fa..bf81f408f7 100644 --- a/hardware/board/config/brd4196a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4196a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4196a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4196a_brd4002a/sl_clock_manager_oscillator_config.h index a19b1d90fa..bf81f408f7 100644 --- a/hardware/board/config/brd4196a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4196a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4196b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4196b_brd4001a/sl_clock_manager_oscillator_config.h index a4c032f9e0..15aec549b9 100644 --- a/hardware/board/config/brd4196b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4196b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4196b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4196b_brd4002a/sl_clock_manager_oscillator_config.h index a4c032f9e0..15aec549b9 100644 --- a/hardware/board/config/brd4196b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4196b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4197a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4197a_brd4001a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4197a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4197a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4197a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4197a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4197a_brd4002a/sl_clock_manager_oscillator_config.h index e8ceba6c83..a27898d03c 100644 --- a/hardware/board/config/brd4197a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4197a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4197a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4198a_brd4001a/sl_clock_manager_oscillator_config.h index f672b232fc..4ab072042b 100644 --- a/hardware/board/config/brd4198a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4198a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4198a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4198a_brd4002a/sl_clock_manager_oscillator_config.h index f672b232fc..4ab072042b 100644 --- a/hardware/board/config/brd4198a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4198a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4198a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4198b_brd4001a/sl_clock_manager_oscillator_config.h index 8e40fc81b1..5a1932a03f 100644 --- a/hardware/board/config/brd4198b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4198b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4198b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4198b_brd4002a/sl_clock_manager_oscillator_config.h index 8e40fc81b1..5a1932a03f 100644 --- a/hardware/board/config/brd4198b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4198b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4198b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4199b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4199b_brd4001a/sl_clock_manager_oscillator_config.h index 64f19be252..21ba0e1258 100644 --- a/hardware/board/config/brd4199b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4199b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4199b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4199b_brd4002a/sl_clock_manager_oscillator_config.h index 64f19be252..21ba0e1258 100644 --- a/hardware/board/config/brd4199b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4199b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204a_brd4001a/sl_clock_manager_oscillator_config.h index 7d0e2cff23..a00d2ef4d9 100644 --- a/hardware/board/config/brd4204a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_eusart_exp_config.h index b452a20739..84276c9376 100644 --- a/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUSART2 CTS on PD04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART2 RTS on PD05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_usart_exp_config.h index 4b7aa604eb..4ab67995e8 100644 --- a/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PD04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART0 RTS on PD05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204a_brd4002a/sl_clock_manager_oscillator_config.h index 7d0e2cff23..a00d2ef4d9 100644 --- a/hardware/board/config/brd4204a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_eusart_exp_config.h index b452a20739..84276c9376 100644 --- a/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUSART2 CTS on PD04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART2 RTS on PD05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_usart_exp_config.h index 4b7aa604eb..4ab67995e8 100644 --- a/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PD04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART0 RTS on PD05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204b_brd4001a/sl_clock_manager_oscillator_config.h index 84ee679f40..454e67b92e 100644 --- a/hardware/board/config/brd4204b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204b_brd4002a/sl_clock_manager_oscillator_config.h index 84ee679f40..454e67b92e 100644 --- a/hardware/board/config/brd4204b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204c_brd4001a/sl_clock_manager_oscillator_config.h index 84ee679f40..454e67b92e 100644 --- a/hardware/board/config/brd4204c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204c_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204c_brd4002a/sl_clock_manager_oscillator_config.h index 84ee679f40..454e67b92e 100644 --- a/hardware/board/config/brd4204c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204c_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204d_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204d_brd4001a/sl_clock_manager_oscillator_config.h index f921f5e822..3b08a0b7df 100644 --- a/hardware/board/config/brd4204d_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204d_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204d_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204d_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4204d_brd4002a/sl_clock_manager_oscillator_config.h index f921f5e822..3b08a0b7df 100644 --- a/hardware/board/config/brd4204d_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4204d_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4204d_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4205a_brd4001a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4205a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4205a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4205a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4205a_brd4002a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4205a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4205a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4205a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4205b_brd4001a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4205b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4205b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4205b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4205b_brd4002a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4205b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4205b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4205b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4210a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4210a_brd4001a/sl_clock_manager_oscillator_config.h index c2d005d355..b810b1b85e 100644 --- a/hardware/board/config/brd4210a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4210a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4210a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4210a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4210a_brd4002a/sl_clock_manager_oscillator_config.h index c2d005d355..b810b1b85e 100644 --- a/hardware/board/config/brd4210a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4210a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4210a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4263a_brd4001a/sl_clock_manager_oscillator_config.h index 7d0e2cff23..a00d2ef4d9 100644 --- a/hardware/board/config/brd4263a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4263a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_eusart_exp_config.h index b452a20739..84276c9376 100644 --- a/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUSART2 CTS on PD04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART2 RTS on PD05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_usart_exp_config.h index 4b7aa604eb..4ab67995e8 100644 --- a/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4263a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PD04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART0 RTS on PD05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4263a_brd4002a/sl_clock_manager_oscillator_config.h index 7d0e2cff23..a00d2ef4d9 100644 --- a/hardware/board/config/brd4263a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4263a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_eusart_exp_config.h index b452a20739..84276c9376 100644 --- a/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUSART2 CTS on PD04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART2 RTS on PD05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_usart_exp_config.h index 4b7aa604eb..4ab67995e8 100644 --- a/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4263a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PD04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART0 RTS on PD05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4263b_brd4001a/sl_clock_manager_oscillator_config.h index 65ed5d9107..89152b7287 100644 --- a/hardware/board/config/brd4263b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4263b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4263b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4263b_brd4002a/sl_clock_manager_oscillator_config.h index 65ed5d9107..89152b7287 100644 --- a/hardware/board/config/brd4263b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4263b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4263b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4263c_brd4001a/sl_clock_manager_oscillator_config.h index 65ed5d9107..89152b7287 100644 --- a/hardware/board/config/brd4263c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4263c_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4263c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4263c_brd4002a/sl_clock_manager_oscillator_config.h index 65ed5d9107..89152b7287 100644 --- a/hardware/board/config/brd4263c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4263c_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4263c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4264a_brd4001a/sl_clock_manager_oscillator_config.h index 7d0e2cff23..a00d2ef4d9 100644 --- a/hardware/board/config/brd4264a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4264a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_eusart_exp_config.h index b452a20739..84276c9376 100644 --- a/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUSART2 CTS on PD04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART2 RTS on PD05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_usart_exp_config.h index 4b7aa604eb..4ab67995e8 100644 --- a/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4264a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PD04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART0 RTS on PD05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4264a_brd4002a/sl_clock_manager_oscillator_config.h index 7d0e2cff23..a00d2ef4d9 100644 --- a/hardware/board/config/brd4264a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4264a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_eusart_exp_config.h index b452a20739..84276c9376 100644 --- a/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUSART2 CTS on PD04 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 4 +// EUSART2 RTS on PD05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_usart_exp_config.h index 4b7aa604eb..4ab67995e8 100644 --- a/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4264a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PD04 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_CTS_PIN 4 +// USART0 RTS on PD05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4264b_brd4001a/sl_clock_manager_oscillator_config.h index 23275540c3..332e326808 100644 --- a/hardware/board/config/brd4264b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4264b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4264b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4264b_brd4002a/sl_clock_manager_oscillator_config.h index 23275540c3..332e326808 100644 --- a/hardware/board/config/brd4264b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4264b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4264b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4264c_brd4001a/sl_clock_manager_oscillator_config.h index 23275540c3..332e326808 100644 --- a/hardware/board/config/brd4264c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4264c_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4264c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4264c_brd4002a/sl_clock_manager_oscillator_config.h index 23275540c3..332e326808 100644 --- a/hardware/board/config/brd4264c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4264c_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4264c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4265a_brd4001a/sl_clock_manager_oscillator_config.h index 7a713a1239..c0d27796ba 100644 --- a/hardware/board/config/brd4265a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4265a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4265a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4265a_brd4002a/sl_clock_manager_oscillator_config.h index 7a713a1239..c0d27796ba 100644 --- a/hardware/board/config/brd4265a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4265a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4265a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4265b_brd4001a/sl_clock_manager_oscillator_config.h index 7a713a1239..c0d27796ba 100644 --- a/hardware/board/config/brd4265b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4265b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4265b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4265b_brd4002a/sl_clock_manager_oscillator_config.h index 7a713a1239..c0d27796ba 100644 --- a/hardware/board/config/brd4265b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4265b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4265b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4270a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4270a_brd4001a/sl_clock_manager_oscillator_config.h index e21b9e8c21..55146dc154 100644 --- a/hardware/board/config/brd4270a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4270a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4270a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4270a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4270a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4270a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4270a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4270a_brd4002a/sl_clock_manager_oscillator_config.h index e21b9e8c21..55146dc154 100644 --- a/hardware/board/config/brd4270a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4270a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4270a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4270a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4270a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4270a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4270b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4270b_brd4001a/sl_clock_manager_oscillator_config.h index e21b9e8c21..55146dc154 100644 --- a/hardware/board/config/brd4270b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4270b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4270b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4270b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4270b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4270b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4270b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4270b_brd4002a/sl_clock_manager_oscillator_config.h index e21b9e8c21..55146dc154 100644 --- a/hardware/board/config/brd4270b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4270b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4270b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4270b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4270b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4270b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4271a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4271a_brd4001a/sl_clock_manager_oscillator_config.h index 3712337acb..95bfe95200 100644 --- a/hardware/board/config/brd4271a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4271a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4271a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4271a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4271a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4271a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4271a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4271a_brd4002a/sl_clock_manager_oscillator_config.h index 3712337acb..95bfe95200 100644 --- a/hardware/board/config/brd4271a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4271a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4271a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4271a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4271a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4271a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4272a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4272a_brd4001a/sl_clock_manager_oscillator_config.h index 3712337acb..95bfe95200 100644 --- a/hardware/board/config/brd4272a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4272a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4272a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4272a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4272a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4272a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4272a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4272a_brd4002a/sl_clock_manager_oscillator_config.h index 3712337acb..95bfe95200 100644 --- a/hardware/board/config/brd4272a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4272a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4272a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4272a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4272a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4272a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4276a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4276a_brd4001a/sl_clock_manager_oscillator_config.h index 9e8773fa6d..f90d5ee64f 100644 --- a/hardware/board/config/brd4276a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4276a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4276a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4276a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4276a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4276a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4276a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4276a_brd4002a/sl_clock_manager_oscillator_config.h index 9e8773fa6d..f90d5ee64f 100644 --- a/hardware/board/config/brd4276a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4276a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4276a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4276a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4276a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4276a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4308a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308a_brd4001a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4308a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308a_brd4002a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4308b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308b_brd4001a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4308b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308b_brd4002a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4308c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308c_brd4001a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308c_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4308c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308c_brd4002a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308c_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4308d_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308d_brd4001a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308d_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308d_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4308d_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4308d_brd4002a/sl_clock_manager_oscillator_config.h index 6ac1f6198f..7d7d9fb621 100644 --- a/hardware/board/config/brd4308d_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4308d_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4309a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4309a_brd4001a/sl_clock_manager_oscillator_config.h index 10a7176bfa..4257d72fb4 100644 --- a/hardware/board/config/brd4309a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4309a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4309a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4309a_brd4002a/sl_clock_manager_oscillator_config.h index 10a7176bfa..4257d72fb4 100644 --- a/hardware/board/config/brd4309a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4309a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4309b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4309b_brd4001a/sl_clock_manager_oscillator_config.h index 10a7176bfa..4257d72fb4 100644 --- a/hardware/board/config/brd4309b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4309b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4309b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4309b_brd4002a/sl_clock_manager_oscillator_config.h index 10a7176bfa..4257d72fb4 100644 --- a/hardware/board/config/brd4309b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4309b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4310a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4310a_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4310a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4310a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4310a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4310a_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4310a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4310a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4311a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4311a_brd4001a/sl_clock_manager_oscillator_config.h index cfbe348662..7e3b71ab33 100644 --- a/hardware/board/config/brd4311a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4311a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4311a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4311a_brd4002a/sl_clock_manager_oscillator_config.h index cfbe348662..7e3b71ab33 100644 --- a/hardware/board/config/brd4311a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4311a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4311b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4311b_brd4001a/sl_clock_manager_oscillator_config.h index cfbe348662..7e3b71ab33 100644 --- a/hardware/board/config/brd4311b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4311b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4311b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4311b_brd4002a/sl_clock_manager_oscillator_config.h index cfbe348662..7e3b71ab33 100644 --- a/hardware/board/config/brd4311b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4311b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4312a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4312a_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4312a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4312a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4312a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4312a_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4312a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4312a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4314a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4314a/sl_clock_manager_oscillator_config.h index cfbe348662..7e3b71ab33 100644 --- a/hardware/board/config/brd4314a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4314a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4316a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4316a_brd4001a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd4316a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4316a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4316a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4316a_brd4002a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd4316a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4316a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4317a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4317a_brd4001a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd4317a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4317a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4317a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4317a_brd4002a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd4317a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4317a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4318a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4318a_brd4001a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd4318a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4318a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4318a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4318a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4318a_brd4002a/sl_clock_manager_oscillator_config.h index 29a791048e..6a5ef1d910 100644 --- a/hardware/board/config/brd4318a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4318a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4318a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4319a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4319a_brd4001a/sl_clock_manager_oscillator_config.h index 8b8740fd42..87c85741c9 100644 --- a/hardware/board/config/brd4319a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4319a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4319a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4319a_brd4002a/sl_clock_manager_oscillator_config.h index 8b8740fd42..87c85741c9 100644 --- a/hardware/board/config/brd4319a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4319a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4328a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4328a_brd4001a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4328a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4328a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4328a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4328a_brd4002a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4328a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4328a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4328a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4328b_brd4001a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4328b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4328b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4328b_brd4002a/sl_clock_manager_oscillator_config.h index 7bc0137384..226a8a7d33 100644 --- a/hardware/board/config/brd4328b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4328b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..eba856839f 100644 --- a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 10 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..20d9fbf92e 100644 --- a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2290372915 100644 --- a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 10 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4329a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4329a_brd4001a/sl_clock_manager_oscillator_config.h index d0090aae4a..1d1170e306 100644 --- a/hardware/board/config/brd4329a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4329a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4329a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4329a_brd4002a/sl_clock_manager_oscillator_config.h index d0090aae4a..1d1170e306 100644 --- a/hardware/board/config/brd4329a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4329a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4330a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4330a_brd4001a/sl_clock_manager_oscillator_config.h index cfbe348662..7e3b71ab33 100644 --- a/hardware/board/config/brd4330a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4330a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4330a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4330a_brd4002a/sl_clock_manager_oscillator_config.h index cfbe348662..7e3b71ab33 100644 --- a/hardware/board/config/brd4330a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4330a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4331a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4331a_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4331a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4331a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4331a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4331a_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..36304c8a18 100644 --- a/hardware/board/config/brd4331a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4331a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4332a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4332a_brd4001a/sl_clock_manager_oscillator_config.h index b627186a62..25cb495f74 100644 --- a/hardware/board/config/brd4332a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4332a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4332a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4332a_brd4002a/sl_clock_manager_oscillator_config.h index b627186a62..25cb495f74 100644 --- a/hardware/board/config/brd4332a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4332a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4335a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4335a_brd4001a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4335a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4335a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4335a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4335a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4335a_brd4002a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4335a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4335a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4335a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4337a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4337a_brd4001a/sl_clock_manager_oscillator_config.h index 8b8740fd42..87c85741c9 100644 --- a/hardware/board/config/brd4337a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4337a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4337a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4337a_brd4002a/sl_clock_manager_oscillator_config.h index 8b8740fd42..87c85741c9 100644 --- a/hardware/board/config/brd4337a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4337a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4350a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4350a_brd4001a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4350a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4350a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_eusart_exp_config.h index 01d786b521..97b6244e32 100644 --- a/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA09 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 9 +// EUSART0 RTS on PB05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_2_config.h index 99212638b2..79600a4a75 100644 --- a/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..5a1d01975b 100644 --- a/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4350a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4350a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4350a_brd4002a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4350a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4350a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_eusart_exp_config.h index 01d786b521..97b6244e32 100644 --- a/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA09 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 9 +// EUSART0 RTS on PB05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_2_config.h index 99212638b2..79600a4a75 100644 --- a/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..5a1d01975b 100644 --- a/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4350a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4351a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4351a_brd4001a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4351a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4351a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_eusart_exp_config.h index 01d786b521..97b6244e32 100644 --- a/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA09 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 9 +// EUSART0 RTS on PB05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_2_config.h index 99212638b2..79600a4a75 100644 --- a/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_config.h index d44463bec2..5a1d01975b 100644 --- a/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4351a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4351a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4351a_brd4002a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4351a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4351a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_eusart_exp_config.h index 01d786b521..97b6244e32 100644 --- a/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 6 +// EUSART0 CTS on PA09 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 9 +// EUSART0 RTS on PB05 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 5 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_2_config.h index 99212638b2..79600a4a75 100644 --- a/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_config.h index d44463bec2..5a1d01975b 100644 --- a/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4351a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 6 +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 9 +// USART0 RTS on PB05 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_RTS_PIN 5 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4400a_brd4001a/sl_clock_manager_oscillator_config.h index ff3c26a2f0..f0afce4b58 100644 --- a/hardware/board/config/brd4400a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4400a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4400a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4400a_brd4002a/sl_clock_manager_oscillator_config.h index ff3c26a2f0..f0afce4b58 100644 --- a/hardware/board/config/brd4400a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4400a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4400a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4400b_brd4001a/sl_clock_manager_oscillator_config.h index ff3c26a2f0..f0afce4b58 100644 --- a/hardware/board/config/brd4400b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4400b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4400b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4400b_brd4002a/sl_clock_manager_oscillator_config.h index ff3c26a2f0..f0afce4b58 100644 --- a/hardware/board/config/brd4400b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4400b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4400b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4400c_brd4001a/sl_clock_manager_oscillator_config.h index 877e05f38f..04dadff4dd 100644 --- a/hardware/board/config/brd4400c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4400c_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4400c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4400c_brd4002a/sl_clock_manager_oscillator_config.h index 877e05f38f..04dadff4dd 100644 --- a/hardware/board/config/brd4400c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4400c_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4400c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4401a_brd4001a/sl_clock_manager_oscillator_config.h index 041f7bc298..f0ce37d1fa 100644 --- a/hardware/board/config/brd4401a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4401a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4401a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4401a_brd4002a/sl_clock_manager_oscillator_config.h index 041f7bc298..f0ce37d1fa 100644 --- a/hardware/board/config/brd4401a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4401a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4401a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4401b_brd4001a/sl_clock_manager_oscillator_config.h index 041f7bc298..f0ce37d1fa 100644 --- a/hardware/board/config/brd4401b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4401b_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4401b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4401b_brd4002a/sl_clock_manager_oscillator_config.h index 041f7bc298..f0ce37d1fa 100644 --- a/hardware/board/config/brd4401b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4401b_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4401b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4401c_brd4001a/sl_clock_manager_oscillator_config.h index 71af26a751..a3d4d955b7 100644 --- a/hardware/board/config/brd4401c_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4401c_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4401c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4401c_brd4002a/sl_clock_manager_oscillator_config.h index 71af26a751..a3d4d955b7 100644 --- a/hardware/board/config/brd4401c_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4401c_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_2_config.h index 4f5fe5ab92..ba59f0ae9a 100644 --- a/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_B #define SL_UARTDRV_USART_EXP_2_RX_PIN 5 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_config.h index 694aaa56ec..02a85a731c 100644 --- a/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4401c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_D #define SL_UARTDRV_USART_EXP_RX_PIN 12 +// USART0 CTS on PA11 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 11 +// USART0 RTS on PA12 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 12 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4402a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4402a_brd4001a/sl_clock_manager_oscillator_config.h index a216404a25..0564d16155 100644 --- a/hardware/board/config/brd4402a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4402a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4402a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4402a_brd4002a/sl_clock_manager_oscillator_config.h index a216404a25..0564d16155 100644 --- a/hardware/board/config/brd4402a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4402a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4402b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4402b_brd4001a/sl_clock_manager_oscillator_config.h index 055b89c372..824936e698 100644 --- a/hardware/board/config/brd4402b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4402b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4402b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4402b_brd4002a/sl_clock_manager_oscillator_config.h index 055b89c372..824936e698 100644 --- a/hardware/board/config/brd4402b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4402b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4402c_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4402c_brd4001a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..cbb40905ec --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 7 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 4 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4402c_brd4001a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..05de747836 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_HOST_INT_PIN 0 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_WAKE_INT_PIN 1 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4402c_brd4001a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..b38ae4ac3f --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 0 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4402c_brd4001a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..51f5098ecf --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CLK_PIN 2 + +// USART0 CS on PA04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_A +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4402c_brd4001a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..f9be2de3e2 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_USART_SPINCP_TX_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_USART_SPINCP_RX_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_RX_PIN 1 + +// USART0 CS on PC03 +#define SL_USART_SPINCP_CS_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_CS_PIN 3 + +// USART0 CLK on PC02 +#define SL_USART_SPINCP_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_CLK_PIN 2 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4402c_brd4001a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..5cc59a69af --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART1 +#define SL_SERIAL_UART_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 7 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 4 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_exp.h b/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..187125d2ec --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 2 + +// USART0 CS on PC03 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 3 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_msc.h b/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..68aa4da557 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 + +// USART0 CS on PA04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_A +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..e73d96fffd --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_ENABLE_PIN 0 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C0 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_EXP_SCL_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_EXP_SDA_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..db08bfb656 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C0 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_SENSOR_SCL_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_SENSOR_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_SENSOR_SDA_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_SENSOR_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_test.h b/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..da5b1dc1f7 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_ENABLE_PIN 0 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C0 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_TEST_SCL_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_TEST_SDA_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..e5c9b7ec52 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 + +// TIMER4 CC0 on PB00 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_EXP_CC0_PIN 0 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..3491018781 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PD02 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_D +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..591df6b19b --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PD03 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_D +#define IOT_PWM_CFG_LED1_CC0_PIN 3 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_spi_cfg_exp.h b/hardware/board/config/brd4402c_brd4001a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..33497d70b2 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_SPI_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_SPI_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_SPI_CFG_EXP_CLK_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define IOT_SPI_CFG_EXP_CS_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_CS_PIN 3 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4402c_brd4001a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..6ec57a4d66 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 2 + +// USART0 CS on PC03 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 3 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..7bc06206fc --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART1 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_EXP_TX_PIN 5 + +// USART1 RX on PA06 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_EXP_RX_PIN 6 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..845944789a --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART1 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_TX_PIN 5 + +// USART1 RX on PA06 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RX_PIN 6 + + + +// USART1 RTS on PA07 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 7 + +// USART1 CTS on PA08 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 8 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..8fc73b21fc --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART1 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RX_PIN 6 + + + +// USART1 RTS on PA07 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 7 + +// USART1 CTS on PA08 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 8 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4402c_brd4001a/legacy_ncp_spi_config.h b/hardware/board/config/brd4402c_brd4001a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..1487968f4d --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define LEGACY_NCP_SPI_TX_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_TX_PIN 0 + +// USART0 RX on PC01 +#define LEGACY_NCP_SPI_RX_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_RX_PIN 1 + +// USART0 CLK on PC02 +#define LEGACY_NCP_SPI_CLK_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_CLK_PIN 2 + +// USART0 CS on PC03 +#define LEGACY_NCP_SPI_CS_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_CS_PIN 3 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_HOST_INT_PIN 0 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_WAKE_INT_PIN 1 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4402c_brd4001a/sl_board_control_config.h new file mode 100644 index 0000000000..fc167dba21 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_B +#define SL_BOARD_ENABLE_VCOM_PIN 4 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_DISPLAY_PIN 7 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 7 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4402c_brd4001a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..36304c8a18 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,285 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 38400000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 76800000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4402c_brd4001a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..6a44cecbe8 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_clock_manager_tree_config.h @@ -0,0 +1,243 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPBCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// CLKIN0 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPBCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for RTCCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE +#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUARTCLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// Selection of the Clock source for EUARTCLK +// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..3929cb1f70 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_IRQ] +#define SL_CPC_DRV_SPI_EXP_IRQ_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_SPI_EXP_IRQ_PIN 0 + +// [GPIO_SL_CPC_DRV_SPI_EXP_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_CPC_DRV_SPI_EXP_COPI_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_COPI_PIN 0 + +// USART0 RX on PC01 +#define SL_CPC_DRV_SPI_EXP_CIPO_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_CIPO_PIN 1 + +// USART0 CLK on PC02 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_CPC_DRV_SPI_EXP_CS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..5e99fd9d9d --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC00 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 + +// EUART0 RX on PC01 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 1 + +// EUART0 CTS on PC02 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 + +// EUART0 RTS on PC03 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..4f35b18129 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..2642727825 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 1 + +// USART0 CTS on PC02 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 + +// USART0 RTS on PC03 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..b80c07a89a --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART1 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..ce3b9b9242 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 0 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..bcec27f078 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4402c_brd4001a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..e331b00d8e --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_10_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_10_config.h new file mode 100644 index 0000000000..53fb502248 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_10_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_10_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_10_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_10 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_10] +#define SL_EMLIB_GPIO_INIT_EXP_10_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_10_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_10]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7e29751d91 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..6587ff3226 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_13_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_13_config.h new file mode 100644 index 0000000000..9bca6524d8 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_13_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_13_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_13_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_13 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_13] +#define SL_EMLIB_GPIO_INIT_EXP_13_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_13_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_13]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..d2b40ac01e --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_15_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_15_config.h new file mode 100644 index 0000000000..e5e7b97bea --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_15_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_15_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_15_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_15 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_15] +#define SL_EMLIB_GPIO_INIT_EXP_15_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_15_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_15]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_16_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_16_config.h new file mode 100644 index 0000000000..31c77c28f0 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_16_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_16_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_16_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_16 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_16] +#define SL_EMLIB_GPIO_INIT_EXP_16_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_16_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_16]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_4_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_4_config.h new file mode 100644 index 0000000000..dad871b441 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_4_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_4_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_4_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_4 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_4] +#define SL_EMLIB_GPIO_INIT_EXP_4_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_4_PIN 0 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_6_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_6_config.h new file mode 100644 index 0000000000..ce92dd3c79 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_6_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_6_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_6_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_6 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_6] +#define SL_EMLIB_GPIO_INIT_EXP_6_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_6_PIN 1 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_6]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..c762679cdf --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 0 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_8_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_8_config.h new file mode 100644 index 0000000000..15e155b3c8 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_8_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_8_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_8_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_8 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_8] +#define SL_EMLIB_GPIO_INIT_EXP_8_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_8_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_8]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_9_config.h b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_9_config.h new file mode 100644 index 0000000000..a1a60a9c60 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_emlib_gpio_init_exp_9_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_9_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_9_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_9 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_9] +#define SL_EMLIB_GPIO_INIT_EXP_9_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_9_PIN 1 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_9]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4402c_brd4001a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..ed664d1067 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C0 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define SL_I2CSPM_SENSOR_SCL_PORT SL_GPIO_PORT_B +#define SL_I2CSPM_SENSOR_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define SL_I2CSPM_SENSOR_SDA_PORT SL_GPIO_PORT_B +#define SL_I2CSPM_SENSOR_SDA_PIN 3 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_exp_2_config.h b/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_exp_2_config.h new file mode 100644 index 0000000000..527c23b414 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_exp_2_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_2_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_2_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_2_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_2_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_2_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP_2 +// $[EUSART_SL_IOSTREAM_EUSART_EXP_2] +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL_NO 0 + +// EUART0 TX on PD02 +#define SL_IOSTREAM_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_TX_PIN 2 + +// EUART0 RX on PD03 +#define SL_IOSTREAM_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..3039a35941 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 6 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..a4bf1049dd --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 7 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_exp_2_config.h b/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_exp_2_config.h new file mode 100644 index 0000000000..7f917483d5 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_exp_2_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_2_CONFIG_H +#define SL_IOSTREAM_USART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_2_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP_2 +// $[USART_SL_IOSTREAM_USART_EXP_2] +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_IOSTREAM_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_IOSTREAM_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..7d057d0bb2 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART1 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_EXP_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_EXP_RX_PIN 6 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..3b2b062275 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART1 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 7 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4001a/sl_memlcd_usart_config.h b/hardware/board/config/brd4402c_brd4001a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..4f4770c765 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 0 + +// USART0 CLK on PC02 +#define SL_MEMLCD_SPI_CLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CLK_PIN 2 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 6 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_A +#define SL_MEMLCD_EXTCOMIN_PIN 0 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4402c_brd4001a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..5c2787e30c --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_A +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4402c_brd4001a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..0756b79fe5 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * @file + * @brief OpenThread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 0 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 0 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_NCP_SPIDRV_USART_TX_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_NCP_SPIDRV_USART_RX_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_NCP_SPIDRV_USART_CLK_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_NCP_SPIDRV_USART_CS_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_CS_PIN 3 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4402c_brd4001a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..cca9c1bb26 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PD02 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_D +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4402c_brd4001a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..abcfb402ef --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PD03 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_D +#define SL_PWM_LED1_OUTPUT_PIN 3 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4402c_brd4001a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..a1a5fce586 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 2 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4402c_brd4001a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..cc8f62c338 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PC04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PC05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4402c_brd4001a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..55e41f3430 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 0 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4402c_brd4001a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..a34574c2ec --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4402c_brd4001a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..f1e5458a62 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_D +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_simple_led_led1_config.h b/hardware/board/config/brd4402c_brd4001a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..0b07e0119e --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_D +#define SL_SIMPLE_LED_LED1_PIN 3 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_spidrv_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..936fdb629f --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_SPIDRV_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_SPIDRV_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_SPIDRV_EXP_CLK_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_SPIDRV_EXP_CS_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_CS_PIN 3 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..b58ba9b398 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_SPIDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_SPIDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_SPIDRV_USART_EXP_CLK_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_SPIDRV_USART_EXP_CS_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_CS_PIN 3 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_exp_2_config.h new file mode 100644 index 0000000000..e59b0c0a00 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_exp_2_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_2_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_2_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_2_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_2_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_2_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_2_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_2_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_2_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP_2 +// $[EUSART_SL_UARTDRV_EUSART_EXP_2] +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL_NO 0 + +// EUART0 TX on PD02 +#define SL_UARTDRV_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_TX_PIN 2 + +// EUART0 RX on PD03 +#define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..7f6f55277f --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RX_PIN 6 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..e9963ec1ee --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_exp_2_config.h new file mode 100644 index 0000000000..5366cb13e7 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_2_CONFIG_H +#define SL_UARTDRV_USART_EXP_2_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_2_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_2_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP_2 +// $[USART_SL_UARTDRV_USART_EXP_2] +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_UARTDRV_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_UARTDRV_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..fd1930c706 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART1 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RX_PIN 6 + + + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..79ea292a51 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4001a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART1 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4402c_brd4002a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..cbb40905ec --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 7 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 4 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4402c_brd4002a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..05de747836 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_HOST_INT_PIN 0 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define SL_EZSPSPI_WAKE_INT_PIN 1 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4402c_brd4002a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..b38ae4ac3f --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_B +#define SL_BTL_BUTTON_PIN 0 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4402c_brd4002a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..51f5098ecf --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CLK_PIN 2 + +// USART0 CS on PA04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_A +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4402c_brd4002a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..f9be2de3e2 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_USART_SPINCP_TX_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_USART_SPINCP_RX_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_RX_PIN 1 + +// USART0 CS on PC03 +#define SL_USART_SPINCP_CS_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_CS_PIN 3 + +// USART0 CLK on PC02 +#define SL_USART_SPINCP_CLK_PORT SL_GPIO_PORT_C +#define SL_USART_SPINCP_CLK_PIN 2 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4402c_brd4002a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..5cc59a69af --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART1 +#define SL_SERIAL_UART_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 7 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_B +#define SL_VCOM_ENABLE_PIN 4 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_exp.h b/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..187125d2ec --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 2 + +// USART0 CS on PC03 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 3 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_msc.h b/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..68aa4da557 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 + +// USART0 CS on PA04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_A +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..e73d96fffd --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_ENABLE_PIN 0 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C0 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_EXP_SCL_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_EXP_SDA_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_EXP_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..db08bfb656 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C0 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_SENSOR_SCL_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_SENSOR_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_SENSOR_SDA_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_SENSOR_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_test.h b/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..da5b1dc1f7 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_ENABLE_PIN 0 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C0 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_TEST_SCL_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_TEST_SDA_PORT SL_GPIO_PORT_B +#define IOT_I2C_CFG_TEST_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..e5c9b7ec52 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 + +// TIMER4 CC0 on PB00 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_B +#define IOT_PWM_CFG_EXP_CC0_PIN 0 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..3491018781 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PD02 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_D +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..591df6b19b --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PD03 +#define IOT_PWM_CFG_LED1_CC0_PORT SL_GPIO_PORT_D +#define IOT_PWM_CFG_LED1_CC0_PIN 3 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_spi_cfg_exp.h b/hardware/board/config/brd4402c_brd4002a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..33497d70b2 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_SPI_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_SPI_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_SPI_CFG_EXP_CLK_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define IOT_SPI_CFG_EXP_CS_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_EXP_CS_PIN 3 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4402c_brd4002a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..6ec57a4d66 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 0 + +// USART0 RX on PC01 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 1 + +// USART0 CLK on PC02 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 2 + +// USART0 CS on PC03 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT SL_GPIO_PORT_C +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 3 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..7bc06206fc --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART1 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_EXP_TX_PIN 5 + +// USART1 RX on PA06 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_EXP_RX_PIN 6 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..845944789a --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART1 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_TX_PIN 5 + +// USART1 RX on PA06 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RX_PIN 6 + + + +// USART1 RTS on PA07 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 7 + +// USART1 CTS on PA08 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 8 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..8fc73b21fc --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART1 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RX_PIN 6 + + + +// USART1 RTS on PA07 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 7 + +// USART1 CTS on PA08 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 8 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4402c_brd4002a/legacy_ncp_spi_config.h b/hardware/board/config/brd4402c_brd4002a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..1487968f4d --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define LEGACY_NCP_SPI_TX_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_TX_PIN 0 + +// USART0 RX on PC01 +#define LEGACY_NCP_SPI_RX_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_RX_PIN 1 + +// USART0 CLK on PC02 +#define LEGACY_NCP_SPI_CLK_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_CLK_PIN 2 + +// USART0 CS on PC03 +#define LEGACY_NCP_SPI_CS_PORT SL_GPIO_PORT_C +#define LEGACY_NCP_SPI_CS_PIN 3 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_HOST_INT_PIN 0 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT SL_GPIO_PORT_B +#define LEGACY_NCP_SPI_WAKE_INT_PIN 1 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4402c_brd4002a/sl_board_control_config.h new file mode 100644 index 0000000000..fc167dba21 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_B +#define SL_BOARD_ENABLE_VCOM_PIN 4 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_DISPLAY_PIN 7 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 7 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4402c_brd4002a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..36304c8a18 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,285 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 38400000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 76800000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4402c_brd4002a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..6a44cecbe8 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_clock_manager_tree_config.h @@ -0,0 +1,243 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPBCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// CLKIN0 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPBCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for RTCCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE +#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUARTCLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// Selection of the Clock source for EUARTCLK +// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..3929cb1f70 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_SPI_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_SPI_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_IRQ] +#define SL_CPC_DRV_SPI_EXP_IRQ_PORT SL_GPIO_PORT_B +#define SL_CPC_DRV_SPI_EXP_IRQ_PIN 0 + +// [GPIO_SL_CPC_DRV_SPI_EXP_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_CPC_DRV_SPI_EXP_COPI_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_COPI_PIN 0 + +// USART0 RX on PC01 +#define SL_CPC_DRV_SPI_EXP_CIPO_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_CIPO_PIN 1 + +// USART0 CLK on PC02 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_CPC_DRV_SPI_EXP_CS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..5e99fd9d9d --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC00 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 + +// EUART0 RX on PC01 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 1 + +// EUART0 CTS on PC02 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 + +// EUART0 RTS on PC03 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..4f35b18129 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..2642727825 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 1 + +// USART0 CTS on PC02 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 + +// USART0 RTS on PC03 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..b80c07a89a --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART1 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..ce3b9b9242 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 0 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..bcec27f078 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT SL_GPIO_PORT_B +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4402c_brd4002a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..e331b00d8e --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_10_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_10_config.h new file mode 100644 index 0000000000..53fb502248 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_10_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_10_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_10_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_10 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_10] +#define SL_EMLIB_GPIO_INIT_EXP_10_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_10_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_10]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_10_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7e29751d91 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..6587ff3226 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_13_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_13_config.h new file mode 100644 index 0000000000..9bca6524d8 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_13_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_13_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_13_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_13 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_13] +#define SL_EMLIB_GPIO_INIT_EXP_13_PORT SL_GPIO_PORT_D +#define SL_EMLIB_GPIO_INIT_EXP_13_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_13]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_13_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..d2b40ac01e --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_15_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_15_config.h new file mode 100644 index 0000000000..e5e7b97bea --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_15_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_15_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_15_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_15 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_15] +#define SL_EMLIB_GPIO_INIT_EXP_15_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_15_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_15]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_15_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_16_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_16_config.h new file mode 100644 index 0000000000..31c77c28f0 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_16_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_16_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_16_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_16 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_16] +#define SL_EMLIB_GPIO_INIT_EXP_16_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_16_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_16]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_16_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_4_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_4_config.h new file mode 100644 index 0000000000..dad871b441 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_4_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_4_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_4_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_4 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_4] +#define SL_EMLIB_GPIO_INIT_EXP_4_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_4_PIN 0 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_4_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_6_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_6_config.h new file mode 100644 index 0000000000..ce92dd3c79 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_6_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_6_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_6_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_6 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_6] +#define SL_EMLIB_GPIO_INIT_EXP_6_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_6_PIN 1 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_6]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_6_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..c762679cdf --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 0 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_8_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_8_config.h new file mode 100644 index 0000000000..15e155b3c8 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_8_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_8_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_8_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_8 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_8] +#define SL_EMLIB_GPIO_INIT_EXP_8_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_8_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_8]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_8_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_9_config.h b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_9_config.h new file mode 100644 index 0000000000..a1a60a9c60 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_emlib_gpio_init_exp_9_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_9_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_9_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_9 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_9] +#define SL_EMLIB_GPIO_INIT_EXP_9_PORT SL_GPIO_PORT_B +#define SL_EMLIB_GPIO_INIT_EXP_9_PIN 1 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_9]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_9_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4402c_brd4002a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..ed664d1067 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C0 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define SL_I2CSPM_SENSOR_SCL_PORT SL_GPIO_PORT_B +#define SL_I2CSPM_SENSOR_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define SL_I2CSPM_SENSOR_SDA_PORT SL_GPIO_PORT_B +#define SL_I2CSPM_SENSOR_SDA_PIN 3 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_exp_2_config.h b/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_exp_2_config.h new file mode 100644 index 0000000000..527c23b414 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_exp_2_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_2_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_2_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_2_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_2_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_2_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP_2 +// $[EUSART_SL_IOSTREAM_EUSART_EXP_2] +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_EXP_2_PERIPHERAL_NO 0 + +// EUART0 TX on PD02 +#define SL_IOSTREAM_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_TX_PIN 2 + +// EUART0 RX on PD03 +#define SL_IOSTREAM_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..3039a35941 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 6 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..a4bf1049dd --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 7 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_exp_2_config.h b/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_exp_2_config.h new file mode 100644 index 0000000000..7f917483d5 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_exp_2_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_2_CONFIG_H +#define SL_IOSTREAM_USART_EXP_2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_2_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_2_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_2_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_2_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP_2 +// $[USART_SL_IOSTREAM_USART_EXP_2] +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_IOSTREAM_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_IOSTREAM_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_IOSTREAM_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..7d057d0bb2 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART1 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_EXP_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_EXP_RX_PIN 6 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..3b2b062275 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART1 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 7 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4002a/sl_memlcd_usart_config.h b/hardware/board/config/brd4402c_brd4002a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..4f4770c765 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_MEMLCD_SPI_TX_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_TX_PIN 0 + +// USART0 CLK on PC02 +#define SL_MEMLCD_SPI_CLK_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CLK_PIN 2 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT SL_GPIO_PORT_C +#define SL_MEMLCD_SPI_CS_PIN 6 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT SL_GPIO_PORT_A +#define SL_MEMLCD_EXTCOMIN_PIN 0 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4402c_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4402c_brd4002a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..5c2787e30c --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_A +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4402c_brd4002a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..0756b79fe5 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * @file + * @brief OpenThread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 0 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT SL_GPIO_PORT_B +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 0 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_NCP_SPIDRV_USART_TX_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_NCP_SPIDRV_USART_RX_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_NCP_SPIDRV_USART_CLK_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_NCP_SPIDRV_USART_CS_PORT SL_GPIO_PORT_C +#define SL_NCP_SPIDRV_USART_CS_PIN 3 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4402c_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4402c_brd4002a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..cca9c1bb26 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PD02 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_D +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4402c_brd4002a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..abcfb402ef --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED1_CONFIG_H +#define SL_PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PD03 +#define SL_PWM_LED1_OUTPUT_PORT SL_GPIO_PORT_D +#define SL_PWM_LED1_OUTPUT_PIN 3 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4402c_brd4002a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..a1a5fce586 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 2 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4402c_brd4002a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..cc8f62c338 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PC04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PC05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4402c_brd4002a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..55e41f3430 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN0_PIN 0 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4402c_brd4002a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..a34574c2ec --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT SL_GPIO_PORT_B +#define SL_SIMPLE_BUTTON_BTN1_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4402c_brd4002a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..f1e5458a62 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_D +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_simple_led_led1_config.h b/hardware/board/config/brd4402c_brd4002a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..0b07e0119e --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT SL_GPIO_PORT_D +#define SL_SIMPLE_LED_LED1_PIN 3 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_spidrv_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..936fdb629f --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_SPIDRV_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_SPIDRV_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_SPIDRV_EXP_CLK_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_SPIDRV_EXP_CS_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_EXP_CS_PIN 3 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..b58ba9b398 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_SPIDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_SPIDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_SPIDRV_USART_EXP_CLK_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_CLK_PIN 2 + +// USART0 CS on PC03 +#define SL_SPIDRV_USART_EXP_CS_PORT SL_GPIO_PORT_C +#define SL_SPIDRV_USART_EXP_CS_PIN 3 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_exp_2_config.h b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_exp_2_config.h new file mode 100644 index 0000000000..e59b0c0a00 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_exp_2_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_2_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_2_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_2_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_2_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_2_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_2_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_2_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_2_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_2_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP_2 +// $[EUSART_SL_UARTDRV_EUSART_EXP_2] +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_EXP_2_PERIPHERAL_NO 0 + +// EUART0 TX on PD02 +#define SL_UARTDRV_EUSART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_TX_PIN 2 + +// EUART0 RX on PD03 +#define SL_UARTDRV_EUSART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_EUSART_EXP_2_RX_PIN 3 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP_2]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..7f6f55277f --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RX_PIN 6 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..e9963ec1ee --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PA05 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 5 + +// EUART0 RX on PA06 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 + +// EUART0 CTS on PA08 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 8 + +// EUART0 RTS on PA07 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 7 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_exp_2_config.h new file mode 100644 index 0000000000..5366cb13e7 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_2_CONFIG_H +#define SL_UARTDRV_USART_EXP_2_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_2_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_2_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_2_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_2_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_2_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_2_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_2_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP_2 +// $[USART_SL_UARTDRV_USART_EXP_2] +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_2_PERIPHERAL_NO 0 + +// USART0 TX on PD02 +#define SL_UARTDRV_USART_EXP_2_TX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_TX_PIN 2 + +// USART0 RX on PD03 +#define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_D +#define SL_UARTDRV_USART_EXP_2_RX_PIN 3 + + + +// [USART_SL_UARTDRV_USART_EXP_2]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_2_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..fd1930c706 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART1 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RX_PIN 6 + + + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..79ea292a51 --- /dev/null +++ b/hardware/board/config/brd4402c_brd4002a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART1 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 1 + +// USART1 TX on PA05 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_TX_PIN 5 + +// USART1 RX on PA06 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RX_PIN 6 + +// USART1 CTS on PA08 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 + +// USART1 RTS on PA07 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 7 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4403a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4403a_brd4001a/sl_clock_manager_oscillator_config.h index edf1d7e213..b0ac78bb3d 100644 --- a/hardware/board/config/brd4403a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4403a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4403a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4403a_brd4002a/sl_clock_manager_oscillator_config.h index edf1d7e213..b0ac78bb3d 100644 --- a/hardware/board/config/brd4403a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4403a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4403b_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4403b_brd4001a/sl_clock_manager_oscillator_config.h index a2932ec5ce..14c8ae48fc 100644 --- a/hardware/board/config/brd4403b_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4403b_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_eusart_exp_config.h index e0c3a7de4b..478b14bb3c 100644 --- a/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUART0 CTS on PA05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUART0 RTS on PA06 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 6 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_usart_exp_config.h index 7eaf0ed7db..be40635b5a 100644 --- a/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4403b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PA05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA06 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 6 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4403b_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4403b_brd4002a/sl_clock_manager_oscillator_config.h index a2932ec5ce..14c8ae48fc 100644 --- a/hardware/board/config/brd4403b_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4403b_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_eusart_exp_config.h index e0c3a7de4b..478b14bb3c 100644 --- a/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_EUSART_EXP_RX_PIN 3 +// EUART0 CTS on PA05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUART0 RTS on PA06 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 6 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_usart_exp_config.h index 7eaf0ed7db..be40635b5a 100644 --- a/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4403b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C #define SL_UARTDRV_USART_EXP_RX_PIN 3 +// USART0 CTS on PA05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA06 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 6 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4403c_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4403c_brd4001a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..2235b6b0c1 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_EUART_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_EUART_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 6 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_C +#define SL_VCOM_ENABLE_PIN 5 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4403c_brd4001a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..0ec505a902 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_A +#define SL_BTL_BUTTON_PIN 0 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4403c_brd4001a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..e092974a64 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PB00 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_B +#define SL_USART_EXTFLASH_TX_PIN 0 + +// USART0 RX on PB01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_B +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PB02 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_B +#define SL_USART_EXTFLASH_CLK_PIN 2 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4403c_brd4001a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..531badc22d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_UART_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_UART_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 6 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_C +#define SL_VCOM_ENABLE_PIN 5 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/iot_flash_cfg_msc.h b/hardware/board/config/brd4403c_brd4001a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4403c_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4403c_brd4001a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..d928fee6fd --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PB00 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_B +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 + +// USART0 RX on PB01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_B +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PB02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_B +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4403c_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4403c_brd4001a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..91b2fd1bd8 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 + +// TIMER4 CC0 on PA00 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_A +#define IOT_PWM_CFG_EXP_CC0_PIN 0 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4403c_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4403c_brd4001a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..85050eb71b --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PA04 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_A +#define IOT_PWM_CFG_LED0_CC0_PIN 4 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..44f13575a7 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_RX_PIN 3 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..d37ae99870 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_LOOPBACK_TX_PIN 2 + +// USART0 RX on PC03 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_LOOPBACK_RX_PIN 3 + + + +// USART0 RTS on PA06 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 6 + +// USART0 CTS on PA05 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 5 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..3b5e8cd6ec --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_VCOM_RX_PIN 3 + + + +// USART0 RTS on PA06 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 6 + +// USART0 CTS on PA05 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 5 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4403c_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4403c_brd4001a/sl_board_control_config.h new file mode 100644 index 0000000000..dd829058db --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_board_control_config.h @@ -0,0 +1,56 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_VCOM_PIN 5 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4403c_brd4001a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..36304c8a18 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,285 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 38400000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 76800000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4001a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4403c_brd4001a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..6a44cecbe8 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_clock_manager_tree_config.h @@ -0,0 +1,243 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPBCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// CLKIN0 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPBCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for RTCCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE +#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUARTCLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// Selection of the Clock source for EUARTCLK +// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..4bb677a452 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_RTS_PIN 6 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..c25e356f6e --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 6 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..e6407809ad --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_RTS_PIN 6 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..2aeca37bbf --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 6 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4403c_brd4001a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..e331b00d8e --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7628300111 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 4 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..4de032796b --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..77c3df590d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_3_config.h b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_3_config.h new file mode 100644 index 0000000000..cab8c0221f --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_3_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_3_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_3_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_3 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_3] +#define SL_EMLIB_GPIO_INIT_EXP_3_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_3_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_5_config.h b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_5_config.h new file mode 100644 index 0000000000..437de6f524 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_5_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_5_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_5_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_5 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_5] +#define SL_EMLIB_GPIO_INIT_EXP_5_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_5_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_5]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..0342a76020 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 0 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4403c_brd4001a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..b2ab58504d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4403c_brd4001a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..1697d021f0 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 6 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4403c_brd4001a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..711b04a4ed --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4403c_brd4001a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..b0d9915242 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_VCOM_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 6 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4403c_brd4001a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..3ae0eacdfb --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PB00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_B +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// USART0 RX on PB01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_B +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PB02 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_B +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4403c_brd4001a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..6cc71bb13f --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PA04 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_A +#define SL_PWM_LED0_OUTPUT_PIN 4 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4403c_brd4001a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..a1a5fce586 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 2 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4403c_brd4001a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..86b3e5f0d1 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PC00 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DOUT_PIN 0 + +// PTI DFRAME on PC01 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 1 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4403c_brd4001a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..944da5e2f6 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_A +#define SL_SIMPLE_BUTTON_BTN0_PIN 0 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4403c_brd4001a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..854c1bc7a3 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_A +#define SL_SIMPLE_LED_LED0_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..478b14bb3c --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 6 + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..8b93c3d44e --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 6 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..be40635b5a --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 6 + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..ac4c27f7ae --- /dev/null +++ b/hardware/board/config/brd4403c_brd4001a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 6 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4403c_brd4002a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..2235b6b0c1 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_SERIAL_EUART_TX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_EUART_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_SERIAL_EUART_RX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_EUART_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_SERIAL_EUART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_SERIAL_EUART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_EUART_RTS_PIN 6 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_C +#define SL_VCOM_ENABLE_PIN 5 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4403c_brd4002a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..0ec505a902 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT SL_GPIO_PORT_A +#define SL_BTL_BUTTON_PIN 0 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4403c_brd4002a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..e092974a64 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PB00 +#define SL_USART_EXTFLASH_TX_PORT SL_GPIO_PORT_B +#define SL_USART_EXTFLASH_TX_PIN 0 + +// USART0 RX on PB01 +#define SL_USART_EXTFLASH_RX_PORT SL_GPIO_PORT_B +#define SL_USART_EXTFLASH_RX_PIN 1 + +// USART0 CLK on PB02 +#define SL_USART_EXTFLASH_CLK_PORT SL_GPIO_PORT_B +#define SL_USART_EXTFLASH_CLK_PIN 2 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT SL_GPIO_PORT_C +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4403c_brd4002a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..531badc22d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_SERIAL_UART_TX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_UART_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_SERIAL_UART_RX_PORT SL_GPIO_PORT_C +#define SL_SERIAL_UART_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_SERIAL_UART_CTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_SERIAL_UART_RTS_PORT SL_GPIO_PORT_A +#define SL_SERIAL_UART_RTS_PIN 6 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT SL_GPIO_PORT_C +#define SL_VCOM_ENABLE_PIN 5 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/iot_flash_cfg_msc.h b/hardware/board/config/brd4403c_brd4002a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4403c_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4403c_brd4002a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..d928fee6fd --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PB00 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT SL_GPIO_PORT_B +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 + +// USART0 RX on PB01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT SL_GPIO_PORT_B +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 + +// USART0 CLK on PB02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT SL_GPIO_PORT_B +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT SL_GPIO_PORT_C +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4403c_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4403c_brd4002a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..91b2fd1bd8 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 + +// TIMER4 CC0 on PA00 +#define IOT_PWM_CFG_EXP_CC0_PORT SL_GPIO_PORT_A +#define IOT_PWM_CFG_EXP_CC0_PIN 0 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4403c_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4403c_brd4002a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..85050eb71b --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PA04 +#define IOT_PWM_CFG_LED0_CC0_PORT SL_GPIO_PORT_A +#define IOT_PWM_CFG_LED0_CC0_PIN 4 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..44f13575a7 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_UART_CFG_EXP_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define IOT_UART_CFG_EXP_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_EXP_RX_PIN 3 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..d37ae99870 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_UART_CFG_LOOPBACK_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_LOOPBACK_TX_PIN 2 + +// USART0 RX on PC03 +#define IOT_UART_CFG_LOOPBACK_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_LOOPBACK_RX_PIN 3 + + + +// USART0 RTS on PA06 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 6 + +// USART0 CTS on PA05 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 5 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..3b5e8cd6ec --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define IOT_UART_CFG_VCOM_TX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define IOT_UART_CFG_VCOM_RX_PORT SL_GPIO_PORT_C +#define IOT_UART_CFG_VCOM_RX_PIN 3 + + + +// USART0 RTS on PA06 +#define IOT_UART_CFG_VCOM_RTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_RTS_PIN 6 + +// USART0 CTS on PA05 +#define IOT_UART_CFG_VCOM_CTS_PORT SL_GPIO_PORT_A +#define IOT_UART_CFG_VCOM_CTS_PIN 5 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4403c_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4403c_brd4002a/sl_board_control_config.h new file mode 100644 index 0000000000..dd829058db --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_board_control_config.h @@ -0,0 +1,56 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT SL_GPIO_PORT_C +#define SL_BOARD_ENABLE_VCOM_PIN 5 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4403c_brd4002a/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..36304c8a18 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_clock_manager_oscillator_config.h @@ -0,0 +1,285 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 38400000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 76800000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4002a/sl_clock_manager_tree_config.h b/hardware/board/config/brd4403c_brd4002a/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..6a44cecbe8 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_clock_manager_tree_config.h @@ -0,0 +1,243 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPBCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// CLKIN0 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPBCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for RTCCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE +#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUARTCLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// Selection of the Clock source for EUARTCLK +// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..4bb677a452 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_RTS_PIN 6 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..c25e356f6e --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 6 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..e6407809ad --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_EXP_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_EXP_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_CPC_DRV_UART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_CPC_DRV_UART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_EXP_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_CPC_DRV_UART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_CPC_DRV_UART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_EXP_RTS_PIN 6 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..2aeca37bbf --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc_config.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Max Rx Payload Length<1-4087> +// Default: SL_CPC_RX_PAYLOAD_MAX_LENGTH +// Maximum size of the payload in bytes of each RX buffer +#define SL_CPC_DRV_UART_VCOM_RX_PAYLOAD_MAX_LENGTH SL_CPC_RX_PAYLOAD_MAX_LENGTH + +// Tx Queue Size +// Default: SL_CPC_TX_QUEUE_ITEM_MAX_COUNT +// The maximum number of outgoing messages capable of being queued for transmission. +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_ITEM_MAX_COUNT SL_CPC_TX_QUEUE_ITEM_MAX_COUNT + +// Total Number of Rx Buffers +// Default: SL_CPC_RX_BUFFER_MAX_COUNT +// Total number of CPC RX buffers available across all endpoints +// Multiple RX buffers can be associated with a single endpoint +#define SL_CPC_DRV_UART_VCOM_RX_BUFFER_MAX_COUNT SL_CPC_RX_BUFFER_MAX_COUNT + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_CPC_DRV_UART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_CPC_DRV_UART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_CPC_DRV_UART_VCOM_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 6 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4403c_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4403c_brd4002a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..e331b00d8e --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_11_config.h b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_11_config.h new file mode 100644 index 0000000000..7628300111 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_11_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_11_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_11_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_11 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_11] +#define SL_EMLIB_GPIO_INIT_EXP_11_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_11_PIN 4 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_11]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_11_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_12_config.h b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_12_config.h new file mode 100644 index 0000000000..4de032796b --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_12_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_12_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_12_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_12 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_12] +#define SL_EMLIB_GPIO_INIT_EXP_12_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_12_PIN 2 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_12]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_12_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_14_config.h b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_14_config.h new file mode 100644 index 0000000000..77c3df590d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_14_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_14_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_14_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_14 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_14] +#define SL_EMLIB_GPIO_INIT_EXP_14_PORT SL_GPIO_PORT_C +#define SL_EMLIB_GPIO_INIT_EXP_14_PIN 3 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_14]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_14_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_3_config.h b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_3_config.h new file mode 100644 index 0000000000..cab8c0221f --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_3_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_3_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_3_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_3 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_3] +#define SL_EMLIB_GPIO_INIT_EXP_3_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_3_PIN 5 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_3_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_5_config.h b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_5_config.h new file mode 100644 index 0000000000..437de6f524 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_5_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_5_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_5_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_5 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_5] +#define SL_EMLIB_GPIO_INIT_EXP_5_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_5_PIN 6 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_5]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_5_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_7_config.h b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_7_config.h new file mode 100644 index 0000000000..0342a76020 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_emlib_gpio_init_exp_7_config.h @@ -0,0 +1,51 @@ +#ifndef SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H +#define SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Pin settings + +// Pin mode +// Disabled +// Input +// Input with pull-up/down +// Input with pull-up/down and filter +// Push-pull output +// Push-pull output (alternate) +// Open-source output +// Open-source output with pull-down +// Open-drain output +// Open-drain output with filter +// Open-drain output with pull-up +// Open-drain output with pull-up and filter +// Open-drain output (alternate) +// Open-drain output with filter (alternate) +// Open-drain output with pull-up (alternate) +// Open-drain output with pull-up and filter (alternate) +// Default: gpioModePushPull +#define SL_EMLIB_GPIO_INIT_EXP_7_MODE gpioModePushPull + +// DOUT <0-1> +// In push-pull mode: The drive direction for the pin +// In input mode: Pull-up (1) or pull-down (0) +// In open-source mode: Set to 0 for the idle state +// In open-drain mode: Set to 1 for the idle state +// Default: 0 +#define SL_EMLIB_GPIO_INIT_EXP_7_DOUT 0 + +// end pin settings + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_EMLIB_GPIO_INIT_EXP_7 +// $[GPIO_SL_EMLIB_GPIO_INIT_EXP_7] +#define SL_EMLIB_GPIO_INIT_EXP_7_PORT SL_GPIO_PORT_A +#define SL_EMLIB_GPIO_INIT_EXP_7_PIN 0 + +// [GPIO_SL_EMLIB_GPIO_INIT_EXP_7]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_EMLIB_GPIO_INIT_EXP_7_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4403c_brd4002a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..b2ab58504d --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_EXP_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 3 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4403c_brd4002a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..1697d021f0 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: SL_IOSTREAM_EUSART_UART_NO_PARITY +#define SL_IOSTREAM_EUSART_VCOM_PARITY SL_IOSTREAM_EUSART_UART_NO_PARITY + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: SL_IOSTREAM_EUSART_UART_STOP_BITS_1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS SL_IOSTREAM_EUSART_UART_STOP_BITS_1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_NONE +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 6 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4403c_brd4002a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..711b04a4ed --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_iostream_usart_exp_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_IOSTREAM_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_IOSTREAM_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_EXP_RX_PIN 3 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4403c_brd4002a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..b0d9915242 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_IOSTREAM_USART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_IOSTREAM_USART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_IOSTREAM_USART_VCOM_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 6 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4403c_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4403c_brd4002a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..3ae0eacdfb --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PB00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT SL_GPIO_PORT_B +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// USART0 RX on PB01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT SL_GPIO_PORT_B +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PB02 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT SL_GPIO_PORT_B +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT SL_GPIO_PORT_C +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4403c_brd4002a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..6cc71bb13f --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PWM_INIT_LED0_CONFIG_H +#define SL_PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PA04 +#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_A +#define SL_PWM_LED0_OUTPUT_PIN 4 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4403c_brd4002a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..a1a5fce586 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 2 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4403c_brd4002a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..86b3e5f0d1 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PC00 +#define SL_RAIL_UTIL_PTI_DOUT_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DOUT_PIN 0 + +// PTI DFRAME on PC01 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT SL_GPIO_PORT_C +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 1 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4403c_brd4002a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..944da5e2f6 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "sl_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT SL_GPIO_PORT_A +#define SL_SIMPLE_BUTTON_BTN0_PIN 0 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4403c_brd4002a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..854c1bc7a3 --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT SL_GPIO_PORT_A +#define SL_SIMPLE_LED_LED0_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..478b14bb3c --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_UARTDRV_EUSART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_EXP_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 6 + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..8b93c3d44e --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUART0 TX on PC02 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 2 + +// EUART0 RX on PC03 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 3 + +// EUART0 CTS on PA05 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 5 + +// EUART0 RTS on PA06 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 6 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..be40635b5a --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_UARTDRV_USART_EXP_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_EXP_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 6 + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..ac4c27f7ae --- /dev/null +++ b/hardware/board/config/brd4403c_brd4002a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PC02 +#define SL_UARTDRV_USART_VCOM_TX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_TX_PIN 2 + +// USART0 RX on PC03 +#define SL_UARTDRV_USART_VCOM_RX_PORT SL_GPIO_PORT_C +#define SL_UARTDRV_USART_VCOM_RX_PIN 3 + +// USART0 CTS on PA05 +#define SL_UARTDRV_USART_VCOM_CTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_CTS_PIN 5 + +// USART0 RTS on PA06 +#define SL_UARTDRV_USART_VCOM_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_VCOM_RTS_PIN 6 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4406a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4406a_brd4001a/sl_clock_manager_oscillator_config.h index 436ef24bfa..511df0576a 100644 --- a/hardware/board/config/brd4406a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4406a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4406a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4406a_brd4002a/sl_clock_manager_oscillator_config.h index 436ef24bfa..511df0576a 100644 --- a/hardware/board/config/brd4406a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4406a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4411a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4411a_brd4001a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4411a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4411a_brd4001a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4411a_brd4001a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4411a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4411a_brd4002a/sl_clock_manager_oscillator_config.h index c554e7b96a..cb830d9392 100644 --- a/hardware/board/config/brd4411a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4411a_brd4002a/sl_clock_manager_oscillator_config.h @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_eusart_exp_config.h index dfc7552f54..844670e81c 100644 --- a/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ b/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -106,7 +106,13 @@ #define SL_UARTDRV_EUSART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_EUSART_EXP_RX_PIN 9 +// EUSART0 CTS on PB05 +#define SL_UARTDRV_EUSART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_EUSART_EXP_CTS_PIN 5 +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_EUSART_EXP_RTS_PIN 0 // [EUSART_SL_UARTDRV_EUSART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_2_config.h b/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_2_config.h index be9e74c913..f56657003d 100644 --- a/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_2_config.h +++ b/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_2_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_2_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_2_RX_PIN 7 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_2_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_2_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_2_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_2_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP_2]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_config.h index f7e3837efe..2800c2d5f0 100644 --- a/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_config.h +++ b/hardware/board/config/brd4411a_brd4002a/sl_uartdrv_usart_exp_config.h @@ -100,7 +100,13 @@ #define SL_UARTDRV_USART_EXP_RX_PORT SL_GPIO_PORT_A #define SL_UARTDRV_USART_EXP_RX_PIN 9 +// USART0 CTS on PB05 +#define SL_UARTDRV_USART_EXP_CTS_PORT SL_GPIO_PORT_B +#define SL_UARTDRV_USART_EXP_CTS_PIN 5 +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_EXP_RTS_PORT SL_GPIO_PORT_A +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 // [USART_SL_UARTDRV_USART_EXP]$ // <<< sl:end pin_tool >>> diff --git a/hardware/board/config/brd4412a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4412a_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..ea71629e98 100644 --- a/hardware/board/config/brd4412a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4412a_brd4001a/sl_clock_manager_oscillator_config.h @@ -81,7 +81,7 @@ // CTUNE <0-255> // 140 #ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#define SL_CLOCK_MANAGER_HFXO_CTUNE 125 #endif // Precision in PPM <0-65535> @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -110,7 +117,7 @@ // CTUNE <0-127> // 63 #ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#define SL_CLOCK_MANAGER_LFXO_CTUNE 38 #endif // LFXO precision in PPM <0-65535> @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4412a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4412a_brd4001a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..13c6f4983b --- /dev/null +++ b/hardware/board/config/brd4412a_brd4001a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 125 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4412a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4412a_brd4001a/sl_device_init_lfxo_config.h index e331b00d8e..bc4ed1f9dc 100644 --- a/hardware/board/config/brd4412a_brd4001a/sl_device_init_lfxo_config.h +++ b/hardware/board/config/brd4412a_brd4001a/sl_device_init_lfxo_config.h @@ -43,7 +43,7 @@ // CTUNE <0-127> // Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 38 // LFXO precision in PPM <0-65535> // Default: 50 diff --git a/hardware/board/config/brd4412a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4412a_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..ea71629e98 100644 --- a/hardware/board/config/brd4412a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4412a_brd4002a/sl_clock_manager_oscillator_config.h @@ -81,7 +81,7 @@ // CTUNE <0-255> // 140 #ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#define SL_CLOCK_MANAGER_HFXO_CTUNE 125 #endif // Precision in PPM <0-65535> @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -110,7 +117,7 @@ // CTUNE <0-127> // 63 #ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#define SL_CLOCK_MANAGER_LFXO_CTUNE 38 #endif // LFXO precision in PPM <0-65535> @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4412a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4412a_brd4002a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..13c6f4983b --- /dev/null +++ b/hardware/board/config/brd4412a_brd4002a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 125 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4412a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4412a_brd4002a/sl_device_init_lfxo_config.h index e331b00d8e..bc4ed1f9dc 100644 --- a/hardware/board/config/brd4412a_brd4002a/sl_device_init_lfxo_config.h +++ b/hardware/board/config/brd4412a_brd4002a/sl_device_init_lfxo_config.h @@ -43,7 +43,7 @@ // CTUNE <0-127> // Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 38 // LFXO precision in PPM <0-65535> // Default: 50 diff --git a/hardware/board/config/brd4413a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4413a_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..c14272516d 100644 --- a/hardware/board/config/brd4413a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4413a_brd4001a/sl_clock_manager_oscillator_config.h @@ -81,7 +81,7 @@ // CTUNE <0-255> // 140 #ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#define SL_CLOCK_MANAGER_HFXO_CTUNE 129 #endif // Precision in PPM <0-65535> @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -110,7 +117,7 @@ // CTUNE <0-127> // 63 #ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#define SL_CLOCK_MANAGER_LFXO_CTUNE 42 #endif // LFXO precision in PPM <0-65535> @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4413a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4413a_brd4001a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..62c7bb41c9 --- /dev/null +++ b/hardware/board/config/brd4413a_brd4001a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 129 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4413a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4413a_brd4001a/sl_device_init_lfxo_config.h index e331b00d8e..24254558f2 100644 --- a/hardware/board/config/brd4413a_brd4001a/sl_device_init_lfxo_config.h +++ b/hardware/board/config/brd4413a_brd4001a/sl_device_init_lfxo_config.h @@ -43,7 +43,7 @@ // CTUNE <0-127> // Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 42 // LFXO precision in PPM <0-65535> // Default: 50 diff --git a/hardware/board/config/brd4413a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4413a_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..c14272516d 100644 --- a/hardware/board/config/brd4413a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4413a_brd4002a/sl_clock_manager_oscillator_config.h @@ -81,7 +81,7 @@ // CTUNE <0-255> // 140 #ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#define SL_CLOCK_MANAGER_HFXO_CTUNE 129 #endif // Precision in PPM <0-65535> @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -110,7 +117,7 @@ // CTUNE <0-127> // 63 #ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#define SL_CLOCK_MANAGER_LFXO_CTUNE 42 #endif // LFXO precision in PPM <0-65535> @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4413a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4413a_brd4002a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..62c7bb41c9 --- /dev/null +++ b/hardware/board/config/brd4413a_brd4002a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 129 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4413a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4413a_brd4002a/sl_device_init_lfxo_config.h index e331b00d8e..24254558f2 100644 --- a/hardware/board/config/brd4413a_brd4002a/sl_device_init_lfxo_config.h +++ b/hardware/board/config/brd4413a_brd4002a/sl_device_init_lfxo_config.h @@ -43,7 +43,7 @@ // CTUNE <0-127> // Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 42 // LFXO precision in PPM <0-65535> // Default: 50 diff --git a/hardware/board/config/brd4414a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4414a_brd4001a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..fba9503db4 100644 --- a/hardware/board/config/brd4414a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4414a_brd4001a/sl_clock_manager_oscillator_config.h @@ -81,7 +81,7 @@ // CTUNE <0-255> // 140 #ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#define SL_CLOCK_MANAGER_HFXO_CTUNE 119 #endif // Precision in PPM <0-65535> @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -110,7 +117,7 @@ // CTUNE <0-127> // 63 #ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#define SL_CLOCK_MANAGER_LFXO_CTUNE 34 #endif // LFXO precision in PPM <0-65535> @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4414a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4414a_brd4001a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..f846f4d041 --- /dev/null +++ b/hardware/board/config/brd4414a_brd4001a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 119 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4414a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4414a_brd4001a/sl_device_init_lfxo_config.h index e331b00d8e..16bb69d769 100644 --- a/hardware/board/config/brd4414a_brd4001a/sl_device_init_lfxo_config.h +++ b/hardware/board/config/brd4414a_brd4001a/sl_device_init_lfxo_config.h @@ -43,7 +43,7 @@ // CTUNE <0-127> // Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 34 // LFXO precision in PPM <0-65535> // Default: 50 diff --git a/hardware/board/config/brd4414a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4414a_brd4002a/sl_clock_manager_oscillator_config.h index 3713dfa3b0..fba9503db4 100644 --- a/hardware/board/config/brd4414a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4414a_brd4002a/sl_clock_manager_oscillator_config.h @@ -81,7 +81,7 @@ // CTUNE <0-255> // 140 #ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#define SL_CLOCK_MANAGER_HFXO_CTUNE 119 #endif // Precision in PPM <0-65535> @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -110,7 +117,7 @@ // CTUNE <0-127> // 63 #ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#define SL_CLOCK_MANAGER_LFXO_CTUNE 34 #endif // LFXO precision in PPM <0-65535> @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4414a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4414a_brd4002a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..f846f4d041 --- /dev/null +++ b/hardware/board/config/brd4414a_brd4002a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 119 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4414a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4414a_brd4002a/sl_device_init_lfxo_config.h index e331b00d8e..16bb69d769 100644 --- a/hardware/board/config/brd4414a_brd4002a/sl_device_init_lfxo_config.h +++ b/hardware/board/config/brd4414a_brd4002a/sl_device_init_lfxo_config.h @@ -43,7 +43,7 @@ // CTUNE <0-127> // Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 34 // LFXO precision in PPM <0-65535> // Default: 50 diff --git a/hardware/board/config/brd4415a_brd4001a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4415a_brd4001a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4415a_brd4001a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4415a_brd4001a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/brd4415a_brd4002a/sl_clock_manager_oscillator_config.h b/hardware/board/config/brd4415a_brd4002a/sl_clock_manager_oscillator_config.h index fe7b7cdf7c..b7632e516e 100644 --- a/hardware/board/config/brd4415a_brd4002a/sl_clock_manager_oscillator_config.h +++ b/hardware/board/config/brd4415a_brd4002a/sl_clock_manager_oscillator_config.h @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/board/config/component/brd2505a_config.slcc b/hardware/board/config/component/brd2505a_config.slcc new file mode 100644 index 0000000000..9bca19f1c4 --- /dev/null +++ b/hardware/board/config/component/brd2505a_config.slcc @@ -0,0 +1,297 @@ +!!omap +- id: brd2505a_config +- label: brd2505a config +- description: Configuration files for BRD2505A +- package: platform +- category: Platform|Board|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd2505a +- provides: + - name: brd2505a_config +- config_file: + - override: + component: board_control + file_id: board_control_config + path: brd2505a/sl_board_control_config.h + - override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd2505a/btl_euart_driver_cfg.h + - override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd2505a/btl_gpio_activation_cfg.h + - override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd2505a/btl_spi_peripheral_eusart_driver_cfg.h + - override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd2505a/btl_spi_peripheral_usart_driver_cfg.h + - override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd2505a/btl_uart_driver_cfg.h + - override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd2505a/sl_clock_manager_oscillator_config.h + - override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd2505a/sl_clock_manager_tree_config.h + - override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd2505a/sl_cpc_gpio_expander_gpio_btn0_config.h + - override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd2505a/sl_cpc_gpio_expander_gpio_btn1_config.h + - override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd2505a/sl_cpc_drv_uart_eusart_exp_config.h + - override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd2505a/sl_cpc_drv_uart_usart_exp_config.h + - override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd2505a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd2505a/sl_cpc_drv_uart_eusart_vcom_config.h + - override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd2505a/sl_cpc_drv_uart_eusart_exp_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd2505a/sl_cpc_drv_uart_usart_vcom_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd2505a/sl_cpc_drv_uart_usart_exp_config.h + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd2505a/sl_device_init_hfxo_config.h + - override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd2505a/sl_device_init_lfxo_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_4 + path: brd2505a/sl_emlib_gpio_init_exp_4_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_6 + path: brd2505a/sl_emlib_gpio_init_exp_6_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_8 + path: brd2505a/sl_emlib_gpio_init_exp_8_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_10 + path: brd2505a/sl_emlib_gpio_init_exp_10_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd2505a/sl_emlib_gpio_init_exp_12_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd2505a/sl_emlib_gpio_init_exp_14_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_15 + path: brd2505a/sl_emlib_gpio_init_exp_15_config.h + - override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_16 + path: brd2505a/sl_emlib_gpio_init_exp_16_config.h + - override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd2505a/sl_i2cspm_sensor_config.h + - override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd2505a/sl_iostream_eusart_exp_config.h + - override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd2505a/sl_iostream_eusart_vcom_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd2505a/sl_iostream_usart_exp_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd2505a/sl_iostream_usart_vcom_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd2505a/iot_flash_cfg_msc.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd2505a/iot_flash_cfg_exp.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd2505a/iot_i2c_cfg_sensor.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd2505a/iot_i2c_cfg_exp.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd2505a/iot_i2c_cfg_test.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd2505a/iot_pwm_cfg_led0.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd2505a/iot_pwm_cfg_led1.h + - override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd2505a/iot_spi_cfg_exp.h + - override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd2505a/iot_spi_cfg_loopback.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd2505a/iot_uart_cfg_vcom.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd2505a/iot_uart_cfg_exp.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd2505a/iot_uart_cfg_loopback.h + - override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd2505a/sl_ncp_spidrv_usart_config.h + - override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd2505a/sl_pwm_init_led0_config.h + - override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd2505a/sl_pwm_init_led1_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd2505a/sl_simple_button_btn0_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd2505a/sl_simple_button_btn1_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd2505a/sl_simple_led_led0_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd2505a/sl_simple_led_led1_config.h + - override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd2505a/sl_spidrv_exp_config.h + - override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd2505a/sl_spidrv_eusart_exp_config.h + - override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd2505a/sl_spidrv_usart_exp_config.h + - override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd2505a/sl_uartdrv_eusart_exp_config.h + - override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd2505a/sl_uartdrv_eusart_vcom_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd2505a/sl_uartdrv_usart_exp_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd2505a/sl_uartdrv_usart_vcom_config.h diff --git a/hardware/board/config/component/brd2713a_config.slcc b/hardware/board/config/component/brd2713a_config.slcc new file mode 100644 index 0000000000..5ac1e3d2a6 --- /dev/null +++ b/hardware/board/config/component/brd2713a_config.slcc @@ -0,0 +1,263 @@ +!!omap +- id: brd2713a_config +- label: brd2713a config +- description: Configuration files for BRD2713A +- package: platform +- category: Platform|Board|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd2713a +- provides: + - name: brd2713a_config +- config_file: + - override: + component: board_control + file_id: board_control_config + path: brd2713a/sl_board_control_config.h + - override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd2713a/btl_euart_driver_cfg.h + - override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd2713a/btl_gpio_activation_cfg.h + - override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd2713a/btl_uart_driver_cfg.h + - override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd2713a/sl_clock_manager_oscillator_config.h + - override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd2713a/sl_clock_manager_tree_config.h + - override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd2713a/sl_cpc_gpio_expander_gpio_btn0_config.h + - override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd2713a/sl_cpc_gpio_expander_gpio_btn1_config.h + - override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: mikroe + path: brd2713a/sl_cpc_drv_uart_eusart_mikroe_config.h + - override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: mikroe + path: brd2713a/sl_cpc_drv_uart_usart_mikroe_config.h + - override: + component: cpc_secondary_driver_spi_eusart + file_id: cpc_drv_secondary_spi_eusart_config + instance: mikroe + path: brd2713a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h + - override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: mikroe + path: brd2713a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h + - override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd2713a/sl_cpc_drv_uart_eusart_vcom_config.h + - override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: mikroe + path: brd2713a/sl_cpc_drv_uart_eusart_mikroe_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd2713a/sl_cpc_drv_uart_usart_vcom_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: mikroe + path: brd2713a/sl_cpc_drv_uart_usart_mikroe_config.h + - override: + component: device_init_dpll + file_id: device_init_dpll_config + path: brd2713a/sl_device_init_dpll_config.h + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd2713a/sl_device_init_hfxo_config.h + - override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd2713a/sl_device_init_lfxo_config.h + - override: + component: i2cspm + file_id: i2cspm_config + instance: mikroe + path: brd2713a/sl_i2cspm_mikroe_config.h + - override: + component: i2cspm + file_id: i2cspm_config + instance: qwiic + path: brd2713a/sl_i2cspm_qwiic_config.h + - override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: mikroe + path: brd2713a/sl_iostream_eusart_mikroe_config.h + - override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd2713a/sl_iostream_eusart_vcom_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: mikroe + path: brd2713a/sl_iostream_usart_mikroe_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd2713a/sl_iostream_usart_vcom_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd2713a/iot_flash_cfg_msc.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: mikroe + path: brd2713a/iot_flash_cfg_mikroe.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: mikroe + path: brd2713a/iot_i2c_cfg_mikroe.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: qwiic + path: brd2713a/iot_i2c_cfg_qwiic.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd2713a/iot_pwm_cfg_led0.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd2713a/iot_pwm_cfg_led1.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: mikroe + path: brd2713a/iot_pwm_cfg_mikroe.h + - override: + component: iot_spi + file_id: iot_spi_cfg + instance: mikroe + path: brd2713a/iot_spi_cfg_mikroe.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd2713a/iot_uart_cfg_vcom.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: mikroe + path: brd2713a/iot_uart_cfg_mikroe.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd2713a/iot_uart_cfg_loopback.h + - override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd2713a/sl_pwm_init_led0_config.h + - override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd2713a/sl_pwm_init_led1_config.h + - override: + component: pwm + file_id: pwm_config + instance: mikroe + path: brd2713a/sl_pwm_init_mikroe_config.h + - override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd2713a/sl_rail_util_pti_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd2713a/sl_simple_button_btn0_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd2713a/sl_simple_button_btn1_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd2713a/sl_simple_led_led0_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd2713a/sl_simple_led_led1_config.h + - override: + component: spidrv + file_id: spidrv_config + instance: mikroe + path: brd2713a/sl_spidrv_mikroe_config.h + - override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: mikroe + path: brd2713a/sl_spidrv_eusart_mikroe_config.h + - override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: mikroe + path: brd2713a/sl_spidrv_usart_mikroe_config.h + - override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: mikroe + path: brd2713a/sl_uartdrv_eusart_mikroe_config.h + - override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd2713a/sl_uartdrv_eusart_vcom_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: mikroe + path: brd2713a/sl_uartdrv_usart_mikroe_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd2713a/sl_uartdrv_usart_vcom_config.h diff --git a/hardware/board/config/component/brd4120a_config.slcc b/hardware/board/config/component/brd4120a_config.slcc new file mode 100644 index 0000000000..8cfd596e47 --- /dev/null +++ b/hardware/board/config/component/brd4120a_config.slcc @@ -0,0 +1,1102 @@ +!!omap +- id: brd4120a_config +- label: brd4120a config +- description: Configuration files for BRD4120A +- package: platform +- category: Platform|Board|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd4120a +- provides: + - name: brd4120a_config +- config_file: + - condition: + - brd4001a + override: + component: board_control + file_id: board_control_config + path: brd4120a_brd4001a/sl_board_control_config.h + - condition: + - brd4002a + override: + component: board_control + file_id: board_control_config + path: brd4120a_brd4002a/sl_board_control_config.h + - condition: + - brd4001a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4120a_brd4001a/btl_euart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4120a_brd4001a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4120a_brd4001a/btl_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4120a_brd4001a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4120a_brd4001a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4120a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4120a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4120a_brd4001a/btl_uart_driver_cfg.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4120a_brd4001a/sl_clock_manager_oscillator_config.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4120a_brd4001a/sl_clock_manager_tree_config.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4120a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4120a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4120a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4120a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4120a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4120a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4120a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4120a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4120a_brd4001a/sl_device_init_hfxo_config.h + - condition: + - brd4001a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4120a_brd4001a/sl_device_init_lfxo_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_3 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_3_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_4 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_4_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_5 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_5_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_6 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_6_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_8 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_8_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_9 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_9_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_10 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_10_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_13 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_13_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_15 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_15_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_16 + path: brd4120a_brd4001a/sl_emlib_gpio_init_exp_16_config.h + - condition: + - brd4001a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4120a_brd4001a/sl_i2cspm_sensor_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4120a_brd4001a/sl_iostream_eusart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp_2 + path: brd4120a_brd4001a/sl_iostream_eusart_exp_2_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4120a_brd4001a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4120a_brd4001a/sl_iostream_usart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp_2 + path: brd4120a_brd4001a/sl_iostream_usart_exp_2_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4120a_brd4001a/sl_iostream_usart_vcom_config.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4120a_brd4001a/iot_flash_cfg_msc.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4120a_brd4001a/iot_flash_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4120a_brd4001a/iot_flash_cfg_spiflash.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4120a_brd4001a/iot_i2c_cfg_sensor.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4120a_brd4001a/iot_i2c_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4120a_brd4001a/iot_i2c_cfg_test.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4120a_brd4001a/iot_pwm_cfg_led0.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4120a_brd4001a/iot_pwm_cfg_led1.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4120a_brd4001a/iot_pwm_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4120a_brd4001a/iot_spi_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4120a_brd4001a/iot_spi_cfg_loopback.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4120a_brd4001a/iot_uart_cfg_vcom.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4120a_brd4001a/iot_uart_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4120a_brd4001a/iot_uart_cfg_loopback.h + - condition: + - brd4001a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4120a_brd4001a/legacy_ncp_spi_config.h + - condition: + - brd4001a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4120a_brd4001a/sl_memlcd_eusart_config.h + - condition: + - brd4001a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4120a_brd4001a/sl_memlcd_usart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4120a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4120a_brd4001a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4001a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4120a_brd4001a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4120a_brd4001a/sl_pwm_init_led0_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4120a_brd4001a/sl_pwm_init_led1_config.h + - condition: + - brd4001a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4120a_brd4001a/sl_rail_util_pa_config.h + - condition: + - brd4001a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4120a_brd4001a/sl_rail_util_pti_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4120a_brd4001a/sl_simple_button_btn0_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4120a_brd4001a/sl_simple_button_btn1_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4120a_brd4001a/sl_simple_led_led0_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4120a_brd4001a/sl_simple_led_led1_config.h + - condition: + - brd4001a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4120a_brd4001a/sl_spidrv_exp_config.h + - condition: + - brd4001a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4120a_brd4001a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4120a_brd4001a/sl_spidrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4120a_brd4001a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp_2 + path: brd4120a_brd4001a/sl_uartdrv_eusart_exp_2_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4120a_brd4001a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4120a_brd4001a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp_2 + path: brd4120a_brd4001a/sl_uartdrv_usart_exp_2_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4120a_brd4001a/sl_uartdrv_usart_vcom_config.h + - condition: + - brd4002a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4120a_brd4002a/btl_euart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4120a_brd4002a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4120a_brd4002a/btl_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4120a_brd4002a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4120a_brd4002a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4120a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4120a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4120a_brd4002a/btl_uart_driver_cfg.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4120a_brd4002a/sl_clock_manager_oscillator_config.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4120a_brd4002a/sl_clock_manager_tree_config.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4120a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4120a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4120a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4120a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4120a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4120a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4120a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4120a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4120a_brd4002a/sl_device_init_hfxo_config.h + - condition: + - brd4002a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4120a_brd4002a/sl_device_init_lfxo_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_3 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_3_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_4 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_4_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_5 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_5_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_6 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_6_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_8 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_8_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_9 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_9_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_10 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_10_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_13 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_13_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_15 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_15_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_16 + path: brd4120a_brd4002a/sl_emlib_gpio_init_exp_16_config.h + - condition: + - brd4002a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4120a_brd4002a/sl_i2cspm_sensor_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4120a_brd4002a/sl_iostream_eusart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp_2 + path: brd4120a_brd4002a/sl_iostream_eusart_exp_2_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4120a_brd4002a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4120a_brd4002a/sl_iostream_usart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp_2 + path: brd4120a_brd4002a/sl_iostream_usart_exp_2_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4120a_brd4002a/sl_iostream_usart_vcom_config.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4120a_brd4002a/iot_flash_cfg_msc.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4120a_brd4002a/iot_flash_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4120a_brd4002a/iot_flash_cfg_spiflash.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4120a_brd4002a/iot_i2c_cfg_sensor.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4120a_brd4002a/iot_i2c_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4120a_brd4002a/iot_i2c_cfg_test.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4120a_brd4002a/iot_pwm_cfg_led0.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4120a_brd4002a/iot_pwm_cfg_led1.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4120a_brd4002a/iot_pwm_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4120a_brd4002a/iot_spi_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4120a_brd4002a/iot_spi_cfg_loopback.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4120a_brd4002a/iot_uart_cfg_vcom.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4120a_brd4002a/iot_uart_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4120a_brd4002a/iot_uart_cfg_loopback.h + - condition: + - brd4002a + override: + component: joystick + file_id: joystick_config + path: brd4120a_brd4002a/sl_joystick_config.h + - condition: + - brd4002a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4120a_brd4002a/legacy_ncp_spi_config.h + - condition: + - brd4002a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4120a_brd4002a/sl_memlcd_eusart_config.h + - condition: + - brd4002a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4120a_brd4002a/sl_memlcd_usart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4120a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4120a_brd4002a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4002a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4120a_brd4002a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4120a_brd4002a/sl_pwm_init_led0_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4120a_brd4002a/sl_pwm_init_led1_config.h + - condition: + - brd4002a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4120a_brd4002a/sl_rail_util_pa_config.h + - condition: + - brd4002a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4120a_brd4002a/sl_rail_util_pti_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4120a_brd4002a/sl_simple_button_btn0_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4120a_brd4002a/sl_simple_button_btn1_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4120a_brd4002a/sl_simple_led_led0_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4120a_brd4002a/sl_simple_led_led1_config.h + - condition: + - brd4002a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4120a_brd4002a/sl_spidrv_exp_config.h + - condition: + - brd4002a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4120a_brd4002a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4120a_brd4002a/sl_spidrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4120a_brd4002a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp_2 + path: brd4120a_brd4002a/sl_uartdrv_eusart_exp_2_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4120a_brd4002a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4120a_brd4002a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp_2 + path: brd4120a_brd4002a/sl_uartdrv_usart_exp_2_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4120a_brd4002a/sl_uartdrv_usart_vcom_config.h diff --git a/hardware/board/config/component/brd4121a_config.slcc b/hardware/board/config/component/brd4121a_config.slcc new file mode 100644 index 0000000000..280050cecc --- /dev/null +++ b/hardware/board/config/component/brd4121a_config.slcc @@ -0,0 +1,1090 @@ +!!omap +- id: brd4121a_config +- label: brd4121a config +- description: Configuration files for BRD4121A +- package: platform +- category: Platform|Board|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd4121a +- provides: + - name: brd4121a_config +- config_file: + - condition: + - brd4001a + override: + component: board_control + file_id: board_control_config + path: brd4121a_brd4001a/sl_board_control_config.h + - condition: + - brd4002a + override: + component: board_control + file_id: board_control_config + path: brd4121a_brd4002a/sl_board_control_config.h + - condition: + - brd4001a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4121a_brd4001a/btl_euart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4121a_brd4001a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4121a_brd4001a/btl_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4121a_brd4001a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4121a_brd4001a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4121a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4121a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4121a_brd4001a/btl_uart_driver_cfg.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4121a_brd4001a/sl_clock_manager_oscillator_config.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4121a_brd4001a/sl_clock_manager_tree_config.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4121a_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4121a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4121a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4121a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4121a_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4121a_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4121a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4121a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4121a_brd4001a/sl_device_init_lfxo_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_3 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_3_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_4 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_4_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_5 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_5_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_6 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_6_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_8 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_8_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_9 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_9_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_10 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_10_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_13 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_13_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_15 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_15_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_16 + path: brd4121a_brd4001a/sl_emlib_gpio_init_exp_16_config.h + - condition: + - brd4001a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4121a_brd4001a/sl_i2cspm_sensor_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4121a_brd4001a/sl_iostream_eusart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp_2 + path: brd4121a_brd4001a/sl_iostream_eusart_exp_2_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4121a_brd4001a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4121a_brd4001a/sl_iostream_usart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp_2 + path: brd4121a_brd4001a/sl_iostream_usart_exp_2_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4121a_brd4001a/sl_iostream_usart_vcom_config.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4121a_brd4001a/iot_flash_cfg_msc.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4121a_brd4001a/iot_flash_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4121a_brd4001a/iot_flash_cfg_spiflash.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4121a_brd4001a/iot_i2c_cfg_sensor.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4121a_brd4001a/iot_i2c_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4121a_brd4001a/iot_i2c_cfg_test.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4121a_brd4001a/iot_pwm_cfg_led0.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4121a_brd4001a/iot_pwm_cfg_led1.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4121a_brd4001a/iot_pwm_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4121a_brd4001a/iot_spi_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4121a_brd4001a/iot_spi_cfg_loopback.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4121a_brd4001a/iot_uart_cfg_vcom.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4121a_brd4001a/iot_uart_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4121a_brd4001a/iot_uart_cfg_loopback.h + - condition: + - brd4001a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4121a_brd4001a/legacy_ncp_spi_config.h + - condition: + - brd4001a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4121a_brd4001a/sl_memlcd_eusart_config.h + - condition: + - brd4001a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4121a_brd4001a/sl_memlcd_usart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4121a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4121a_brd4001a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4001a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4121a_brd4001a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4121a_brd4001a/sl_pwm_init_led0_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4121a_brd4001a/sl_pwm_init_led1_config.h + - condition: + - brd4001a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4121a_brd4001a/sl_rail_util_pa_config.h + - condition: + - brd4001a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4121a_brd4001a/sl_rail_util_pti_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4121a_brd4001a/sl_simple_button_btn0_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4121a_brd4001a/sl_simple_button_btn1_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4121a_brd4001a/sl_simple_led_led0_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4121a_brd4001a/sl_simple_led_led1_config.h + - condition: + - brd4001a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4121a_brd4001a/sl_spidrv_exp_config.h + - condition: + - brd4001a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4121a_brd4001a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4121a_brd4001a/sl_spidrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4121a_brd4001a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp_2 + path: brd4121a_brd4001a/sl_uartdrv_eusart_exp_2_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4121a_brd4001a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4121a_brd4001a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp_2 + path: brd4121a_brd4001a/sl_uartdrv_usart_exp_2_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4121a_brd4001a/sl_uartdrv_usart_vcom_config.h + - condition: + - brd4002a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4121a_brd4002a/btl_euart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4121a_brd4002a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4121a_brd4002a/btl_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4121a_brd4002a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4121a_brd4002a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4121a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4121a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4121a_brd4002a/btl_uart_driver_cfg.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4121a_brd4002a/sl_clock_manager_oscillator_config.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4121a_brd4002a/sl_clock_manager_tree_config.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4121a_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4121a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4121a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4121a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4121a_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4121a_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4121a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4121a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4121a_brd4002a/sl_device_init_lfxo_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_3 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_3_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_4 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_4_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_5 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_5_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_6 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_6_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_8 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_8_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_9 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_9_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_10 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_10_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_13 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_13_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_15 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_15_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_16 + path: brd4121a_brd4002a/sl_emlib_gpio_init_exp_16_config.h + - condition: + - brd4002a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4121a_brd4002a/sl_i2cspm_sensor_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4121a_brd4002a/sl_iostream_eusart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp_2 + path: brd4121a_brd4002a/sl_iostream_eusart_exp_2_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4121a_brd4002a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4121a_brd4002a/sl_iostream_usart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp_2 + path: brd4121a_brd4002a/sl_iostream_usart_exp_2_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4121a_brd4002a/sl_iostream_usart_vcom_config.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4121a_brd4002a/iot_flash_cfg_msc.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4121a_brd4002a/iot_flash_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4121a_brd4002a/iot_flash_cfg_spiflash.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4121a_brd4002a/iot_i2c_cfg_sensor.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4121a_brd4002a/iot_i2c_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4121a_brd4002a/iot_i2c_cfg_test.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4121a_brd4002a/iot_pwm_cfg_led0.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4121a_brd4002a/iot_pwm_cfg_led1.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4121a_brd4002a/iot_pwm_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4121a_brd4002a/iot_spi_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4121a_brd4002a/iot_spi_cfg_loopback.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4121a_brd4002a/iot_uart_cfg_vcom.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4121a_brd4002a/iot_uart_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4121a_brd4002a/iot_uart_cfg_loopback.h + - condition: + - brd4002a + override: + component: joystick + file_id: joystick_config + path: brd4121a_brd4002a/sl_joystick_config.h + - condition: + - brd4002a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4121a_brd4002a/legacy_ncp_spi_config.h + - condition: + - brd4002a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4121a_brd4002a/sl_memlcd_eusart_config.h + - condition: + - brd4002a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4121a_brd4002a/sl_memlcd_usart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4121a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4121a_brd4002a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4002a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4121a_brd4002a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4121a_brd4002a/sl_pwm_init_led0_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4121a_brd4002a/sl_pwm_init_led1_config.h + - condition: + - brd4002a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4121a_brd4002a/sl_rail_util_pa_config.h + - condition: + - brd4002a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4121a_brd4002a/sl_rail_util_pti_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4121a_brd4002a/sl_simple_button_btn0_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4121a_brd4002a/sl_simple_button_btn1_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4121a_brd4002a/sl_simple_led_led0_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4121a_brd4002a/sl_simple_led_led1_config.h + - condition: + - brd4002a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4121a_brd4002a/sl_spidrv_exp_config.h + - condition: + - brd4002a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4121a_brd4002a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4121a_brd4002a/sl_spidrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4121a_brd4002a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp_2 + path: brd4121a_brd4002a/sl_uartdrv_eusart_exp_2_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4121a_brd4002a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4121a_brd4002a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp_2 + path: brd4121a_brd4002a/sl_uartdrv_usart_exp_2_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4121a_brd4002a/sl_uartdrv_usart_vcom_config.h diff --git a/hardware/board/config/component/brd4350a_config.slcc b/hardware/board/config/component/brd4350a_config.slcc index 299196303d..43d8438800 100644 --- a/hardware/board/config/component/brd4350a_config.slcc +++ b/hardware/board/config/component/brd4350a_config.slcc @@ -4,7 +4,7 @@ - description: Configuration files for BRD4350A - package: platform - category: Platform|Board|Config -- quality: evaluation +- quality: production - metadata: sbom: license: Zlib diff --git a/hardware/board/config/component/brd4351a_config.slcc b/hardware/board/config/component/brd4351a_config.slcc index e9cece71e2..d1a1186a05 100644 --- a/hardware/board/config/component/brd4351a_config.slcc +++ b/hardware/board/config/component/brd4351a_config.slcc @@ -4,7 +4,7 @@ - description: Configuration files for BRD4351A - package: platform - category: Platform|Board|Config -- quality: evaluation +- quality: production - metadata: sbom: license: Zlib diff --git a/hardware/board/config/component/brd4402c_config.slcc b/hardware/board/config/component/brd4402c_config.slcc new file mode 100644 index 0000000000..ae4affe260 --- /dev/null +++ b/hardware/board/config/component/brd4402c_config.slcc @@ -0,0 +1,994 @@ +!!omap +- id: brd4402c_config +- label: brd4402c config +- description: Configuration files for BRD4402C +- package: platform +- category: Platform|Board|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd4402c +- provides: + - name: brd4402c_config +- config_file: + - condition: + - brd4001a + override: + component: board_control + file_id: board_control_config + path: brd4402c_brd4001a/sl_board_control_config.h + - condition: + - brd4002a + override: + component: board_control + file_id: board_control_config + path: brd4402c_brd4002a/sl_board_control_config.h + - condition: + - brd4001a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4402c_brd4001a/btl_euart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4402c_brd4001a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4402c_brd4001a/btl_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4402c_brd4001a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4402c_brd4001a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4402c_brd4001a/btl_uart_driver_cfg.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4402c_brd4001a/sl_clock_manager_oscillator_config.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4402c_brd4001a/sl_clock_manager_tree_config.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4402c_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4402c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4402c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4402c_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4402c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4402c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4402c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4402c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4402c_brd4001a/sl_device_init_lfxo_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_4 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_4_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_6 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_6_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_8 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_8_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_9 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_9_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_10 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_10_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_13 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_13_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_15 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_15_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_16 + path: brd4402c_brd4001a/sl_emlib_gpio_init_exp_16_config.h + - condition: + - brd4001a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4402c_brd4001a/sl_i2cspm_sensor_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4402c_brd4001a/sl_iostream_eusart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp_2 + path: brd4402c_brd4001a/sl_iostream_eusart_exp_2_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4402c_brd4001a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4402c_brd4001a/sl_iostream_usart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp_2 + path: brd4402c_brd4001a/sl_iostream_usart_exp_2_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4402c_brd4001a/sl_iostream_usart_vcom_config.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4402c_brd4001a/iot_flash_cfg_msc.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4402c_brd4001a/iot_flash_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4402c_brd4001a/iot_flash_cfg_spiflash.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4402c_brd4001a/iot_i2c_cfg_sensor.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4402c_brd4001a/iot_i2c_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4402c_brd4001a/iot_i2c_cfg_test.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4402c_brd4001a/iot_pwm_cfg_led0.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4402c_brd4001a/iot_pwm_cfg_led1.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4402c_brd4001a/iot_pwm_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4402c_brd4001a/iot_spi_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4402c_brd4001a/iot_spi_cfg_loopback.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4402c_brd4001a/iot_uart_cfg_vcom.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4402c_brd4001a/iot_uart_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4402c_brd4001a/iot_uart_cfg_loopback.h + - condition: + - brd4001a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4402c_brd4001a/legacy_ncp_spi_config.h + - condition: + - brd4001a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4402c_brd4001a/sl_memlcd_usart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4402c_brd4001a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4001a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4402c_brd4001a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4402c_brd4001a/sl_pwm_init_led0_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4402c_brd4001a/sl_pwm_init_led1_config.h + - condition: + - brd4001a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4402c_brd4001a/sl_rail_util_pa_config.h + - condition: + - brd4001a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4402c_brd4001a/sl_rail_util_pti_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4402c_brd4001a/sl_simple_button_btn0_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4402c_brd4001a/sl_simple_button_btn1_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4402c_brd4001a/sl_simple_led_led0_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4402c_brd4001a/sl_simple_led_led1_config.h + - condition: + - brd4001a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4402c_brd4001a/sl_spidrv_exp_config.h + - condition: + - brd4001a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4402c_brd4001a/sl_spidrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4402c_brd4001a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp_2 + path: brd4402c_brd4001a/sl_uartdrv_eusart_exp_2_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4402c_brd4001a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4402c_brd4001a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp_2 + path: brd4402c_brd4001a/sl_uartdrv_usart_exp_2_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4402c_brd4001a/sl_uartdrv_usart_vcom_config.h + - condition: + - brd4002a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4402c_brd4002a/btl_euart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4402c_brd4002a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4402c_brd4002a/btl_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4402c_brd4002a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4402c_brd4002a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4402c_brd4002a/btl_uart_driver_cfg.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4402c_brd4002a/sl_clock_manager_oscillator_config.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4402c_brd4002a/sl_clock_manager_tree_config.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4402c_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4402c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4402c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4402c_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4402c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4402c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4402c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4402c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4402c_brd4002a/sl_device_init_lfxo_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_4 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_4_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_6 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_6_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_8 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_8_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_9 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_9_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_10 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_10_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_13 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_13_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_15 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_15_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_16 + path: brd4402c_brd4002a/sl_emlib_gpio_init_exp_16_config.h + - condition: + - brd4002a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4402c_brd4002a/sl_i2cspm_sensor_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4402c_brd4002a/sl_iostream_eusart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp_2 + path: brd4402c_brd4002a/sl_iostream_eusart_exp_2_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4402c_brd4002a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4402c_brd4002a/sl_iostream_usart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp_2 + path: brd4402c_brd4002a/sl_iostream_usart_exp_2_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4402c_brd4002a/sl_iostream_usart_vcom_config.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4402c_brd4002a/iot_flash_cfg_msc.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4402c_brd4002a/iot_flash_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4402c_brd4002a/iot_flash_cfg_spiflash.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4402c_brd4002a/iot_i2c_cfg_sensor.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4402c_brd4002a/iot_i2c_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4402c_brd4002a/iot_i2c_cfg_test.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4402c_brd4002a/iot_pwm_cfg_led0.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4402c_brd4002a/iot_pwm_cfg_led1.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4402c_brd4002a/iot_pwm_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4402c_brd4002a/iot_spi_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4402c_brd4002a/iot_spi_cfg_loopback.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4402c_brd4002a/iot_uart_cfg_vcom.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4402c_brd4002a/iot_uart_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4402c_brd4002a/iot_uart_cfg_loopback.h + - condition: + - brd4002a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4402c_brd4002a/legacy_ncp_spi_config.h + - condition: + - brd4002a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4402c_brd4002a/sl_memlcd_usart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4402c_brd4002a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4002a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4402c_brd4002a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4402c_brd4002a/sl_pwm_init_led0_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4402c_brd4002a/sl_pwm_init_led1_config.h + - condition: + - brd4002a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4402c_brd4002a/sl_rail_util_pa_config.h + - condition: + - brd4002a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4402c_brd4002a/sl_rail_util_pti_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4402c_brd4002a/sl_simple_button_btn0_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4402c_brd4002a/sl_simple_button_btn1_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4402c_brd4002a/sl_simple_led_led0_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4402c_brd4002a/sl_simple_led_led1_config.h + - condition: + - brd4002a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4402c_brd4002a/sl_spidrv_exp_config.h + - condition: + - brd4002a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4402c_brd4002a/sl_spidrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4402c_brd4002a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp_2 + path: brd4402c_brd4002a/sl_uartdrv_eusart_exp_2_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4402c_brd4002a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4402c_brd4002a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp_2 + path: brd4402c_brd4002a/sl_uartdrv_usart_exp_2_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4402c_brd4002a/sl_uartdrv_usart_vcom_config.h diff --git a/hardware/board/config/component/brd4403c_config.slcc b/hardware/board/config/component/brd4403c_config.slcc new file mode 100644 index 0000000000..c2c0599f97 --- /dev/null +++ b/hardware/board/config/component/brd4403c_config.slcc @@ -0,0 +1,570 @@ +!!omap +- id: brd4403c_config +- label: brd4403c config +- description: Configuration files for BRD4403C +- package: platform +- category: Platform|Board|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd4403c +- provides: + - name: brd4403c_config +- config_file: + - condition: + - brd4001a + override: + component: board_control + file_id: board_control_config + path: brd4403c_brd4001a/sl_board_control_config.h + - condition: + - brd4002a + override: + component: board_control + file_id: board_control_config + path: brd4403c_brd4002a/sl_board_control_config.h + - condition: + - brd4001a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4403c_brd4001a/btl_euart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4403c_brd4001a/btl_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4403c_brd4001a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4403c_brd4001a/btl_uart_driver_cfg.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4403c_brd4001a/sl_clock_manager_oscillator_config.h + - condition: + - brd4001a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4403c_brd4001a/sl_clock_manager_tree_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4403c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4403c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4403c_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4403c_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4403c_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4403c_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4403c_brd4001a/sl_device_init_lfxo_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_3 + path: brd4403c_brd4001a/sl_emlib_gpio_init_exp_3_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_5 + path: brd4403c_brd4001a/sl_emlib_gpio_init_exp_5_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4403c_brd4001a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4403c_brd4001a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4403c_brd4001a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4001a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4403c_brd4001a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4403c_brd4001a/sl_iostream_eusart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4403c_brd4001a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4403c_brd4001a/sl_iostream_usart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4403c_brd4001a/sl_iostream_usart_vcom_config.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4403c_brd4001a/iot_flash_cfg_msc.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4403c_brd4001a/iot_flash_cfg_spiflash.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4403c_brd4001a/iot_pwm_cfg_led0.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4403c_brd4001a/iot_pwm_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4403c_brd4001a/iot_uart_cfg_vcom.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4403c_brd4001a/iot_uart_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4403c_brd4001a/iot_uart_cfg_loopback.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4403c_brd4001a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4403c_brd4001a/sl_pwm_init_led0_config.h + - condition: + - brd4001a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4403c_brd4001a/sl_rail_util_pa_config.h + - condition: + - brd4001a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4403c_brd4001a/sl_rail_util_pti_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4403c_brd4001a/sl_simple_button_btn0_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4403c_brd4001a/sl_simple_led_led0_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4403c_brd4001a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4403c_brd4001a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4403c_brd4001a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4403c_brd4001a/sl_uartdrv_usart_vcom_config.h + - condition: + - brd4002a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4403c_brd4002a/btl_euart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4403c_brd4002a/btl_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4403c_brd4002a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4403c_brd4002a/btl_uart_driver_cfg.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: brd4403c_brd4002a/sl_clock_manager_oscillator_config.h + - condition: + - brd4002a + override: + component: clock_manager + file_id: clock_manager_tree_config + path: brd4403c_brd4002a/sl_clock_manager_tree_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4403c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4403c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4403c_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4403c_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4403c_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4403c_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4403c_brd4002a/sl_device_init_lfxo_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_3 + path: brd4403c_brd4002a/sl_emlib_gpio_init_exp_3_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_5 + path: brd4403c_brd4002a/sl_emlib_gpio_init_exp_5_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_7 + path: brd4403c_brd4002a/sl_emlib_gpio_init_exp_7_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_11 + path: brd4403c_brd4002a/sl_emlib_gpio_init_exp_11_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_12 + path: brd4403c_brd4002a/sl_emlib_gpio_init_exp_12_config.h + - condition: + - brd4002a + override: + component: emlib_gpio_simple_init + file_id: emlib_gpio_simple_init_config_file_id + instance: exp_14 + path: brd4403c_brd4002a/sl_emlib_gpio_init_exp_14_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4403c_brd4002a/sl_iostream_eusart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4403c_brd4002a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4403c_brd4002a/sl_iostream_usart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4403c_brd4002a/sl_iostream_usart_vcom_config.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4403c_brd4002a/iot_flash_cfg_msc.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4403c_brd4002a/iot_flash_cfg_spiflash.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4403c_brd4002a/iot_pwm_cfg_led0.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4403c_brd4002a/iot_pwm_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4403c_brd4002a/iot_uart_cfg_vcom.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4403c_brd4002a/iot_uart_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4403c_brd4002a/iot_uart_cfg_loopback.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4403c_brd4002a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4403c_brd4002a/sl_pwm_init_led0_config.h + - condition: + - brd4002a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4403c_brd4002a/sl_rail_util_pa_config.h + - condition: + - brd4002a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4403c_brd4002a/sl_rail_util_pti_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4403c_brd4002a/sl_simple_button_btn0_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4403c_brd4002a/sl_simple_led_led0_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4403c_brd4002a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4403c_brd4002a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4403c_brd4002a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4403c_brd4002a/sl_uartdrv_usart_vcom_config.h diff --git a/hardware/board/config/component/brd4412a_config.slcc b/hardware/board/config/component/brd4412a_config.slcc index 02c6adaaa7..c99c701fa2 100644 --- a/hardware/board/config/component/brd4412a_config.slcc +++ b/hardware/board/config/component/brd4412a_config.slcc @@ -158,6 +158,12 @@ file_id: cpc_drv_uart_usart_config instance: exp path: brd4412a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4412a_brd4001a/sl_device_init_hfxo_config.h - condition: - brd4001a override: @@ -643,6 +649,12 @@ file_id: cpc_drv_uart_usart_config instance: exp path: brd4412a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4412a_brd4002a/sl_device_init_hfxo_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4413a_config.slcc b/hardware/board/config/component/brd4413a_config.slcc index c96a3cb36c..a280a967e0 100644 --- a/hardware/board/config/component/brd4413a_config.slcc +++ b/hardware/board/config/component/brd4413a_config.slcc @@ -158,6 +158,12 @@ file_id: cpc_drv_uart_usart_config instance: exp path: brd4413a_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4413a_brd4001a/sl_device_init_hfxo_config.h - condition: - brd4001a override: @@ -636,6 +642,12 @@ file_id: cpc_drv_uart_usart_config instance: exp path: brd4413a_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4413a_brd4002a/sl_device_init_hfxo_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4414a_config.slcc b/hardware/board/config/component/brd4414a_config.slcc index 1578832bac..8b6cd0869a 100644 --- a/hardware/board/config/component/brd4414a_config.slcc +++ b/hardware/board/config/component/brd4414a_config.slcc @@ -98,6 +98,12 @@ file_id: cpc_drv_uart_usart_config instance: vcom path: brd4414a_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4001a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4414a_brd4001a/sl_device_init_hfxo_config.h - condition: - brd4001a override: @@ -317,6 +323,12 @@ file_id: cpc_drv_uart_usart_config instance: vcom path: brd4414a_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4002a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4414a_brd4002a/sl_device_init_hfxo_config.h - condition: - brd4002a override: diff --git a/hardware/driver/component/segment_lcd_driver.slcc b/hardware/driver/component/segment_lcd_driver.slcc index f0b5ef332c..0d7b8cfc2a 100644 --- a/hardware/driver/component/segment_lcd_driver.slcc +++ b/hardware/driver/component/segment_lcd_driver.slcc @@ -30,6 +30,10 @@ include: file_list: - path: sl_segmentlcd_pin_config.h condition: [brd2504a] + - path: inc/brd2505a/ + file_list: + - path: sl_segmentlcd_pin_config.h + condition: [brd2505a] - path: inc/brd2506a/ file_list: - path: sl_segmentlcd_pin_config.h @@ -43,6 +47,9 @@ config_file: - path: config/ce322_1002/sl_segmentlcd_config.h file_id: sl_segmentlcd_config condition: [brd2504a] + - path: config/cl010_1087/sl_segmentlcd_config.h + file_id: sl_segmentlcd_config + condition: [brd2505a] - path: config/cl010_1087/sl_segmentlcd_config.h file_id: sl_segmentlcd_config condition: [brd2506a] diff --git a/hardware/driver/memlcd/src/memlcd_eusart/sl_memlcd_spi.c b/hardware/driver/memlcd/src/memlcd_eusart/sl_memlcd_spi.c index c5b980a2c7..7f18faaca3 100644 --- a/hardware/driver/memlcd/src/memlcd_eusart/sl_memlcd_spi.c +++ b/hardware/driver/memlcd/src/memlcd_eusart/sl_memlcd_spi.c @@ -141,7 +141,8 @@ sl_status_t sli_memlcd_spi_tx(sli_memlcd_spi_handle_t *handle, const void *data, #if defined(_SILICON_LABS_32B_SERIES_2) EUSART_Tx(eusart, SL_RBIT8(buffer[i])); #else - sl_hal_eusart_tx(eusart, SL_RBIT16((uint16_t) buffer[i])); + uint16_t reversed_data = (uint16_t)SL_RBIT8(buffer[i]); + sl_hal_eusart_tx(eusart,reversed_data); #endif #endif } diff --git a/hardware/driver/mic/src/sl_mic_pdm.c b/hardware/driver/mic/src/sl_mic_pdm.c index c4a5f67c99..fb9c106e5d 100644 --- a/hardware/driver/mic/src/sl_mic_pdm.c +++ b/hardware/driver/mic/src/sl_mic_pdm.c @@ -39,6 +39,10 @@ #include "sl_sleeptimer.h" #include "sl_device_peripheral.h" +#if (defined(SL_CATALOG_POWER_MANAGER_PRESENT)) +#include "sl_power_manager.h" +#endif + static bool dma_complete(unsigned int channel, unsigned int sequence_no, void *user_param); // Local variables @@ -184,6 +188,11 @@ sl_status_t sl_mic_init(uint32_t sample_rate, uint8_t n_channels) dma_descriptor[1].xfer.size = ldmaCtrlSizeHalf; } +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + //Add EM1 request to use LDMA + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); +#endif + reading_samples_to_buffer = false; streaming_in_progress = false; num_channels = n_channels; @@ -282,6 +291,11 @@ sl_status_t sl_mic_deinit(void) /* Free resources */ DMADRV_FreeChannel(dma_channel_id); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + //Remove EM1 request + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); +#endif + mic_running = false; initialized = false; diff --git a/hardware/driver/segment_lcd/inc/brd2505a/sl_segmentlcd_pin_config.h b/hardware/driver/segment_lcd/inc/brd2505a/sl_segmentlcd_pin_config.h new file mode 100644 index 0000000000..ff291b8cde --- /dev/null +++ b/hardware/driver/segment_lcd/inc/brd2505a/sl_segmentlcd_pin_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief Segment LCD Pin map for the EFM32PG26 Pro Kit Board (BRD2505A) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SEGMENTLCD_PIN_CONFIG_H +#define SL_SEGMENTLCD_PIN_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// Map LCD segment S0 to LCD peripheral LCD_SEG0 etc +// Seg0 pin +#define SL_SEGMENT_LCD_SEG_S00 0 +// Seg1 pin +#define SL_SEGMENT_LCD_SEG_S01 1 +// Seg2 pin +#define SL_SEGMENT_LCD_SEG_S02 2 +// Seg3 pin +#define SL_SEGMENT_LCD_SEG_S03 3 +// Seg4 pin +#define SL_SEGMENT_LCD_SEG_S04 4 +// Seg5 pin +#define SL_SEGMENT_LCD_SEG_S05 5 +// Seg6 pin +#define SL_SEGMENT_LCD_SEG_S06 6 +// Seg7 pin +#define SL_SEGMENT_LCD_SEG_S07 7 +// Seg8 pin +#define SL_SEGMENT_LCD_SEG_S08 8 +// Seg9 pin +#define SL_SEGMENT_LCD_SEG_S09 22 +// Seg10 pin +#define SL_SEGMENT_LCD_SEG_S10 10 +// Seg11 pin +#define SL_SEGMENT_LCD_SEG_S11 11 +// Seg12 pin +#define SL_SEGMENT_LCD_SEG_S12 12 +// Seg13 pin +#define SL_SEGMENT_LCD_SEG_S13 13 +// Seg14 pin +#define SL_SEGMENT_LCD_SEG_S14 20 +// Seg15 pin +#define SL_SEGMENT_LCD_SEG_S15 21 +// Seg16 pin +#define SL_SEGMENT_LCD_SEG_S16 16 +// Seg17 pin +#define SL_SEGMENT_LCD_SEG_S17 17 +// Seg18 pin +#define SL_SEGMENT_LCD_SEG_S18 18 +// Seg19 pin +#define SL_SEGMENT_LCD_SEG_S19 19 + +// Map LCD COM0 to LCD peripheral LCD_COM0 etc +// Com0 pin +#define SL_SEGMENT_LCD_COM_C00 0 +// Com1 pin +#define SL_SEGMENT_LCD_COM_C01 1 +// Com2 pin +#define SL_SEGMENT_LCD_COM_C02 2 +// Com3 pin +#define SL_SEGMENT_LCD_COM_C03 3 +// Com4 pin +#define SL_SEGMENT_LCD_COM_C04 4 +// Com5 pin +#define SL_SEGMENT_LCD_COM_C05 5 +// Com6 pin +#define SL_SEGMENT_LCD_COM_C06 6 +// Com7 pin +#define SL_SEGMENT_LCD_COM_C07 7 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/module/config/BGM210LA22JIF/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210LA22JIF/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210LA22JIF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210LA22JIF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210LA22JIF/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210LA22JIF/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210LA22JIF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210LA22JIF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM210LA22JNF/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210LA22JNF/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210LA22JNF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210LA22JNF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210LA22JNF/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210LA22JNF/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210LA22JNF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210LA22JNF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM210P022JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210P022JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210P022JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210P022JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210P022JIA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210P022JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210P022JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210P022JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM210P032JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210P032JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210P032JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210P032JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210P032JIA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210P032JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210P032JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210P032JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM210PA22JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210PA22JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210PA22JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210PA22JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210PA22JIA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210PA22JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210PA22JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210PA22JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM210PA32JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210PA32JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210PA32JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210PA32JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210PA32JIA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210PA32JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210PA32JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210PA32JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM210PB22JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210PB22JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210PB22JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210PB22JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210PB22JIA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210PB22JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210PB22JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210PB22JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM210PB32JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM210PB32JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/BGM210PB32JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM210PB32JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM210PB32JIA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM210PB32JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/BGM210PB32JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM210PB32JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM220PC22HNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM220PC22HNA/sl_clock_manager_oscillator_config.h index cfbe348662..41a84a09f0 100644 --- a/hardware/module/config/BGM220PC22HNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM220PC22HNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM220PC22HNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM220PC22HNA/sl_clock_manager_tree_config.h index 6a44cecbe8..88b05924c1 100644 --- a/hardware/module/config/BGM220PC22HNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM220PC22HNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM220PC22WGA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM220PC22WGA/sl_clock_manager_oscillator_config.h index 984a00b33f..d18f743d5f 100644 --- a/hardware/module/config/BGM220PC22WGA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM220PC22WGA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM220PC22WGA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM220PC22WGA/sl_clock_manager_tree_config.h index 721eaf6c38..e7d0d573c7 100644 --- a/hardware/module/config/BGM220PC22WGA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM220PC22WGA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM220SC12WGA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM220SC12WGA/sl_clock_manager_oscillator_config.h index 984a00b33f..d18f743d5f 100644 --- a/hardware/module/config/BGM220SC12WGA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM220SC12WGA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM220SC12WGA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM220SC12WGA/sl_clock_manager_tree_config.h index 721eaf6c38..e7d0d573c7 100644 --- a/hardware/module/config/BGM220SC12WGA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM220SC12WGA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM220SC22HNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM220SC22HNA/sl_clock_manager_oscillator_config.h index 984a00b33f..d18f743d5f 100644 --- a/hardware/module/config/BGM220SC22HNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM220SC22HNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM220SC22HNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM220SC22HNA/sl_clock_manager_tree_config.h index 721eaf6c38..e7d0d573c7 100644 --- a/hardware/module/config/BGM220SC22HNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM220SC22HNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM220SC22WGA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM220SC22WGA/sl_clock_manager_oscillator_config.h index 984a00b33f..d18f743d5f 100644 --- a/hardware/module/config/BGM220SC22WGA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM220SC22WGA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM220SC22WGA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM220SC22WGA/sl_clock_manager_tree_config.h index 721eaf6c38..e7d0d573c7 100644 --- a/hardware/module/config/BGM220SC22WGA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM220SC22WGA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM220SC23HNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM220SC23HNA/sl_clock_manager_oscillator_config.h index 984a00b33f..d18f743d5f 100644 --- a/hardware/module/config/BGM220SC23HNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM220SC23HNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM220SC23HNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM220SC23HNA/sl_clock_manager_tree_config.h index 721eaf6c38..e7d0d573c7 100644 --- a/hardware/module/config/BGM220SC23HNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM220SC23HNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240PA22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240PA22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240PA22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240PA22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240PA22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240PA22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240PA22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240PA22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240PA32VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240PA32VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240PA32VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240PA32VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240PA32VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240PA32VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240PA32VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240PA32VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240PA32VNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240PA32VNN/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240PA32VNN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240PA32VNN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240PA32VNN/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240PA32VNN/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240PA32VNN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240PA32VNN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240PB22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240PB22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240PB22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240PB22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240PB22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240PB22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240PB22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240PB22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240PB32VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240PB32VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240PB32VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240PB32VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240PB32VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240PB32VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240PB32VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240PB32VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240PB32VNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240PB32VNN/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240PB32VNN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240PB32VNN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240PB32VNN/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240PB32VNN/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240PB32VNN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240PB32VNN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240SA22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240SA22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240SA22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240SA22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240SA22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240SA22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240SA22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240SA22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM240SB22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM240SB22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/BGM240SB22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM240SB22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM240SB22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM240SB22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM240SB22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM240SB22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM241SB22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM241SB22VNA/sl_clock_manager_oscillator_config.h index 20840e6c32..1dc28caac5 100644 --- a/hardware/module/config/BGM241SB22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM241SB22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM241SB22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM241SB22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM241SB22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM241SB22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM241SD22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM241SD22VNA/sl_clock_manager_oscillator_config.h index 20840e6c32..1dc28caac5 100644 --- a/hardware/module/config/BGM241SD22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/BGM241SD22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/BGM241SD22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM241SD22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/BGM241SD22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/BGM241SD22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/BGM260PB22VNA/iot_flash_cfg_msc.h b/hardware/module/config/BGM260PB22VNA/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/module/config/BGM260PB22VNA/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/module/config/BGM260PB22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM260PB22VNA/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..1dc28caac5 --- /dev/null +++ b/hardware/module/config/BGM260PB22VNA/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 40000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 0 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/module/config/BGM260PB22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM260PB22VNA/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..88a9e6bba4 --- /dev/null +++ b/hardware/module/config/BGM260PB22VNA/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/module/config/BGM260PB22VNA/sl_device_init_dpll_config.h b/hardware/module/config/BGM260PB22VNA/sl_device_init_dpll_config.h new file mode 100644 index 0000000000..d640c6ea05 --- /dev/null +++ b/hardware/module/config/BGM260PB22VNA/sl_device_init_dpll_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DPLL Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H +#define SL_DEVICE_INIT_DPLL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// Default: 78000000 +#define SL_DEVICE_INIT_DPLL_FREQ 80000000 + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 3839 +#define SL_DEVICE_INIT_DPLL_N 3839 + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 1919 +#define SL_DEVICE_INIT_DPLL_M 1919 + +// Reference Clock +// Reference clock source for DPLL +// HFXO +// LFXO +// CLKIN0 +// Default: cmuSelect_HFXO +#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// Default: cmuDPLLEdgeSel_Fall +#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// Default: cmuDPLLLockMode_Freq +#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase + +// Automatic Lock Recovery +// Default: 1 +#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 + +// Enable Dither +// Default: 0 +#define SL_DEVICE_INIT_DPLL_DITHER 0 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/hardware/module/config/BGM260PB22VNA/sl_device_init_hfxo_config.h b/hardware/module/config/BGM260PB22VNA/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..5c118546ba --- /dev/null +++ b/hardware/module/config/BGM260PB22VNA/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 40000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/BGM260PB22VNA/sl_rail_util_pa_config.h b/hardware/module/config/BGM260PB22VNA/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..8d9bde66bd --- /dev/null +++ b/hardware/module/config/BGM260PB22VNA/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <10-10:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/module/config/BGM260PB32VNA/iot_flash_cfg_msc.h b/hardware/module/config/BGM260PB32VNA/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/module/config/BGM260PB32VNA/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/module/config/BGM260PB32VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/BGM260PB32VNA/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..1dc28caac5 --- /dev/null +++ b/hardware/module/config/BGM260PB32VNA/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 40000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 0 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/module/config/BGM260PB32VNA/sl_clock_manager_tree_config.h b/hardware/module/config/BGM260PB32VNA/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..88a9e6bba4 --- /dev/null +++ b/hardware/module/config/BGM260PB32VNA/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/module/config/BGM260PB32VNA/sl_device_init_dpll_config.h b/hardware/module/config/BGM260PB32VNA/sl_device_init_dpll_config.h new file mode 100644 index 0000000000..d640c6ea05 --- /dev/null +++ b/hardware/module/config/BGM260PB32VNA/sl_device_init_dpll_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DPLL Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H +#define SL_DEVICE_INIT_DPLL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// Default: 78000000 +#define SL_DEVICE_INIT_DPLL_FREQ 80000000 + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 3839 +#define SL_DEVICE_INIT_DPLL_N 3839 + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 1919 +#define SL_DEVICE_INIT_DPLL_M 1919 + +// Reference Clock +// Reference clock source for DPLL +// HFXO +// LFXO +// CLKIN0 +// Default: cmuSelect_HFXO +#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// Default: cmuDPLLEdgeSel_Fall +#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// Default: cmuDPLLLockMode_Freq +#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase + +// Automatic Lock Recovery +// Default: 1 +#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 + +// Enable Dither +// Default: 0 +#define SL_DEVICE_INIT_DPLL_DITHER 0 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/hardware/module/config/BGM260PB32VNA/sl_device_init_hfxo_config.h b/hardware/module/config/BGM260PB32VNA/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..5c118546ba --- /dev/null +++ b/hardware/module/config/BGM260PB32VNA/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 40000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/BGM260PB32VNA/sl_rail_util_pa_config.h b/hardware/module/config/BGM260PB32VNA/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..26c6fb28c3 --- /dev/null +++ b/hardware/module/config/BGM260PB32VNA/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <10-10:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/module/config/FGM230SA27HGN/sl_clock_manager_oscillator_config.h b/hardware/module/config/FGM230SA27HGN/sl_clock_manager_oscillator_config.h index 7bc0137384..42cd842881 100644 --- a/hardware/module/config/FGM230SA27HGN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/FGM230SA27HGN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/FGM230SA27HGN/sl_clock_manager_tree_config.h b/hardware/module/config/FGM230SA27HGN/sl_clock_manager_tree_config.h index a1e2a6709f..dbd5ff2250 100644 --- a/hardware/module/config/FGM230SA27HGN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/FGM230SA27HGN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/FGM230SB27HGN/sl_clock_manager_oscillator_config.h b/hardware/module/config/FGM230SB27HGN/sl_clock_manager_oscillator_config.h index 7bc0137384..42cd842881 100644 --- a/hardware/module/config/FGM230SB27HGN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/FGM230SB27HGN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/FGM230SB27HGN/sl_clock_manager_tree_config.h b/hardware/module/config/FGM230SB27HGN/sl_clock_manager_tree_config.h index a1e2a6709f..dbd5ff2250 100644 --- a/hardware/module/config/FGM230SB27HGN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/FGM230SB27HGN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210L022JIF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210L022JIF/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210L022JIF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210L022JIF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210L022JIF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210L022JIF/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210L022JIF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210L022JIF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210L022JNF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210L022JNF/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210L022JNF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210L022JNF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210L022JNF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210L022JNF/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210L022JNF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210L022JNF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210LA22JIF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210LA22JIF/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210LA22JIF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210LA22JIF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210LA22JIF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210LA22JIF/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210LA22JIF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210LA22JIF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210LA22JNF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210LA22JNF/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210LA22JNF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210LA22JNF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210LA22JNF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210LA22JNF/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210LA22JNF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210LA22JNF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210P022JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210P022JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210P022JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210P022JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210P022JIA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210P022JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210P022JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210P022JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210P032JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210P032JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210P032JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210P032JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210P032JIA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210P032JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210P032JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210P032JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210PA22JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210PA22JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210PA22JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210PA22JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210PA22JIA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210PA22JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210PA22JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210PA22JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210PA32JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210PA32JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210PA32JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210PA32JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210PA32JIA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210PA32JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210PA32JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210PA32JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210PB22JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210PB22JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210PB22JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210PB22JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210PB22JIA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210PB22JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210PB22JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210PB22JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM210PB32JIA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM210PB32JIA/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM210PB32JIA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM210PB32JIA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM210PB32JIA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM210PB32JIA/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM210PB32JIA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM210PB32JIA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM211LA02JNF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM211LA02JNF/sl_clock_manager_oscillator_config.h index 10a7176bfa..de7017b08b 100644 --- a/hardware/module/config/MGM211LA02JNF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM211LA02JNF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM211LA02JNF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM211LA02JNF/sl_clock_manager_tree_config.h index a9d61780a9..baa63960e2 100644 --- a/hardware/module/config/MGM211LA02JNF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM211LA02JNF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM220PC22HNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM220PC22HNA/sl_clock_manager_oscillator_config.h index cfbe348662..41a84a09f0 100644 --- a/hardware/module/config/MGM220PC22HNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM220PC22HNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM220PC22HNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM220PC22HNA/sl_clock_manager_tree_config.h index 6a44cecbe8..88b05924c1 100644 --- a/hardware/module/config/MGM220PC22HNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM220PC22HNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240L022RNF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240L022RNF/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240L022RNF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240L022RNF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240L022RNF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240L022RNF/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240L022RNF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240L022RNF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240L022VIF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240L022VIF/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240L022VIF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240L022VIF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240L022VIF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240L022VIF/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240L022VIF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240L022VIF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240L022VNF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240L022VNF/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240L022VNF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240L022VNF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240L022VNF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240L022VNF/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240L022VNF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240L022VNF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240LA22UIF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240LA22UIF/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240LA22UIF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240LA22UIF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240LA22UIF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240LA22UIF/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240LA22UIF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240LA22UIF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240LA22VIF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240LA22VIF/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240LA22VIF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240LA22VIF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240LA22VIF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240LA22VIF/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240LA22VIF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240LA22VIF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240LD22VIF/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240LD22VIF/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240LD22VIF/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240LD22VIF/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240LD22VIF/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240LD22VIF/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240LD22VIF/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240LD22VIF/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240PA22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240PA22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240PA22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240PA22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240PA22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240PA22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240PA22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240PA22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240PA32VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240PA32VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240PA32VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240PA32VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240PA32VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240PA32VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240PA32VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240PA32VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240PA32VNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240PA32VNN/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240PA32VNN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240PA32VNN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240PA32VNN/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240PA32VNN/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240PA32VNN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240PA32VNN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240PB22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240PB22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240PB22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240PB22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240PB22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240PB22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240PB22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240PB22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240PB32VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240PB32VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240PB32VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240PB32VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240PB32VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240PB32VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240PB32VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240PB32VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240PB32VNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240PB32VNN/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240PB32VNN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240PB32VNN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240PB32VNN/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240PB32VNN/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240PB32VNN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240PB32VNN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240SA22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240SA22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240SA22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240SA22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240SA22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240SA22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240SA22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240SA22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240SB22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240SB22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240SB22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240SB22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240SB22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240SB22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240SB22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240SB22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM240SD22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM240SD22VNA/sl_clock_manager_oscillator_config.h index 8b8740fd42..785882b1d3 100644 --- a/hardware/module/config/MGM240SD22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM240SD22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM240SD22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM240SD22VNA/sl_clock_manager_tree_config.h index 6ad37ed993..16b2ea6c72 100644 --- a/hardware/module/config/MGM240SD22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM240SD22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM260PB22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM260PB22VNA/sl_clock_manager_oscillator_config.h index 20840e6c32..1dc28caac5 100644 --- a/hardware/module/config/MGM260PB22VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM260PB22VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM260PB22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM260PB22VNA/sl_clock_manager_tree_config.h index de6abeeab1..88a9e6bba4 100644 --- a/hardware/module/config/MGM260PB22VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM260PB22VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM260PB32VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM260PB32VNA/sl_clock_manager_oscillator_config.h index 20840e6c32..1dc28caac5 100644 --- a/hardware/module/config/MGM260PB32VNA/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM260PB32VNA/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM260PB32VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM260PB32VNA/sl_clock_manager_tree_config.h index de6abeeab1..88a9e6bba4 100644 --- a/hardware/module/config/MGM260PB32VNA/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM260PB32VNA/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM260PB32VNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM260PB32VNN/sl_clock_manager_oscillator_config.h index 20840e6c32..1dc28caac5 100644 --- a/hardware/module/config/MGM260PB32VNN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/MGM260PB32VNN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/MGM260PB32VNN/sl_clock_manager_tree_config.h b/hardware/module/config/MGM260PB32VNN/sl_clock_manager_tree_config.h index de6abeeab1..88a9e6bba4 100644 --- a/hardware/module/config/MGM260PB32VNN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/MGM260PB32VNN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/MGM260PD22VNA/iot_flash_cfg_msc.h b/hardware/module/config/MGM260PD22VNA/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/module/config/MGM260PD22VNA/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/module/config/MGM260PD22VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM260PD22VNA/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..1dc28caac5 --- /dev/null +++ b/hardware/module/config/MGM260PD22VNA/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 40000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 0 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/module/config/MGM260PD22VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM260PD22VNA/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..88a9e6bba4 --- /dev/null +++ b/hardware/module/config/MGM260PD22VNA/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/module/config/MGM260PD22VNA/sl_device_init_dpll_config.h b/hardware/module/config/MGM260PD22VNA/sl_device_init_dpll_config.h new file mode 100644 index 0000000000..d640c6ea05 --- /dev/null +++ b/hardware/module/config/MGM260PD22VNA/sl_device_init_dpll_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DPLL Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H +#define SL_DEVICE_INIT_DPLL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// Default: 78000000 +#define SL_DEVICE_INIT_DPLL_FREQ 80000000 + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 3839 +#define SL_DEVICE_INIT_DPLL_N 3839 + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 1919 +#define SL_DEVICE_INIT_DPLL_M 1919 + +// Reference Clock +// Reference clock source for DPLL +// HFXO +// LFXO +// CLKIN0 +// Default: cmuSelect_HFXO +#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// Default: cmuDPLLEdgeSel_Fall +#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// Default: cmuDPLLLockMode_Freq +#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase + +// Automatic Lock Recovery +// Default: 1 +#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 + +// Enable Dither +// Default: 0 +#define SL_DEVICE_INIT_DPLL_DITHER 0 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/hardware/module/config/MGM260PD22VNA/sl_device_init_hfxo_config.h b/hardware/module/config/MGM260PD22VNA/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..5c118546ba --- /dev/null +++ b/hardware/module/config/MGM260PD22VNA/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 40000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/MGM260PD22VNA/sl_rail_util_pa_config.h b/hardware/module/config/MGM260PD22VNA/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..8d9bde66bd --- /dev/null +++ b/hardware/module/config/MGM260PD22VNA/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <10-10:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/module/config/MGM260PD32VNA/iot_flash_cfg_msc.h b/hardware/module/config/MGM260PD32VNA/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/module/config/MGM260PD32VNA/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/module/config/MGM260PD32VNA/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM260PD32VNA/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..1dc28caac5 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNA/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 40000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 0 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/module/config/MGM260PD32VNA/sl_clock_manager_tree_config.h b/hardware/module/config/MGM260PD32VNA/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..88a9e6bba4 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNA/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/module/config/MGM260PD32VNA/sl_device_init_dpll_config.h b/hardware/module/config/MGM260PD32VNA/sl_device_init_dpll_config.h new file mode 100644 index 0000000000..d640c6ea05 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNA/sl_device_init_dpll_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DPLL Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H +#define SL_DEVICE_INIT_DPLL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// Default: 78000000 +#define SL_DEVICE_INIT_DPLL_FREQ 80000000 + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 3839 +#define SL_DEVICE_INIT_DPLL_N 3839 + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 1919 +#define SL_DEVICE_INIT_DPLL_M 1919 + +// Reference Clock +// Reference clock source for DPLL +// HFXO +// LFXO +// CLKIN0 +// Default: cmuSelect_HFXO +#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// Default: cmuDPLLEdgeSel_Fall +#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// Default: cmuDPLLLockMode_Freq +#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase + +// Automatic Lock Recovery +// Default: 1 +#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 + +// Enable Dither +// Default: 0 +#define SL_DEVICE_INIT_DPLL_DITHER 0 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/hardware/module/config/MGM260PD32VNA/sl_device_init_hfxo_config.h b/hardware/module/config/MGM260PD32VNA/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..5c118546ba --- /dev/null +++ b/hardware/module/config/MGM260PD32VNA/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 40000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/MGM260PD32VNA/sl_rail_util_pa_config.h b/hardware/module/config/MGM260PD32VNA/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..26c6fb28c3 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNA/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <10-10:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/module/config/MGM260PD32VNN/iot_flash_cfg_msc.h b/hardware/module/config/MGM260PD32VNN/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/module/config/MGM260PD32VNN/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/module/config/MGM260PD32VNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/MGM260PD32VNN/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..1dc28caac5 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNN/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 40000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 0 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/hardware/module/config/MGM260PD32VNN/sl_clock_manager_tree_config.h b/hardware/module/config/MGM260PD32VNN/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..88a9e6bba4 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNN/sl_clock_manager_tree_config.h @@ -0,0 +1,319 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/hardware/module/config/MGM260PD32VNN/sl_device_init_dpll_config.h b/hardware/module/config/MGM260PD32VNN/sl_device_init_dpll_config.h new file mode 100644 index 0000000000..d640c6ea05 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNN/sl_device_init_dpll_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DPLL Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H +#define SL_DEVICE_INIT_DPLL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// Default: 78000000 +#define SL_DEVICE_INIT_DPLL_FREQ 80000000 + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 3839 +#define SL_DEVICE_INIT_DPLL_N 3839 + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 1919 +#define SL_DEVICE_INIT_DPLL_M 1919 + +// Reference Clock +// Reference clock source for DPLL +// HFXO +// LFXO +// CLKIN0 +// Default: cmuSelect_HFXO +#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// Default: cmuDPLLEdgeSel_Fall +#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// Default: cmuDPLLLockMode_Freq +#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase + +// Automatic Lock Recovery +// Default: 1 +#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 + +// Enable Dither +// Default: 0 +#define SL_DEVICE_INIT_DPLL_DITHER 0 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/hardware/module/config/MGM260PD32VNN/sl_device_init_hfxo_config.h b/hardware/module/config/MGM260PD32VNN/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..5c118546ba --- /dev/null +++ b/hardware/module/config/MGM260PD32VNN/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 40000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/MGM260PD32VNN/sl_rail_util_pa_config.h b/hardware/module/config/MGM260PD32VNN/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..26c6fb28c3 --- /dev/null +++ b/hardware/module/config/MGM260PD32VNN/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <10-10:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_oscillator_config.h b/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_oscillator_config.h index 7bc0137384..42cd842881 100644 --- a/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_tree_config.h b/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_tree_config.h index a1e2a6709f..dbd5ff2250 100644 --- a/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/ZGM230SA27HGN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_oscillator_config.h index 7bc0137384..42cd842881 100644 --- a/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_tree_config.h b/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_tree_config.h index a1e2a6709f..dbd5ff2250 100644 --- a/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/ZGM230SA27HNN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_oscillator_config.h b/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_oscillator_config.h index 7bc0137384..42cd842881 100644 --- a/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_tree_config.h b/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_tree_config.h index a1e2a6709f..dbd5ff2250 100644 --- a/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/ZGM230SB27HGN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_oscillator_config.h b/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_oscillator_config.h index 7bc0137384..42cd842881 100644 --- a/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_oscillator_config.h +++ b/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_tree_config.h b/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_tree_config.h index a1e2a6709f..dbd5ff2250 100644 --- a/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_tree_config.h +++ b/hardware/module/config/ZGM230SB27HNN/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/hardware/module/config/component/BGM210LA22JIF_config.slcc b/hardware/module/config/component/BGM210LA22JIF_config.slcc index 764859dc89..fb0c338eef 100644 --- a/hardware/module/config/component/BGM210LA22JIF_config.slcc +++ b/hardware/module/config/component/BGM210LA22JIF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210LA22JIF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210LA22JIF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210LA22JIF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM210LA22JNF_config.slcc b/hardware/module/config/component/BGM210LA22JNF_config.slcc index 410500fd8a..7750865f03 100644 --- a/hardware/module/config/component/BGM210LA22JNF_config.slcc +++ b/hardware/module/config/component/BGM210LA22JNF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210LA22JNF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210LA22JNF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210LA22JNF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM210P022JIA_config.slcc b/hardware/module/config/component/BGM210P022JIA_config.slcc index ec1549fb83..eceec061a1 100644 --- a/hardware/module/config/component/BGM210P022JIA_config.slcc +++ b/hardware/module/config/component/BGM210P022JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210P022JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210P022JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210P022JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM210P032JIA_config.slcc b/hardware/module/config/component/BGM210P032JIA_config.slcc index c312c01d8f..70002a5d72 100644 --- a/hardware/module/config/component/BGM210P032JIA_config.slcc +++ b/hardware/module/config/component/BGM210P032JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210P032JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210P032JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210P032JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM210PA22JIA_config.slcc b/hardware/module/config/component/BGM210PA22JIA_config.slcc index 4ca191c1e2..a4bfca2b06 100644 --- a/hardware/module/config/component/BGM210PA22JIA_config.slcc +++ b/hardware/module/config/component/BGM210PA22JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210PA22JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210PA22JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210PA22JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM210PA32JIA_config.slcc b/hardware/module/config/component/BGM210PA32JIA_config.slcc index a0ae1d25e5..af2d639ad0 100644 --- a/hardware/module/config/component/BGM210PA32JIA_config.slcc +++ b/hardware/module/config/component/BGM210PA32JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210PA32JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210PA32JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210PA32JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM210PB22JIA_config.slcc b/hardware/module/config/component/BGM210PB22JIA_config.slcc index a505d8c894..046236ad22 100644 --- a/hardware/module/config/component/BGM210PB22JIA_config.slcc +++ b/hardware/module/config/component/BGM210PB22JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210PB22JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210PB22JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210PB22JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM210PB32JIA_config.slcc b/hardware/module/config/component/BGM210PB32JIA_config.slcc index 2a660faa91..1d7acf6cf5 100644 --- a/hardware/module/config/component/BGM210PB32JIA_config.slcc +++ b/hardware/module/config/component/BGM210PB32JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM210PB32JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM210PB32JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM210PB32JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM220PC22HNA_config.slcc b/hardware/module/config/component/BGM220PC22HNA_config.slcc index 57732b68bc..286b19c489 100644 --- a/hardware/module/config/component/BGM220PC22HNA_config.slcc +++ b/hardware/module/config/component/BGM220PC22HNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM220PC22HNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM220PC22HNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM220PC22HNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: device_init_lfxo file_id: device_init_lfxo_config path: BGM220PC22HNA/sl_device_init_lfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM220PC22WGA_config.slcc b/hardware/module/config/component/BGM220PC22WGA_config.slcc index 4e5cab1cdb..e52a212f8e 100644 --- a/hardware/module/config/component/BGM220PC22WGA_config.slcc +++ b/hardware/module/config/component/BGM220PC22WGA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM220PC22WGA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM220PC22WGA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM220PC22WGA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM220SC12WGA_config.slcc b/hardware/module/config/component/BGM220SC12WGA_config.slcc index 931360c987..e597e724a8 100644 --- a/hardware/module/config/component/BGM220SC12WGA_config.slcc +++ b/hardware/module/config/component/BGM220SC12WGA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM220SC12WGA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM220SC12WGA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM220SC12WGA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM220SC22HNA_config.slcc b/hardware/module/config/component/BGM220SC22HNA_config.slcc index 5a07d89ab3..9cf0a3cc91 100644 --- a/hardware/module/config/component/BGM220SC22HNA_config.slcc +++ b/hardware/module/config/component/BGM220SC22HNA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM220SC22HNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM220SC22HNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM220SC22HNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM220SC22WGA_config.slcc b/hardware/module/config/component/BGM220SC22WGA_config.slcc index 57582a3daa..61716765a1 100644 --- a/hardware/module/config/component/BGM220SC22WGA_config.slcc +++ b/hardware/module/config/component/BGM220SC22WGA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM220SC22WGA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM220SC22WGA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM220SC22WGA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM220SC23HNA_config.slcc b/hardware/module/config/component/BGM220SC23HNA_config.slcc index 18672f098e..f630efb1e4 100644 --- a/hardware/module/config/component/BGM220SC23HNA_config.slcc +++ b/hardware/module/config/component/BGM220SC23HNA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: BGM220SC23HNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM220SC23HNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM220SC23HNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240PA22VNA_config.slcc b/hardware/module/config/component/BGM240PA22VNA_config.slcc index e14773a60c..c5c6d4ca18 100644 --- a/hardware/module/config/component/BGM240PA22VNA_config.slcc +++ b/hardware/module/config/component/BGM240PA22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240PA22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240PA22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240PA22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240PA22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240PA32VNA_config.slcc b/hardware/module/config/component/BGM240PA32VNA_config.slcc index fdee1531a4..c42d1e0be3 100644 --- a/hardware/module/config/component/BGM240PA32VNA_config.slcc +++ b/hardware/module/config/component/BGM240PA32VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240PA32VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240PA32VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240PA32VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240PA32VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240PA32VNN_config.slcc b/hardware/module/config/component/BGM240PA32VNN_config.slcc index 2e2133234b..445b18130c 100644 --- a/hardware/module/config/component/BGM240PA32VNN_config.slcc +++ b/hardware/module/config/component/BGM240PA32VNN_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240PA32VNN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240PA32VNN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240PA32VNN/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240PA32VNN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240PB22VNA_config.slcc b/hardware/module/config/component/BGM240PB22VNA_config.slcc index dfe68caa38..f236d8d2ca 100644 --- a/hardware/module/config/component/BGM240PB22VNA_config.slcc +++ b/hardware/module/config/component/BGM240PB22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240PB22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240PB22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240PB22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240PB22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240PB32VNA_config.slcc b/hardware/module/config/component/BGM240PB32VNA_config.slcc index 30dbf54c56..66aab3104a 100644 --- a/hardware/module/config/component/BGM240PB32VNA_config.slcc +++ b/hardware/module/config/component/BGM240PB32VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240PB32VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240PB32VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240PB32VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240PB32VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240PB32VNN_config.slcc b/hardware/module/config/component/BGM240PB32VNN_config.slcc index ddc0bd2404..c6eaadff40 100644 --- a/hardware/module/config/component/BGM240PB32VNN_config.slcc +++ b/hardware/module/config/component/BGM240PB32VNN_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240PB32VNN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240PB32VNN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240PB32VNN/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240PB32VNN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240SA22VNA_config.slcc b/hardware/module/config/component/BGM240SA22VNA_config.slcc index 1ef16150a8..c24dbaa553 100644 --- a/hardware/module/config/component/BGM240SA22VNA_config.slcc +++ b/hardware/module/config/component/BGM240SA22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240SA22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240SA22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240SA22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240SA22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM240SB22VNA_config.slcc b/hardware/module/config/component/BGM240SB22VNA_config.slcc index 12a95d418f..181aefaad7 100644 --- a/hardware/module/config/component/BGM240SB22VNA_config.slcc +++ b/hardware/module/config/component/BGM240SB22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: BGM240SB22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM240SB22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM240SB22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM240SB22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM241SB22VNA_config.slcc b/hardware/module/config/component/BGM241SB22VNA_config.slcc index 7289e9e73a..c78001b6c8 100644 --- a/hardware/module/config/component/BGM241SB22VNA_config.slcc +++ b/hardware/module/config/component/BGM241SB22VNA_config.slcc @@ -21,25 +21,31 @@ file_id: clock_manager_oscillator_config path: BGM241SB22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM241SB22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM241SB22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_dpll file_id: device_init_dpll_config path: BGM241SB22VNA/sl_device_init_dpll_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM241SB22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM241SD22VNA_config.slcc b/hardware/module/config/component/BGM241SD22VNA_config.slcc index 812af3574f..3360bdca64 100644 --- a/hardware/module/config/component/BGM241SD22VNA_config.slcc +++ b/hardware/module/config/component/BGM241SD22VNA_config.slcc @@ -21,25 +21,31 @@ file_id: clock_manager_oscillator_config path: BGM241SD22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: BGM241SD22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: BGM241SD22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_dpll file_id: device_init_dpll_config path: BGM241SD22VNA/sl_device_init_dpll_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: BGM241SD22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/BGM260PB22VNA_config.slcc b/hardware/module/config/component/BGM260PB22VNA_config.slcc new file mode 100644 index 0000000000..061bccf368 --- /dev/null +++ b/hardware/module/config/component/BGM260PB22VNA_config.slcc @@ -0,0 +1,51 @@ +!!omap +- id: BGM260PB22VNA_config +- label: BGM260PB22VNA config +- description: Configuration files for BGM260PB22VNA +- package: platform +- category: Platform|Device|BGM26|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/module/config +- requires: + - name: bgm260pb22vna +- provides: + - name: BGM260PB22VNA_config +- config_file: + - override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: BGM260PB22VNA/sl_clock_manager_oscillator_config.h + unless: + - hardware_board + - override: + component: clock_manager + file_id: clock_manager_tree_config + path: BGM260PB22VNA/sl_clock_manager_tree_config.h + unless: + - hardware_board + - override: + component: device_init_dpll + file_id: device_init_dpll_config + path: BGM260PB22VNA/sl_device_init_dpll_config.h + unless: + - hardware_board + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: BGM260PB22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: BGM260PB22VNA/iot_flash_cfg_msc.h + - override: + component: rail_util_pa + file_id: rail_util_pa_config + path: BGM260PB22VNA/sl_rail_util_pa_config.h diff --git a/hardware/module/config/component/BGM260PB32VNA_config.slcc b/hardware/module/config/component/BGM260PB32VNA_config.slcc new file mode 100644 index 0000000000..88c0bdc62a --- /dev/null +++ b/hardware/module/config/component/BGM260PB32VNA_config.slcc @@ -0,0 +1,51 @@ +!!omap +- id: BGM260PB32VNA_config +- label: BGM260PB32VNA config +- description: Configuration files for BGM260PB32VNA +- package: platform +- category: Platform|Device|BGM26|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/module/config +- requires: + - name: bgm260pb32vna +- provides: + - name: BGM260PB32VNA_config +- config_file: + - override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: BGM260PB32VNA/sl_clock_manager_oscillator_config.h + unless: + - hardware_board + - override: + component: clock_manager + file_id: clock_manager_tree_config + path: BGM260PB32VNA/sl_clock_manager_tree_config.h + unless: + - hardware_board + - override: + component: device_init_dpll + file_id: device_init_dpll_config + path: BGM260PB32VNA/sl_device_init_dpll_config.h + unless: + - hardware_board + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: BGM260PB32VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: BGM260PB32VNA/iot_flash_cfg_msc.h + - override: + component: rail_util_pa + file_id: rail_util_pa_config + path: BGM260PB32VNA/sl_rail_util_pa_config.h diff --git a/hardware/module/config/component/FGM230SA27HGN_config.slcc b/hardware/module/config/component/FGM230SA27HGN_config.slcc index 6507286835..31bea70d25 100644 --- a/hardware/module/config/component/FGM230SA27HGN_config.slcc +++ b/hardware/module/config/component/FGM230SA27HGN_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: FGM230SA27HGN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: FGM230SA27HGN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: FGM230SA27HGN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/FGM230SB27HGN_config.slcc b/hardware/module/config/component/FGM230SB27HGN_config.slcc index bb429796c6..b833fa7693 100644 --- a/hardware/module/config/component/FGM230SB27HGN_config.slcc +++ b/hardware/module/config/component/FGM230SB27HGN_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: FGM230SB27HGN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: FGM230SB27HGN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: FGM230SB27HGN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210L022JIF_config.slcc b/hardware/module/config/component/MGM210L022JIF_config.slcc index 25e30f74c5..796168543d 100644 --- a/hardware/module/config/component/MGM210L022JIF_config.slcc +++ b/hardware/module/config/component/MGM210L022JIF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210L022JIF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210L022JIF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210L022JIF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210L022JNF_config.slcc b/hardware/module/config/component/MGM210L022JNF_config.slcc index cdfb764850..becbf88192 100644 --- a/hardware/module/config/component/MGM210L022JNF_config.slcc +++ b/hardware/module/config/component/MGM210L022JNF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210L022JNF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210L022JNF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210L022JNF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210LA22JIF_config.slcc b/hardware/module/config/component/MGM210LA22JIF_config.slcc index 1ec45bcfbb..d6c39266cb 100644 --- a/hardware/module/config/component/MGM210LA22JIF_config.slcc +++ b/hardware/module/config/component/MGM210LA22JIF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210LA22JIF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210LA22JIF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210LA22JIF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210LA22JNF_config.slcc b/hardware/module/config/component/MGM210LA22JNF_config.slcc index efd179cf6b..23731ab5c0 100644 --- a/hardware/module/config/component/MGM210LA22JNF_config.slcc +++ b/hardware/module/config/component/MGM210LA22JNF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210LA22JNF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210LA22JNF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210LA22JNF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210P022JIA_config.slcc b/hardware/module/config/component/MGM210P022JIA_config.slcc index 00cf876002..8ecfa73806 100644 --- a/hardware/module/config/component/MGM210P022JIA_config.slcc +++ b/hardware/module/config/component/MGM210P022JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210P022JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210P022JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210P022JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210P032JIA_config.slcc b/hardware/module/config/component/MGM210P032JIA_config.slcc index 6a90e7ba2c..4eb67e6b23 100644 --- a/hardware/module/config/component/MGM210P032JIA_config.slcc +++ b/hardware/module/config/component/MGM210P032JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210P032JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210P032JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210P032JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210PA22JIA_config.slcc b/hardware/module/config/component/MGM210PA22JIA_config.slcc index 944dddaf23..93e3197b1a 100644 --- a/hardware/module/config/component/MGM210PA22JIA_config.slcc +++ b/hardware/module/config/component/MGM210PA22JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210PA22JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210PA22JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210PA22JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210PA32JIA_config.slcc b/hardware/module/config/component/MGM210PA32JIA_config.slcc index a9d63d4ad5..71fe79451e 100644 --- a/hardware/module/config/component/MGM210PA32JIA_config.slcc +++ b/hardware/module/config/component/MGM210PA32JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210PA32JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210PA32JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210PA32JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210PB22JIA_config.slcc b/hardware/module/config/component/MGM210PB22JIA_config.slcc index 85d1d54d71..3eb8db6901 100644 --- a/hardware/module/config/component/MGM210PB22JIA_config.slcc +++ b/hardware/module/config/component/MGM210PB22JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210PB22JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210PB22JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210PB22JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM210PB32JIA_config.slcc b/hardware/module/config/component/MGM210PB32JIA_config.slcc index 39a4ac2e3e..5bb61957df 100644 --- a/hardware/module/config/component/MGM210PB32JIA_config.slcc +++ b/hardware/module/config/component/MGM210PB32JIA_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM210PB32JIA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM210PB32JIA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210PB32JIA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM211LA02JNF_config.slcc b/hardware/module/config/component/MGM211LA02JNF_config.slcc index f27c66edd4..e8d9dd3a62 100644 --- a/hardware/module/config/component/MGM211LA02JNF_config.slcc +++ b/hardware/module/config/component/MGM211LA02JNF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM211LA02JNF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM211LA02JNF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM211LA02JNF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM220PC22HNA_config.slcc b/hardware/module/config/component/MGM220PC22HNA_config.slcc index c89c79c338..507a2e35a6 100644 --- a/hardware/module/config/component/MGM220PC22HNA_config.slcc +++ b/hardware/module/config/component/MGM220PC22HNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM220PC22HNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM220PC22HNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM220PC22HNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: device_init_lfxo file_id: device_init_lfxo_config path: MGM220PC22HNA/sl_device_init_lfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240L022RNF_config.slcc b/hardware/module/config/component/MGM240L022RNF_config.slcc index 545ee4d84e..93f19864c8 100644 --- a/hardware/module/config/component/MGM240L022RNF_config.slcc +++ b/hardware/module/config/component/MGM240L022RNF_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240L022RNF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240L022RNF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240L022RNF/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240L022RNF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240L022VIF_config.slcc b/hardware/module/config/component/MGM240L022VIF_config.slcc index d605dbd589..2a8582ab0e 100644 --- a/hardware/module/config/component/MGM240L022VIF_config.slcc +++ b/hardware/module/config/component/MGM240L022VIF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM240L022VIF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240L022VIF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240L022VIF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240L022VNF_config.slcc b/hardware/module/config/component/MGM240L022VNF_config.slcc index 187b924c4a..f967776f19 100644 --- a/hardware/module/config/component/MGM240L022VNF_config.slcc +++ b/hardware/module/config/component/MGM240L022VNF_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240L022VNF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240L022VNF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240L022VNF/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240L022VNF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240LA22UIF_config.slcc b/hardware/module/config/component/MGM240LA22UIF_config.slcc index c42362001f..f6e62bba5d 100644 --- a/hardware/module/config/component/MGM240LA22UIF_config.slcc +++ b/hardware/module/config/component/MGM240LA22UIF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM240LA22UIF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240LA22UIF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240LA22UIF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240LA22VIF_config.slcc b/hardware/module/config/component/MGM240LA22VIF_config.slcc index 8ba71e2105..1fcfdde137 100644 --- a/hardware/module/config/component/MGM240LA22VIF_config.slcc +++ b/hardware/module/config/component/MGM240LA22VIF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM240LA22VIF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240LA22VIF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240LA22VIF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240LD22VIF_config.slcc b/hardware/module/config/component/MGM240LD22VIF_config.slcc index ccefd93bec..2ede08a6d4 100644 --- a/hardware/module/config/component/MGM240LD22VIF_config.slcc +++ b/hardware/module/config/component/MGM240LD22VIF_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: MGM240LD22VIF/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240LD22VIF/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240LD22VIF/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240PA22VNA_config.slcc b/hardware/module/config/component/MGM240PA22VNA_config.slcc index 2281d76c69..23ba7eb0b2 100644 --- a/hardware/module/config/component/MGM240PA22VNA_config.slcc +++ b/hardware/module/config/component/MGM240PA22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240PA22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240PA22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240PA22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240PA22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240PA32VNA_config.slcc b/hardware/module/config/component/MGM240PA32VNA_config.slcc index 2bdc4b25f5..0184c46871 100644 --- a/hardware/module/config/component/MGM240PA32VNA_config.slcc +++ b/hardware/module/config/component/MGM240PA32VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240PA32VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240PA32VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240PA32VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240PA32VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240PA32VNN_config.slcc b/hardware/module/config/component/MGM240PA32VNN_config.slcc index 608eb2ae3c..9987fbb791 100644 --- a/hardware/module/config/component/MGM240PA32VNN_config.slcc +++ b/hardware/module/config/component/MGM240PA32VNN_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240PA32VNN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240PA32VNN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240PA32VNN/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240PA32VNN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240PB22VNA_config.slcc b/hardware/module/config/component/MGM240PB22VNA_config.slcc index 4c7da9d7fe..0101b42b9d 100644 --- a/hardware/module/config/component/MGM240PB22VNA_config.slcc +++ b/hardware/module/config/component/MGM240PB22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240PB22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240PB22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240PB22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240PB22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240PB32VNA_config.slcc b/hardware/module/config/component/MGM240PB32VNA_config.slcc index c15f637f37..669349d9cc 100644 --- a/hardware/module/config/component/MGM240PB32VNA_config.slcc +++ b/hardware/module/config/component/MGM240PB32VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240PB32VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240PB32VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240PB32VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240PB32VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240PB32VNN_config.slcc b/hardware/module/config/component/MGM240PB32VNN_config.slcc index cd11b917d5..061afd7652 100644 --- a/hardware/module/config/component/MGM240PB32VNN_config.slcc +++ b/hardware/module/config/component/MGM240PB32VNN_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240PB32VNN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240PB32VNN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240PB32VNN/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240PB32VNN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240SA22VNA_config.slcc b/hardware/module/config/component/MGM240SA22VNA_config.slcc index 413982b140..37b38417f1 100644 --- a/hardware/module/config/component/MGM240SA22VNA_config.slcc +++ b/hardware/module/config/component/MGM240SA22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240SA22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240SA22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240SA22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240SA22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240SB22VNA_config.slcc b/hardware/module/config/component/MGM240SB22VNA_config.slcc index 99600fd314..69da7fed50 100644 --- a/hardware/module/config/component/MGM240SB22VNA_config.slcc +++ b/hardware/module/config/component/MGM240SB22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240SB22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240SB22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240SB22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240SB22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM240SD22VNA_config.slcc b/hardware/module/config/component/MGM240SD22VNA_config.slcc index 4c51c01c3a..476dedd8c2 100644 --- a/hardware/module/config/component/MGM240SD22VNA_config.slcc +++ b/hardware/module/config/component/MGM240SD22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM240SD22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM240SD22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: MGM240SD22VNA/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM240SD22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM260PB22VNA_config.slcc b/hardware/module/config/component/MGM260PB22VNA_config.slcc index d11d24ed02..7bd3eaa20c 100644 --- a/hardware/module/config/component/MGM260PB22VNA_config.slcc +++ b/hardware/module/config/component/MGM260PB22VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM260PB22VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM260PB22VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dpll file_id: device_init_dpll_config path: MGM260PB22VNA/sl_device_init_dpll_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM260PB22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM260PB32VNA_config.slcc b/hardware/module/config/component/MGM260PB32VNA_config.slcc index eb6a25b60d..0889bfc70e 100644 --- a/hardware/module/config/component/MGM260PB32VNA_config.slcc +++ b/hardware/module/config/component/MGM260PB32VNA_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM260PB32VNA/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM260PB32VNA/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dpll file_id: device_init_dpll_config path: MGM260PB32VNA/sl_device_init_dpll_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM260PB32VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM260PB32VNN_config.slcc b/hardware/module/config/component/MGM260PB32VNN_config.slcc index 5d8f4129fb..683d5a0634 100644 --- a/hardware/module/config/component/MGM260PB32VNN_config.slcc +++ b/hardware/module/config/component/MGM260PB32VNN_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: MGM260PB32VNN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: MGM260PB32VNN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dpll file_id: device_init_dpll_config path: MGM260PB32VNN/sl_device_init_dpll_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: MGM260PB32VNN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/MGM260PD22VNA_config.slcc b/hardware/module/config/component/MGM260PD22VNA_config.slcc new file mode 100644 index 0000000000..28770b301f --- /dev/null +++ b/hardware/module/config/component/MGM260PD22VNA_config.slcc @@ -0,0 +1,51 @@ +!!omap +- id: MGM260PD22VNA_config +- label: MGM260PD22VNA config +- description: Configuration files for MGM260PD22VNA +- package: platform +- category: Platform|Device|MGM26|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/module/config +- requires: + - name: mgm260pd22vna +- provides: + - name: MGM260PD22VNA_config +- config_file: + - override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: MGM260PD22VNA/sl_clock_manager_oscillator_config.h + unless: + - hardware_board + - override: + component: clock_manager + file_id: clock_manager_tree_config + path: MGM260PD22VNA/sl_clock_manager_tree_config.h + unless: + - hardware_board + - override: + component: device_init_dpll + file_id: device_init_dpll_config + path: MGM260PD22VNA/sl_device_init_dpll_config.h + unless: + - hardware_board + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: MGM260PD22VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: MGM260PD22VNA/iot_flash_cfg_msc.h + - override: + component: rail_util_pa + file_id: rail_util_pa_config + path: MGM260PD22VNA/sl_rail_util_pa_config.h diff --git a/hardware/module/config/component/MGM260PD32VNA_config.slcc b/hardware/module/config/component/MGM260PD32VNA_config.slcc new file mode 100644 index 0000000000..e74e788908 --- /dev/null +++ b/hardware/module/config/component/MGM260PD32VNA_config.slcc @@ -0,0 +1,51 @@ +!!omap +- id: MGM260PD32VNA_config +- label: MGM260PD32VNA config +- description: Configuration files for MGM260PD32VNA +- package: platform +- category: Platform|Device|MGM26|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/module/config +- requires: + - name: mgm260pd32vna +- provides: + - name: MGM260PD32VNA_config +- config_file: + - override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: MGM260PD32VNA/sl_clock_manager_oscillator_config.h + unless: + - hardware_board + - override: + component: clock_manager + file_id: clock_manager_tree_config + path: MGM260PD32VNA/sl_clock_manager_tree_config.h + unless: + - hardware_board + - override: + component: device_init_dpll + file_id: device_init_dpll_config + path: MGM260PD32VNA/sl_device_init_dpll_config.h + unless: + - hardware_board + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: MGM260PD32VNA/sl_device_init_hfxo_config.h + unless: + - hardware_board + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: MGM260PD32VNA/iot_flash_cfg_msc.h + - override: + component: rail_util_pa + file_id: rail_util_pa_config + path: MGM260PD32VNA/sl_rail_util_pa_config.h diff --git a/hardware/module/config/component/MGM260PD32VNN_config.slcc b/hardware/module/config/component/MGM260PD32VNN_config.slcc new file mode 100644 index 0000000000..c848fc646c --- /dev/null +++ b/hardware/module/config/component/MGM260PD32VNN_config.slcc @@ -0,0 +1,51 @@ +!!omap +- id: MGM260PD32VNN_config +- label: MGM260PD32VNN config +- description: Configuration files for MGM260PD32VNN +- package: platform +- category: Platform|Device|MGM26|Config +- quality: production +- metadata: + sbom: + license: Zlib +- ui_hints: + visibility: never +- root_path: hardware/module/config +- requires: + - name: mgm260pd32vnn +- provides: + - name: MGM260PD32VNN_config +- config_file: + - override: + component: clock_manager + file_id: clock_manager_oscillator_config + path: MGM260PD32VNN/sl_clock_manager_oscillator_config.h + unless: + - hardware_board + - override: + component: clock_manager + file_id: clock_manager_tree_config + path: MGM260PD32VNN/sl_clock_manager_tree_config.h + unless: + - hardware_board + - override: + component: device_init_dpll + file_id: device_init_dpll_config + path: MGM260PD32VNN/sl_device_init_dpll_config.h + unless: + - hardware_board + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: MGM260PD32VNN/sl_device_init_hfxo_config.h + unless: + - hardware_board + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: MGM260PD32VNN/iot_flash_cfg_msc.h + - override: + component: rail_util_pa + file_id: rail_util_pa_config + path: MGM260PD32VNN/sl_rail_util_pa_config.h diff --git a/hardware/module/config/component/ZGM230SA27HGN_config.slcc b/hardware/module/config/component/ZGM230SA27HGN_config.slcc index 16bbdcdd4c..8f196f211f 100644 --- a/hardware/module/config/component/ZGM230SA27HGN_config.slcc +++ b/hardware/module/config/component/ZGM230SA27HGN_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: ZGM230SA27HGN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: ZGM230SA27HGN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: ZGM230SA27HGN/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: ZGM230SA27HGN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/ZGM230SA27HNN_config.slcc b/hardware/module/config/component/ZGM230SA27HNN_config.slcc index d4d4e215b5..a1ce1c5401 100644 --- a/hardware/module/config/component/ZGM230SA27HNN_config.slcc +++ b/hardware/module/config/component/ZGM230SA27HNN_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: ZGM230SA27HNN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: ZGM230SA27HNN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: ZGM230SA27HNN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/ZGM230SB27HGN_config.slcc b/hardware/module/config/component/ZGM230SB27HGN_config.slcc index 7e82723a9a..6c628ac7ac 100644 --- a/hardware/module/config/component/ZGM230SB27HGN_config.slcc +++ b/hardware/module/config/component/ZGM230SB27HGN_config.slcc @@ -21,21 +21,25 @@ file_id: clock_manager_oscillator_config path: ZGM230SB27HGN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: ZGM230SB27HGN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_dcdc file_id: device_init_dcdc_config path: ZGM230SB27HGN/sl_device_init_dcdc_config.h + unless: + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: ZGM230SB27HGN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/hardware/module/config/component/ZGM230SB27HNN_config.slcc b/hardware/module/config/component/ZGM230SB27HNN_config.slcc index 755a0ba0c7..775657bad6 100644 --- a/hardware/module/config/component/ZGM230SB27HNN_config.slcc +++ b/hardware/module/config/component/ZGM230SB27HNN_config.slcc @@ -21,17 +21,19 @@ file_id: clock_manager_oscillator_config path: ZGM230SB27HNN/sl_clock_manager_oscillator_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: clock_manager file_id: clock_manager_tree_config path: ZGM230SB27HNN/sl_clock_manager_tree_config.h unless: - - board_config_clock_manager + - hardware_board - override: component: device_init_hfxo file_id: device_init_hfxo_config path: ZGM230SB27HNN/sl_device_init_hfxo_config.h + unless: + - hardware_board - override: component: iot_flash file_id: iot_flash_cfg diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h index 2a6085bec9..5fbe6e5f45 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h @@ -4,7 +4,7 @@ * for BGM210LA22JIF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h index 9b030e9fae..7f17658a9e 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h @@ -4,7 +4,7 @@ * for BGM210LA22JNF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h index 825edbe338..35db9abc01 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h @@ -4,7 +4,7 @@ * for BGM210P022JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h index 2c2fd078e9..7eaab4d9fe 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h @@ -4,7 +4,7 @@ * for BGM210P032JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h index 9a4151c5ce..afd581c111 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h @@ -4,7 +4,7 @@ * for BGM210PA22JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h index 1430135a83..870069f81d 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h @@ -4,7 +4,7 @@ * for BGM210PA32JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h index 4f21c04615..8cb1ce375a 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h @@ -4,7 +4,7 @@ * for BGM210PB22JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h index 3029c64844..6bb6a31653 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h @@ -4,7 +4,7 @@ * for BGM210PB32JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h index c5fd93c83d..f70e7db90d 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h @@ -3,7 +3,7 @@ * @brief BGM21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h index 02ca542a85..a4076e0bba 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h @@ -3,7 +3,7 @@ * @brief BGM21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h index b16839d902..9ba5753e04 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h @@ -3,7 +3,7 @@ * @brief BGM21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h index 700b6d0224..acacca57f0 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h @@ -3,7 +3,7 @@ * @brief BGM21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h index 9361f59a62..e3da788760 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h @@ -3,7 +3,7 @@ * @brief BGM21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h index cccb8f51ab..406f3f142e 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h @@ -3,7 +3,7 @@ * @brief BGM21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h index 91752e8aba..e07ca26b8e 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h @@ -3,7 +3,7 @@ * @brief BGM21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h index 7d5f1dc774..2b57898865 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief BGM21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM21_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h index aef2c2fcb0..f436f9ee74 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h @@ -3,7 +3,7 @@ * @brief BGM21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h index 0c93634711..99dce6a209 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h @@ -3,7 +3,7 @@ * @brief BGM21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h index e21f54de82..051c274160 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h @@ -3,7 +3,7 @@ * @brief BGM21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h index 3a41fa5f05..e4f05854ac 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h @@ -3,7 +3,7 @@ * @brief BGM21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h index b60fc24218..fb950aa803 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h @@ -3,7 +3,7 @@ * @brief BGM21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h index 9e1bed449c..4bad655c5a 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h @@ -3,7 +3,7 @@ * @brief BGM21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h index 382a822000..6302b6439c 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h @@ -3,7 +3,7 @@ * @brief BGM21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h index 4fff874978..70ae151d5a 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h @@ -3,7 +3,7 @@ * @brief BGM21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h index a0182b729a..bb1d67156c 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h @@ -3,7 +3,7 @@ * @brief BGM21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h index 6df0b63169..f919d37c07 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h @@ -3,7 +3,7 @@ * @brief BGM21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h index e390d266e8..56b60dfeb4 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h @@ -3,7 +3,7 @@ * @brief BGM21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h index fff55e0c91..32d399d826 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h @@ -3,7 +3,7 @@ * @brief BGM21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h index 568c6775e2..d62473fde5 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief BGM21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h index e87b9b256b..9b5ab800e7 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief BGM21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM21_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h index c5134c40c4..eec1f0c9d7 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h @@ -3,7 +3,7 @@ * @brief BGM21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h index 13d1bc0ceb..3e46b22a47 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h @@ -3,7 +3,7 @@ * @brief BGM21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h index cee931480a..6db5217471 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h @@ -3,7 +3,7 @@ * @brief BGM21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h index c891ec2af3..eee950e44f 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h @@ -3,7 +3,7 @@ * @brief BGM21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h index dab27bcef7..a4f6474a8c 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h @@ -3,7 +3,7 @@ * @brief BGM21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h index ed10e12051..872cd705c6 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h @@ -3,7 +3,7 @@ * @brief BGM21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h index 77535d6a97..53fe226b72 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h @@ -3,16 +3,28 @@ * @brief BGM21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM21_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h index 8d6672a524..1d634400ba 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h @@ -3,7 +3,7 @@ * @brief BGM21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h index b049e0c887..4e27080d9f 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h @@ -3,7 +3,7 @@ * @brief BGM21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h index 5e6a09de3d..ec0c4dc135 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h @@ -3,7 +3,7 @@ * @brief BGM21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h index 2b99916384..0afeba356e 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h @@ -3,7 +3,7 @@ * @brief BGM21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h index 2db072a1fc..334052839f 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h @@ -3,7 +3,7 @@ * @brief BGM21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h index 60384778e5..a25c533bff 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h @@ -3,7 +3,7 @@ * @brief BGM21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h index 454f031b63..8487b8d7c7 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h @@ -3,7 +3,7 @@ * @brief BGM21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h index 3644b32c78..5987aa3c86 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h @@ -3,7 +3,7 @@ * @brief BGM21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/em_device.h b/platform/Device/SiliconLabs/BGM21/Include/em_device.h index f7b2844fc0..13255685f5 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/em_device.h +++ b/platform/Device/SiliconLabs/BGM21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h b/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h index 9e83e3cbd2..774c4a0522 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h +++ b/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for BGM21 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Source/startup_bgm21.c b/platform/Device/SiliconLabs/BGM21/Source/startup_bgm21.c index 93545b492d..7434a99a08 100644 --- a/platform/Device/SiliconLabs/BGM21/Source/startup_bgm21.c +++ b/platform/Device/SiliconLabs/BGM21/Source/startup_bgm21.c @@ -4,17 +4,6 @@ * Device BGM21 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c b/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c index 22c763a0e1..5edabc99b1 100644 --- a/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c +++ b/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for BGM21 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h index a5f71c3426..7986d0dab6 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h @@ -4,7 +4,7 @@ * for BGM220PC22HNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h index cdc79e36dd..9f62248eb0 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h @@ -4,7 +4,7 @@ * for BGM220PC22WGA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h index 734bf44c13..8e50aede2e 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h @@ -4,7 +4,7 @@ * for BGM220SC12WGA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h index 2f4a3306bc..550a70e62e 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h @@ -4,7 +4,7 @@ * for BGM220SC22HNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h index e5ecd8ada8..f2bacdf8e8 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h @@ -4,7 +4,7 @@ * for BGM220SC22WGA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h index c0dce29062..784f8128a7 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h @@ -4,7 +4,7 @@ * for BGM220SC23HNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h index 9486ced35d..55bb821636 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h @@ -3,7 +3,7 @@ * @brief BGM22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h index 69ca317f8b..02a57bb55e 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h @@ -3,7 +3,7 @@ * @brief BGM22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h index 3570aa4787..ebd83fd5c2 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h @@ -3,7 +3,7 @@ * @brief BGM22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h index cdb87bc09c..106f8bfb1a 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h @@ -3,7 +3,7 @@ * @brief BGM22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h index e8fbebf1dc..0cd6eede25 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief BGM22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h index e25447f985..a0d55859a2 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h @@ -3,7 +3,7 @@ * @brief BGM22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h index 2d8c86da26..6bec5deb3a 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h @@ -3,7 +3,7 @@ * @brief BGM22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h index b969f5c118..206e07fb0e 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief BGM22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM22_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h index 5f391f9db8..c999b85874 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h @@ -3,7 +3,7 @@ * @brief BGM22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h index db6819ed20..825dbc6774 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h @@ -3,7 +3,7 @@ * @brief BGM22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h index df433fa843..b6770b425f 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h @@ -3,7 +3,7 @@ * @brief BGM22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h index 19c87c0615..1c8c1baf6c 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h @@ -3,7 +3,7 @@ * @brief BGM22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h index c288f9f1a3..75e3a1734f 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h @@ -3,7 +3,7 @@ * @brief BGM22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h index fe13cfc6be..597f562228 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h @@ -3,7 +3,7 @@ * @brief BGM22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h index d1be2ecc19..8ae28f4aac 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h @@ -3,7 +3,7 @@ * @brief BGM22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h index 599d65d19c..50795ff4f8 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h @@ -3,7 +3,7 @@ * @brief BGM22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h index 59cd4f8fe8..f62c7177e5 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h @@ -3,7 +3,7 @@ * @brief BGM22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h index 8cf7976522..faa533bb7b 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h @@ -3,7 +3,7 @@ * @brief BGM22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h index b5e0b8df83..b77d7a30a9 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h @@ -3,7 +3,7 @@ * @brief BGM22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h index 301e530856..9bb5f23151 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h @@ -3,7 +3,7 @@ * @brief BGM22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h index 73b8bf3a51..518b73f0d2 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h @@ -3,7 +3,7 @@ * @brief BGM22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h index 5b06543154..5fb4d9b197 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief BGM22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h index 74e273f14f..47ffccc284 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief BGM22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM22_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h index 374d96b197..855c4cb7e1 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h @@ -3,7 +3,7 @@ * @brief BGM22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h index b0bacbca41..2c3db725a3 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h @@ -3,7 +3,7 @@ * @brief BGM22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h index b74fd49989..1f831a738e 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h @@ -3,7 +3,7 @@ * @brief BGM22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h index 8bc0ac0c19..6b15b9724d 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h @@ -3,7 +3,7 @@ * @brief BGM22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h index d746ecfc40..f55d480bac 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h @@ -3,7 +3,7 @@ * @brief BGM22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h index 6cbfae1d5b..de4ff2e5d0 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h @@ -3,7 +3,7 @@ * @brief BGM22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h index b885ceae14..0cdc174e9b 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h @@ -3,16 +3,28 @@ * @brief BGM22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM22_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h index c782a1e376..5041d7e98c 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h @@ -3,7 +3,7 @@ * @brief BGM22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h index 51ff26f83b..ab2692af06 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h @@ -3,7 +3,7 @@ * @brief BGM22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h index 51b07a5734..6087b98134 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h @@ -3,7 +3,7 @@ * @brief BGM22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h index 0c0546a993..f94601176d 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h @@ -3,7 +3,7 @@ * @brief BGM22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h index 0150a07df9..ca5710cb26 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h @@ -3,7 +3,7 @@ * @brief BGM22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h index 4623b27477..a939c39e00 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h @@ -3,7 +3,7 @@ * @brief BGM22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h index 95a45a461b..47e7b69aac 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h @@ -3,7 +3,7 @@ * @brief BGM22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/em_device.h b/platform/Device/SiliconLabs/BGM22/Include/em_device.h index 9d72b53e0d..a2620b0f31 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/em_device.h +++ b/platform/Device/SiliconLabs/BGM22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h b/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h index 83d0ebfaf5..f89f1cb6fe 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h +++ b/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for BGM22 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Source/startup_bgm22.c b/platform/Device/SiliconLabs/BGM22/Source/startup_bgm22.c index 81af06ac31..08747ef5b9 100644 --- a/platform/Device/SiliconLabs/BGM22/Source/startup_bgm22.c +++ b/platform/Device/SiliconLabs/BGM22/Source/startup_bgm22.c @@ -4,17 +4,6 @@ * Device BGM22 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c b/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c index 2dc802252e..40e307ab4f 100644 --- a/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c +++ b/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for BGM22 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h index c04bbc9aef..ca93d0dafa 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h @@ -4,7 +4,7 @@ * for BGM240PA22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h index c77c1ad213..9f9cf4d8c2 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h @@ -4,7 +4,7 @@ * for BGM240PA32VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h index 6cac205a3e..6828e93352 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h @@ -4,7 +4,7 @@ * for BGM240PA32VNN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h index aa86e501e0..3f7c2cf34d 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h @@ -4,7 +4,7 @@ * for BGM240PB22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h index 2f4570ab18..bad1e97ed2 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h @@ -4,7 +4,7 @@ * for BGM240PB32VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h index 99d87454e3..3ce4d3eeea 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h @@ -4,7 +4,7 @@ * for BGM240PB32VNN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h index 0080d6e70d..1e64402fc0 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h @@ -4,7 +4,7 @@ * for BGM240SA22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h index 8c059373f3..6c9c058a66 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h @@ -4,7 +4,7 @@ * for BGM240SB22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h index f51061826d..3c16196794 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h @@ -4,7 +4,7 @@ * for BGM241SB22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h index 17aa376703..c3a32f007a 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h @@ -4,7 +4,7 @@ * for BGM241SD22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h index e8d2450ef6..164e84faf1 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h @@ -3,7 +3,7 @@ * @brief BGM24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h index 022fbf1550..e494e969bf 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h @@ -3,7 +3,7 @@ * @brief BGM24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h index 4ff5fd65d2..c182951a3b 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h @@ -3,7 +3,7 @@ * @brief BGM24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h index 5fbbf00fdf..599ffdbae1 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h @@ -3,7 +3,7 @@ * @brief BGM24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h index de43a39a03..80cf8cc46f 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h @@ -3,7 +3,7 @@ * @brief BGM24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h index a0436cfc7f..1938a606bf 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h @@ -3,7 +3,7 @@ * @brief BGM24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h index 010cf1d8dd..620cbf93ca 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h @@ -3,7 +3,7 @@ * @brief BGM24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h index b654e01db2..eb55dafa76 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief BGM24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM24_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h index 071d9206b1..2b826ffd86 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h @@ -3,7 +3,7 @@ * @brief BGM24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h index 0abb4a2258..6db3801a54 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h @@ -3,7 +3,7 @@ * @brief BGM24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h index 799bf8f38f..6da209cf57 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h @@ -3,7 +3,7 @@ * @brief BGM24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h index 9ea460d61f..51cefa9467 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h @@ -3,7 +3,7 @@ * @brief BGM24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h index 5e35f4a7f1..a9e6f3baf7 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h @@ -3,7 +3,7 @@ * @brief BGM24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h index a7f679b08e..03e594d765 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h @@ -3,7 +3,7 @@ * @brief BGM24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h index db37bf260f..9d6b50f8f5 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h @@ -3,7 +3,7 @@ * @brief BGM24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h index 5856fdbcce..a405dddfd8 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h @@ -3,7 +3,7 @@ * @brief BGM24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h index 508ba0df28..bfe32cf377 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h @@ -3,7 +3,7 @@ * @brief BGM24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h index 57f7151c66..3b16e54a40 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h @@ -3,7 +3,7 @@ * @brief BGM24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h index 69e8ec0fca..1e35aa0cf2 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h @@ -3,7 +3,7 @@ * @brief BGM24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h index 452c117dc0..ec0b34e9b0 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h @@ -3,7 +3,7 @@ * @brief BGM24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h index 1e8a12f3c6..b1467181c7 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h @@ -3,7 +3,7 @@ * @brief BGM24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h index 5a5b1ce75f..fe0ef2db02 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h @@ -3,7 +3,7 @@ * @brief BGM24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h index ba8e11d926..14514ef66b 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief BGM24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h index 6e94a6a9bc..17a6e8cad9 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief BGM24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM24_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h index d44a35232e..967b8ecc87 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h @@ -3,7 +3,7 @@ * @brief BGM24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h index 35555cb049..c105f1ccba 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h @@ -3,7 +3,7 @@ * @brief BGM24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h index b25bbd224d..f9bef67a1e 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h @@ -3,7 +3,7 @@ * @brief BGM24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h index 20d926ca7d..f0068fd5d5 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h @@ -3,7 +3,7 @@ * @brief BGM24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h index 6380a30245..0181668992 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h @@ -3,7 +3,7 @@ * @brief BGM24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h index 63c7658b77..73c96e1c0a 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h @@ -3,7 +3,7 @@ * @brief BGM24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h index 3240503ddf..bc49288012 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h @@ -3,7 +3,7 @@ * @brief BGM24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h index 6581549b9f..bff16e9815 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h @@ -3,7 +3,7 @@ * @brief BGM24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h index 105889197d..fa0d9128db 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h @@ -3,7 +3,7 @@ * @brief BGM24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h index 959b096de0..acdad0ad6d 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h @@ -3,16 +3,28 @@ * @brief BGM24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef BGM24_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h index 692d990469..1b6448c2c1 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h @@ -3,7 +3,7 @@ * @brief BGM24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h index 5c15045c90..500c3f13cc 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h @@ -3,7 +3,7 @@ * @brief BGM24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h index a33220a769..dc21214bf1 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h @@ -3,7 +3,7 @@ * @brief BGM24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h index f03fcc3fa0..5bff7657ec 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h @@ -3,7 +3,7 @@ * @brief BGM24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h index 7cd70f6ef3..d5e79479cf 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h @@ -3,7 +3,7 @@ * @brief BGM24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h index 0e1f5e9f54..fa5cb9e499 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h @@ -3,7 +3,7 @@ * @brief BGM24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h index f1e807d3fe..b84dc5bcfd 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h @@ -3,7 +3,7 @@ * @brief BGM24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h index e5b7e588af..e3516048c4 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h @@ -3,7 +3,7 @@ * @brief BGM24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h index b8d26f1cc1..8a807ea7c7 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h @@ -3,7 +3,7 @@ * @brief BGM24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h index f34938d7ed..95e6df2e07 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h @@ -3,7 +3,7 @@ * @brief BGM24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/em_device.h b/platform/Device/SiliconLabs/BGM24/Include/em_device.h index 71ae9d18a1..4f87965d1e 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/em_device.h +++ b/platform/Device/SiliconLabs/BGM24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h b/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h index 388fc891bd..5758ce148a 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h +++ b/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for BGM24 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c b/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c index 62068512a4..d1167b17bb 100644 --- a/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c +++ b/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c @@ -4,17 +4,6 @@ * Device BGM24 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c b/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c index 456c7bffd9..136b6ee20e 100644 --- a/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c +++ b/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for BGM24 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm260pb22vna.h b/platform/Device/SiliconLabs/BGM26/Include/bgm260pb22vna.h new file mode 100644 index 0000000000..fcfc306c1c --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm260pb22vna.h @@ -0,0 +1,2011 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for BGM260PB22VNA + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM260PB22VNA_H +#define BGM260PB22VNA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup BGM260PB22VNA BGM260PB22VNA + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** BGM26 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + TIMER5_IRQn = 9, /*!< 9 EFR32 TIMER5 Interrupt */ + TIMER6_IRQn = 10, /*!< 10 EFR32 TIMER6 Interrupt */ + TIMER7_IRQn = 11, /*!< 11 EFR32 TIMER7 Interrupt */ + TIMER8_IRQn = 12, /*!< 12 EFR32 TIMER8 Interrupt */ + TIMER9_IRQn = 13, /*!< 13 EFR32 TIMER9 Interrupt */ + USART0_RX_IRQn = 14, /*!< 14 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 15, /*!< 15 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 16, /*!< 16 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 17, /*!< 17 EFR32 USART1_TX Interrupt */ + USART2_RX_IRQn = 18, /*!< 18 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 19, /*!< 19 EFR32 USART2_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 22, /*!< 22 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 23, /*!< 23 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 24, /*!< 24 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ + EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ + EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ + ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 32, /*!< 32 EFR32 SYSCFG Interrupt */ + MPAHBRAM0_IRQn = 33, /*!< 33 EFR32 MPAHBRAM0 Interrupt */ + MPAHBRAM1_IRQn = 34, /*!< 34 EFR32 MPAHBRAM1 Interrupt */ + LDMA_IRQn = 35, /*!< 35 EFR32 LDMA Interrupt */ + LFXO_IRQn = 36, /*!< 36 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 37, /*!< 37 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 38, /*!< 38 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 39, /*!< 39 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 40, /*!< 40 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 41, /*!< 41 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + I2C2_IRQn = 43, /*!< 43 EFR32 I2C2 Interrupt */ + I2C3_IRQn = 44, /*!< 44 EFR32 I2C3 Interrupt */ + EMUDG_IRQn = 45, /*!< 45 EFR32 EMUDG Interrupt */ + AGC_IRQn = 46, /*!< 46 EFR32 AGC Interrupt */ + BUFC_IRQn = 47, /*!< 47 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 48, /*!< 48 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 49, /*!< 49 EFR32 FRC Interrupt */ + MODEM_IRQn = 50, /*!< 50 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 51, /*!< 51 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 52, /*!< 52 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 53, /*!< 53 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 54, /*!< 54 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 55, /*!< 55 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 56, /*!< 56 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 57, /*!< 57 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 58, /*!< 58 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 59, /*!< 59 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 60, /*!< 60 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 61, /*!< 61 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 62, /*!< 62 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 63, /*!< 63 EFR32 CMU Interrupt */ + AES_IRQn = 64, /*!< 64 EFR32 AES Interrupt */ + IADC_IRQn = 65, /*!< 65 EFR32 IADC Interrupt */ + MSC_IRQn = 66, /*!< 66 EFR32 MSC Interrupt */ + DPLL0_IRQn = 67, /*!< 67 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 68, /*!< 68 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 69, /*!< 69 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 70, /*!< 70 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 71, /*!< 71 EFR32 SW0 Interrupt */ + SW1_IRQn = 72, /*!< 72 EFR32 SW1 Interrupt */ + SW2_IRQn = 73, /*!< 73 EFR32 SW2 Interrupt */ + SW3_IRQn = 74, /*!< 74 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 75, /*!< 75 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 76, /*!< 76 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 77, /*!< 77 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 78, /*!< 78 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 79, /*!< 79 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 80, /*!< 80 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 81, /*!< 81 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 82, /*!< 82 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 83, /*!< 83 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 84, /*!< 84 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 85, /*!< 85 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 86, /*!< 86 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 87, /*!< 87 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 88, /*!< 88 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 89, /*!< 89 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 90, /*!< 90 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 91, /*!< 91 EFR32 AHB2AHB1 Interrupt */ + LCD_IRQn = 92, /*!< 92 EFR32 LCD Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup BGM260PB22VNA_Core BGM260PB22VNA Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group BGM260PB22VNA_Core */ + +/**************************************************************************//** +* @defgroup BGM260PB22VNA_Part BGM260PB22VNA Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(BGM260PB22VNA) +#define BGM260PB22VNA 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "BGM260PB22VNA" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_MODULE 1 /** Silicon Labs multi-chip module */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_6 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 6 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00320000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0831FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x16UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00320000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0831FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x16UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM0_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM0_RAM0_RAM_MEM base address */ +#define DMEM0_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM0_RAM0_RAM_MEM available address space */ +#define DMEM0_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM0_RAM0_RAM_MEM end address */ +#define DMEM0_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM0_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define DMEM1_RAM0_RAM_MEM_BASE (0x20040000UL) /** DMEM1_RAM0_RAM_MEM base address */ +#define DMEM1_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM1_RAM0_RAM_MEM available address space */ +#define DMEM1_RAM0_RAM_MEM_END (0x2007FFFFUL) /** DMEM1_RAM0_RAM_MEM end address */ +#define DMEM1_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM1_RAM0_RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for BGM260PB22VNA */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00320000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 93 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG20_PORT GPIO_PA_INDEX /**< Port of SEG20.*/ +#define LCD_SEG20_PIN 9U /**< Pin of SEG20.*/ +#define LCD_SEG26_PORT GPIO_PB_INDEX /**< Port of SEG26.*/ +#define LCD_SEG26_PIN 4U /**< Pin of SEG26.*/ +#define LCD_SEG27_PORT GPIO_PB_INDEX /**< Port of SEG27.*/ +#define LCD_SEG27_PIN 5U /**< Pin of SEG27.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 2 /** 2 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 4 /** 4 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 4 /** 4 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 10 /** 10 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 3 /** 3 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_bgm26.h" /* System Header File */ + +/** @} End of group BGM260PB22VNA_Part */ + +/**************************************************************************//** + * @defgroup BGM260PB22VNA_Peripheral_TypeDefs BGM260PB22VNA Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "bgm26_emu.h" +#include "bgm26_cmu.h" +#include "bgm26_burtc.h" +#include "bgm26_hfrco.h" +#include "bgm26_fsrco.h" +#include "bgm26_dpll.h" +#include "bgm26_lfxo.h" +#include "bgm26_lfrco.h" +#include "bgm26_ulfrco.h" +#include "bgm26_keyscan.h" +#include "bgm26_msc.h" +#include "bgm26_icache.h" +#include "bgm26_prs.h" +#include "bgm26_gpio.h" +#include "bgm26_ldma.h" +#include "bgm26_ldmaxbar.h" +#include "bgm26_timer.h" +#include "bgm26_mpahbram.h" +#include "bgm26_syscfg.h" +#include "bgm26_buram.h" +#include "bgm26_gpcrc.h" +#include "bgm26_eusart.h" +#include "bgm26_dcdc.h" +#include "bgm26_mailbox.h" +#include "bgm26_usart.h" +#include "bgm26_sysrtc.h" +#include "bgm26_i2c.h" +#include "bgm26_lcd.h" +#include "bgm26_lcdrf.h" +#include "bgm26_aes.h" +#include "bgm26_smu.h" +#include "bgm26_letimer.h" +#include "bgm26_iadc.h" +#include "bgm26_acmp.h" +#include "bgm26_amuxcp.h" +#include "bgm26_vdac.h" +#include "bgm26_pcnt.h" +#include "bgm26_hfxo.h" +#include "bgm26_wdog.h" +#include "bgm26_semailbox.h" +#include "bgm26_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "bgm26_prs_signals.h" +#include "bgm26_dma_descriptor.h" +#include "bgm26_ldmaxbar_defines.h" + +/** @} End of group BGM260PB22VNA_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup BGM260PB22VNA_Peripheral_Base BGM260PB22VNA Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define BURTC_S_BASE (0x4000C000UL) /* BURTC_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define KEYSCAN_S_BASE (0x4002C000UL) /* KEYSCAN_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define TIMER5_S_BASE (0x4005C000UL) /* TIMER5_S base address */ +#define TIMER6_S_BASE (0x40060000UL) /* TIMER6_S base address */ +#define TIMER7_S_BASE (0x40064000UL) /* TIMER7_S base address */ +#define TIMER8_S_BASE (0x40068000UL) /* TIMER8_S base address */ +#define TIMER9_S_BASE (0x4006C000UL) /* TIMER9_S base address */ +#define DMEM0_S_BASE (0x40074000UL) /* DMEM0_S base address */ +#define DMEM1_S_BASE (0x40078000UL) /* DMEM1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x4007C000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x40080000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40084000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define EUSART1_S_BASE (0x4008C000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x40090000UL) /* EUSART2_S base address */ +#define EUSART3_S_BASE (0x40094000UL) /* EUSART3_S base address */ +#define DCDC_S_BASE (0x40098000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x4009C000UL) /* HOSTMAILBOX_S base address */ +#define USART0_S_BASE (0x400A0000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x400A4000UL) /* USART1_S base address */ +#define USART2_S_BASE (0x400A8000UL) /* USART2_S base address */ +#define SYSRTC0_S_BASE (0x400AC000UL) /* SYSRTC0_S base address */ +#define I2C1_S_BASE (0x400B0000UL) /* I2C1_S base address */ +#define I2C2_S_BASE (0x400B4000UL) /* I2C2_S base address */ +#define I2C3_S_BASE (0x400B8000UL) /* I2C3_S base address */ +#define LCD_S_BASE (0x400BC000UL) /* LCD_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define KEYSCAN_NS_BASE (0x5002C000UL) /* KEYSCAN_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define TIMER5_NS_BASE (0x5005C000UL) /* TIMER5_NS base address */ +#define TIMER6_NS_BASE (0x50060000UL) /* TIMER6_NS base address */ +#define TIMER7_NS_BASE (0x50064000UL) /* TIMER7_NS base address */ +#define TIMER8_NS_BASE (0x50068000UL) /* TIMER8_NS base address */ +#define TIMER9_NS_BASE (0x5006C000UL) /* TIMER9_NS base address */ +#define DMEM0_NS_BASE (0x50074000UL) /* DMEM0_NS base address */ +#define DMEM1_NS_BASE (0x50078000UL) /* DMEM1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x5007C000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x50080000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50084000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define EUSART1_NS_BASE (0x5008C000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x50090000UL) /* EUSART2_NS base address */ +#define EUSART3_NS_BASE (0x50094000UL) /* EUSART3_NS base address */ +#define DCDC_NS_BASE (0x50098000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x5009C000UL) /* HOSTMAILBOX_NS base address */ +#define USART0_NS_BASE (0x500A0000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x500A4000UL) /* USART1_NS base address */ +#define USART2_NS_BASE (0x500A8000UL) /* USART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500AC000UL) /* SYSRTC0_NS base address */ +#define I2C1_NS_BASE (0x500B0000UL) /* I2C1_NS base address */ +#define I2C2_NS_BASE (0x500B4000UL) /* I2C2_NS base address */ +#define I2C3_NS_BASE (0x500B8000UL) /* I2C3_NS base address */ +#define LCD_NS_BASE (0x500BC000UL) /* LCD_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) +#define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ +#else +#define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER5_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) +#define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ +#else +#define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER6_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) +#define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ +#else +#define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER7_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER8_S != 0))) +#define TIMER8_BASE (TIMER8_S_BASE) /* TIMER8 base address */ +#else +#define TIMER8_BASE (TIMER8_NS_BASE) /* TIMER8 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER8_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER9_S != 0))) +#define TIMER9_BASE (TIMER9_S_BASE) /* TIMER9 base address */ +#else +#define TIMER9_BASE (TIMER9_NS_BASE) /* TIMER9 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER9_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM0_S != 0))) +#define DMEM0_BASE (DMEM0_S_BASE) /* DMEM0 base address */ +#else +#define DMEM0_BASE (DMEM0_NS_BASE) /* DMEM0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM1_S != 0))) +#define DMEM1_BASE (DMEM1_S_BASE) /* DMEM1 base address */ +#else +#define DMEM1_BASE (DMEM1_NS_BASE) /* DMEM1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) +#define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ +#else +#define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) +#define USART2_BASE (USART2_S_BASE) /* USART2 base address */ +#else +#define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S) && (SL_TRUSTZONE_PERIPHERAL_I2C2_S != 0))) +#define I2C2_BASE (I2C2_S_BASE) /* I2C2 base address */ +#else +#define I2C2_BASE (I2C2_NS_BASE) /* I2C2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S) && (SL_TRUSTZONE_PERIPHERAL_I2C3_S != 0))) +#define I2C3_BASE (I2C3_S_BASE) /* I2C3 base address */ +#else +#define I2C3_BASE (I2C3_NS_BASE) /* I2C3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group BGM260PB22VNA_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup BGM260PB22VNA_Peripheral_Declaration BGM260PB22VNA Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define TIMER5_S ((TIMER_TypeDef *) TIMER5_S_BASE) /**< TIMER5_S base pointer */ +#define TIMER6_S ((TIMER_TypeDef *) TIMER6_S_BASE) /**< TIMER6_S base pointer */ +#define TIMER7_S ((TIMER_TypeDef *) TIMER7_S_BASE) /**< TIMER7_S base pointer */ +#define TIMER8_S ((TIMER_TypeDef *) TIMER8_S_BASE) /**< TIMER8_S base pointer */ +#define TIMER9_S ((TIMER_TypeDef *) TIMER9_S_BASE) /**< TIMER9_S base pointer */ +#define DMEM0_S ((MPAHBRAM_TypeDef *) DMEM0_S_BASE) /**< DMEM0_S base pointer */ +#define DMEM1_S ((MPAHBRAM_TypeDef *) DMEM1_S_BASE) /**< DMEM1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define EUSART3_S ((EUSART_TypeDef *) EUSART3_S_BASE) /**< EUSART3_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define USART2_S ((USART_TypeDef *) USART2_S_BASE) /**< USART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define I2C2_S ((I2C_TypeDef *) I2C2_S_BASE) /**< I2C2_S base pointer */ +#define I2C3_S ((I2C_TypeDef *) I2C3_S_BASE) /**< I2C3_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define TIMER5_NS ((TIMER_TypeDef *) TIMER5_NS_BASE) /**< TIMER5_NS base pointer */ +#define TIMER6_NS ((TIMER_TypeDef *) TIMER6_NS_BASE) /**< TIMER6_NS base pointer */ +#define TIMER7_NS ((TIMER_TypeDef *) TIMER7_NS_BASE) /**< TIMER7_NS base pointer */ +#define TIMER8_NS ((TIMER_TypeDef *) TIMER8_NS_BASE) /**< TIMER8_NS base pointer */ +#define TIMER9_NS ((TIMER_TypeDef *) TIMER9_NS_BASE) /**< TIMER9_NS base pointer */ +#define DMEM0_NS ((MPAHBRAM_TypeDef *) DMEM0_NS_BASE) /**< DMEM0_NS base pointer */ +#define DMEM1_NS ((MPAHBRAM_TypeDef *) DMEM1_NS_BASE) /**< DMEM1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define EUSART3_NS ((EUSART_TypeDef *) EUSART3_NS_BASE) /**< EUSART3_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define USART2_NS ((USART_TypeDef *) USART2_NS_BASE) /**< USART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define I2C2_NS ((I2C_TypeDef *) I2C2_NS_BASE) /**< I2C2_NS base pointer */ +#define I2C3_NS ((I2C_TypeDef *) I2C3_NS_BASE) /**< I2C3_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define TIMER7 ((TIMER_TypeDef *) TIMER7_BASE) /**< TIMER7 base pointer */ +#define TIMER8 ((TIMER_TypeDef *) TIMER8_BASE) /**< TIMER8 base pointer */ +#define TIMER9 ((TIMER_TypeDef *) TIMER9_BASE) /**< TIMER9 base pointer */ +#define DMEM0 ((MPAHBRAM_TypeDef *) DMEM0_BASE) /**< DMEM0 base pointer */ +#define DMEM1 ((MPAHBRAM_TypeDef *) DMEM1_BASE) /**< DMEM1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define EUSART3 ((EUSART_TypeDef *) EUSART3_BASE) /**< EUSART3 base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) /**< I2C3 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group BGM260PB22VNA_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup BGM260PB22VNA_Peripheral_Parameters BGM260PB22VNA Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x16UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x16UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x1A0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x4UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM0_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM0_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM0_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM0_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM0_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM0_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM0_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM0_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM0_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM0_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM0_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM0_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM0_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM0_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM0_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM0_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM0_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM0_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM0_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM0_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM0_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM0_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM0_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM0_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM0_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM0_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM0_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM0_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM0_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM0_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM0_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM0_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM0_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM0_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM0_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM0_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM0_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM0_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM0_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define DMEM1_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM1_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM1_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM1_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM1_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM1_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM1_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM1_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM1_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM1_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM1_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM1_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM1_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM1_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM1_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM1_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM1_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM1_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM1_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM1_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM1_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM1_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM1_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM1_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM1_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM1_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM1_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM1_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM1_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM1_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM1_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM1_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM1_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM1_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM1_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM1_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM1_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM1_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM1_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x0UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x320000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x320000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x8UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x8UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x8UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x8UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0x10UL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x8UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x8UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x8UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x8UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x10UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x10UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x10UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x10UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x28UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define TIMER5_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER5_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER5_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER5_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER5_NO_DTI 0x0UL /**> */ +#define TIMER6_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER6_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER6_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER6_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER6_NO_DTI 0x0UL /**> */ +#define TIMER7_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER7_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER7_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER7_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER7_NO_DTI 0x0UL /**> */ +#define TIMER8_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER8_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER8_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER8_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER8_NO_DTI 0x0UL /**> */ +#define TIMER9_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER9_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER9_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER9_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER9_NO_DTI 0x0UL /**> */ +#define SYSCFG_CHIP_PARTNUMBER 0x3UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART3_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART3_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define USART2_AUTOTX_REG 0x1UL /**> None */ +#define USART2_AUTOTX_REG_B 0x0UL /**> None */ +#define USART2_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART2_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART2_CLK_PRS 0x1UL /**> None */ +#define USART2_CLK_PRS_B 0x0UL /**> New Param */ +#define USART2_FLOW_CONTROL 0x1UL /**> None */ +#define USART2_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART2_I2S 0x1UL /**> None */ +#define USART2_I2S_B 0x0UL /**> New Param */ +#define USART2_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART2_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_MVDIS_FUNC 0x1UL /**> None */ +#define USART2_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART2_RX_PRS 0x1UL /**> None */ +#define USART2_RX_PRS_B 0x0UL /**> New Param */ +#define USART2_SC_AVAILABLE 0x1UL /**> None */ +#define USART2_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART2_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART2_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART2_TIMER 0x1UL /**> New Param */ +#define USART2_TIMER_B 0x0UL /**> New Param */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C2_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C2_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C3_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C3_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_OCTAPLEX 0x1UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x0UL /**> */ +#define LCD_SEG_NUM 0x28UL /**> None */ +#define LCD_SEGASCOM_SEGSTART 0x24UL /**> */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x44UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x4UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_64 0x4UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : ((n) == 3) ? EUSART3 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : ((ref) == EUSART3) ? 3 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : ((n) == 2) ? I2C2 \ + : ((n) == 3) ? I2C3 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : ((ref) == I2C2) ? 2 \ + : ((ref) == I2C3) ? 3 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : ((n) == 2) ? I2C2_DELAY \ + : ((n) == 3) ? I2C3_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : ((n) == 2) ? I2C2_DELAY_CHAIN_NUM \ + : ((n) == 3) ? I2C3_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : ((n) == 5) ? TIMER5 \ + : ((n) == 6) ? TIMER6 \ + : ((n) == 7) ? TIMER7 \ + : ((n) == 8) ? TIMER8 \ + : ((n) == 9) ? TIMER9 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : ((ref) == TIMER5) ? 5 \ + : ((ref) == TIMER6) ? 6 \ + : ((ref) == TIMER7) ? 7 \ + : ((ref) == TIMER8) ? 8 \ + : ((ref) == TIMER9) ? 9 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : ((n) == 5) ? TIMER5_CC_NUM \ + : ((n) == 6) ? TIMER6_CC_NUM \ + : ((n) == 7) ? TIMER7_CC_NUM \ + : ((n) == 8) ? TIMER8_CC_NUM \ + : ((n) == 9) ? TIMER9_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : ((n) == 5) ? TIMER5_CNTWIDTH \ + : ((n) == 6) ? TIMER6_CNTWIDTH \ + : ((n) == 7) ? TIMER7_CNTWIDTH \ + : ((n) == 8) ? TIMER8_CNTWIDTH \ + : ((n) == 9) ? TIMER9_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : ((n) == 5) ? TIMER5_DTI \ + : ((n) == 6) ? TIMER6_DTI \ + : ((n) == 7) ? TIMER7_DTI \ + : ((n) == 8) ? TIMER8_DTI \ + : ((n) == 9) ? TIMER9_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : ((n) == 5) ? TIMER5_DTI_CC_NUM \ + : ((n) == 6) ? TIMER6_DTI_CC_NUM \ + : ((n) == 7) ? TIMER7_DTI_CC_NUM \ + : ((n) == 8) ? TIMER8_DTI_CC_NUM \ + : ((n) == 9) ? TIMER9_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : ((n) == 5) ? TIMER5_NO_DTI \ + : ((n) == 6) ? TIMER6_NO_DTI \ + : ((n) == 7) ? TIMER7_NO_DTI \ + : ((n) == 8) ? TIMER8_NO_DTI \ + : ((n) == 9) ? TIMER9_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : ((n) == 2) ? USART2 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : ((ref) == USART2) ? 2 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : ((n) == 2) ? USART2_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : ((n) == 2) ? USART2_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : ((n) == 2) ? USART2_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : ((n) == 2) ? USART2_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : ((n) == 2) ? USART2_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : ((n) == 2) ? USART2_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : ((n) == 2) ? USART2_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : ((n) == 2) ? USART2_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : ((n) == 2) ? USART2_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : ((n) == 2) ? USART2_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : ((n) == 2) ? USART2_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : ((n) == 2) ? USART2_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : ((n) == 2) ? USART2_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : ((n) == 2) ? USART2_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : ((n) == 2) ? USART2_TIMER_B \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group BGM260PB22VNA_Peripheral_Parameters */ + +/** @} End of group BGM260PB22VNA */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm260pb32vna.h b/platform/Device/SiliconLabs/BGM26/Include/bgm260pb32vna.h new file mode 100644 index 0000000000..8160ebc81f --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm260pb32vna.h @@ -0,0 +1,2009 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for BGM260PB32VNA + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM260PB32VNA_H +#define BGM260PB32VNA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup BGM260PB32VNA BGM260PB32VNA + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** BGM26 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + TIMER5_IRQn = 9, /*!< 9 EFR32 TIMER5 Interrupt */ + TIMER6_IRQn = 10, /*!< 10 EFR32 TIMER6 Interrupt */ + TIMER7_IRQn = 11, /*!< 11 EFR32 TIMER7 Interrupt */ + TIMER8_IRQn = 12, /*!< 12 EFR32 TIMER8 Interrupt */ + TIMER9_IRQn = 13, /*!< 13 EFR32 TIMER9 Interrupt */ + USART0_RX_IRQn = 14, /*!< 14 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 15, /*!< 15 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 16, /*!< 16 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 17, /*!< 17 EFR32 USART1_TX Interrupt */ + USART2_RX_IRQn = 18, /*!< 18 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 19, /*!< 19 EFR32 USART2_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 22, /*!< 22 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 23, /*!< 23 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 24, /*!< 24 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ + EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ + EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ + ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 32, /*!< 32 EFR32 SYSCFG Interrupt */ + MPAHBRAM0_IRQn = 33, /*!< 33 EFR32 MPAHBRAM0 Interrupt */ + MPAHBRAM1_IRQn = 34, /*!< 34 EFR32 MPAHBRAM1 Interrupt */ + LDMA_IRQn = 35, /*!< 35 EFR32 LDMA Interrupt */ + LFXO_IRQn = 36, /*!< 36 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 37, /*!< 37 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 38, /*!< 38 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 39, /*!< 39 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 40, /*!< 40 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 41, /*!< 41 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + I2C2_IRQn = 43, /*!< 43 EFR32 I2C2 Interrupt */ + I2C3_IRQn = 44, /*!< 44 EFR32 I2C3 Interrupt */ + EMUDG_IRQn = 45, /*!< 45 EFR32 EMUDG Interrupt */ + AGC_IRQn = 46, /*!< 46 EFR32 AGC Interrupt */ + BUFC_IRQn = 47, /*!< 47 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 48, /*!< 48 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 49, /*!< 49 EFR32 FRC Interrupt */ + MODEM_IRQn = 50, /*!< 50 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 51, /*!< 51 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 52, /*!< 52 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 53, /*!< 53 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 54, /*!< 54 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 55, /*!< 55 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 56, /*!< 56 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 57, /*!< 57 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 58, /*!< 58 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 59, /*!< 59 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 60, /*!< 60 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 61, /*!< 61 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 62, /*!< 62 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 63, /*!< 63 EFR32 CMU Interrupt */ + AES_IRQn = 64, /*!< 64 EFR32 AES Interrupt */ + IADC_IRQn = 65, /*!< 65 EFR32 IADC Interrupt */ + MSC_IRQn = 66, /*!< 66 EFR32 MSC Interrupt */ + DPLL0_IRQn = 67, /*!< 67 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 68, /*!< 68 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 69, /*!< 69 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 70, /*!< 70 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 71, /*!< 71 EFR32 SW0 Interrupt */ + SW1_IRQn = 72, /*!< 72 EFR32 SW1 Interrupt */ + SW2_IRQn = 73, /*!< 73 EFR32 SW2 Interrupt */ + SW3_IRQn = 74, /*!< 74 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 75, /*!< 75 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 76, /*!< 76 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 77, /*!< 77 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 78, /*!< 78 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 79, /*!< 79 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 80, /*!< 80 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 81, /*!< 81 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 82, /*!< 82 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 83, /*!< 83 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 84, /*!< 84 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 85, /*!< 85 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 86, /*!< 86 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 87, /*!< 87 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 88, /*!< 88 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 89, /*!< 89 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 90, /*!< 90 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 91, /*!< 91 EFR32 AHB2AHB1 Interrupt */ + LCD_IRQn = 92, /*!< 92 EFR32 LCD Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup BGM260PB32VNA_Core BGM260PB32VNA Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group BGM260PB32VNA_Core */ + +/**************************************************************************//** +* @defgroup BGM260PB32VNA_Part BGM260PB32VNA Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(BGM260PB32VNA) +#define BGM260PB32VNA 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "BGM260PB32VNA" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_MODULE 1 /** Silicon Labs multi-chip module */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_6 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 6 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00320000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0831FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x16UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00320000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0831FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x16UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM0_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM0_RAM0_RAM_MEM base address */ +#define DMEM0_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM0_RAM0_RAM_MEM available address space */ +#define DMEM0_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM0_RAM0_RAM_MEM end address */ +#define DMEM0_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM0_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define DMEM1_RAM0_RAM_MEM_BASE (0x20040000UL) /** DMEM1_RAM0_RAM_MEM base address */ +#define DMEM1_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM1_RAM0_RAM_MEM available address space */ +#define DMEM1_RAM0_RAM_MEM_END (0x2007FFFFUL) /** DMEM1_RAM0_RAM_MEM end address */ +#define DMEM1_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM1_RAM0_RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for BGM260PB32VNA */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00320000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 93 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG20_PORT GPIO_PA_INDEX /**< Port of SEG20.*/ +#define LCD_SEG20_PIN 9U /**< Pin of SEG20.*/ +#define LCD_SEG26_PORT GPIO_PB_INDEX /**< Port of SEG26.*/ +#define LCD_SEG26_PIN 4U /**< Pin of SEG26.*/ +#define LCD_SEG27_PORT GPIO_PB_INDEX /**< Port of SEG27.*/ +#define LCD_SEG27_PIN 5U /**< Pin of SEG27.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 2 /** 2 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 4 /** 4 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 4 /** 4 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 10 /** 10 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 3 /** 3 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_bgm26.h" /* System Header File */ + +/** @} End of group BGM260PB32VNA_Part */ + +/**************************************************************************//** + * @defgroup BGM260PB32VNA_Peripheral_TypeDefs BGM260PB32VNA Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "bgm26_emu.h" +#include "bgm26_cmu.h" +#include "bgm26_burtc.h" +#include "bgm26_hfrco.h" +#include "bgm26_fsrco.h" +#include "bgm26_dpll.h" +#include "bgm26_lfxo.h" +#include "bgm26_lfrco.h" +#include "bgm26_ulfrco.h" +#include "bgm26_keyscan.h" +#include "bgm26_msc.h" +#include "bgm26_icache.h" +#include "bgm26_prs.h" +#include "bgm26_gpio.h" +#include "bgm26_ldma.h" +#include "bgm26_ldmaxbar.h" +#include "bgm26_timer.h" +#include "bgm26_mpahbram.h" +#include "bgm26_syscfg.h" +#include "bgm26_buram.h" +#include "bgm26_gpcrc.h" +#include "bgm26_eusart.h" +#include "bgm26_dcdc.h" +#include "bgm26_mailbox.h" +#include "bgm26_usart.h" +#include "bgm26_sysrtc.h" +#include "bgm26_i2c.h" +#include "bgm26_lcd.h" +#include "bgm26_lcdrf.h" +#include "bgm26_aes.h" +#include "bgm26_smu.h" +#include "bgm26_letimer.h" +#include "bgm26_iadc.h" +#include "bgm26_acmp.h" +#include "bgm26_amuxcp.h" +#include "bgm26_vdac.h" +#include "bgm26_pcnt.h" +#include "bgm26_hfxo.h" +#include "bgm26_wdog.h" +#include "bgm26_semailbox.h" +#include "bgm26_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "bgm26_prs_signals.h" +#include "bgm26_dma_descriptor.h" +#include "bgm26_ldmaxbar_defines.h" + +/** @} End of group BGM260PB32VNA_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup BGM260PB32VNA_Peripheral_Base BGM260PB32VNA Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define BURTC_S_BASE (0x4000C000UL) /* BURTC_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define KEYSCAN_S_BASE (0x4002C000UL) /* KEYSCAN_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define TIMER5_S_BASE (0x4005C000UL) /* TIMER5_S base address */ +#define TIMER6_S_BASE (0x40060000UL) /* TIMER6_S base address */ +#define TIMER7_S_BASE (0x40064000UL) /* TIMER7_S base address */ +#define TIMER8_S_BASE (0x40068000UL) /* TIMER8_S base address */ +#define TIMER9_S_BASE (0x4006C000UL) /* TIMER9_S base address */ +#define DMEM0_S_BASE (0x40074000UL) /* DMEM0_S base address */ +#define DMEM1_S_BASE (0x40078000UL) /* DMEM1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x4007C000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x40080000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40084000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define EUSART1_S_BASE (0x4008C000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x40090000UL) /* EUSART2_S base address */ +#define EUSART3_S_BASE (0x40094000UL) /* EUSART3_S base address */ +#define DCDC_S_BASE (0x40098000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x4009C000UL) /* HOSTMAILBOX_S base address */ +#define USART0_S_BASE (0x400A0000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x400A4000UL) /* USART1_S base address */ +#define USART2_S_BASE (0x400A8000UL) /* USART2_S base address */ +#define SYSRTC0_S_BASE (0x400AC000UL) /* SYSRTC0_S base address */ +#define I2C1_S_BASE (0x400B0000UL) /* I2C1_S base address */ +#define I2C2_S_BASE (0x400B4000UL) /* I2C2_S base address */ +#define I2C3_S_BASE (0x400B8000UL) /* I2C3_S base address */ +#define LCD_S_BASE (0x400BC000UL) /* LCD_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define KEYSCAN_NS_BASE (0x5002C000UL) /* KEYSCAN_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define TIMER5_NS_BASE (0x5005C000UL) /* TIMER5_NS base address */ +#define TIMER6_NS_BASE (0x50060000UL) /* TIMER6_NS base address */ +#define TIMER7_NS_BASE (0x50064000UL) /* TIMER7_NS base address */ +#define TIMER8_NS_BASE (0x50068000UL) /* TIMER8_NS base address */ +#define TIMER9_NS_BASE (0x5006C000UL) /* TIMER9_NS base address */ +#define DMEM0_NS_BASE (0x50074000UL) /* DMEM0_NS base address */ +#define DMEM1_NS_BASE (0x50078000UL) /* DMEM1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x5007C000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x50080000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50084000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define EUSART1_NS_BASE (0x5008C000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x50090000UL) /* EUSART2_NS base address */ +#define EUSART3_NS_BASE (0x50094000UL) /* EUSART3_NS base address */ +#define DCDC_NS_BASE (0x50098000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x5009C000UL) /* HOSTMAILBOX_NS base address */ +#define USART0_NS_BASE (0x500A0000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x500A4000UL) /* USART1_NS base address */ +#define USART2_NS_BASE (0x500A8000UL) /* USART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500AC000UL) /* SYSRTC0_NS base address */ +#define I2C1_NS_BASE (0x500B0000UL) /* I2C1_NS base address */ +#define I2C2_NS_BASE (0x500B4000UL) /* I2C2_NS base address */ +#define I2C3_NS_BASE (0x500B8000UL) /* I2C3_NS base address */ +#define LCD_NS_BASE (0x500BC000UL) /* LCD_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) +#define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ +#else +#define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER5_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) +#define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ +#else +#define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER6_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) +#define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ +#else +#define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER7_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER8_S != 0))) +#define TIMER8_BASE (TIMER8_S_BASE) /* TIMER8 base address */ +#else +#define TIMER8_BASE (TIMER8_NS_BASE) /* TIMER8 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER8_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER9_S != 0))) +#define TIMER9_BASE (TIMER9_S_BASE) /* TIMER9 base address */ +#else +#define TIMER9_BASE (TIMER9_NS_BASE) /* TIMER9 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER9_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM0_S != 0))) +#define DMEM0_BASE (DMEM0_S_BASE) /* DMEM0 base address */ +#else +#define DMEM0_BASE (DMEM0_NS_BASE) /* DMEM0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM1_S != 0))) +#define DMEM1_BASE (DMEM1_S_BASE) /* DMEM1 base address */ +#else +#define DMEM1_BASE (DMEM1_NS_BASE) /* DMEM1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) +#define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ +#else +#define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) +#define USART2_BASE (USART2_S_BASE) /* USART2 base address */ +#else +#define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S) && (SL_TRUSTZONE_PERIPHERAL_I2C2_S != 0))) +#define I2C2_BASE (I2C2_S_BASE) /* I2C2 base address */ +#else +#define I2C2_BASE (I2C2_NS_BASE) /* I2C2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S) && (SL_TRUSTZONE_PERIPHERAL_I2C3_S != 0))) +#define I2C3_BASE (I2C3_S_BASE) /* I2C3 base address */ +#else +#define I2C3_BASE (I2C3_NS_BASE) /* I2C3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group BGM260PB32VNA_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup BGM260PB32VNA_Peripheral_Declaration BGM260PB32VNA Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define TIMER5_S ((TIMER_TypeDef *) TIMER5_S_BASE) /**< TIMER5_S base pointer */ +#define TIMER6_S ((TIMER_TypeDef *) TIMER6_S_BASE) /**< TIMER6_S base pointer */ +#define TIMER7_S ((TIMER_TypeDef *) TIMER7_S_BASE) /**< TIMER7_S base pointer */ +#define TIMER8_S ((TIMER_TypeDef *) TIMER8_S_BASE) /**< TIMER8_S base pointer */ +#define TIMER9_S ((TIMER_TypeDef *) TIMER9_S_BASE) /**< TIMER9_S base pointer */ +#define DMEM0_S ((MPAHBRAM_TypeDef *) DMEM0_S_BASE) /**< DMEM0_S base pointer */ +#define DMEM1_S ((MPAHBRAM_TypeDef *) DMEM1_S_BASE) /**< DMEM1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define EUSART3_S ((EUSART_TypeDef *) EUSART3_S_BASE) /**< EUSART3_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define USART2_S ((USART_TypeDef *) USART2_S_BASE) /**< USART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define I2C2_S ((I2C_TypeDef *) I2C2_S_BASE) /**< I2C2_S base pointer */ +#define I2C3_S ((I2C_TypeDef *) I2C3_S_BASE) /**< I2C3_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define TIMER5_NS ((TIMER_TypeDef *) TIMER5_NS_BASE) /**< TIMER5_NS base pointer */ +#define TIMER6_NS ((TIMER_TypeDef *) TIMER6_NS_BASE) /**< TIMER6_NS base pointer */ +#define TIMER7_NS ((TIMER_TypeDef *) TIMER7_NS_BASE) /**< TIMER7_NS base pointer */ +#define TIMER8_NS ((TIMER_TypeDef *) TIMER8_NS_BASE) /**< TIMER8_NS base pointer */ +#define TIMER9_NS ((TIMER_TypeDef *) TIMER9_NS_BASE) /**< TIMER9_NS base pointer */ +#define DMEM0_NS ((MPAHBRAM_TypeDef *) DMEM0_NS_BASE) /**< DMEM0_NS base pointer */ +#define DMEM1_NS ((MPAHBRAM_TypeDef *) DMEM1_NS_BASE) /**< DMEM1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define EUSART3_NS ((EUSART_TypeDef *) EUSART3_NS_BASE) /**< EUSART3_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define USART2_NS ((USART_TypeDef *) USART2_NS_BASE) /**< USART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define I2C2_NS ((I2C_TypeDef *) I2C2_NS_BASE) /**< I2C2_NS base pointer */ +#define I2C3_NS ((I2C_TypeDef *) I2C3_NS_BASE) /**< I2C3_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define TIMER7 ((TIMER_TypeDef *) TIMER7_BASE) /**< TIMER7 base pointer */ +#define TIMER8 ((TIMER_TypeDef *) TIMER8_BASE) /**< TIMER8 base pointer */ +#define TIMER9 ((TIMER_TypeDef *) TIMER9_BASE) /**< TIMER9 base pointer */ +#define DMEM0 ((MPAHBRAM_TypeDef *) DMEM0_BASE) /**< DMEM0 base pointer */ +#define DMEM1 ((MPAHBRAM_TypeDef *) DMEM1_BASE) /**< DMEM1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define EUSART3 ((EUSART_TypeDef *) EUSART3_BASE) /**< EUSART3 base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) /**< I2C3 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group BGM260PB32VNA_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup BGM260PB32VNA_Peripheral_Parameters BGM260PB32VNA Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x16UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x16UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x1A0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x4UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM0_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM0_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM0_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM0_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM0_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM0_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM0_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM0_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM0_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM0_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM0_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM0_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM0_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM0_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM0_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM0_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM0_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM0_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM0_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM0_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM0_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM0_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM0_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM0_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM0_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM0_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM0_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM0_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM0_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM0_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM0_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM0_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM0_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM0_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM0_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM0_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM0_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM0_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM0_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define DMEM1_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM1_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM1_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM1_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM1_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM1_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM1_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM1_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM1_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM1_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM1_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM1_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM1_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM1_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM1_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM1_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM1_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM1_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM1_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM1_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM1_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM1_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM1_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM1_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM1_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM1_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM1_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM1_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM1_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM1_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM1_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM1_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM1_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM1_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM1_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM1_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM1_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM1_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM1_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x0UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x320000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x320000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x8UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x8UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x8UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x8UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0x10UL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x8UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x8UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x8UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x8UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x10UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x10UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x10UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x10UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x28UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define TIMER5_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER5_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER5_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER5_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER5_NO_DTI 0x0UL /**> */ +#define TIMER6_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER6_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER6_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER6_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER6_NO_DTI 0x0UL /**> */ +#define TIMER7_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER7_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER7_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER7_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER7_NO_DTI 0x0UL /**> */ +#define TIMER8_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER8_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER8_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER8_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER8_NO_DTI 0x0UL /**> */ +#define TIMER9_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER9_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER9_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER9_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER9_NO_DTI 0x0UL /**> */ +#define SYSCFG_CHIP_PARTNUMBER 0x3UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART3_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART3_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define USART2_AUTOTX_REG 0x1UL /**> None */ +#define USART2_AUTOTX_REG_B 0x0UL /**> None */ +#define USART2_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART2_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART2_CLK_PRS 0x1UL /**> None */ +#define USART2_CLK_PRS_B 0x0UL /**> New Param */ +#define USART2_FLOW_CONTROL 0x1UL /**> None */ +#define USART2_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART2_I2S 0x1UL /**> None */ +#define USART2_I2S_B 0x0UL /**> New Param */ +#define USART2_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART2_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_MVDIS_FUNC 0x1UL /**> None */ +#define USART2_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART2_RX_PRS 0x1UL /**> None */ +#define USART2_RX_PRS_B 0x0UL /**> New Param */ +#define USART2_SC_AVAILABLE 0x1UL /**> None */ +#define USART2_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART2_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART2_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART2_TIMER 0x1UL /**> New Param */ +#define USART2_TIMER_B 0x0UL /**> New Param */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C2_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C2_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C3_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C3_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_OCTAPLEX 0x1UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x0UL /**> */ +#define LCD_SEG_NUM 0x28UL /**> None */ +#define LCD_SEGASCOM_SEGSTART 0x24UL /**> */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x44UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x4UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_64 0x4UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : ((n) == 3) ? EUSART3 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : ((ref) == EUSART3) ? 3 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : ((n) == 2) ? I2C2 \ + : ((n) == 3) ? I2C3 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : ((ref) == I2C2) ? 2 \ + : ((ref) == I2C3) ? 3 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : ((n) == 2) ? I2C2_DELAY \ + : ((n) == 3) ? I2C3_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : ((n) == 2) ? I2C2_DELAY_CHAIN_NUM \ + : ((n) == 3) ? I2C3_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : ((n) == 5) ? TIMER5 \ + : ((n) == 6) ? TIMER6 \ + : ((n) == 7) ? TIMER7 \ + : ((n) == 8) ? TIMER8 \ + : ((n) == 9) ? TIMER9 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : ((ref) == TIMER5) ? 5 \ + : ((ref) == TIMER6) ? 6 \ + : ((ref) == TIMER7) ? 7 \ + : ((ref) == TIMER8) ? 8 \ + : ((ref) == TIMER9) ? 9 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : ((n) == 5) ? TIMER5_CC_NUM \ + : ((n) == 6) ? TIMER6_CC_NUM \ + : ((n) == 7) ? TIMER7_CC_NUM \ + : ((n) == 8) ? TIMER8_CC_NUM \ + : ((n) == 9) ? TIMER9_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : ((n) == 5) ? TIMER5_CNTWIDTH \ + : ((n) == 6) ? TIMER6_CNTWIDTH \ + : ((n) == 7) ? TIMER7_CNTWIDTH \ + : ((n) == 8) ? TIMER8_CNTWIDTH \ + : ((n) == 9) ? TIMER9_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : ((n) == 5) ? TIMER5_DTI \ + : ((n) == 6) ? TIMER6_DTI \ + : ((n) == 7) ? TIMER7_DTI \ + : ((n) == 8) ? TIMER8_DTI \ + : ((n) == 9) ? TIMER9_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : ((n) == 5) ? TIMER5_DTI_CC_NUM \ + : ((n) == 6) ? TIMER6_DTI_CC_NUM \ + : ((n) == 7) ? TIMER7_DTI_CC_NUM \ + : ((n) == 8) ? TIMER8_DTI_CC_NUM \ + : ((n) == 9) ? TIMER9_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : ((n) == 5) ? TIMER5_NO_DTI \ + : ((n) == 6) ? TIMER6_NO_DTI \ + : ((n) == 7) ? TIMER7_NO_DTI \ + : ((n) == 8) ? TIMER8_NO_DTI \ + : ((n) == 9) ? TIMER9_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : ((n) == 2) ? USART2 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : ((ref) == USART2) ? 2 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : ((n) == 2) ? USART2_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : ((n) == 2) ? USART2_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : ((n) == 2) ? USART2_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : ((n) == 2) ? USART2_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : ((n) == 2) ? USART2_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : ((n) == 2) ? USART2_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : ((n) == 2) ? USART2_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : ((n) == 2) ? USART2_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : ((n) == 2) ? USART2_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : ((n) == 2) ? USART2_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : ((n) == 2) ? USART2_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : ((n) == 2) ? USART2_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : ((n) == 2) ? USART2_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : ((n) == 2) ? USART2_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : ((n) == 2) ? USART2_TIMER_B \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group BGM260PB32VNA_Peripheral_Parameters */ + +/** @} End of group BGM260PB32VNA */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_acmp.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_acmp.h new file mode 100644 index 0000000000..7fdbe5e2c1 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_acmp.h @@ -0,0 +1,654 @@ +/**************************************************************************//** + * @file + * @brief BGM26 ACMP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_ACMP_H +#define BGM26_ACMP_H +#define ACMP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_ACMP ACMP + * @{ + * @brief BGM26 ACMP Register Declaration. + *****************************************************************************/ + +/** ACMP Register Declaration. */ +typedef struct acmp_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +} ACMP_TypeDef; +/** @} End of group BGM26_ACMP */ + +/**************************************************************************//** + * @addtogroup BGM26_ACMP + * @{ + * @defgroup BGM26_ACMP_BitFields ACMP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ + +/* Bit fields for ACMP EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ + +/* Bit fields for ACMP SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ + +/* Bit fields for ACMP CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 0x00000041UL /**< Mode VDAC0OUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 0x00000043UL /**< Mode VDAC1OUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 << 0) /**< Shifted mode VDAC0OUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 << 0) /**< Shifted mode VDAC1OUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 0x00000040UL /**< Mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 0x00000042UL /**< Mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 << 8) /**< Shifted mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 << 8) /**< Shifted mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ + +/** @} End of group BGM26_ACMP_BitFields */ +/** @} End of group BGM26_ACMP */ +/** @} End of group Parts */ + +#endif // BGM26_ACMP_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_aes.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_aes.h new file mode 100644 index 0000000000..f925e81066 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_aes.h @@ -0,0 +1,453 @@ +/**************************************************************************//** + * @file + * @brief BGM26 AES register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_AES_H +#define BGM26_AES_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_AES AES + * @{ + * @brief BGM26 AES Register Declaration. + *****************************************************************************/ + +/** AES Register Declaration. */ +typedef struct aes_typedef{ + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +} AES_TypeDef; +/** @} End of group BGM26_AES */ + +/**************************************************************************//** + * @addtogroup BGM26_AES + * @{ + * @defgroup BGM26_AES_BitFields AES Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AES FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ + +/* Bit fields for AES FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ + +/* Bit fields for AES FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ + +/* Bit fields for AES PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ + +/* Bit fields for AES PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ + +/* Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ + +/* Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ + +/* Bit fields for AES BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ + +/* Bit fields for AES BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ + +/* Bit fields for AES BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ + +/* Bit fields for AES BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ + +/* Bit fields for AES BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ + +/** @} End of group BGM26_AES_BitFields */ +/** @} End of group BGM26_AES */ +/** @} End of group Parts */ + +#endif // BGM26_AES_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_amuxcp.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_amuxcp.h new file mode 100644 index 0000000000..bd7429a011 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_amuxcp.h @@ -0,0 +1,261 @@ +/**************************************************************************//** + * @file + * @brief BGM26 AMUXCP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_AMUXCP_H +#define BGM26_AMUXCP_H +#define AMUXCP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_AMUXCP AMUXCP + * @{ + * @brief BGM26 AMUXCP Register Declaration. + *****************************************************************************/ + +/** AMUXCP Register Declaration. */ +typedef struct amuxcp_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t TEST; /**< Test */ + __IOM uint32_t TRIM; /**< Trim */ + uint32_t RESERVED1[1018U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t TEST_SET; /**< Test */ + __IOM uint32_t TRIM_SET; /**< Trim */ + uint32_t RESERVED3[1018U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t TEST_CLR; /**< Test */ + __IOM uint32_t TRIM_CLR; /**< Trim */ + uint32_t RESERVED5[1018U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t TEST_TGL; /**< Test */ + __IOM uint32_t TRIM_TGL; /**< Trim */ +} AMUXCP_TypeDef; +/** @} End of group BGM26_AMUXCP */ + +/**************************************************************************//** + * @addtogroup BGM26_AMUXCP + * @{ + * @defgroup BGM26_AMUXCP_BitFields AMUXCP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AMUXCP IPVERSION */ +#define _AMUXCP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_IPVERSION */ +#define AMUXCP_IPVERSION_IPVERSION_DEFAULT (_AMUXCP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_IPVERSION */ + +/* Bit fields for AMUXCP CTRL */ +#define _AMUXCP_CTRL_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_CTRL */ +#define _AMUXCP_CTRL_MASK 0x00000033UL /**< Mask for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCEHP (0x1UL << 0) /**< Force High Power */ +#define _AMUXCP_CTRL_FORCEHP_SHIFT 0 /**< Shift value for AMUXCP_FORCEHP */ +#define _AMUXCP_CTRL_FORCEHP_MASK 0x1UL /**< Bit mask for AMUXCP_FORCEHP */ +#define _AMUXCP_CTRL_FORCEHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCEHP_DEFAULT (_AMUXCP_CTRL_FORCEHP_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCELP (0x1UL << 1) /**< Force Low Power */ +#define _AMUXCP_CTRL_FORCELP_SHIFT 1 /**< Shift value for AMUXCP_FORCELP */ +#define _AMUXCP_CTRL_FORCELP_MASK 0x2UL /**< Bit mask for AMUXCP_FORCELP */ +#define _AMUXCP_CTRL_FORCELP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCELP_DEFAULT (_AMUXCP_CTRL_FORCELP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCERUN (0x1UL << 4) /**< Force run */ +#define _AMUXCP_CTRL_FORCERUN_SHIFT 4 /**< Shift value for AMUXCP_FORCERUN */ +#define _AMUXCP_CTRL_FORCERUN_MASK 0x10UL /**< Bit mask for AMUXCP_FORCERUN */ +#define _AMUXCP_CTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCERUN_DEFAULT (_AMUXCP_CTRL_FORCERUN_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCESTOP (0x1UL << 5) /**< Force stop */ +#define _AMUXCP_CTRL_FORCESTOP_SHIFT 5 /**< Shift value for AMUXCP_FORCESTOP */ +#define _AMUXCP_CTRL_FORCESTOP_MASK 0x20UL /**< Bit mask for AMUXCP_FORCESTOP */ +#define _AMUXCP_CTRL_FORCESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCESTOP_DEFAULT (_AMUXCP_CTRL_FORCESTOP_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ + +/* Bit fields for AMUXCP STATUS */ +#define _AMUXCP_STATUS_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_STATUS */ +#define _AMUXCP_STATUS_MASK 0x00000003UL /**< Mask for AMUXCP_STATUS */ +#define AMUXCP_STATUS_RUN (0x1UL << 0) /**< running */ +#define _AMUXCP_STATUS_RUN_SHIFT 0 /**< Shift value for AMUXCP_RUN */ +#define _AMUXCP_STATUS_RUN_MASK 0x1UL /**< Bit mask for AMUXCP_RUN */ +#define _AMUXCP_STATUS_RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */ +#define AMUXCP_STATUS_RUN_DEFAULT (_AMUXCP_STATUS_RUN_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_STATUS */ +#define AMUXCP_STATUS_HICAP (0x1UL << 1) /**< high cap */ +#define _AMUXCP_STATUS_HICAP_SHIFT 1 /**< Shift value for AMUXCP_HICAP */ +#define _AMUXCP_STATUS_HICAP_MASK 0x2UL /**< Bit mask for AMUXCP_HICAP */ +#define _AMUXCP_STATUS_HICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */ +#define AMUXCP_STATUS_HICAP_DEFAULT (_AMUXCP_STATUS_HICAP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_STATUS */ + +/* Bit fields for AMUXCP TEST */ +#define _AMUXCP_TEST_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_TEST */ +#define _AMUXCP_TEST_MASK 0x80003313UL /**< Mask for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCCLK (0x1UL << 0) /**< Sync Clock */ +#define _AMUXCP_TEST_SYNCCLK_SHIFT 0 /**< Shift value for AMUXCP_SYNCCLK */ +#define _AMUXCP_TEST_SYNCCLK_MASK 0x1UL /**< Bit mask for AMUXCP_SYNCCLK */ +#define _AMUXCP_TEST_SYNCCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCCLK_DEFAULT (_AMUXCP_TEST_SYNCCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCMODE (0x1UL << 1) /**< Sync Mode */ +#define _AMUXCP_TEST_SYNCMODE_SHIFT 1 /**< Shift value for AMUXCP_SYNCMODE */ +#define _AMUXCP_TEST_SYNCMODE_MASK 0x2UL /**< Bit mask for AMUXCP_SYNCMODE */ +#define _AMUXCP_TEST_SYNCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCMODE_DEFAULT (_AMUXCP_TEST_SYNCMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEREQUEST (0x1UL << 4) /**< Force Request */ +#define _AMUXCP_TEST_FORCEREQUEST_SHIFT 4 /**< Shift value for AMUXCP_FORCEREQUEST */ +#define _AMUXCP_TEST_FORCEREQUEST_MASK 0x10UL /**< Bit mask for AMUXCP_FORCEREQUEST */ +#define _AMUXCP_TEST_FORCEREQUEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEREQUEST_DEFAULT (_AMUXCP_TEST_FORCEREQUEST_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEHICAP (0x1UL << 8) /**< Force high capacitance driver */ +#define _AMUXCP_TEST_FORCEHICAP_SHIFT 8 /**< Shift value for AMUXCP_FORCEHICAP */ +#define _AMUXCP_TEST_FORCEHICAP_MASK 0x100UL /**< Bit mask for AMUXCP_FORCEHICAP */ +#define _AMUXCP_TEST_FORCEHICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEHICAP_DEFAULT (_AMUXCP_TEST_FORCEHICAP_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCELOCAP (0x1UL << 9) /**< Force low capacitance driver */ +#define _AMUXCP_TEST_FORCELOCAP_SHIFT 9 /**< Shift value for AMUXCP_FORCELOCAP */ +#define _AMUXCP_TEST_FORCELOCAP_MASK 0x200UL /**< Bit mask for AMUXCP_FORCELOCAP */ +#define _AMUXCP_TEST_FORCELOCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCELOCAP_DEFAULT (_AMUXCP_TEST_FORCELOCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTON (0x1UL << 12) /**< Force Boost On */ +#define _AMUXCP_TEST_FORCEBOOSTON_SHIFT 12 /**< Shift value for AMUXCP_FORCEBOOSTON */ +#define _AMUXCP_TEST_FORCEBOOSTON_MASK 0x1000UL /**< Bit mask for AMUXCP_FORCEBOOSTON */ +#define _AMUXCP_TEST_FORCEBOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTON_DEFAULT (_AMUXCP_TEST_FORCEBOOSTON_DEFAULT << 12) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTOFF (0x1UL << 13) /**< Force Boost Off */ +#define _AMUXCP_TEST_FORCEBOOSTOFF_SHIFT 13 /**< Shift value for AMUXCP_FORCEBOOSTOFF */ +#define _AMUXCP_TEST_FORCEBOOSTOFF_MASK 0x2000UL /**< Bit mask for AMUXCP_FORCEBOOSTOFF */ +#define _AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT (_AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_STATUSEN (0x1UL << 31) /**< Enable write to status bits */ +#define _AMUXCP_TEST_STATUSEN_SHIFT 31 /**< Shift value for AMUXCP_STATUSEN */ +#define _AMUXCP_TEST_STATUSEN_MASK 0x80000000UL /**< Bit mask for AMUXCP_STATUSEN */ +#define _AMUXCP_TEST_STATUSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_STATUSEN_DEFAULT (_AMUXCP_TEST_STATUSEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AMUXCP_TEST */ + +/* Bit fields for AMUXCP TRIM */ +#define _AMUXCP_TRIM_RESETVALUE 0x77E44AB1UL /**< Default value for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_MASK 0x77FFEFFFUL /**< Mask for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_SHIFT 0 /**< Shift value for AMUXCP_WARMUPTIME */ +#define _AMUXCP_TRIM_WARMUPTIME_MASK 0x3UL /**< Bit mask for AMUXCP_WARMUPTIME */ +#define _AMUXCP_TRIM_WARMUPTIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 0x00000000UL /**< Mode WUCYCLES72 for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 0x00000001UL /**< Mode WUCYCLES96 for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 0x00000002UL /**< Mode WUCYCLES128 for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 0x00000003UL /**< Mode WUCYCLES160 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_DEFAULT (_AMUXCP_TRIM_WARMUPTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 << 0) /**< Shifted mode WUCYCLES72 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 << 0) /**< Shifted mode WUCYCLES96 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 << 0) /**< Shifted mode WUCYCLES128 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 << 0) /**< Shifted mode WUCYCLES160 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPLO (0x1UL << 2) /**< Float VDDCP Low Power */ +#define _AMUXCP_TRIM_FLOATVDDCPLO_SHIFT 2 /**< Shift value for AMUXCP_FLOATVDDCPLO */ +#define _AMUXCP_TRIM_FLOATVDDCPLO_MASK 0x4UL /**< Bit mask for AMUXCP_FLOATVDDCPLO */ +#define _AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT << 2) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPHI (0x1UL << 3) /**< Float VDDCP High Power */ +#define _AMUXCP_TRIM_FLOATVDDCPHI_SHIFT 3 /**< Shift value for AMUXCP_FLOATVDDCPHI */ +#define _AMUXCP_TRIM_FLOATVDDCPHI_MASK 0x8UL /**< Bit mask for AMUXCP_FLOATVDDCPHI */ +#define _AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT << 3) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2LO (0x1UL << 4) /**< Bypass Div2 Low Power */ +#define _AMUXCP_TRIM_BYPASSDIV2LO_SHIFT 4 /**< Shift value for AMUXCP_BYPASSDIV2LO */ +#define _AMUXCP_TRIM_BYPASSDIV2LO_MASK 0x10UL /**< Bit mask for AMUXCP_BYPASSDIV2LO */ +#define _AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2HI (0x1UL << 5) /**< Bypass Div2 High Power */ +#define _AMUXCP_TRIM_BYPASSDIV2HI_SHIFT 5 /**< Shift value for AMUXCP_BYPASSDIV2HI */ +#define _AMUXCP_TRIM_BYPASSDIV2HI_MASK 0x20UL /**< Bit mask for AMUXCP_BYPASSDIV2HI */ +#define _AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XLO (0x1UL << 6) /**< Bump 0.5X Low Power */ +#define _AMUXCP_TRIM_BUMP0P5XLO_SHIFT 6 /**< Shift value for AMUXCP_BUMP0P5XLO */ +#define _AMUXCP_TRIM_BUMP0P5XLO_MASK 0x40UL /**< Bit mask for AMUXCP_BUMP0P5XLO */ +#define _AMUXCP_TRIM_BUMP0P5XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XLO_DEFAULT (_AMUXCP_TRIM_BUMP0P5XLO_DEFAULT << 6) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XHI (0x1UL << 7) /**< Bump 0.5X High Power */ +#define _AMUXCP_TRIM_BUMP0P5XHI_SHIFT 7 /**< Shift value for AMUXCP_BUMP0P5XHI */ +#define _AMUXCP_TRIM_BUMP0P5XHI_MASK 0x80UL /**< Bit mask for AMUXCP_BUMP0P5XHI */ +#define _AMUXCP_TRIM_BUMP0P5XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XHI_DEFAULT (_AMUXCP_TRIM_BUMP0P5XHI_DEFAULT << 7) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XLO (0x1UL << 8) /**< Bias 2x Low Power */ +#define _AMUXCP_TRIM_BIAS2XLO_SHIFT 8 /**< Shift value for AMUXCP_BIAS2XLO */ +#define _AMUXCP_TRIM_BIAS2XLO_MASK 0x100UL /**< Bit mask for AMUXCP_BIAS2XLO */ +#define _AMUXCP_TRIM_BIAS2XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XLO_DEFAULT (_AMUXCP_TRIM_BIAS2XLO_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XHI (0x1UL << 9) /**< Bias 2x High Power */ +#define _AMUXCP_TRIM_BIAS2XHI_SHIFT 9 /**< Shift value for AMUXCP_BIAS2XHI */ +#define _AMUXCP_TRIM_BIAS2XHI_MASK 0x200UL /**< Bit mask for AMUXCP_BIAS2XHI */ +#define _AMUXCP_TRIM_BIAS2XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XHI_DEFAULT (_AMUXCP_TRIM_BIAS2XHI_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_VOLTAGECTRLLO_SHIFT 10 /**< Shift value for AMUXCP_VOLTAGECTRLLO */ +#define _AMUXCP_TRIM_VOLTAGECTRLLO_MASK 0xC00UL /**< Bit mask for AMUXCP_VOLTAGECTRLLO */ +#define _AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT << 10) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_VOLTAGECTRLHI_SHIFT 13 /**< Shift value for AMUXCP_VOLTAGECTRLHI */ +#define _AMUXCP_TRIM_VOLTAGECTRLHI_MASK 0x6000UL /**< Bit mask for AMUXCP_VOLTAGECTRLHI */ +#define _AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_BIASCTRLLO_SHIFT 15 /**< Shift value for AMUXCP_BIASCTRLLO */ +#define _AMUXCP_TRIM_BIASCTRLLO_MASK 0x38000UL /**< Bit mask for AMUXCP_BIASCTRLLO */ +#define _AMUXCP_TRIM_BIASCTRLLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIASCTRLLO_DEFAULT (_AMUXCP_TRIM_BIASCTRLLO_DEFAULT << 15) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_BIASCTRLLOCONT_SHIFT 18 /**< Shift value for AMUXCP_BIASCTRLLOCONT */ +#define _AMUXCP_TRIM_BIASCTRLLOCONT_MASK 0x1C0000UL /**< Bit mask for AMUXCP_BIASCTRLLOCONT */ +#define _AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT (_AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT << 18) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_BIASCTRLHI_SHIFT 21 /**< Shift value for AMUXCP_BIASCTRLHI */ +#define _AMUXCP_TRIM_BIASCTRLHI_MASK 0xE00000UL /**< Bit mask for AMUXCP_BIASCTRLHI */ +#define _AMUXCP_TRIM_BIASCTRLHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIASCTRLHI_DEFAULT (_AMUXCP_TRIM_BIASCTRLHI_DEFAULT << 21) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_PUMPCAPLO_SHIFT 24 /**< Shift value for AMUXCP_PUMPCAPLO */ +#define _AMUXCP_TRIM_PUMPCAPLO_MASK 0x7000000UL /**< Bit mask for AMUXCP_PUMPCAPLO */ +#define _AMUXCP_TRIM_PUMPCAPLO_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_PUMPCAPLO_DEFAULT (_AMUXCP_TRIM_PUMPCAPLO_DEFAULT << 24) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_PUMPCAPHI_SHIFT 28 /**< Shift value for AMUXCP_PUMPCAPHI */ +#define _AMUXCP_TRIM_PUMPCAPHI_MASK 0x70000000UL /**< Bit mask for AMUXCP_PUMPCAPHI */ +#define _AMUXCP_TRIM_PUMPCAPHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_PUMPCAPHI_DEFAULT (_AMUXCP_TRIM_PUMPCAPHI_DEFAULT << 28) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ + +/** @} End of group BGM26_AMUXCP_BitFields */ +/** @} End of group BGM26_AMUXCP */ +/** @} End of group Parts */ + +#endif // BGM26_AMUXCP_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_buram.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_buram.h new file mode 100644 index 0000000000..74be4fdfa6 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_buram.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file + * @brief BGM26 BURAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_BURAM_H +#define BGM26_BURAM_H +#define BURAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_BURAM BURAM + * @{ + * @brief BGM26 BURAM Register Declaration. + *****************************************************************************/ + +/** BURAM RET Register Group Declaration. */ +typedef struct buram_ret_typedef{ + __IOM uint32_t REG; /**< Retention Register */ +} BURAM_RET_TypeDef; + +/** BURAM Register Declaration. */ +typedef struct buram_typedef{ + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +} BURAM_TypeDef; +/** @} End of group BGM26_BURAM */ + +/**************************************************************************//** + * @addtogroup BGM26_BURAM + * @{ + * @defgroup BGM26_BURAM_BitFields BURAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURAM RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ + +/** @} End of group BGM26_BURAM_BitFields */ +/** @} End of group BGM26_BURAM */ +/** @} End of group Parts */ + +#endif // BGM26_BURAM_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_burtc.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_burtc.h new file mode 100644 index 0000000000..74b8cb09c3 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_burtc.h @@ -0,0 +1,332 @@ +/**************************************************************************//** + * @file + * @brief BGM26 BURTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_BURTC_H +#define BGM26_BURTC_H +#define BURTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_BURTC BURTC + * @{ + * @brief BGM26 BURTC Register Declaration. + *****************************************************************************/ + +/** BURTC Register Declaration. */ +typedef struct burtc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +} BURTC_TypeDef; +/** @} End of group BGM26_BURTC */ + +/**************************************************************************//** + * @addtogroup BGM26_BURTC + * @{ + * @defgroup BGM26_BURTC_BitFields BURTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURTC IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ + +/* Bit fields for BURTC EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ + +/* Bit fields for BURTC CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ + +/* Bit fields for BURTC CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ + +/* Bit fields for BURTC IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ + +/* Bit fields for BURTC CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ + +/* Bit fields for BURTC SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ + +/** @} End of group BGM26_BURTC_BitFields */ +/** @} End of group BGM26_BURTC */ +/** @} End of group Parts */ + +#endif // BGM26_BURTC_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_cmu.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_cmu.h new file mode 100644 index 0000000000..420a623376 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_cmu.h @@ -0,0 +1,1207 @@ +/**************************************************************************//** + * @file + * @brief BGM26 CMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_CMU_H +#define BGM26_CMU_H +#define CMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_CMU CMU + * @{ + * @brief BGM26 CMU Register Declaration. + *****************************************************************************/ + +/** CMU Register Declaration. */ +typedef struct cmu_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + __IOM uint32_t CLKEN2; /**< Clock Enable Register 1 */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED7[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED11[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED13[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ + uint32_t RESERVED17[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL; /**< LCD Clock Control */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + uint32_t RESERVED21[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL; /**< VDAC1 Clock Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED27[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED28[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + __IOM uint32_t CLKEN2_SET; /**< Clock Enable Register 1 */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED30[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED31[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED32[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED34[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED35[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED36[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED37[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ + uint32_t RESERVED39[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED40[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ + uint32_t RESERVED41[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_SET; /**< LCD Clock Control */ + uint32_t RESERVED42[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_SET; /**< VDAC1 Clock Control */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED49[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED50[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED51[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED52[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + __IOM uint32_t CLKEN2_CLR; /**< Clock Enable Register 1 */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED53[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED54[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED55[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED56[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED57[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED58[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED59[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED60[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED61[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED62[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ + uint32_t RESERVED63[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED64[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ + uint32_t RESERVED65[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_CLR; /**< LCD Clock Control */ + uint32_t RESERVED66[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ + uint32_t RESERVED67[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED68[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + uint32_t RESERVED69[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_CLR; /**< VDAC1 Clock Control */ + uint32_t RESERVED70[1U]; /**< Reserved for future use */ + uint32_t RESERVED71[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED72[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED73[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED74[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED75[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED76[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + __IOM uint32_t CLKEN2_TGL; /**< Clock Enable Register 1 */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED77[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED78[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED79[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED80[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED81[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED82[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED83[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED84[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED85[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED86[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED87[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED88[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ + uint32_t RESERVED89[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_TGL; /**< LCD Clock Control */ + uint32_t RESERVED90[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ + uint32_t RESERVED91[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED92[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + uint32_t RESERVED93[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_TGL; /**< VDAC1 Clock Control */ + uint32_t RESERVED94[1U]; /**< Reserved for future use */ +} CMU_TypeDef; +/** @} End of group BGM26_CMU */ + +/**************************************************************************//** + * @addtogroup BGM26_CMU + * @{ + * @defgroup BGM26_CMU_BitFields CMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFDFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ + +/* Bit fields for CMU CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x7EFFFFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_CLKEN1_LCD_MASK 0x1000UL /**< Bit mask for CMU_LCD */ +#define _CMU_CLKEN1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD_DEFAULT (_CMU_CLKEN1_LCD_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC1 (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC1_SHIFT 29 /**< Shift value for CMU_VDAC1 */ +#define _CMU_CLKEN1_VDAC1_MASK 0x20000000UL /**< Bit mask for CMU_VDAC1 */ +#define _CMU_CLKEN1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC1_DEFAULT (_CMU_CLKEN1_VDAC1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MVP_SHIFT 30 /**< Shift value for CMU_MVP */ +#define _CMU_CLKEN1_MVP_MASK 0x40000000UL /**< Bit mask for CMU_MVP */ +#define _CMU_CLKEN1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP_DEFAULT (_CMU_CLKEN1_MVP_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ + +/* Bit fields for CMU CLKEN2 */ +#define _CMU_CLKEN2_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN2 */ +#define _CMU_CLKEN2_MASK 0x000007FFUL /**< Mask for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER5 (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_TIMER5_SHIFT 0 /**< Shift value for CMU_TIMER5 */ +#define _CMU_CLKEN2_TIMER5_MASK 0x1UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_CLKEN2_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER5_DEFAULT (_CMU_CLKEN2_TIMER5_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER6 (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_TIMER6_SHIFT 1 /**< Shift value for CMU_TIMER6 */ +#define _CMU_CLKEN2_TIMER6_MASK 0x2UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_CLKEN2_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER6_DEFAULT (_CMU_CLKEN2_TIMER6_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER7 (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_TIMER7_SHIFT 2 /**< Shift value for CMU_TIMER7 */ +#define _CMU_CLKEN2_TIMER7_MASK 0x4UL /**< Bit mask for CMU_TIMER7 */ +#define _CMU_CLKEN2_TIMER7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER7_DEFAULT (_CMU_CLKEN2_TIMER7_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER8 (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_TIMER8_SHIFT 3 /**< Shift value for CMU_TIMER8 */ +#define _CMU_CLKEN2_TIMER8_MASK 0x8UL /**< Bit mask for CMU_TIMER8 */ +#define _CMU_CLKEN2_TIMER8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER8_DEFAULT (_CMU_CLKEN2_TIMER8_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER9 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_TIMER9_SHIFT 4 /**< Shift value for CMU_TIMER9 */ +#define _CMU_CLKEN2_TIMER9_MASK 0x10UL /**< Bit mask for CMU_TIMER9 */ +#define _CMU_CLKEN2_TIMER9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_TIMER9_DEFAULT (_CMU_CLKEN2_TIMER9_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_EUSART2 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_EUSART2_SHIFT 5 /**< Shift value for CMU_EUSART2 */ +#define _CMU_CLKEN2_EUSART2_MASK 0x20UL /**< Bit mask for CMU_EUSART2 */ +#define _CMU_CLKEN2_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_EUSART2_DEFAULT (_CMU_CLKEN2_EUSART2_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_EUSART3 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_EUSART3_SHIFT 6 /**< Shift value for CMU_EUSART3 */ +#define _CMU_CLKEN2_EUSART3_MASK 0x40UL /**< Bit mask for CMU_EUSART3 */ +#define _CMU_CLKEN2_EUSART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_EUSART3_DEFAULT (_CMU_CLKEN2_EUSART3_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_USART1 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_USART1_SHIFT 7 /**< Shift value for CMU_USART1 */ +#define _CMU_CLKEN2_USART1_MASK 0x80UL /**< Bit mask for CMU_USART1 */ +#define _CMU_CLKEN2_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_USART1_DEFAULT (_CMU_CLKEN2_USART1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_USART2 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_USART2_SHIFT 8 /**< Shift value for CMU_USART2 */ +#define _CMU_CLKEN2_USART2_MASK 0x100UL /**< Bit mask for CMU_USART2 */ +#define _CMU_CLKEN2_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_USART2_DEFAULT (_CMU_CLKEN2_USART2_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_I2C2 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_I2C2_SHIFT 9 /**< Shift value for CMU_I2C2 */ +#define _CMU_CLKEN2_I2C2_MASK 0x200UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_CLKEN2_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_I2C2_DEFAULT (_CMU_CLKEN2_I2C2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_I2C3 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN2_I2C3_SHIFT 10 /**< Shift value for CMU_I2C3 */ +#define _CMU_CLKEN2_I2C3_MASK 0x400UL /**< Bit mask for CMU_I2C3 */ +#define _CMU_CLKEN2_I2C3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN2 */ +#define CMU_CLKEN2_I2C3_DEFAULT (_CMU_CLKEN2_I2C3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN2 */ + +/* Bit fields for CMU SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ + +/* Bit fields for CMU TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DISABLE 0x00000000UL /**< Mode DISABLE for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000003UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DISABLE (_CMU_TRACECLKCTRL_CLKSEL_DISABLE << 0) /**< Shifted mode DISABLE for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ + +/* Bit fields for CMU EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ + +/* Bit fields for CMU DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ + +/* Bit fields for CMU EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ + +/* Bit fields for CMU EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ + +/* Bit fields for CMU EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ + +/* Bit fields for CMU EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ + +/* Bit fields for CMU IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ + +/* Bit fields for CMU WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ + +/* Bit fields for CMU WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ + +/* Bit fields for CMU EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ + +/* Bit fields for CMU SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ + +/* Bit fields for CMU LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_DEFAULT (_CMU_LCDCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFRCO (_CMU_LCDCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFXO (_CMU_LCDCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_ULFRCO (_CMU_LCDCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LCDCLKCTRL */ + +/* Bit fields for CMU VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ + +/* Bit fields for CMU PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ +#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ + +/* Bit fields for CMU RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ + +/* Bit fields for CMU VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC1CLKCTRL*/ +#define CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC1CLKCTRL*/ +#define CMU_VDAC1CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC1CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ + +/** @} End of group BGM26_CMU_BitFields */ +/** @} End of group BGM26_CMU */ +/** @} End of group Parts */ + +#endif // BGM26_CMU_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_dcdc.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_dcdc.h new file mode 100644 index 0000000000..0103b953fc --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_dcdc.h @@ -0,0 +1,455 @@ +/**************************************************************************//** + * @file + * @brief BGM26 DCDC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_DCDC_H +#define BGM26_DCDC_H +#define DCDC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_DCDC DCDC + * @{ + * @brief BGM26 DCDC Register Declaration. + *****************************************************************************/ + +/** DCDC Register Declaration. */ +typedef struct dcdc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t EM01CTRL0; /**< EM01 Control */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0; /**< EM23 Control */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL; /**< PFMX Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + uint32_t RESERVED6[7U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ + uint32_t RESERVED15[2U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[7U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ + uint32_t RESERVED23[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[7U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[7U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + uint32_t RESERVED32[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ + uint32_t RESERVED34[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ + uint32_t RESERVED37[2U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[7U]; /**< Reserved for future use */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[7U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ +} DCDC_TypeDef; +/** @} End of group BGM26_DCDC */ + +/**************************************************************************//** + * @addtogroup BGM26_DCDC + * @{ + * @defgroup BGM26_DCDC_BitFields DCDC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DCDC IPVERSION */ +#define _DCDC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for DCDC_IPVERSION */ +#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ + +/* Bit fields for DCDC CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ + +/* Bit fields for DCDC EM01CTRL0 */ +#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ + +/* Bit fields for DCDC EM23CTRL0 */ +#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ + +/* Bit fields for DCDC PFMXCTRL */ +#define _DCDC_PFMXCTRL_RESETVALUE 0x00000C0CUL /**< Default value for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD50MA 0x00000003UL /**< Mode LOAD50MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD65MA 0x00000004UL /**< Mode LOAD65MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD73MA 0x00000005UL /**< Mode LOAD73MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD80MA 0x00000006UL /**< Mode LOAD80MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD86MA 0x00000007UL /**< Mode LOAD86MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD93MA 0x00000008UL /**< Mode LOAD93MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD100MA 0x00000009UL /**< Mode LOAD100MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD106MA 0x0000000AUL /**< Mode LOAD106MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD113MA 0x0000000BUL /**< Mode LOAD113MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD120MA 0x0000000CUL /**< Mode LOAD120MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD50MA (_DCDC_PFMXCTRL_IPKVAL_LOAD50MA << 0) /**< Shifted mode LOAD50MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD65MA (_DCDC_PFMXCTRL_IPKVAL_LOAD65MA << 0) /**< Shifted mode LOAD65MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD73MA (_DCDC_PFMXCTRL_IPKVAL_LOAD73MA << 0) /**< Shifted mode LOAD73MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD80MA (_DCDC_PFMXCTRL_IPKVAL_LOAD80MA << 0) /**< Shifted mode LOAD80MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD86MA (_DCDC_PFMXCTRL_IPKVAL_LOAD86MA << 0) /**< Shifted mode LOAD86MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD93MA (_DCDC_PFMXCTRL_IPKVAL_LOAD93MA << 0) /**< Shifted mode LOAD93MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD100MA (_DCDC_PFMXCTRL_IPKVAL_LOAD100MA << 0) /**< Shifted mode LOAD100MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD106MA (_DCDC_PFMXCTRL_IPKVAL_LOAD106MA << 0) /**< Shifted mode LOAD106MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD113MA (_DCDC_PFMXCTRL_IPKVAL_LOAD113MA << 0) /**< Shifted mode LOAD113MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD120MA (_DCDC_PFMXCTRL_IPKVAL_LOAD120MA << 0) /**< Shifted mode LOAD120MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ + +/* Bit fields for DCDC IF */ +#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ +#define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */ +#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ +#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ +#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ +#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */ +#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */ +#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ +#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ +#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ +#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */ +#define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */ + +/* Bit fields for DCDC IEN */ +#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ +#define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */ +#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ +#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ +#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ +#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ +#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ +#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ +#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */ +#define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */ + +/* Bit fields for DCDC STATUS */ +#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ +#define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ +#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ +#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ +#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ +#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ +#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */ +#define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */ + +/* Bit fields for DCDC SYNCBUSY */ +#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */ +#define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ + +/* Bit fields for DCDC LOCK */ +#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ +#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ + +/* Bit fields for DCDC LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ +#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ + +/** @} End of group BGM26_DCDC_BitFields */ +/** @} End of group BGM26_DCDC */ +/** @} End of group Parts */ + +#endif // BGM26_DCDC_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_devinfo.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_devinfo.h new file mode 100644 index 0000000000..3d079e55ab --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_devinfo.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file + * @brief BGM26 DEVINFO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_DEVINFO_H +#define BGM26_DEVINFO_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_DEVINFO DEVINFO + * @{ + * @brief BGM26 DEVINFO Register Declaration. + *****************************************************************************/ + +/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ +typedef struct devinfo_hfrcodpllcal_typedef{ + __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ +} DEVINFO_HFRCODPLLCAL_TypeDef; + +/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ +typedef struct devinfo_hfrcoem23cal_typedef{ + __IM uint32_t HFRCOEM23CAL; /**< HFRCOEM23 Calibration */ +} DEVINFO_HFRCOEM23CAL_TypeDef; + +/** DEVINFO HFRCOSECAL Register Group Declaration. */ +typedef struct devinfo_hfrcosecal_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOSECAL_TypeDef; + +/** DEVINFO Register Declaration. */ +typedef struct devinfo_typedef{ + __IM uint32_t INFO; /**< DI Information */ + __IM uint32_t PART; /**< Part Info */ + __IM uint32_t MEMINFO; /**< Memory Info */ + __IM uint32_t MSIZE; /**< Memory Size */ + __IM uint32_t PKGINFO; /**< Misc Device Info */ + __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ + __IM uint32_t SWFIX; /**< SW Fix Register */ + __IM uint32_t SWCAPA0; /**< Software Restriction */ + __IM uint32_t SWCAPA1; /**< Software Restriction */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t EXTINFO; /**< External Component Info */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t EUI48L; /**< EUI 48 Low */ + __IM uint32_t EUI48H; /**< EUI 48 High */ + __IM uint32_t EUI64L; /**< EUI64 Low */ + __IM uint32_t EUI64H; /**< EUI64 High */ + __IM uint32_t CALTEMP; /**< Calibration temperature */ + __IM uint32_t EMUTEMP; /**< EMU Temp */ + DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ + DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ + DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ + __IM uint32_t MODULENAME0; /**< Module Name Information */ + __IM uint32_t MODULENAME1; /**< Module Name Information */ + __IM uint32_t MODULENAME2; /**< Module Name Information */ + __IM uint32_t MODULENAME3; /**< Module Name Information */ + __IM uint32_t MODULENAME4; /**< Module Name Information */ + __IM uint32_t MODULENAME5; /**< Module Name Information */ + __IM uint32_t MODULENAME6; /**< Module Name Information */ + __IM uint32_t MODULEINFO; /**< Module Information */ + __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ + __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ + __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ + uint32_t RESERVED4[24U]; /**< Reserved for future use */ + __IM uint32_t LEGACY; /**< Legacy Device Info */ + uint32_t RESERVED5[23U]; /**< Reserved for future use */ + __IM uint32_t RTHERM; /**< Thermistor Calibration */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t FENOTCHCAL; /**< FENOTCH Calibration */ + uint32_t RESERVED7[78U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ +} DEVINFO_TypeDef; +/** @} End of group BGM26_DEVINFO */ + +/**************************************************************************//** + * @addtogroup BGM26_DEVINFO + * @{ + * @defgroup BGM26_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x0B000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ +#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ +#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_PG 0x00000005UL /**< Mode PG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_PG (_DEVINFO_PART_FAMILY_PG << 24) /**< Shifted mode PG for DEVINFO_PART */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ + +/* Bit fields for DEVINFO PKGINFO */ +#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ +#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ + +/* Bit fields for DEVINFO SWFIX */ +#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ +#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ + +/* Bit fields for DEVINFO SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_MASK 0x07333333UL /**< Mask for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_SHIFT 24 /**< Shift value for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_MASK 0x7000000UL /**< Bit mask for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL4 0x00000004UL /**< Mode LEVEL4 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_DEFAULT (_DEVINFO_SWCAPA0_ZWAVE_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL0 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL0 << 24) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL1 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL1 << 24) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL2 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL2 << 24) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL3 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL3 << 24) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL4 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL4 << 24) /**< Shifted mode LEVEL4 for DEVINFO_SWCAPA0 */ + +/* Bit fields for DEVINFO SWCAPA1 */ +#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ +#define _DEVINFO_SWCAPA1_MASK 0x0000001FUL /**< Mask for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ +#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ +#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ +#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT (0x1UL << 3) /**< XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_SHIFT 3 /**< Shift value for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_MASK 0x8UL /**< Bit mask for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT_DEFAULT (_DEVINFO_SWCAPA1_XOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_FENOTCH (0x1UL << 4) /**< FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_SHIFT 4 /**< Shift value for DEVINFO_FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_MASK 0x10UL /**< Bit mask for DEVINFO_FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_FENOTCH_DEFAULT (_DEVINFO_SWCAPA1_FENOTCH_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ + +/* Bit fields for DEVINFO EUI64L */ +#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ +#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ + +/* Bit fields for DEVINFO EUI64H */ +#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ + +/* Bit fields for DEVINFO CALTEMP */ +#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ +#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ +#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ + +/* Bit fields for DEVINFO HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ + +/* Bit fields for DEVINFO HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define DEVINFO_HFRCOEM23CAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT (_DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT (_DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT (_DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ + +/* Bit fields for DEVINFO MODULENAME0 */ +#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ + +/* Bit fields for DEVINFO MODULENAME1 */ +#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ + +/* Bit fields for DEVINFO MODULENAME2 */ +#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ + +/* Bit fields for DEVINFO MODULENAME3 */ +#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ + +/* Bit fields for DEVINFO MODULENAME4 */ +#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ + +/* Bit fields for DEVINFO MODULENAME5 */ +#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ + +/* Bit fields for DEVINFO MODULENAME6 */ +#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ +#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ +#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ + +/* Bit fields for DEVINFO IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ + +/* Bit fields for DEVINFO IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ + +/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ + +/* Bit fields for DEVINFO LEGACY */ +#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ + +/* Bit fields for DEVINFO RTHERM */ +#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ +#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ + +/* Bit fields for DEVINFO FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_RESETVALUE 0x000000FFUL /**< Default value for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_SHIFT 0 /**< Shift value for DEVINFO_FENOTCHCAPCRSE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_MASK 0xFUL /**< Bit mask for DEVINFO_FENOTCHCAPCRSE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_SHIFT 4 /**< Shift value for DEVINFO_FENOTCHCAPFINE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_MASK 0xF0UL /**< Bit mask for DEVINFO_FENOTCHCAPFINE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ + +/** @} End of group BGM26_DEVINFO_BitFields */ +/** @} End of group BGM26_DEVINFO */ +/** @} End of group Parts */ + +#endif // BGM26_DEVINFO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_dma_descriptor.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_dma_descriptor.h new file mode 100644 index 0000000000..a84859214e --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_dma_descriptor.h @@ -0,0 +1,59 @@ +/**************************************************************************//** + * @file + * @brief BGM26 DMA descriptor bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_DMA_DESCRIPTOR_H +#define BGM26_DMA_DESCRIPTOR_H + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup DMA_DESCRIPTOR DMA Descriptor + * @{ + *****************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + +#endif // BGM26_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_dpll.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_dpll.h new file mode 100644 index 0000000000..ddf9fad8c8 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_dpll.h @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file + * @brief BGM26 DPLL register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_DPLL_H +#define BGM26_DPLL_H +#define DPLL_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_DPLL DPLL + * @{ + * @brief BGM26 DPLL Register Declaration. + *****************************************************************************/ + +/** DPLL Register Declaration. */ +typedef struct dpll_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ +} DPLL_TypeDef; +/** @} End of group BGM26_DPLL */ + +/**************************************************************************//** + * @addtogroup BGM26_DPLL + * @{ + * @defgroup BGM26_DPLL_BitFields DPLL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DPLL IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ + +/* Bit fields for DPLL EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ + +/* Bit fields for DPLL CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ + +/* Bit fields for DPLL CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ + +/* Bit fields for DPLL IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ + +/* Bit fields for DPLL IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ + +/* Bit fields for DPLL STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ + +/* Bit fields for DPLL LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ + +/** @} End of group BGM26_DPLL_BitFields */ +/** @} End of group BGM26_DPLL */ +/** @} End of group Parts */ + +#endif // BGM26_DPLL_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_emu.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_emu.h new file mode 100644 index 0000000000..3e603a75c2 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_emu.h @@ -0,0 +1,779 @@ +/**************************************************************************//** + * @file + * @brief BGM26 EMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_EMU_H +#define BGM26_EMU_H +#define EMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_EMU EMU + * @{ + * @brief BGM26 EMU Register Declaration. + *****************************************************************************/ + +/** EMU Register Declaration. */ +typedef struct emu_typedef{ + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[6U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[14U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[18U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[924U]; /**< Reserved for future use */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED17[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED22[6U]; /**< Reserved for future use */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED25[14U]; /**< Reserved for future use */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[18U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[924U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED32[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED33[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED37[6U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED40[14U]; /**< Reserved for future use */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + uint32_t RESERVED42[18U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[924U]; /**< Reserved for future use */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED47[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED48[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED49[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED52[6U]; /**< Reserved for future use */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED55[14U]; /**< Reserved for future use */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[18U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ +} EMU_TypeDef; +/** @} End of group BGM26_EMU */ + +/**************************************************************************//** + * @addtogroup BGM26_EMU + * @{ + * @defgroup BGM26_EMU_BitFields EMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ + +/* Bit fields for EMU BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ + +/* Bit fields for EMU VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ + +/* Bit fields for EMU PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ + +/* Bit fields for EMU IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ +#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFFFEFFFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 8) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 8 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x100UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 9) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 9 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x200UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 10) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 10 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x400UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ + +/* Bit fields for EMU RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ +#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ +#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ + +/* Bit fields for EMU TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ + +/* Bit fields for EMU DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ + +/* Bit fields for EMU DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ + +/* Bit fields for EMU EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ + +/* Bit fields for EMU EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ + +/** @} End of group BGM26_EMU_BitFields */ +/** @} End of group BGM26_EMU */ +/** @} End of group Parts */ + +#endif // BGM26_EMU_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_eusart.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_eusart.h new file mode 100644 index 0000000000..97d88cf4ff --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_eusart.h @@ -0,0 +1,1319 @@ +/**************************************************************************//** + * @file + * @brief BGM26 EUSART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_EUSART_H +#define BGM26_EUSART_H +#define EUSART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_EUSART EUSART + * @{ + * @brief BGM26 EUSART Register Declaration. + *****************************************************************************/ + +/** EUSART Register Declaration. */ +typedef struct eusart_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG; /**< DALI Config Register */ + uint32_t RESERVED0[41U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_SET; /**< DALI Config Register */ + uint32_t RESERVED3[41U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_CLR; /**< DALI Config Register */ + uint32_t RESERVED6[41U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_TGL; /**< DALI Config Register */ + uint32_t RESERVED9[41U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} EUSART_TypeDef; +/** @} End of group BGM26_EUSART */ + +/**************************************************************************//** + * @addtogroup BGM26_EUSART + * @{ + * @defgroup BGM26_EUSART_BitFields EUSART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EUSART IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ + +/* Bit fields for EUSART EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ + +/* Bit fields for EUSART CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ + +/* Bit fields for EUSART CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ + +/* Bit fields for EUSART CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ + +/* Bit fields for EUSART FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ + +/* Bit fields for EUSART DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ + +/* Bit fields for EUSART IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ + +/* Bit fields for EUSART IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ + +/* Bit fields for EUSART TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ + +/* Bit fields for EUSART STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ + +/* Bit fields for EUSART SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ + +/* Bit fields for EUSART CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ + +/* Bit fields for EUSART TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ + +/* Bit fields for EUSART CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ + +/* Bit fields for EUSART RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ + +/* Bit fields for EUSART RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ + +/* Bit fields for EUSART TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ + +/* Bit fields for EUSART STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ + +/* Bit fields for EUSART IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ + +/* Bit fields for EUSART IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ + +/* Bit fields for EUSART SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ + +/* Bit fields for EUSART DALICFG */ +#define _EUSART_DALICFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DALICFG */ +#define _EUSART_DALICFG_MASK 0x00009F3FUL /**< Mask for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIEN (0x1UL << 0) /**< DALI Enable Bit */ +#define _EUSART_DALICFG_DALIEN_SHIFT 0 /**< Shift value for EUSART_DALIEN */ +#define _EUSART_DALICFG_DALIEN_MASK 0x1UL /**< Bit mask for EUSART_DALIEN */ +#define _EUSART_DALICFG_DALIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIEN_DEFAULT (_EUSART_DALICFG_DALIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SHIFT 1 /**< Shift value for EUSART_DALITXDATABITS */ +#define _EUSART_DALICFG_DALITXDATABITS_MASK 0x3EUL /**< Bit mask for EUSART_DALITXDATABITS */ +#define _EUSART_DALICFG_DALITXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_DEFAULT (_EUSART_DALICFG_DALITXDATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_EIGHT (_EUSART_DALICFG_DALITXDATABITS_EIGHT << 1) /**< Shifted mode EIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_NINE (_EUSART_DALICFG_DALITXDATABITS_NINE << 1) /**< Shifted mode NINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TEN (_EUSART_DALICFG_DALITXDATABITS_TEN << 1) /**< Shifted mode TEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_ELEVEN (_EUSART_DALICFG_DALITXDATABITS_ELEVEN << 1) /**< Shifted mode ELEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWELVE (_EUSART_DALICFG_DALITXDATABITS_TWELVE << 1) /**< Shifted mode TWELVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTEEN (_EUSART_DALICFG_DALITXDATABITS_THIRTEEN << 1) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_FOURTEEN (_EUSART_DALICFG_DALITXDATABITS_FOURTEEN << 1) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_FIFTEEN (_EUSART_DALICFG_DALITXDATABITS_FIFTEEN << 1) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_SIXTEEN (_EUSART_DALICFG_DALITXDATABITS_SIXTEEN << 1) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALITXDATABITS_SEVENTEEN << 1) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALITXDATABITS_EIGHTEEN << 1) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_NINETEEN (_EUSART_DALICFG_DALITXDATABITS_NINETEEN << 1) /**< Shifted mode NINETEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTY (_EUSART_DALICFG_DALITXDATABITS_TWENTY << 1) /**< Shifted mode TWENTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYONE (_EUSART_DALICFG_DALITXDATABITS_TWENTYONE << 1) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALITXDATABITS_TWENTYTWO << 1) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE << 1) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR << 1) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE << 1) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALITXDATABITS_TWENTYSIX << 1) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN << 1) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT << 1) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALITXDATABITS_TWENTYNINE << 1) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTY (_EUSART_DALICFG_DALITXDATABITS_THIRTY << 1) /**< Shifted mode THIRTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTYONE (_EUSART_DALICFG_DALITXDATABITS_THIRTYONE << 1) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALITXDATABITS_THIRTYTWO << 1) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SHIFT 8 /**< Shift value for EUSART_DALIRXDATABITS */ +#define _EUSART_DALICFG_DALIRXDATABITS_MASK 0x1F00UL /**< Bit mask for EUSART_DALIRXDATABITS */ +#define _EUSART_DALICFG_DALIRXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_DEFAULT (_EUSART_DALICFG_DALIRXDATABITS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_EIGHT (_EUSART_DALICFG_DALIRXDATABITS_EIGHT << 8) /**< Shifted mode EIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_NINE (_EUSART_DALICFG_DALIRXDATABITS_NINE << 8) /**< Shifted mode NINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TEN (_EUSART_DALICFG_DALIRXDATABITS_TEN << 8) /**< Shifted mode TEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_ELEVEN (_EUSART_DALICFG_DALIRXDATABITS_ELEVEN << 8) /**< Shifted mode ELEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWELVE (_EUSART_DALICFG_DALIRXDATABITS_TWELVE << 8) /**< Shifted mode TWELVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTEEN (_EUSART_DALICFG_DALIRXDATABITS_THIRTEEN << 8) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_FOURTEEN (_EUSART_DALICFG_DALIRXDATABITS_FOURTEEN << 8) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_FIFTEEN (_EUSART_DALICFG_DALIRXDATABITS_FIFTEEN << 8) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_SIXTEEN (_EUSART_DALICFG_DALIRXDATABITS_SIXTEEN << 8) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN << 8) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN << 8) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_NINETEEN (_EUSART_DALICFG_DALIRXDATABITS_NINETEEN << 8) /**< Shifted mode NINETEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTY (_EUSART_DALICFG_DALIRXDATABITS_TWENTY << 8) /**< Shifted mode TWENTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYONE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYONE << 8) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO << 8) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE << 8) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR << 8) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE << 8) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX << 8) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN << 8) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT << 8) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE << 8) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTY (_EUSART_DALICFG_DALIRXDATABITS_THIRTY << 8) /**< Shifted mode THIRTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTYONE (_EUSART_DALICFG_DALIRXDATABITS_THIRTYONE << 8) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO << 8) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXENDT (0x1UL << 15) /**< DALI RX Enabled During Transmission */ +#define _EUSART_DALICFG_DALIRXENDT_SHIFT 15 /**< Shift value for EUSART_DALIRXENDT */ +#define _EUSART_DALICFG_DALIRXENDT_MASK 0x8000UL /**< Bit mask for EUSART_DALIRXENDT */ +#define _EUSART_DALICFG_DALIRXENDT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXENDT_DEFAULT (_EUSART_DALICFG_DALIRXENDT_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_DALICFG */ + +/** @} End of group BGM26_EUSART_BitFields */ +/** @} End of group BGM26_EUSART */ +/** @} End of group Parts */ + +#endif // BGM26_EUSART_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_fsrco.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_fsrco.h new file mode 100644 index 0000000000..46ea471026 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_fsrco.h @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file + * @brief BGM26 FSRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_FSRCO_H +#define BGM26_FSRCO_H +#define FSRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_FSRCO FSRCO + * @{ + * @brief BGM26 FSRCO Register Declaration. + *****************************************************************************/ + +/** FSRCO Register Declaration. */ +typedef struct fsrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ +} FSRCO_TypeDef; +/** @} End of group BGM26_FSRCO */ + +/**************************************************************************//** + * @addtogroup BGM26_FSRCO + * @{ + * @defgroup BGM26_FSRCO_BitFields FSRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FSRCO IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ + +/** @} End of group BGM26_FSRCO_BitFields */ +/** @} End of group BGM26_FSRCO */ +/** @} End of group Parts */ + +#endif // BGM26_FSRCO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpcrc.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpcrc.h new file mode 100644 index 0000000000..a219e65cd2 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpcrc.h @@ -0,0 +1,246 @@ +/**************************************************************************//** + * @file + * @brief BGM26 GPCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_GPCRC_H +#define BGM26_GPCRC_H +#define GPCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_GPCRC GPCRC + * @{ + * @brief BGM26 GPCRC Register Declaration. + *****************************************************************************/ + +/** GPCRC Register Declaration. */ +typedef struct gpcrc_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; +/** @} End of group BGM26_GPCRC */ + +/**************************************************************************//** + * @addtogroup BGM26_GPCRC + * @{ + * @defgroup BGM26_GPCRC_BitFields GPCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ + +/* Bit fields for GPCRC EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group BGM26_GPCRC_BitFields */ +/** @} End of group BGM26_GPCRC */ +/** @} End of group Parts */ + +#endif // BGM26_GPCRC_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpio.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpio.h new file mode 100644 index 0000000000..db40c73824 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpio.h @@ -0,0 +1,2818 @@ +/**************************************************************************//** + * @file + * @brief BGM26 GPIO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_GPIO_H +#define BGM26_GPIO_H +#define GPIO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +#include "bgm26_gpio_port.h" + +typedef struct gpio_acmproute_typedef{ + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_ACMPROUTE_TypeDef; + +typedef struct gpio_cmuroute_typedef{ + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ +} GPIO_CMUROUTE_TypeDef; + +typedef struct gpio_eusartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_EUSARTROUTE_TypeDef; + +typedef struct gpio_frcroute_typedef{ + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_FRCROUTE_TypeDef; + +typedef struct gpio_i2croute_typedef{ + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_I2CROUTE_TypeDef; + +typedef struct gpio_keyscanroute_typedef{ + __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ + __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ + __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ + __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ + __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ + __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ + __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ + __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ + __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ + __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ + __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ + __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ + __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ + __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ + __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_KEYSCANROUTE_TypeDef; + +typedef struct gpio_letimerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LETIMERROUTE_TypeDef; + +typedef struct gpio_modemroute_typedef{ + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_MODEMROUTE_TypeDef; + +typedef struct gpio_pcntroute_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ + __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_PCNTROUTE_TypeDef; + +typedef struct gpio_prsroute_typedef{ + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t ASYNCH12ROUTE; /**< ASYNCH12 port/pin select */ + __IOM uint32_t ASYNCH13ROUTE; /**< ASYNCH13 port/pin select */ + __IOM uint32_t ASYNCH14ROUTE; /**< ASYNCH14 port/pin select */ + __IOM uint32_t ASYNCH15ROUTE; /**< ASYNCH15 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PRSROUTE_TypeDef; + +typedef struct gpio_racroute_typedef{ + __IOM uint32_t ROUTEEN; /**< RAC pin enable */ + __IOM uint32_t LNAENROUTE; /**< LNAEN port/pin select */ + __IOM uint32_t PAENROUTE; /**< PAEN port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_RACROUTE_TypeDef; + +typedef struct gpio_syxoroute_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_SYXOROUTE_TypeDef; + +typedef struct gpio_timerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_TIMERROUTE_TypeDef; + +typedef struct gpio_usartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_USARTROUTE_TypeDef; + +typedef struct gpio_typedef{ + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[68U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEGL; /**< LCD Segment Enable Low */ + __IOM uint32_t LCDSEGH; /**< LCD Segment Enable High */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM; /**< LCD Common Enable */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + uint32_t RESERVED4[56U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED7[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED12[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[4U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[4U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keyscan DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE; /**< rac DBUS config registers */ + uint32_t RESERVED13[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[10U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[3U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED14[480U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED15[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED16[68U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEGL_SET; /**< LCD Segment Enable Low */ + __IOM uint32_t LCDSEGH_SET; /**< LCD Segment Enable High */ + uint32_t RESERVED17[2U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_SET; /**< LCD Common Enable */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + uint32_t RESERVED19[56U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED22[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED23[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED27[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[4U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[4U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keyscan DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_SET; /**< rac DBUS config registers */ + uint32_t RESERVED28[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[10U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[3U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED29[480U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED30[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED31[68U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEGL_CLR; /**< LCD Segment Enable Low */ + __IOM uint32_t LCDSEGH_CLR; /**< LCD Segment Enable High */ + uint32_t RESERVED32[2U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_CLR; /**< LCD Common Enable */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + uint32_t RESERVED34[56U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED35[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED37[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED38[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[4U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[4U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keyscan DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_CLR; /**< rac DBUS config registers */ + uint32_t RESERVED43[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[10U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[3U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED44[480U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED45[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED46[68U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEGL_TGL; /**< LCD Segment Enable Low */ + __IOM uint32_t LCDSEGH_TGL; /**< LCD Segment Enable High */ + uint32_t RESERVED47[2U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_TGL; /**< LCD Common Enable */ + uint32_t RESERVED48[3U]; /**< Reserved for future use */ + uint32_t RESERVED49[56U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED50[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED51[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED52[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED53[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED55[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED56[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED57[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[4U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[4U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keyscan DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_TGL; /**< rac DBUS config registers */ + uint32_t RESERVED58[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[10U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[3U]; /**< usart0 DBUS config registers */ +} GPIO_TypeDef; + +/* Bit fields for GPIO IPVERSION */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ + +/* Bit fields for GPIO LCDSEGL */ +#define _GPIO_LCDSEGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDSEGL */ +#define _GPIO_LCDSEGL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_LCDSEGL */ +#define _GPIO_LCDSEGL_LCDSEGALLOC_SHIFT 0 /**< Shift value for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEGL_LCDSEGALLOC_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEGL_LCDSEGALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDSEGL */ +#define GPIO_LCDSEGL_LCDSEGALLOC_DEFAULT (_GPIO_LCDSEGL_LCDSEGALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDSEGL */ + +/* Bit fields for GPIO LCDSEGH */ +#define _GPIO_LCDSEGH_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDSEGH */ +#define _GPIO_LCDSEGH_MASK 0x000000FFUL /**< Mask for GPIO_LCDSEGH */ +#define _GPIO_LCDSEGH_LCDSEGALLOC_SHIFT 0 /**< Shift value for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEGH_LCDSEGALLOC_MASK 0xFFUL /**< Bit mask for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEGH_LCDSEGALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDSEGH */ +#define GPIO_LCDSEGH_LCDSEGALLOC_DEFAULT (_GPIO_LCDSEGH_LCDSEGALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDSEGH */ + +/* Bit fields for GPIO LCDCOM */ +#define _GPIO_LCDCOM_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_MASK 0x0000000FUL /**< Mask for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_LCDCOMALLOC_SHIFT 0 /**< Shift value for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_MASK 0xFUL /**< Bit mask for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDCOM */ +#define GPIO_LCDCOM_LCDCOMALLOC_DEFAULT (_GPIO_LCDCOM_LCDCOMALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDCOM */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/* Bit fields for GPIO GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ + +/* Bit fields for GPIO ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC1CH0 (_GPIO_ABUSALLOC_AODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC1CH1 (_GPIO_ABUSALLOC_AODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ + +/* Bit fields for GPIO BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC1CH0 (_GPIO_BBUSALLOC_BODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC1CH1 (_GPIO_BBUSALLOC_BODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ + +/* Bit fields for GPIO CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_REPEFUSE 0x0000000BUL /**< Mode REPEFUSE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_REPEFUSE (_GPIO_CDBUSALLOC_CDEVEN0_REPEFUSE << 0) /**< Shifted mode REPEFUSE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTA (_GPIO_EXTIPSELH_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTB (_GPIO_EXTIPSELH_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTC (_GPIO_EXTIPSELH_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTD (_GPIO_EXTIPSELH_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTA (_GPIO_EXTIPSELH_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTB (_GPIO_EXTIPSELH_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTC (_GPIO_EXTIPSELH_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTD (_GPIO_EXTIPSELH_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTA (_GPIO_EXTIPSELH_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTB (_GPIO_EXTIPSELH_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTC (_GPIO_EXTIPSELH_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTD (_GPIO_EXTIPSELH_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTA (_GPIO_EXTIPSELH_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTB (_GPIO_EXTIPSELH_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTC (_GPIO_EXTIPSELH_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTD (_GPIO_EXTIPSELH_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 << 16) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 << 16) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 << 16) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 << 16) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 << 20) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 << 20) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 << 20) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 << 20) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 << 24) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 << 24) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 << 24) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 << 24) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 << 28) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 << 28) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 << 28) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 << 28) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFFFFFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF12 (0x1UL << 12) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF12_SHIFT 12 /**< Shift value for GPIO_EXTIF12 */ +#define _GPIO_IF_EXTIF12_MASK 0x1000UL /**< Bit mask for GPIO_EXTIF12 */ +#define _GPIO_IF_EXTIF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF12_DEFAULT (_GPIO_IF_EXTIF12_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF13 (0x1UL << 13) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF13_SHIFT 13 /**< Shift value for GPIO_EXTIF13 */ +#define _GPIO_IF_EXTIF13_MASK 0x2000UL /**< Bit mask for GPIO_EXTIF13 */ +#define _GPIO_IF_EXTIF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF13_DEFAULT (_GPIO_IF_EXTIF13_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF14 (0x1UL << 14) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF14_SHIFT 14 /**< Shift value for GPIO_EXTIF14 */ +#define _GPIO_IF_EXTIF14_MASK 0x4000UL /**< Bit mask for GPIO_EXTIF14 */ +#define _GPIO_IF_EXTIF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF14_DEFAULT (_GPIO_IF_EXTIF14_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF15 (0x1UL << 15) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF15_SHIFT 15 /**< Shift value for GPIO_EXTIF15 */ +#define _GPIO_IF_EXTIF15_MASK 0x8000UL /**< Bit mask for GPIO_EXTIF15 */ +#define _GPIO_IF_EXTIF15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF15_DEFAULT (_GPIO_IF_EXTIF15_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFFFFFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN12 (0x1UL << 12) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN12_SHIFT 12 /**< Shift value for GPIO_EXTIEN12 */ +#define _GPIO_IEN_EXTIEN12_MASK 0x1000UL /**< Bit mask for GPIO_EXTIEN12 */ +#define _GPIO_IEN_EXTIEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN12_DEFAULT (_GPIO_IEN_EXTIEN12_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN13 (0x1UL << 13) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN13_SHIFT 13 /**< Shift value for GPIO_EXTIEN13 */ +#define _GPIO_IEN_EXTIEN13_MASK 0x2000UL /**< Bit mask for GPIO_EXTIEN13 */ +#define _GPIO_IEN_EXTIEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN13_DEFAULT (_GPIO_IEN_EXTIEN13_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN14 (0x1UL << 14) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN14_SHIFT 14 /**< Shift value for GPIO_EXTIEN14 */ +#define _GPIO_IEN_EXTIEN14_MASK 0x4000UL /**< Bit mask for GPIO_EXTIEN14 */ +#define _GPIO_IEN_EXTIEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN14_DEFAULT (_GPIO_IEN_EXTIEN14_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN15 (0x1UL << 15) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN15_SHIFT 15 /**< Shift value for GPIO_EXTIEN15 */ +#define _GPIO_IEN_EXTIEN15_MASK 0x8000UL /**< Bit mask for GPIO_EXTIEN15 */ +#define _GPIO_IEN_EXTIEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN15_DEFAULT (_GPIO_IEN_EXTIEN15_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ + +/* Bit fields for GPIO DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ + +/* Bit fields for GPIO TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ + +/* Bit fields for GPIO_ACMP ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ + +/* Bit fields for GPIO_ACMP ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ + +/* Bit fields for GPIO_CMU ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ + +/* Bit fields for GPIO_CMU CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ + +/* Bit fields for GPIO_EUSART ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ + +/* Bit fields for GPIO_EUSART CSROUTE */ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ + +/* Bit fields for GPIO_EUSART CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ + +/* Bit fields for GPIO_EUSART RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ + +/* Bit fields for GPIO_EUSART RXROUTE */ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ + +/* Bit fields for GPIO_EUSART SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ + +/* Bit fields for GPIO_EUSART TXROUTE */ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ + +/* Bit fields for GPIO_FRC ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ + +/* Bit fields for GPIO_FRC DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ + +/* Bit fields for GPIO_FRC DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ + +/* Bit fields for GPIO_FRC DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ + +/* Bit fields for GPIO_I2C ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ + +/* Bit fields for GPIO_I2C SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ + +/* Bit fields for GPIO_I2C SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ + +/* Bit fields for GPIO_KEYSCAN ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ + +/* Bit fields for GPIO_LETIMER ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ + +/* Bit fields for GPIO_LETIMER OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ + +/* Bit fields for GPIO_LETIMER OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ + +/* Bit fields for GPIO_MODEM ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ + +/* Bit fields for GPIO_MODEM DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ + +/* Bit fields for GPIO_MODEM DINROUTE */ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ + +/* Bit fields for GPIO_MODEM DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ + +/* Bit fields for GPIO_PCNT S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ + +/* Bit fields for GPIO_PCNT S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ + +/* Bit fields for GPIO_PRS ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x000FFFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH12PEN (0x1UL << 12) /**< ASYNCH12 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_SHIFT 12 /**< Shift value for GPIO_ASYNCH12PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_MASK 0x1000UL /**< Bit mask for GPIO_ASYNCH12PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH13PEN (0x1UL << 13) /**< ASYNCH13 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_SHIFT 13 /**< Shift value for GPIO_ASYNCH13PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_MASK 0x2000UL /**< Bit mask for GPIO_ASYNCH13PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH14PEN (0x1UL << 14) /**< ASYNCH14 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_SHIFT 14 /**< Shift value for GPIO_ASYNCH14PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_MASK 0x4000UL /**< Bit mask for GPIO_ASYNCH14PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH15PEN (0x1UL << 15) /**< ASYNCH15 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_SHIFT 15 /**< Shift value for GPIO_ASYNCH15PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_MASK 0x8000UL /**< Bit mask for GPIO_ASYNCH15PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 16) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 16 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x10000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 17) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 17 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x20000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 18) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 18 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x40000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 19) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 19 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x80000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ + +/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ +#define GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ +#define GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ +#define GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ +#define GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ +#define GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ +#define GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ +#define GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ +#define GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ + +/* Bit fields for GPIO_RAC ROUTEEN */ +#define _GPIO_RAC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_ROUTEEN */ +#define _GPIO_RAC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_LNAENPEN (0x1UL << 0) /**< LNAEN pin enable control bit */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_SHIFT 0 /**< Shift value for GPIO_LNAENPEN */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_MASK 0x1UL /**< Bit mask for GPIO_LNAENPEN */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_PAENPEN (0x1UL << 1) /**< PAEN pin enable control bit */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_SHIFT 1 /**< Shift value for GPIO_PAENPEN */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_MASK 0x2UL /**< Bit mask for GPIO_PAENPEN */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ + +/* Bit fields for GPIO_RAC LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_RAC_LNAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_RAC_LNAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ +#define GPIO_RAC_LNAENROUTE_PORT_DEFAULT (_GPIO_RAC_LNAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ +#define _GPIO_RAC_LNAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_RAC_LNAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_RAC_LNAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ +#define GPIO_RAC_LNAENROUTE_PIN_DEFAULT (_GPIO_RAC_LNAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ + +/* Bit fields for GPIO_RAC PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_RAC_PAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_RAC_PAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define GPIO_RAC_PAENROUTE_PORT_DEFAULT (_GPIO_RAC_PAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_RAC_PAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_RAC_PAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define GPIO_RAC_PAENROUTE_PIN_DEFAULT (_GPIO_RAC_PAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ + +/* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ + +/* Bit fields for GPIO_TIMER ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ + +/* Bit fields for GPIO_TIMER CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ + +/* Bit fields for GPIO_TIMER CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ + +/* Bit fields for GPIO_TIMER CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ + +/* Bit fields for GPIO_USART ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ + +/* Bit fields for GPIO_USART CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ + +/* Bit fields for GPIO_USART CTSROUTE */ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ + +/* Bit fields for GPIO_USART RTSROUTE */ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ + +/* Bit fields for GPIO_USART RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ + +/* Bit fields for GPIO_USART CLKROUTE */ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ + +/* Bit fields for GPIO_USART TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +/** @} End of group Parts */ + +#endif // BGM26_GPIO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpio_port.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpio_port.h new file mode 100644 index 0000000000..a913441c88 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_gpio_port.h @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file + * @brief BGM26 GPIO Port register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef GPIO_PORT_H +#define GPIO_PORT_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief BGM26 GPIO PORT + *****************************************************************************/ +typedef struct gpio_port_typedef{ + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ +} GPIO_PORT_TypeDef; + +/* Bit fields for GPIO_P CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO_P MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ + +/* Bit fields for GPIO_P MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_DEFAULT (_GPIO_P_MODEH_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_DISABLED (_GPIO_P_MODEH_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUT (_GPIO_P_MODEH_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULL (_GPIO_P_MODEH_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULLFILTER (_GPIO_P_MODEH_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_PUSHPULL (_GPIO_P_MODEH_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_PUSHPULLALT (_GPIO_P_MODEH_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDOR (_GPIO_P_MODEH_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDAND (_GPIO_P_MODEH_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDFILTER (_GPIO_P_MODEH_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALT (_GPIO_P_MODEH_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEH_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEH_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_DEFAULT (_GPIO_P_MODEH_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_DISABLED (_GPIO_P_MODEH_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_INPUT (_GPIO_P_MODEH_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_INPUTPULL (_GPIO_P_MODEH_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_INPUTPULLFILTER (_GPIO_P_MODEH_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_PUSHPULL (_GPIO_P_MODEH_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_PUSHPULLALT (_GPIO_P_MODEH_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDOR (_GPIO_P_MODEH_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDAND (_GPIO_P_MODEH_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDANDFILTER (_GPIO_P_MODEH_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDPULLUP (_GPIO_P_MODEH_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDALT (_GPIO_P_MODEH_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEH_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEH_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_DEFAULT (_GPIO_P_MODEH_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_DISABLED (_GPIO_P_MODEH_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_INPUT (_GPIO_P_MODEH_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_INPUTPULL (_GPIO_P_MODEH_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_INPUTPULLFILTER (_GPIO_P_MODEH_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_PUSHPULL (_GPIO_P_MODEH_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_PUSHPULLALT (_GPIO_P_MODEH_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDOR (_GPIO_P_MODEH_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDAND (_GPIO_P_MODEH_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDANDFILTER (_GPIO_P_MODEH_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDPULLUP (_GPIO_P_MODEH_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDALT (_GPIO_P_MODEH_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEH_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEH_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_DEFAULT (_GPIO_P_MODEH_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_DISABLED (_GPIO_P_MODEH_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_INPUT (_GPIO_P_MODEH_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_INPUTPULL (_GPIO_P_MODEH_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_INPUTPULLFILTER (_GPIO_P_MODEH_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_PUSHPULL (_GPIO_P_MODEH_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_PUSHPULLALT (_GPIO_P_MODEH_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDOR (_GPIO_P_MODEH_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDAND (_GPIO_P_MODEH_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDANDFILTER (_GPIO_P_MODEH_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDPULLUP (_GPIO_P_MODEH_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDALT (_GPIO_P_MODEH_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEH_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEH_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_DEFAULT (_GPIO_P_MODEH_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_DISABLED (_GPIO_P_MODEH_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_INPUT (_GPIO_P_MODEH_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_INPUTPULL (_GPIO_P_MODEH_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_INPUTPULLFILTER (_GPIO_P_MODEH_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_PUSHPULL (_GPIO_P_MODEH_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_PUSHPULLALT (_GPIO_P_MODEH_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDOR (_GPIO_P_MODEH_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDAND (_GPIO_P_MODEH_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDANDFILTER (_GPIO_P_MODEH_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDPULLUP (_GPIO_P_MODEH_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDALT (_GPIO_P_MODEH_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEH_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEH_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_DEFAULT (_GPIO_P_MODEH_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_DISABLED (_GPIO_P_MODEH_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_INPUT (_GPIO_P_MODEH_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_INPUTPULL (_GPIO_P_MODEH_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_INPUTPULLFILTER (_GPIO_P_MODEH_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_PUSHPULL (_GPIO_P_MODEH_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_PUSHPULLALT (_GPIO_P_MODEH_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_WIREDOR (_GPIO_P_MODEH_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_WIREDAND (_GPIO_P_MODEH_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_WIREDANDFILTER (_GPIO_P_MODEH_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_WIREDANDPULLUP (_GPIO_P_MODEH_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_WIREDANDALT (_GPIO_P_MODEH_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ + +/* Bit fields for GPIO_P DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO_P DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +/** @} End of group Parts */ + +#endif // GPIO_PORT_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_hfrco.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_hfrco.h new file mode 100644 index 0000000000..c9a3a740ff --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_hfrco.h @@ -0,0 +1,226 @@ +/**************************************************************************//** + * @file + * @brief BGM26 HFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_HFRCO_H +#define BGM26_HFRCO_H +#define HFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_HFRCO HFRCO + * @{ + * @brief BGM26 HFRCO Register Declaration. + *****************************************************************************/ + +/** HFRCO Register Declaration. */ +typedef struct hfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ +} HFRCO_TypeDef; +/** @} End of group BGM26_HFRCO */ + +/**************************************************************************//** + * @addtogroup BGM26_HFRCO + * @{ + * @defgroup BGM26_HFRCO_BitFields HFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFRCO IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ + +/* Bit fields for HFRCO CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ + +/* Bit fields for HFRCO CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ + +/* Bit fields for HFRCO STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ + +/* Bit fields for HFRCO IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ + +/* Bit fields for HFRCO IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ + +/* Bit fields for HFRCO LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ + +/** @} End of group BGM26_HFRCO_BitFields */ +/** @} End of group BGM26_HFRCO */ +/** @} End of group Parts */ + +#endif // BGM26_HFRCO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_hfxo.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_hfxo.h new file mode 100644 index 0000000000..12736128f6 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_hfxo.h @@ -0,0 +1,801 @@ +/**************************************************************************//** + * @file + * @brief BGM26 HFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_HFXO_H +#define BGM26_HFXO_H +#define HFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_HFXO HFXO + * @{ + * @brief BGM26 HFXO Register Declaration. + *****************************************************************************/ + +/** HFXO Register Declaration. */ +typedef struct hfxo_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED3[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED12[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED21[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} HFXO_TypeDef; +/** @} End of group BGM26_HFXO */ + +/**************************************************************************//** + * @addtogroup BGM26_HFXO + * @{ + * @defgroup BGM26_HFXO_BitFields HFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFXO IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ + +/* Bit fields for HFXO XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ + +/* Bit fields for HFXO XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ + +/* Bit fields for HFXO XTALCTRL1 */ +#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ +#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ + +/* Bit fields for HFXO CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ +#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ + +/* Bit fields for HFXO CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ +#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ +#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ +#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ +#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ +#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ +#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ + +/* Bit fields for HFXO BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ +#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ + +/* Bit fields for HFXO BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ + +/* Bit fields for HFXO CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ + +/* Bit fields for HFXO STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ +#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ +#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ +#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ +#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ +#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ +#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ + +/* Bit fields for HFXO IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ + +/* Bit fields for HFXO IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ + +/* Bit fields for HFXO LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ + +/** @} End of group BGM26_HFXO_BitFields */ +/** @} End of group BGM26_HFXO */ +/** @} End of group Parts */ + +#endif // BGM26_HFXO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_i2c.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_i2c.h new file mode 100644 index 0000000000..793a27e3c0 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_i2c.h @@ -0,0 +1,744 @@ +/**************************************************************************//** + * @file + * @brief BGM26 I2C register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_I2C_H +#define BGM26_I2C_H +#define I2C_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_I2C I2C + * @{ + * @brief BGM26 I2C Register Declaration. + *****************************************************************************/ + +/** I2C Register Declaration. */ +typedef struct i2c_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} I2C_TypeDef; +/** @} End of group BGM26_I2C */ + +/**************************************************************************//** + * @addtogroup BGM26_I2C + * @{ + * @defgroup BGM26_I2C_BitFields I2C Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ + +/* Bit fields for I2C EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ + +/** @} End of group BGM26_I2C_BitFields */ +/** @} End of group BGM26_I2C */ +/** @} End of group Parts */ + +#endif // BGM26_I2C_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_iadc.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_iadc.h new file mode 100644 index 0000000000..891b6b6d9b --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_iadc.h @@ -0,0 +1,1050 @@ +/**************************************************************************//** + * @file + * @brief BGM26 IADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_IADC_H +#define BGM26_IADC_H +#define IADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_IADC IADC + * @{ + * @brief BGM26 IADC Register Declaration. + *****************************************************************************/ + +/** IADC CFG Register Group Declaration. */ +typedef struct iadc_cfg_typedef{ + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ +} IADC_CFG_TypeDef; + +/** IADC SCANTABLE Register Group Declaration. */ +typedef struct iadc_scantable_typedef{ + __IOM uint32_t SCAN; /**< SCAN Entry */ +} IADC_SCANTABLE_TypeDef; + +/** IADC Register Declaration. */ +typedef struct iadc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ +} IADC_TypeDef; +/** @} End of group BGM26_IADC */ + +/**************************************************************************//** + * @addtogroup BGM26_IADC + * @{ + * @defgroup BGM26_IADC_BitFields IADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for IADC IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ + +/* Bit fields for IADC EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ +#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ +#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ +#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ + +/* Bit fields for IADC CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ + +/* Bit fields for IADC CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ + +/* Bit fields for IADC TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ + +/* Bit fields for IADC STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ + +/* Bit fields for IADC MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ + +/* Bit fields for IADC STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ + +/* Bit fields for IADC CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ + +/* Bit fields for IADC IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ + +/* Bit fields for IADC IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ + +/* Bit fields for IADC TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ + +/* Bit fields for IADC CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ + +/* Bit fields for IADC SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ + +/* Bit fields for IADC SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ + +/* Bit fields for IADC SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ + +/* Bit fields for IADC SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ + +/* Bit fields for IADC SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ + +/* Bit fields for IADC SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ + +/* Bit fields for IADC SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ + +/* Bit fields for IADC SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ + +/* Bit fields for IADC SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ + +/* Bit fields for IADC SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ + +/* Bit fields for IADC SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ + +/* Bit fields for IADC SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ + +/** @} End of group BGM26_IADC_BitFields */ +/** @} End of group BGM26_IADC */ +/** @} End of group Parts */ + +#endif // BGM26_IADC_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_icache.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_icache.h new file mode 100644 index 0000000000..7b3acec1db --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_icache.h @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file + * @brief BGM26 ICACHE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_ICACHE_H +#define BGM26_ICACHE_H +#define ICACHE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_ICACHE ICACHE + * @{ + * @brief BGM26 ICACHE Register Declaration. + *****************************************************************************/ + +/** ICACHE Register Declaration. */ +typedef struct icache_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +} ICACHE_TypeDef; +/** @} End of group BGM26_ICACHE */ + +/**************************************************************************//** + * @addtogroup BGM26_ICACHE + * @{ + * @defgroup BGM26_ICACHE_BitFields ICACHE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ICACHE IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ + +/* Bit fields for ICACHE CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ + +/* Bit fields for ICACHE PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ + +/* Bit fields for ICACHE PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ + +/* Bit fields for ICACHE PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ + +/* Bit fields for ICACHE STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ + +/* Bit fields for ICACHE CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ + +/* Bit fields for ICACHE LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ + +/* Bit fields for ICACHE IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ + +/* Bit fields for ICACHE IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ + +/** @} End of group BGM26_ICACHE_BitFields */ +/** @} End of group BGM26_ICACHE */ +/** @} End of group Parts */ + +#endif // BGM26_ICACHE_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_keyscan.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_keyscan.h new file mode 100644 index 0000000000..e126902d6d --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_keyscan.h @@ -0,0 +1,386 @@ +/**************************************************************************//** + * @file + * @brief BGM26 KEYSCAN register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_KEYSCAN_H +#define BGM26_KEYSCAN_H +#define KEYSCAN_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_KEYSCAN KEYSCAN + * @{ + * @brief BGM26 KEYSCAN Register Declaration. + *****************************************************************************/ + +/** KEYSCAN Register Declaration. */ +typedef struct keyscan_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t DELAY; /**< Delay */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t DELAY_SET; /**< Delay */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t DELAY_CLR; /**< Delay */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t DELAY_TGL; /**< Delay */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ +} KEYSCAN_TypeDef; +/** @} End of group BGM26_KEYSCAN */ + +/**************************************************************************//** + * @addtogroup BGM26_KEYSCAN + * @{ + * @defgroup BGM26_KEYSCAN_BitFields KEYSCAN Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for KEYSCAN IPVERSION */ +#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ +#define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */ + +/* Bit fields for KEYSCAN EN */ +#define _KEYSCAN_EN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_EN */ +#define _KEYSCAN_EN_MASK 0x00000003UL /**< Mask for KEYSCAN_EN */ +#define KEYSCAN_EN_EN (0x1UL << 0) /**< Enable */ +#define _KEYSCAN_EN_EN_SHIFT 0 /**< Shift value for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_MASK 0x1UL /**< Bit mask for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DEFAULT (_KEYSCAN_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DISABLE (_KEYSCAN_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_ENABLE (_KEYSCAN_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _KEYSCAN_EN_DISABLING_SHIFT 1 /**< Shift value for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_MASK 0x2UL /**< Bit mask for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING_DEFAULT (_KEYSCAN_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_EN */ + +/* Bit fields for KEYSCAN SWRST */ +#define _KEYSCAN_SWRST_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_MASK 0x00000003UL /**< Mask for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _KEYSCAN_SWRST_SWRST_SHIFT 0 /**< Shift value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_MASK 0x1UL /**< Bit mask for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST_DEFAULT (_KEYSCAN_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _KEYSCAN_SWRST_RESETTING_SHIFT 1 /**< Shift value for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ + +/* Bit fields for KEYSCAN CFG */ +#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ +#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ +#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ + +/* Bit fields for KEYSCAN CMD */ +#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ +#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ +#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ + +/* Bit fields for KEYSCAN DELAY */ +#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY16 (_KEYSCAN_DELAY_STABDLY_STABDLY16 << 24) /**< Shifted mode STABDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY18 (_KEYSCAN_DELAY_STABDLY_STABDLY18 << 24) /**< Shifted mode STABDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY20 (_KEYSCAN_DELAY_STABDLY_STABDLY20 << 24) /**< Shifted mode STABDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY22 (_KEYSCAN_DELAY_STABDLY_STABDLY22 << 24) /**< Shifted mode STABDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY24 (_KEYSCAN_DELAY_STABDLY_STABDLY24 << 24) /**< Shifted mode STABDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY26 (_KEYSCAN_DELAY_STABDLY_STABDLY26 << 24) /**< Shifted mode STABDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY28 (_KEYSCAN_DELAY_STABDLY_STABDLY28 << 24) /**< Shifted mode STABDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY30 (_KEYSCAN_DELAY_STABDLY_STABDLY30 << 24) /**< Shifted mode STABDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */ + +/* Bit fields for KEYSCAN STATUS */ +#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ +#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ +#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ +#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ + +/* Bit fields for KEYSCAN IF */ +#define _KEYSCAN_IF_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IF */ +#define _KEYSCAN_IF_MASK 0x0000000FUL /**< Mask for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY (0x1UL << 0) /**< No key was pressed */ +#define _KEYSCAN_IF_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY_DEFAULT (_KEYSCAN_IF_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY (0x1UL << 1) /**< A key was pressed */ +#define _KEYSCAN_IF_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY_DEFAULT (_KEYSCAN_IF_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED (0x1UL << 2) /**< Completed scan */ +#define _KEYSCAN_IF_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED_DEFAULT (_KEYSCAN_IF_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IF_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP_DEFAULT (_KEYSCAN_IF_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IF */ + +/* Bit fields for KEYSCAN IEN */ +#define _KEYSCAN_IEN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IEN */ +#define _KEYSCAN_IEN_MASK 0x0000000FUL /**< Mask for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY (0x1UL << 0) /**< No Key was pressed */ +#define _KEYSCAN_IEN_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY_DEFAULT (_KEYSCAN_IEN_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY (0x1UL << 1) /**< A Key was pressed */ +#define _KEYSCAN_IEN_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY_DEFAULT (_KEYSCAN_IEN_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED (0x1UL << 2) /**< Completed Scanning */ +#define _KEYSCAN_IEN_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED_DEFAULT (_KEYSCAN_IEN_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IEN_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP_DEFAULT (_KEYSCAN_IEN_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ + +/** @} End of group BGM26_KEYSCAN_BitFields */ +/** @} End of group BGM26_KEYSCAN */ +/** @} End of group Parts */ + +#endif // BGM26_KEYSCAN_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_lcd.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lcd.h new file mode 100644 index 0000000000..e8569c1a52 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lcd.h @@ -0,0 +1,792 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LCD register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LCD_H +#define BGM26_LCD_H +#define LCD_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_LCD LCD + * @{ + * @brief BGM26 LCD Register Declaration. + *****************************************************************************/ + +/** LCD Register Declaration. */ +typedef struct lcd_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t DISPCTRL; /**< Display Control Register */ + __IOM uint32_t BACFG; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t AREGA; /**< Animation Register A */ + __IOM uint32_t AREGB; /**< Animation Register B */ + __IOM uint32_t IF; /**< Interrupt Enable Register */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX; /**< Display Control Extended */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0; /**< Segment Data Register 0 */ + __IOM uint32_t SEGD0H; /**< Segment Data Register 0 MSB */ + __IOM uint32_t SEGD1; /**< Segment Data Register 1 */ + __IOM uint32_t SEGD1H; /**< Segment Data Register 1 MSB */ + __IOM uint32_t SEGD2; /**< Segment Data Register 2 */ + __IOM uint32_t SEGD2H; /**< Segment Data Register 2 MSB */ + __IOM uint32_t SEGD3; /**< Segment Data Register 3 */ + __IOM uint32_t SEGD3H; /**< Segment Data Register 3 MSB */ + __IOM uint32_t SEGD4; /**< Segment Data Register 4 */ + __IOM uint32_t SEGD4H; /**< Segment Data Register 4 MSB */ + __IOM uint32_t SEGD5; /**< Segment Data Register 5 */ + __IOM uint32_t SEGD5H; /**< Segment Data Register 5 MSB */ + __IOM uint32_t SEGD6; /**< Segment Data Register 6 */ + __IOM uint32_t SEGD6H; /**< Segment Data Register 6 MSB */ + __IOM uint32_t SEGD7; /**< Segment Data Register 7 */ + __IOM uint32_t SEGD7H; /**< Segment Data Register 7 MSB */ + uint32_t RESERVED1[16U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL; /**< Update Control */ + uint32_t RESERVED2[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE; /**< Frame Rate */ + uint32_t RESERVED3[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t DISPCTRL_SET; /**< Display Control Register */ + __IOM uint32_t BACFG_SET; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_SET; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t AREGA_SET; /**< Animation Register A */ + __IOM uint32_t AREGB_SET; /**< Animation Register B */ + __IOM uint32_t IF_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_SET; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_SET; /**< Display Control Extended */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_SET; /**< Segment Data Register 0 */ + __IOM uint32_t SEGD0H_SET; /**< Segment Data Register 0 MSB */ + __IOM uint32_t SEGD1_SET; /**< Segment Data Register 1 */ + __IOM uint32_t SEGD1H_SET; /**< Segment Data Register 1 MSB */ + __IOM uint32_t SEGD2_SET; /**< Segment Data Register 2 */ + __IOM uint32_t SEGD2H_SET; /**< Segment Data Register 2 MSB */ + __IOM uint32_t SEGD3_SET; /**< Segment Data Register 3 */ + __IOM uint32_t SEGD3H_SET; /**< Segment Data Register 3 MSB */ + __IOM uint32_t SEGD4_SET; /**< Segment Data Register 4 */ + __IOM uint32_t SEGD4H_SET; /**< Segment Data Register 4 MSB */ + __IOM uint32_t SEGD5_SET; /**< Segment Data Register 5 */ + __IOM uint32_t SEGD5H_SET; /**< Segment Data Register 5 MSB */ + __IOM uint32_t SEGD6_SET; /**< Segment Data Register 6 */ + __IOM uint32_t SEGD6H_SET; /**< Segment Data Register 6 MSB */ + __IOM uint32_t SEGD7_SET; /**< Segment Data Register 7 */ + __IOM uint32_t SEGD7H_SET; /**< Segment Data Register 7 MSB */ + uint32_t RESERVED5[16U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_SET; /**< Update Control */ + uint32_t RESERVED6[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_SET; /**< Frame Rate */ + uint32_t RESERVED7[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t DISPCTRL_CLR; /**< Display Control Register */ + __IOM uint32_t BACFG_CLR; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_CLR; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t AREGA_CLR; /**< Animation Register A */ + __IOM uint32_t AREGB_CLR; /**< Animation Register B */ + __IOM uint32_t IF_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_CLR; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_CLR; /**< Display Control Extended */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_CLR; /**< Segment Data Register 0 */ + __IOM uint32_t SEGD0H_CLR; /**< Segment Data Register 0 MSB */ + __IOM uint32_t SEGD1_CLR; /**< Segment Data Register 1 */ + __IOM uint32_t SEGD1H_CLR; /**< Segment Data Register 1 MSB */ + __IOM uint32_t SEGD2_CLR; /**< Segment Data Register 2 */ + __IOM uint32_t SEGD2H_CLR; /**< Segment Data Register 2 MSB */ + __IOM uint32_t SEGD3_CLR; /**< Segment Data Register 3 */ + __IOM uint32_t SEGD3H_CLR; /**< Segment Data Register 3 MSB */ + __IOM uint32_t SEGD4_CLR; /**< Segment Data Register 4 */ + __IOM uint32_t SEGD4H_CLR; /**< Segment Data Register 4 MSB */ + __IOM uint32_t SEGD5_CLR; /**< Segment Data Register 5 */ + __IOM uint32_t SEGD5H_CLR; /**< Segment Data Register 5 MSB */ + __IOM uint32_t SEGD6_CLR; /**< Segment Data Register 6 */ + __IOM uint32_t SEGD6H_CLR; /**< Segment Data Register 6 MSB */ + __IOM uint32_t SEGD7_CLR; /**< Segment Data Register 7 */ + __IOM uint32_t SEGD7H_CLR; /**< Segment Data Register 7 MSB */ + uint32_t RESERVED9[16U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_CLR; /**< Update Control */ + uint32_t RESERVED10[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_CLR; /**< Frame Rate */ + uint32_t RESERVED11[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t DISPCTRL_TGL; /**< Display Control Register */ + __IOM uint32_t BACFG_TGL; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_TGL; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t AREGA_TGL; /**< Animation Register A */ + __IOM uint32_t AREGB_TGL; /**< Animation Register B */ + __IOM uint32_t IF_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_TGL; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_TGL; /**< Display Control Extended */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_TGL; /**< Segment Data Register 0 */ + __IOM uint32_t SEGD0H_TGL; /**< Segment Data Register 0 MSB */ + __IOM uint32_t SEGD1_TGL; /**< Segment Data Register 1 */ + __IOM uint32_t SEGD1H_TGL; /**< Segment Data Register 1 MSB */ + __IOM uint32_t SEGD2_TGL; /**< Segment Data Register 2 */ + __IOM uint32_t SEGD2H_TGL; /**< Segment Data Register 2 MSB */ + __IOM uint32_t SEGD3_TGL; /**< Segment Data Register 3 */ + __IOM uint32_t SEGD3H_TGL; /**< Segment Data Register 3 MSB */ + __IOM uint32_t SEGD4_TGL; /**< Segment Data Register 4 */ + __IOM uint32_t SEGD4H_TGL; /**< Segment Data Register 4 MSB */ + __IOM uint32_t SEGD5_TGL; /**< Segment Data Register 5 */ + __IOM uint32_t SEGD5H_TGL; /**< Segment Data Register 5 MSB */ + __IOM uint32_t SEGD6_TGL; /**< Segment Data Register 6 */ + __IOM uint32_t SEGD6H_TGL; /**< Segment Data Register 6 MSB */ + __IOM uint32_t SEGD7_TGL; /**< Segment Data Register 7 */ + __IOM uint32_t SEGD7H_TGL; /**< Segment Data Register 7 MSB */ + uint32_t RESERVED13[16U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_TGL; /**< Update Control */ + uint32_t RESERVED14[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_TGL; /**< Frame Rate */ +} LCD_TypeDef; +/** @} End of group BGM26_LCD */ + +/**************************************************************************//** + * @addtogroup BGM26_LCD + * @{ + * @defgroup BGM26_LCD_BitFields LCD Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LCD IPVERSION */ +#define _LCD_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LCD_IPVERSION */ +#define _LCD_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_IPVERSION */ +#define LCD_IPVERSION_IPVERSION_DEFAULT (_LCD_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IPVERSION */ + +/* Bit fields for LCD EN */ +#define _LCD_EN_RESETVALUE 0x00000000UL /**< Default value for LCD_EN */ +#define _LCD_EN_MASK 0x00000003UL /**< Mask for LCD_EN */ +#define LCD_EN_EN (0x1UL << 0) /**< Enable */ +#define _LCD_EN_EN_SHIFT 0 /**< Shift value for LCD_EN */ +#define _LCD_EN_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ +#define _LCD_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ +#define _LCD_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_EN */ +#define _LCD_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_EN */ +#define LCD_EN_EN_DEFAULT (_LCD_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_EN */ +#define LCD_EN_EN_DISABLE (_LCD_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LCD_EN */ +#define LCD_EN_EN_ENABLE (_LCD_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LCD_EN */ +#define LCD_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LCD_EN_DISABLING_SHIFT 1 /**< Shift value for LCD_DISABLING */ +#define _LCD_EN_DISABLING_MASK 0x2UL /**< Bit mask for LCD_DISABLING */ +#define _LCD_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ +#define LCD_EN_DISABLING_DEFAULT (_LCD_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_EN */ + +/* Bit fields for LCD SWRST */ +#define _LCD_SWRST_RESETVALUE 0x00000000UL /**< Default value for LCD_SWRST */ +#define _LCD_SWRST_MASK 0x00000003UL /**< Mask for LCD_SWRST */ +#define LCD_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LCD_SWRST_SWRST_SHIFT 0 /**< Shift value for LCD_SWRST */ +#define _LCD_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LCD_SWRST */ +#define _LCD_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_SWRST_DEFAULT (_LCD_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LCD_SWRST_RESETTING_SHIFT 1 /**< Shift value for LCD_RESETTING */ +#define _LCD_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LCD_RESETTING */ +#define _LCD_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_RESETTING_DEFAULT (_LCD_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SWRST */ + +/* Bit fields for LCD CTRL */ +#define _LCD_CTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_CTRL */ +#define _LCD_CTRL_MASK 0x7F1D0006UL /**< Mask for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000001UL /**< Mode FRAMESTART for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000002UL /**< Mode FCEVENT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_DISPLAYEVENT 0x00000003UL /**< Mode DISPLAYEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DISPLAYEVENT (_LCD_CTRL_UDCTRL_DISPLAYEVENT << 1) /**< Shifted mode DISPLAYEVENT for LCD_CTRL */ +#define LCD_CTRL_DSC (0x1UL << 16) /**< Direct Segment Control */ +#define _LCD_CTRL_DSC_SHIFT 16 /**< Shift value for LCD_DSC */ +#define _LCD_CTRL_DSC_MASK 0x10000UL /**< Bit mask for LCD_DSC */ +#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_DSC_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_CTRL */ +#define _LCD_CTRL_DSC_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_CTRL */ +#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_DSC_DISABLE (_LCD_CTRL_DSC_DISABLE << 16) /**< Shifted mode DISABLE for LCD_CTRL */ +#define LCD_CTRL_DSC_ENABLE (_LCD_CTRL_DSC_ENABLE << 16) /**< Shifted mode ENABLE for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_SHIFT 18 /**< Shift value for LCD_WARMUPDLY */ +#define _LCD_CTRL_WARMUPDLY_MASK 0x1C0000UL /**< Bit mask for LCD_WARMUPDLY */ +#define _LCD_CTRL_WARMUPDLY_DEFAULT 0x00000004UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP1 0x00000000UL /**< Mode WARMUP1 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP31 0x00000001UL /**< Mode WARMUP31 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP63 0x00000002UL /**< Mode WARMUP63 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP125 0x00000003UL /**< Mode WARMUP125 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP250 0x00000004UL /**< Mode WARMUP250 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP500 0x00000005UL /**< Mode WARMUP500 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP1000 0x00000006UL /**< Mode WARMUP1000 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP2000 0x00000007UL /**< Mode WARMUP2000 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_DEFAULT (_LCD_CTRL_WARMUPDLY_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP1 (_LCD_CTRL_WARMUPDLY_WARMUP1 << 18) /**< Shifted mode WARMUP1 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP31 (_LCD_CTRL_WARMUPDLY_WARMUP31 << 18) /**< Shifted mode WARMUP31 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP63 (_LCD_CTRL_WARMUPDLY_WARMUP63 << 18) /**< Shifted mode WARMUP63 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP125 (_LCD_CTRL_WARMUPDLY_WARMUP125 << 18) /**< Shifted mode WARMUP125 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP250 (_LCD_CTRL_WARMUPDLY_WARMUP250 << 18) /**< Shifted mode WARMUP250 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP500 (_LCD_CTRL_WARMUPDLY_WARMUP500 << 18) /**< Shifted mode WARMUP500 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP1000 (_LCD_CTRL_WARMUPDLY_WARMUP1000 << 18) /**< Shifted mode WARMUP1000 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP2000 (_LCD_CTRL_WARMUPDLY_WARMUP2000 << 18) /**< Shifted mode WARMUP2000 for LCD_CTRL */ +#define _LCD_CTRL_PRESCALE_SHIFT 24 /**< Shift value for LCD_PRESCALE */ +#define _LCD_CTRL_PRESCALE_MASK 0x7F000000UL /**< Bit mask for LCD_PRESCALE */ +#define _LCD_CTRL_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_PRESCALE_DEFAULT (_LCD_CTRL_PRESCALE_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_CTRL */ + +/* Bit fields for LCD CMD */ +#define _LCD_CMD_RESETVALUE 0x00000000UL /**< Default value for LCD_CMD */ +#define _LCD_CMD_MASK 0x00000003UL /**< Mask for LCD_CMD */ +#define LCD_CMD_LOAD (0x1UL << 0) /**< Load command */ +#define _LCD_CMD_LOAD_SHIFT 0 /**< Shift value for LCD_LOAD */ +#define _LCD_CMD_LOAD_MASK 0x1UL /**< Bit mask for LCD_LOAD */ +#define _LCD_CMD_LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ +#define LCD_CMD_LOAD_DEFAULT (_LCD_CMD_LOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CMD */ +#define LCD_CMD_CLEAR (0x1UL << 1) /**< Clear command */ +#define _LCD_CMD_CLEAR_SHIFT 1 /**< Shift value for LCD_CLEAR */ +#define _LCD_CMD_CLEAR_MASK 0x2UL /**< Bit mask for LCD_CLEAR */ +#define _LCD_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ +#define LCD_CMD_CLEAR_DEFAULT (_LCD_CMD_CLEAR_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CMD */ + +/* Bit fields for LCD DISPCTRL */ +#define _LCD_DISPCTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MASK 0x03700017UL /**< Mask for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SEXTAPLEX 0x00000005UL /**< Mode SEXTAPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_OCTAPLEX 0x00000007UL /**< Mode OCTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_SEXTAPLEX (_LCD_DISPCTRL_MUX_SEXTAPLEX << 0) /**< Shifted mode SEXTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_OCTAPLEX (_LCD_DISPCTRL_MUX_OCTAPLEX << 0) /**< Shifted mode OCTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ +#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_TYPEB 0x00000000UL /**< Mode TYPEB for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_TYPEA 0x00000001UL /**< Mode TYPEA for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_TYPEB (_LCD_DISPCTRL_WAVE_TYPEB << 4) /**< Shifted mode TYPEB for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_TYPEA (_LCD_DISPCTRL_WAVE_TYPEA << 4) /**< Shifted mode TYPEA for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */ + +/* Bit fields for LCD BACFG */ +#define _LCD_BACFG_RESETVALUE 0x00000007UL /**< Default value for LCD_BACFG */ +#define _LCD_BACFG_MASK 0x00FF0007UL /**< Mask for LCD_BACFG */ +#define _LCD_BACFG_ASTATETOP_SHIFT 0 /**< Shift value for LCD_ASTATETOP */ +#define _LCD_BACFG_ASTATETOP_MASK 0x7UL /**< Bit mask for LCD_ASTATETOP */ +#define _LCD_BACFG_ASTATETOP_DEFAULT 0x00000007UL /**< Mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_ASTATETOP_DEFAULT (_LCD_BACFG_ASTATETOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ +#define _LCD_BACFG_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ +#define _LCD_BACFG_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DEFAULT (_LCD_BACFG_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV1 (_LCD_BACFG_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV2 (_LCD_BACFG_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV4 (_LCD_BACFG_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV8 (_LCD_BACFG_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACFG */ +#define _LCD_BACFG_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ +#define _LCD_BACFG_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ +#define _LCD_BACFG_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_FCTOP_DEFAULT (_LCD_BACFG_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACFG */ + +/* Bit fields for LCD BACTRL */ +#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ +#define _LCD_BACTRL_MASK 0x100003FFUL /**< Mask for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ +#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ +#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_BLANK_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ +#define _LCD_BACTRL_BLANK_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DISABLE (_LCD_BACTRL_BLANK_DISABLE << 1) /**< Shifted mode DISABLE for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_ENABLE (_LCD_BACTRL_BLANK_ENABLE << 1) /**< Shifted mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ +#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ +#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ +#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ +#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ +#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ +#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN (0x1UL << 9) /**< Display Counter Enable */ +#define _LCD_BACTRL_DISPLAYCNTEN_SHIFT 9 /**< Shift value for LCD_DISPLAYCNTEN */ +#define _LCD_BACTRL_DISPLAYCNTEN_MASK 0x200UL /**< Bit mask for LCD_DISPLAYCNTEN */ +#define _LCD_BACTRL_DISPLAYCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_DISPLAYCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ +#define _LCD_BACTRL_DISPLAYCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_DEFAULT (_LCD_BACTRL_DISPLAYCNTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_DISABLE (_LCD_BACTRL_DISPLAYCNTEN_DISABLE << 9) /**< Shifted mode DISABLE for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_ENABLE (_LCD_BACTRL_DISPLAYCNTEN_ENABLE << 9) /**< Shifted mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */ +#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */ + +/* Bit fields for LCD STATUS */ +#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ +#define _LCD_STATUS_MASK 0x0000090FUL /**< Mask for LCD_STATUS */ +#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ +#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ +#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ +#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_LOADBUSY (0x1UL << 11) /**< Load Synchronization is busy */ +#define _LCD_STATUS_LOADBUSY_SHIFT 11 /**< Shift value for LCD_LOADBUSY */ +#define _LCD_STATUS_LOADBUSY_MASK 0x800UL /**< Bit mask for LCD_LOADBUSY */ +#define _LCD_STATUS_LOADBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_LOADBUSY_DEFAULT (_LCD_STATUS_LOADBUSY_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_STATUS */ + +/* Bit fields for LCD AREGA */ +#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ +#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ +#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ +#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ + +/* Bit fields for LCD AREGB */ +#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ +#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ +#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ +#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ + +/* Bit fields for LCD IF */ +#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ +#define _LCD_IF_MASK 0x00000007UL /**< Mask for LCD_IF */ +#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter */ +#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ +#define LCD_IF_DISPLAY (0x1UL << 1) /**< Display Update Event */ +#define _LCD_IF_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ +#define _LCD_IF_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ +#define _LCD_IF_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_DISPLAY_DEFAULT (_LCD_IF_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IF */ +#define LCD_IF_SYNCBUSYDONE (0x1UL << 2) /**< Synchronization is Done */ +#define _LCD_IF_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ +#define _LCD_IF_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ +#define _LCD_IF_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_SYNCBUSYDONE_DEFAULT (_LCD_IF_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IF */ + +/* Bit fields for LCD IEN */ +#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ +#define _LCD_IEN_MASK 0x00000007UL /**< Mask for LCD_IEN */ +#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter */ +#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ +#define LCD_IEN_DISPLAY (0x1UL << 1) /**< Display Update Event */ +#define _LCD_IEN_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ +#define _LCD_IEN_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ +#define _LCD_IEN_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_DISPLAY_DEFAULT (_LCD_IEN_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IEN */ +#define LCD_IEN_SYNCBUSYDONE (0x1UL << 2) /**< Sync Busy Done */ +#define _LCD_IEN_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ +#define _LCD_IEN_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ +#define _LCD_IEN_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_SYNCBUSYDONE_DEFAULT (_LCD_IEN_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IEN */ + +/* Bit fields for LCD BIASCTRL */ +#define _LCD_BIASCTRL_RESETVALUE 0x001F0000UL /**< Default value for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MASK 0xC45F137FUL /**< Mask for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_RESISTOR_SHIFT 0 /**< Shift value for LCD_RESISTOR */ +#define _LCD_BIASCTRL_RESISTOR_MASK 0xFUL /**< Bit mask for LCD_RESISTOR */ +#define _LCD_BIASCTRL_RESISTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_RESISTOR_DEFAULT (_LCD_BIASCTRL_RESISTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_MASK 0x70UL /**< Bit mask for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFBIAS_SHIFT 8 /**< Shift value for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_MASK 0x300UL /**< Bit mask for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE (0x1UL << 12) /**< Mode Setting */ +#define _LCD_BIASCTRL_MODE_SHIFT 12 /**< Shift value for LCD_MODE */ +#define _LCD_BIASCTRL_MODE_MASK 0x1000UL /**< Bit mask for LCD_MODE */ +#define _LCD_BIASCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MODE_STEPDOWN 0x00000000UL /**< Mode STEPDOWN for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MODE_CHARGEPUMP 0x00000001UL /**< Mode CHARGEPUMP for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_DEFAULT (_LCD_BIASCTRL_MODE_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_STEPDOWN (_LCD_BIASCTRL_MODE_STEPDOWN << 12) /**< Shifted mode STEPDOWN for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_CHARGEPUMP (_LCD_BIASCTRL_MODE_CHARGEPUMP << 12) /**< Shifted mode CHARGEPUMP for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VLCD_SHIFT 16 /**< Shift value for LCD_VLCD */ +#define _LCD_BIASCTRL_VLCD_MASK 0x1F0000UL /**< Bit mask for LCD_VLCD */ +#define _LCD_BIASCTRL_VLCD_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VLCD_DEFAULT (_LCD_BIASCTRL_VLCD_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL (0x1UL << 22) /**< VDDX select */ +#define _LCD_BIASCTRL_VDDXSEL_SHIFT 22 /**< Shift value for LCD_VDDXSEL */ +#define _LCD_BIASCTRL_VDDXSEL_MASK 0x400000UL /**< Bit mask for LCD_VDDXSEL */ +#define _LCD_BIASCTRL_VDDXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VDDXSEL_DVDD 0x00000000UL /**< Mode DVDD for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VDDXSEL_AVDD 0x00000001UL /**< Mode AVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_DEFAULT (_LCD_BIASCTRL_VDDXSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_DVDD (_LCD_BIASCTRL_VDDXSEL_DVDD << 22) /**< Shifted mode DVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_AVDD (_LCD_BIASCTRL_VDDXSEL_AVDD << 22) /**< Shifted mode AVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE (0x1UL << 26) /**< LCD Gate */ +#define _LCD_BIASCTRL_LCDGATE_SHIFT 26 /**< Shift value for LCD_LCDGATE */ +#define _LCD_BIASCTRL_LCDGATE_MASK 0x4000000UL /**< Bit mask for LCD_LCDGATE */ +#define _LCD_BIASCTRL_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_DEFAULT (_LCD_BIASCTRL_LCDGATE_DEFAULT << 26) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_UNGATE (_LCD_BIASCTRL_LCDGATE_UNGATE << 26) /**< Shifted mode UNGATE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_GATE (_LCD_BIASCTRL_LCDGATE_GATE << 26) /**< Shifted mode GATE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_SHIFT 30 /**< Shift value for LCD_DMAMODE */ +#define _LCD_BIASCTRL_DMAMODE_MASK 0xC0000000UL /**< Bit mask for LCD_DMAMODE */ +#define _LCD_BIASCTRL_DMAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMADISABLE 0x00000000UL /**< Mode DMADISABLE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMAFC 0x00000001UL /**< Mode DMAFC for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMADISPLAY 0x00000002UL /**< Mode DMADISPLAY for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DEFAULT (_LCD_BIASCTRL_DMAMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMADISABLE (_LCD_BIASCTRL_DMAMODE_DMADISABLE << 30) /**< Shifted mode DMADISABLE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMAFC (_LCD_BIASCTRL_DMAMODE_DMAFC << 30) /**< Shifted mode DMAFC for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMADISPLAY (_LCD_BIASCTRL_DMAMODE_DMADISPLAY << 30) /**< Shifted mode DMADISPLAY for LCD_BIASCTRL */ + +/* Bit fields for LCD DISPCTRLX */ +#define _LCD_DISPCTRLX_RESETVALUE 0x00000000UL /**< Default value for LCD_DISPCTRLX */ +#define _LCD_DISPCTRLX_MASK 0x000003FFUL /**< Mask for LCD_DISPCTRLX */ +#define _LCD_DISPCTRLX_DISPLAYDIV_SHIFT 0 /**< Shift value for LCD_DISPLAYDIV */ +#define _LCD_DISPCTRLX_DISPLAYDIV_MASK 0x3FFUL /**< Bit mask for LCD_DISPLAYDIV */ +#define _LCD_DISPCTRLX_DISPLAYDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRLX */ +#define LCD_DISPCTRLX_DISPLAYDIV_DEFAULT (_LCD_DISPCTRLX_DISPLAYDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRLX */ + +/* Bit fields for LCD SEGD0 */ +#define _LCD_SEGD0_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0 */ +#define _LCD_SEGD0_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_SHIFT 0 /**< Shift value for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0 */ +#define LCD_SEGD0_SEGD0_DEFAULT (_LCD_SEGD0_SEGD0_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0 */ + +/* Bit fields for LCD SEGD0H */ +#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */ +#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */ +#define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */ + +/* Bit fields for LCD SEGD1 */ +#define _LCD_SEGD1_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1 */ +#define _LCD_SEGD1_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_SHIFT 0 /**< Shift value for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1 */ +#define LCD_SEGD1_SEGD1_DEFAULT (_LCD_SEGD1_SEGD1_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1 */ + +/* Bit fields for LCD SEGD1H */ +#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */ +#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */ +#define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */ + +/* Bit fields for LCD SEGD2 */ +#define _LCD_SEGD2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2 */ +#define _LCD_SEGD2_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_SHIFT 0 /**< Shift value for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2 */ +#define LCD_SEGD2_SEGD2_DEFAULT (_LCD_SEGD2_SEGD2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2 */ + +/* Bit fields for LCD SEGD2H */ +#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */ +#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */ +#define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */ + +/* Bit fields for LCD SEGD3 */ +#define _LCD_SEGD3_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3 */ +#define _LCD_SEGD3_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_SHIFT 0 /**< Shift value for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3 */ +#define LCD_SEGD3_SEGD3_DEFAULT (_LCD_SEGD3_SEGD3_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3 */ + +/* Bit fields for LCD SEGD3H */ +#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */ +#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */ +#define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */ + +/* Bit fields for LCD SEGD4 */ +#define _LCD_SEGD4_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4 */ +#define _LCD_SEGD4_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4 */ +#define _LCD_SEGD4_SEGD4_SHIFT 0 /**< Shift value for LCD_SEGD4 */ +#define _LCD_SEGD4_SEGD4_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4 */ +#define _LCD_SEGD4_SEGD4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4 */ +#define LCD_SEGD4_SEGD4_DEFAULT (_LCD_SEGD4_SEGD4_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4 */ + +/* Bit fields for LCD SEGD4H */ +#define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */ +#define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */ +#define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */ + +/* Bit fields for LCD SEGD5 */ +#define _LCD_SEGD5_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5 */ +#define _LCD_SEGD5_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5 */ +#define _LCD_SEGD5_SEGD5_SHIFT 0 /**< Shift value for LCD_SEGD5 */ +#define _LCD_SEGD5_SEGD5_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5 */ +#define _LCD_SEGD5_SEGD5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5 */ +#define LCD_SEGD5_SEGD5_DEFAULT (_LCD_SEGD5_SEGD5_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5 */ + +/* Bit fields for LCD SEGD5H */ +#define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */ +#define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */ +#define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */ + +/* Bit fields for LCD SEGD6 */ +#define _LCD_SEGD6_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6 */ +#define _LCD_SEGD6_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6 */ +#define _LCD_SEGD6_SEGD6_SHIFT 0 /**< Shift value for LCD_SEGD6 */ +#define _LCD_SEGD6_SEGD6_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6 */ +#define _LCD_SEGD6_SEGD6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6 */ +#define LCD_SEGD6_SEGD6_DEFAULT (_LCD_SEGD6_SEGD6_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6 */ + +/* Bit fields for LCD SEGD6H */ +#define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */ +#define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */ +#define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */ + +/* Bit fields for LCD SEGD7 */ +#define _LCD_SEGD7_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7 */ +#define _LCD_SEGD7_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7 */ +#define _LCD_SEGD7_SEGD7_SHIFT 0 /**< Shift value for LCD_SEGD7 */ +#define _LCD_SEGD7_SEGD7_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7 */ +#define _LCD_SEGD7_SEGD7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7 */ +#define LCD_SEGD7_SEGD7_DEFAULT (_LCD_SEGD7_SEGD7_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7 */ + +/* Bit fields for LCD SEGD7H */ +#define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */ +#define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */ +#define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */ + +/* Bit fields for LCD UPDATECTRL */ +#define _LCD_UPDATECTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_MASK 0x0003E100UL /**< Mask for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD (0x1UL << 8) /**< Auto Load */ +#define _LCD_UPDATECTRL_AUTOLOAD_SHIFT 8 /**< Shift value for LCD_AUTOLOAD */ +#define _LCD_UPDATECTRL_AUTOLOAD_MASK 0x100UL /**< Bit mask for LCD_AUTOLOAD */ +#define _LCD_UPDATECTRL_AUTOLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_AUTOLOAD_MANUAL 0x00000000UL /**< Mode MANUAL for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_AUTOLOAD_AUTO 0x00000001UL /**< Mode AUTO for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_DEFAULT (_LCD_UPDATECTRL_AUTOLOAD_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_MANUAL (_LCD_UPDATECTRL_AUTOLOAD_MANUAL << 8) /**< Shifted mode MANUAL for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_AUTO (_LCD_UPDATECTRL_AUTOLOAD_AUTO << 8) /**< Shifted mode AUTO for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SHIFT 13 /**< Shift value for LCD_LOADADDR */ +#define _LCD_UPDATECTRL_LOADADDR_MASK 0x3E000UL /**< Bit mask for LCD_LOADADDR */ +#define _LCD_UPDATECTRL_LOADADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_BACTRLWR 0x00000000UL /**< Mode BACTRLWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_AREGAWR 0x00000001UL /**< Mode AREGAWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_AREGBWR 0x00000002UL /**< Mode AREGBWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD0WR 0x00000003UL /**< Mode SEGD0WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD1WR 0x00000004UL /**< Mode SEGD1WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD2WR 0x00000005UL /**< Mode SEGD2WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD3WR 0x00000006UL /**< Mode SEGD3WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD4WR 0x00000007UL /**< Mode SEGD4WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD5WR 0x00000008UL /**< Mode SEGD5WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD6WR 0x00000009UL /**< Mode SEGD6WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD7WR 0x0000000AUL /**< Mode SEGD7WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD0HWR 0x0000000BUL /**< Mode SEGD0HWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD1HWR 0x0000000CUL /**< Mode SEGD1HWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD2HWR 0x0000000DUL /**< Mode SEGD2HWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD3HWR 0x0000000EUL /**< Mode SEGD3HWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD4HWR 0x0000000FUL /**< Mode SEGD4HWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD5HWR 0x00000010UL /**< Mode SEGD5HWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD6HWR 0x00000011UL /**< Mode SEGD6HWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD7HWR 0x00000012UL /**< Mode SEGD7HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_DEFAULT (_LCD_UPDATECTRL_LOADADDR_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_BACTRLWR (_LCD_UPDATECTRL_LOADADDR_BACTRLWR << 13) /**< Shifted mode BACTRLWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_AREGAWR (_LCD_UPDATECTRL_LOADADDR_AREGAWR << 13) /**< Shifted mode AREGAWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_AREGBWR (_LCD_UPDATECTRL_LOADADDR_AREGBWR << 13) /**< Shifted mode AREGBWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD0WR (_LCD_UPDATECTRL_LOADADDR_SEGD0WR << 13) /**< Shifted mode SEGD0WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD1WR (_LCD_UPDATECTRL_LOADADDR_SEGD1WR << 13) /**< Shifted mode SEGD1WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD2WR (_LCD_UPDATECTRL_LOADADDR_SEGD2WR << 13) /**< Shifted mode SEGD2WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD3WR (_LCD_UPDATECTRL_LOADADDR_SEGD3WR << 13) /**< Shifted mode SEGD3WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD4WR (_LCD_UPDATECTRL_LOADADDR_SEGD4WR << 13) /**< Shifted mode SEGD4WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD5WR (_LCD_UPDATECTRL_LOADADDR_SEGD5WR << 13) /**< Shifted mode SEGD5WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD6WR (_LCD_UPDATECTRL_LOADADDR_SEGD6WR << 13) /**< Shifted mode SEGD6WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD7WR (_LCD_UPDATECTRL_LOADADDR_SEGD7WR << 13) /**< Shifted mode SEGD7WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD0HWR (_LCD_UPDATECTRL_LOADADDR_SEGD0HWR << 13) /**< Shifted mode SEGD0HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD1HWR (_LCD_UPDATECTRL_LOADADDR_SEGD1HWR << 13) /**< Shifted mode SEGD1HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD2HWR (_LCD_UPDATECTRL_LOADADDR_SEGD2HWR << 13) /**< Shifted mode SEGD2HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD3HWR (_LCD_UPDATECTRL_LOADADDR_SEGD3HWR << 13) /**< Shifted mode SEGD3HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD4HWR (_LCD_UPDATECTRL_LOADADDR_SEGD4HWR << 13) /**< Shifted mode SEGD4HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD5HWR (_LCD_UPDATECTRL_LOADADDR_SEGD5HWR << 13) /**< Shifted mode SEGD5HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD6HWR (_LCD_UPDATECTRL_LOADADDR_SEGD6HWR << 13) /**< Shifted mode SEGD6HWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD7HWR (_LCD_UPDATECTRL_LOADADDR_SEGD7HWR << 13) /**< Shifted mode SEGD7HWR for LCD_UPDATECTRL */ + +/* Bit fields for LCD FRAMERATE */ +#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */ +#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */ + +/** @} End of group BGM26_LCD_BitFields */ +/** @} End of group BGM26_LCD */ +/** @} End of group Parts */ + +#endif // BGM26_LCD_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_lcdrf.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lcdrf.h new file mode 100644 index 0000000000..83f0922b77 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lcdrf.h @@ -0,0 +1,104 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LCDRF register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LCDRF_H +#define BGM26_LCDRF_H +#define LCDRF_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_LCDRF LCDRF + * @{ + * @brief BGM26 LCDRF Register Declaration. + *****************************************************************************/ + +/** LCDRF Register Declaration. */ +typedef struct lcdrf_typedef{ + __IOM uint32_t RFIMLCDCTRL; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_SET; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_CLR; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_TGL; /**< RF Interference Mitigation LCD Control */ +} LCDRF_TypeDef; +/** @} End of group BGM26_LCDRF */ + +/**************************************************************************//** + * @addtogroup BGM26_LCDRF + * @{ + * @defgroup BGM26_LCDRF_BitFields LCDRF Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LCDRF RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_RESETVALUE 0x00000000UL /**< Default value for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_MASK 0x0000001FUL /**< Mask for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOEN (0x1UL << 0) /**< LCD Charge Pump XO Clock Enable */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_SHIFT 0 /**< Shift value for LCDRF_LCDCPXOEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_MASK 0x1UL /**< Bit mask for LCDRF_LCDCPXOEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL (0x1UL << 1) /**< LCD Charge Pump XO Select */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_SHIFT 1 /**< Shift value for LCDRF_LCDCPXOSEL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_MASK 0x2UL /**< Bit mask for LCDRF_LCDCPXOSEL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO 0x00000000UL /**< Mode INTRCO for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV 0x00000001UL /**< Mode HFXODIV for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO << 1) /**< Shifted mode INTRCO for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV << 1) /**< Shifted mode HFXODIV for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN (0x1UL << 2) /**< LCD Charge Pump XO Retime Enable */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_SHIFT 2 /**< Shift value for LCDRF_LCDCPXORETIMEEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_MASK 0x4UL /**< Bit mask for LCDRF_LCDCPXORETIMEEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE (0x1UL << 3) /**< LCD Low Noise */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SHIFT 3 /**< Shift value for LCDRF_LCDLOWNOISE */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_MASK 0x8UL /**< Bit mask for LCDRF_LCDLOWNOISE */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL 0x00000000UL /**< Mode NORMAL for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW 0x00000001UL /**< Mode SLOW for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT << 3) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL << 3) /**< Shifted mode NORMAL for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW << 3) /**< Shifted mode SLOW for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT (0x1UL << 4) /**< LCD Comparator Dout */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_SHIFT 4 /**< Shift value for LCDRF_LCDCMPDOUT */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_MASK 0x10UL /**< Bit mask for LCDRF_LCDCMPDOUT */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ + +/** @} End of group BGM26_LCDRF_BitFields */ +/** @} End of group BGM26_LCDRF */ +/** @} End of group Parts */ + +#endif // BGM26_LCDRF_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldma.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldma.h new file mode 100644 index 0000000000..393cd1c96e --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldma.h @@ -0,0 +1,685 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LDMA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LDMA_H +#define BGM26_LDMA_H +#define LDMA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_LDMA LDMA + * @{ + * @brief BGM26 LDMA Register Declaration. + *****************************************************************************/ + +/** LDMA CH Register Group Declaration. */ +typedef struct ldma_ch_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ +} LDMA_CH_TypeDef; + +/** LDMA Register Declaration. */ +typedef struct ldma_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; +/** @} End of group BGM26_LDMA */ + +/**************************************************************************//** + * @addtogroup BGM26_LDMA + * @{ + * @defgroup BGM26_LDMA_BitFields LDMA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ + +/* Bit fields for LDMA EN */ +#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ +#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ +#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ +#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ +#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ +#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ +#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ +#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ + +/* Bit fields for LDMA SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ + +/* Bit fields for LDMA SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ + +/* Bit fields for LDMA SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ + +/* Bit fields for LDMA SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHDIS */ +#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ +#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ +#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ + +/* Bit fields for LDMA CHSTATUS */ +#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ +#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group BGM26_LDMA_BitFields */ +/** @} End of group BGM26_LDMA */ +/** @} End of group Parts */ + +#endif // BGM26_LDMA_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldmaxbar.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldmaxbar.h new file mode 100644 index 0000000000..98d73b4683 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldmaxbar.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LDMAXBAR register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LDMAXBAR_H +#define BGM26_LDMAXBAR_H +#define LDMAXBAR_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_LDMAXBAR LDMAXBAR + * @{ + * @brief BGM26 LDMAXBAR Register Declaration. + *****************************************************************************/ + +/** LDMAXBAR CH Register Group Declaration. */ +typedef struct ldmaxbar_ch_typedef{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +} LDMAXBAR_CH_TypeDef; + +/** LDMAXBAR Register Declaration. */ +typedef struct ldmaxbar_typedef{ + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMAXBAR_TypeDef; +/** @} End of group BGM26_LDMAXBAR */ + +/**************************************************************************//** + * @addtogroup BGM26_LDMAXBAR + * @{ + * @defgroup BGM26_LDMAXBAR_BitFields LDMAXBAR Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMAXBAR IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ + +/* Bit fields for LDMAXBAR CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ + +/** @} End of group BGM26_LDMAXBAR_BitFields */ +/** @} End of group BGM26_LDMAXBAR */ +/** @} End of group Parts */ + +#endif // BGM26_LDMAXBAR_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldmaxbar_defines.h new file mode 100644 index 0000000000..34b77f1469 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ldmaxbar_defines.h @@ -0,0 +1,259 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LDMA XBAR channel request soruce definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LDMAXBAR_DEFINES_H +#define BGM26_LDMAXBAR_DEFINES_H + +// Module source selection indices +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x0000000fUL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000010UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x00000011UL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 0x00000012UL /**< Mode VDAC1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 0x00000013UL /**< Mode EUSART2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3 0x00000014UL /**< Mode EUSART3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 0x00000015UL /**< Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART2 0x00000016UL /**< Mode USART2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5 0x00000017UL /**< Mode TIMER5 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6 0x00000018UL /**< Mode TIMER6 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7 0x00000019UL /**< Mode TIMER7 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER8 0x0000001aUL /**< Mode TIMER8 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER9 0x0000001bUL /**< Mode TIMER9 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C2 0x0000001cUL /**< Mode I2C2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C3 0x0000001dUL /**< Mode I2C3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LCD 0x0000001eUL /**< Mode LCD for LDMAXBAR_CH_REQSEL */ + +// Shifted source selection indices +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 << 16) /**< Shifted Mode VDAC1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 << 16) /**< Shifted Mode EUSART2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3 << 16) /**< Shifted Mode EUSART3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted Mode USART2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5 << 16) /**< Shifted Mode TIMER5 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6 << 16) /**< Shifted Mode TIMER6 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7 << 16) /**< Shifted Mode TIMER7 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER8 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER8 << 16) /**< Shifted Mode TIMER8 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER9 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER9 << 16) /**< Shifted Mode TIMER9 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C2 << 16) /**< Shifted Mode I2C2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C3 << 16) /**< Shifted Mode I2C3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LCD (_LDMAXBAR_CH_REQSEL_SOURCESEL_LCD << 16) /**< Shifted Mode LCD for LDMAXBAR_CH_REQSEL */ + +// Module signal selection indices +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ 0x00000000UL /** Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ 0x00000001UL /** Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL 0x00000000UL /** Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL 0x00000001UL /** Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL 0x00000000UL /** Mode EUSART3RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL 0x00000001UL /** Mode EUSART3TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /** Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000001UL /** Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL 0x00000002UL /** Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000003UL /** Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000004UL /** Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /** Mode USART2RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT 0x00000001UL /** Mode USART2RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT 0x00000002UL /** Mode USART2TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000003UL /** Mode USART2TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL 0x00000004UL /** Mode USART2TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 0x00000000UL /** Mode TIMER5CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 0x00000001UL /** Mode TIMER5CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 0x00000002UL /** Mode TIMER5CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF 0x00000003UL /** Mode TIMER5UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 0x00000000UL /** Mode TIMER6CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 0x00000001UL /** Mode TIMER6CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 0x00000002UL /** Mode TIMER6CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF 0x00000003UL /** Mode TIMER6UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 0x00000000UL /** Mode TIMER7CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 0x00000001UL /** Mode TIMER7CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 0x00000002UL /** Mode TIMER7CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF 0x00000003UL /** Mode TIMER7UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC0 0x00000000UL /** Mode TIMER8CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC1 0x00000001UL /** Mode TIMER8CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC2 0x00000002UL /** Mode TIMER8CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8UFOF 0x00000003UL /** Mode TIMER8UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC0 0x00000000UL /** Mode TIMER9CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC1 0x00000001UL /** Mode TIMER9CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC2 0x00000002UL /** Mode TIMER9CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9UFOF 0x00000003UL /** Mode TIMER9UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C2RXDATAV 0x00000000UL /** Mode I2C2RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C2TXBL 0x00000001UL /** Mode I2C2TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C3RXDATAV 0x00000000UL /** Mode I2C3RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C3TXBL 0x00000001UL /** Mode I2C3TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LCD 0x00000000UL /** Mode LCD for LDMAXBAR_CH_REQSEL**/ + +// Shifted Module signal selection indices +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL << 0) /** Shifted Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL << 0) /** Shifted Mode EUSART3RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL << 0) /** Shifted Mode EUSART3TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /** Shifted Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /** Shifted Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL << 0) /** Shifted Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /** Shifted Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /** Shifted Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /** Shifted Mode USART2RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT << 0) /** Shifted Mode USART2RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT << 0) /** Shifted Mode USART2TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /** Shifted Mode USART2TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL << 0) /** Shifted Mode USART2TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 << 0) /** Shifted Mode TIMER5CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 << 0) /** Shifted Mode TIMER5CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 << 0) /** Shifted Mode TIMER5CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF << 0) /** Shifted Mode TIMER5UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 << 0) /** Shifted Mode TIMER6CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 << 0) /** Shifted Mode TIMER6CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 << 0) /** Shifted Mode TIMER6CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF << 0) /** Shifted Mode TIMER6UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 << 0) /** Shifted Mode TIMER7CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 << 0) /** Shifted Mode TIMER7CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 << 0) /** Shifted Mode TIMER7CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF << 0) /** Shifted Mode TIMER7UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC0 << 0) /** Shifted Mode TIMER8CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC1 << 0) /** Shifted Mode TIMER8CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8CC2 << 0) /** Shifted Mode TIMER8CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER8UFOF << 0) /** Shifted Mode TIMER8UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC0 << 0) /** Shifted Mode TIMER9CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC1 << 0) /** Shifted Mode TIMER9CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9CC2 << 0) /** Shifted Mode TIMER9CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER9UFOF << 0) /** Shifted Mode TIMER9UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C2RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C2RXDATAV << 0) /** Shifted Mode I2C2RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C2TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C2TXBL << 0) /** Shifted Mode I2C2TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C3RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C3RXDATAV << 0) /** Shifted Mode I2C3RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C3TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C3TXBL << 0) /** Shifted Mode I2C3TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ + +#endif // BGM26_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_letimer.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_letimer.h new file mode 100644 index 0000000000..a12d199764 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_letimer.h @@ -0,0 +1,534 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LETIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LETIMER_H +#define BGM26_LETIMER_H +#define LETIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_LETIMER LETIMER + * @{ + * @brief BGM26 LETIMER Register Declaration. + *****************************************************************************/ + +/** LETIMER Register Declaration. */ +typedef struct letimer_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED5[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +} LETIMER_TypeDef; +/** @} End of group BGM26_LETIMER */ + +/**************************************************************************//** + * @addtogroup BGM26_LETIMER + * @{ + * @defgroup BGM26_LETIMER_BitFields LETIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ + +/* Bit fields for LETIMER EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ + +/* Bit fields for LETIMER SWRST */ +#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ +#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ + +/* Bit fields for LETIMER TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER LOCK */ +#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ +#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ + +/** @} End of group BGM26_LETIMER_BitFields */ +/** @} End of group BGM26_LETIMER */ +/** @} End of group Parts */ + +#endif // BGM26_LETIMER_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_lfrco.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lfrco.h new file mode 100644 index 0000000000..60ca96abdc --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lfrco.h @@ -0,0 +1,304 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LFRCO_H +#define BGM26_LFRCO_H +#define LFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_LFRCO LFRCO + * @{ + * @brief BGM26 LFRCO Register Declaration. + *****************************************************************************/ + +/** LFRCO Register Declaration. */ +typedef struct lfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED3[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED7[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED11[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ +} LFRCO_TypeDef; +/** @} End of group BGM26_LFRCO */ + +/**************************************************************************//** + * @addtogroup BGM26_LFRCO + * @{ + * @defgroup BGM26_LFRCO_BitFields LFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFRCO IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ + +/* Bit fields for LFRCO CTRL */ +#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ +#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ +#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ + +/* Bit fields for LFRCO STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ + +/* Bit fields for LFRCO IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ +#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ +#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ +#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ +#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ +#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ +#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ + +/* Bit fields for LFRCO IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ +#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ +#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ +#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ +#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ +#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ +#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ + +/* Bit fields for LFRCO LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ + +/* Bit fields for LFRCO CFG */ +#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ +#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ +#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ + +/* Bit fields for LFRCO NOMCAL */ +#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ +#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ + +/* Bit fields for LFRCO NOMCALINV */ +#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ +#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ + +/* Bit fields for LFRCO CMD */ +#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ +#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ +#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ + +/** @} End of group BGM26_LFRCO_BitFields */ +/** @} End of group BGM26_LFRCO */ +/** @} End of group Parts */ + +#endif // BGM26_LFRCO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_lfxo.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lfxo.h new file mode 100644 index 0000000000..b50ff8ea12 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_lfxo.h @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file + * @brief BGM26 LFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_LFXO_H +#define BGM26_LFXO_H +#define LFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_LFXO LFXO + * @{ + * @brief BGM26 LFXO Register Declaration. + *****************************************************************************/ + +/** LFXO Register Declaration. */ +typedef struct lfxo_typedef{ + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFXO_TypeDef; +/** @} End of group BGM26_LFXO */ + +/**************************************************************************//** + * @addtogroup BGM26_LFXO + * @{ + * @defgroup BGM26_LFXO_BitFields LFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFXO IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ + +/* Bit fields for LFXO CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ + +/* Bit fields for LFXO CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ + +/* Bit fields for LFXO STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ + +/* Bit fields for LFXO CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ + +/* Bit fields for LFXO IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ + +/* Bit fields for LFXO IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ + +/* Bit fields for LFXO SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ + +/* Bit fields for LFXO LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ + +/** @} End of group BGM26_LFXO_BitFields */ +/** @} End of group BGM26_LFXO */ +/** @} End of group Parts */ + +#endif // BGM26_LFXO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_mailbox.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_mailbox.h new file mode 100644 index 0000000000..b8514fba9e --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_mailbox.h @@ -0,0 +1,140 @@ +/**************************************************************************//** + * @file + * @brief BGM26 MAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_MAILBOX_H +#define BGM26_MAILBOX_H +#define MAILBOX_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_MAILBOX MAILBOX + * @{ + * @brief BGM26 MAILBOX Register Declaration. + *****************************************************************************/ + +/** MAILBOX MSGPTRS Register Group Declaration. */ +typedef struct mailbox_msgptrs_typedef{ + __IOM uint32_t MSGPTR; /**< Message Pointer */ +} MAILBOX_MSGPTRS_TypeDef; + +/** MAILBOX Register Declaration. */ +typedef struct mailbox_typedef{ + MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ + uint32_t RESERVED0[12U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + uint32_t RESERVED1[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ + uint32_t RESERVED2[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ + uint32_t RESERVED4[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ + uint32_t RESERVED6[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ +} MAILBOX_TypeDef; +/** @} End of group BGM26_MAILBOX */ + +/**************************************************************************//** + * @addtogroup BGM26_MAILBOX + * @{ + * @defgroup BGM26_MAILBOX_BitFields MAILBOX Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MAILBOX MSGPTR */ +#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ +#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ + +/* Bit fields for MAILBOX IF */ +#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ +#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ + +/* Bit fields for MAILBOX IEN */ +#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ +#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ + +/** @} End of group BGM26_MAILBOX_BitFields */ +/** @} End of group BGM26_MAILBOX */ +/** @} End of group Parts */ + +#endif // BGM26_MAILBOX_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_mpahbram.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_mpahbram.h new file mode 100644 index 0000000000..e0da76052c --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_mpahbram.h @@ -0,0 +1,325 @@ +/**************************************************************************//** + * @file + * @brief BGM26 MPAHBRAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_MPAHBRAM_H +#define BGM26_MPAHBRAM_H +#define MPAHBRAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_MPAHBRAM MPAHBRAM + * @{ + * @brief BGM26 MPAHBRAM Register Declaration. + *****************************************************************************/ + +/** MPAHBRAM Register Declaration. */ +typedef struct mpahbram_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t CTRL; /**< Control register */ + __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t CTRL_SET; /**< Control register */ + __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_SET; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_SET; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED3[7U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t CTRL_CLR; /**< Control register */ + __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_CLR; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_CLR; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED6[7U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t CTRL_TGL; /**< Control register */ + __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_TGL; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_TGL; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} MPAHBRAM_TypeDef; +/** @} End of group BGM26_MPAHBRAM */ + +/**************************************************************************//** + * @addtogroup BGM26_MPAHBRAM + * @{ + * @defgroup BGM26_MPAHBRAM_BitFields MPAHBRAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MPAHBRAM IPVERSION */ +#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ + +/* Bit fields for MPAHBRAM CMD */ +#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_MASK 0x0000000FUL /**< Mask for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR2 (0x1UL << 2) /**< Clear ECCERRADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_SHIFT 2 /**< Shift value for MPAHBRAM_CLEARECCADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_MASK 0x4UL /**< Bit mask for MPAHBRAM_CLEARECCADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR3 (0x1UL << 3) /**< Clear ECCERRADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_SHIFT 3 /**< Shift value for MPAHBRAM_CLEARECCADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_MASK 0x8UL /**< Bit mask for MPAHBRAM_CLEARECCADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ + +/* Bit fields for MPAHBRAM CTRL */ +#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_MASK 0x0000007FUL /**< Mask for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ +#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ +#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 0x00000003UL /**< Mode PORT2 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 0x00000004UL /**< Mode PORT3 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 << 3) /**< Shifted mode PORT2 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 << 3) /**< Shifted mode PORT3 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ + +/* Bit fields for MPAHBRAM ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ +#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ + +/* Bit fields for MPAHBRAM ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ +#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ + +/* Bit fields for MPAHBRAM ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR2 */ +#define MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR2*/ + +/* Bit fields for MPAHBRAM ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR3 */ +#define MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR3*/ + +/* Bit fields for MPAHBRAM ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_MASK 0x0000000FUL /**< Mask for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ +#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ +#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P2 (0x1UL << 2) /**< Multiple ECC errors on AHB port 2 */ +#define _MPAHBRAM_ECCMERRIND_P2_SHIFT 2 /**< Shift value for MPAHBRAM_P2 */ +#define _MPAHBRAM_ECCMERRIND_P2_MASK 0x4UL /**< Bit mask for MPAHBRAM_P2 */ +#define _MPAHBRAM_ECCMERRIND_P2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P2_DEFAULT (_MPAHBRAM_ECCMERRIND_P2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P3 (0x1UL << 3) /**< Multiple ECC errors on AHB port 2 */ +#define _MPAHBRAM_ECCMERRIND_P3_SHIFT 3 /**< Shift value for MPAHBRAM_P3 */ +#define _MPAHBRAM_ECCMERRIND_P3_MASK 0x8UL /**< Bit mask for MPAHBRAM_P3 */ +#define _MPAHBRAM_ECCMERRIND_P3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P3_DEFAULT (_MPAHBRAM_ECCMERRIND_P3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ + +/* Bit fields for MPAHBRAM IF */ +#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IF_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IF_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR1B_DEFAULT (_MPAHBRAM_IF_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IF_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IF_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR1B_DEFAULT (_MPAHBRAM_IF_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IF_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IF_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR2B_DEFAULT (_MPAHBRAM_IF_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IF_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IF_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR2B_DEFAULT (_MPAHBRAM_IF_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ + +/* Bit fields for MPAHBRAM IEN */ +#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IEN_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IEN_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IEN_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IEN_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IEN_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IEN_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IEN_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IEN_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ + +/** @} End of group BGM26_MPAHBRAM_BitFields */ +/** @} End of group BGM26_MPAHBRAM */ +/** @} End of group Parts */ + +#endif // BGM26_MPAHBRAM_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_msc.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_msc.h new file mode 100644 index 0000000000..969d15d037 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_msc.h @@ -0,0 +1,635 @@ +/**************************************************************************//** + * @file + * @brief BGM26 MSC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_MSC_H +#define BGM26_MSC_H +#define MSC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_MSC MSC + * @{ + * @brief BGM26 MSC Register Declaration. + *****************************************************************************/ + +/** MSC Register Declaration. */ +typedef struct msc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED2[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCKWORD4; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCKWORD5; /**< Main space page 160-191 lock word */ + __IOM uint32_t PAGELOCKWORD6; /**< Main space page 192-223 lock word */ + __IOM uint32_t PAGELOCKWORD7; /**< Main space page 224- 255 lock word */ + __IOM uint32_t PAGELOCKWORD8; /**< Main space page 256-287 lock word */ + __IOM uint32_t PAGELOCKWORD9; /**< Main space page 288-319 lock word */ + __IOM uint32_t PAGELOCKWORD10; /**< Main space page 320-351 lock word */ + __IOM uint32_t PAGELOCKWORD11; /**< Main space page 352-383 lock word */ + __IOM uint32_t PAGELOCKWORD12; /**< Main space page 384-399 lock word */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + uint32_t RESERVED4[4U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[4U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[9U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[909U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED14[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCKWORD4_SET; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCKWORD5_SET; /**< Main space page 160-191 lock word */ + __IOM uint32_t PAGELOCKWORD6_SET; /**< Main space page 192-223 lock word */ + __IOM uint32_t PAGELOCKWORD7_SET; /**< Main space page 224- 255 lock word */ + __IOM uint32_t PAGELOCKWORD8_SET; /**< Main space page 256-287 lock word */ + __IOM uint32_t PAGELOCKWORD9_SET; /**< Main space page 288-319 lock word */ + __IOM uint32_t PAGELOCKWORD10_SET; /**< Main space page 320-351 lock word */ + __IOM uint32_t PAGELOCKWORD11_SET; /**< Main space page 352-383 lock word */ + __IOM uint32_t PAGELOCKWORD12_SET; /**< Main space page 384-399 lock word */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + uint32_t RESERVED17[4U]; /**< Reserved for future use */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + uint32_t RESERVED19[4U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[9U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[909U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED26[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCKWORD4_CLR; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCKWORD5_CLR; /**< Main space page 160-191 lock word */ + __IOM uint32_t PAGELOCKWORD6_CLR; /**< Main space page 192-223 lock word */ + __IOM uint32_t PAGELOCKWORD7_CLR; /**< Main space page 224- 255 lock word */ + __IOM uint32_t PAGELOCKWORD8_CLR; /**< Main space page 256-287 lock word */ + __IOM uint32_t PAGELOCKWORD9_CLR; /**< Main space page 288-319 lock word */ + __IOM uint32_t PAGELOCKWORD10_CLR; /**< Main space page 320-351 lock word */ + __IOM uint32_t PAGELOCKWORD11_CLR; /**< Main space page 352-383 lock word */ + __IOM uint32_t PAGELOCKWORD12_CLR; /**< Main space page 384-399 lock word */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + uint32_t RESERVED28[4U]; /**< Reserved for future use */ + uint32_t RESERVED29[4U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + uint32_t RESERVED31[4U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[9U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + uint32_t RESERVED35[909U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED38[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCKWORD4_TGL; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCKWORD5_TGL; /**< Main space page 160-191 lock word */ + __IOM uint32_t PAGELOCKWORD6_TGL; /**< Main space page 192-223 lock word */ + __IOM uint32_t PAGELOCKWORD7_TGL; /**< Main space page 224- 255 lock word */ + __IOM uint32_t PAGELOCKWORD8_TGL; /**< Main space page 256-287 lock word */ + __IOM uint32_t PAGELOCKWORD9_TGL; /**< Main space page 288-319 lock word */ + __IOM uint32_t PAGELOCKWORD10_TGL; /**< Main space page 320-351 lock word */ + __IOM uint32_t PAGELOCKWORD11_TGL; /**< Main space page 352-383 lock word */ + __IOM uint32_t PAGELOCKWORD12_TGL; /**< Main space page 384-399 lock word */ + uint32_t RESERVED39[3U]; /**< Reserved for future use */ + uint32_t RESERVED40[4U]; /**< Reserved for future use */ + uint32_t RESERVED41[4U]; /**< Reserved for future use */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + uint32_t RESERVED43[4U]; /**< Reserved for future use */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + uint32_t RESERVED45[9U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ +} MSC_TypeDef; +/** @} End of group BGM26_MSC */ + +/**************************************************************************//** + * @addtogroup BGM26_MSC + * @{ + * @defgroup BGM26_MSC_BitFields MSC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ + +/* Bit fields for MSC RDATACTRL */ +#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ +#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ +#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFB0100FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ +#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON0 (0x1UL << 24) /**< Flash Bank 0 Power On Status */ +#define _MSC_STATUS_PWRON0_SHIFT 24 /**< Shift value for MSC_PWRON0 */ +#define _MSC_STATUS_PWRON0_MASK 0x1000000UL /**< Bit mask for MSC_PWRON0 */ +#define _MSC_STATUS_PWRON0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON0_DEFAULT (_MSC_STATUS_PWRON0_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON1 (0x1UL << 25) /**< Flash Bank 1 Power On Status */ +#define _MSC_STATUS_PWRON1_SHIFT 25 /**< Shift value for MSC_PWRON1 */ +#define _MSC_STATUS_PWRON1_MASK 0x2000000UL /**< Bit mask for MSC_PWRON1 */ +#define _MSC_STATUS_PWRON1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON1_DEFAULT (_MSC_STATUS_PWRON1_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ + +/* Bit fields for MSC PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ + +/* Bit fields for MSC PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ + +/* Bit fields for MSC PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ + +/* Bit fields for MSC PAGELOCK2 */ +#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ +#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ + +/* Bit fields for MSC PAGELOCK3 */ +#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ +#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ + +/* Bit fields for MSC PAGELOCKWORD4 */ +#define _MSC_PAGELOCKWORD4_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD4 */ +#define _MSC_PAGELOCKWORD4_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD4 */ +#define _MSC_PAGELOCKWORD4_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD4_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD4_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD4 */ +#define MSC_PAGELOCKWORD4_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD4_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD4 */ + +/* Bit fields for MSC PAGELOCKWORD5 */ +#define _MSC_PAGELOCKWORD5_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD5 */ +#define _MSC_PAGELOCKWORD5_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD5 */ +#define _MSC_PAGELOCKWORD5_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD5_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD5_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD5 */ +#define MSC_PAGELOCKWORD5_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD5_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD5 */ + +/* Bit fields for MSC PAGELOCKWORD6 */ +#define _MSC_PAGELOCKWORD6_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD6 */ +#define _MSC_PAGELOCKWORD6_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD6 */ +#define _MSC_PAGELOCKWORD6_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD6_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD6_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD6 */ +#define MSC_PAGELOCKWORD6_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD6_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD6 */ + +/* Bit fields for MSC PAGELOCKWORD7 */ +#define _MSC_PAGELOCKWORD7_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD7 */ +#define _MSC_PAGELOCKWORD7_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD7 */ +#define _MSC_PAGELOCKWORD7_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD7_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD7_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD7 */ +#define MSC_PAGELOCKWORD7_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD7_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD7 */ + +/* Bit fields for MSC PAGELOCKWORD8 */ +#define _MSC_PAGELOCKWORD8_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD8 */ +#define _MSC_PAGELOCKWORD8_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD8 */ +#define _MSC_PAGELOCKWORD8_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD8_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD8_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD8 */ +#define MSC_PAGELOCKWORD8_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD8_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD8 */ + +/* Bit fields for MSC PAGELOCKWORD9 */ +#define _MSC_PAGELOCKWORD9_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD9 */ +#define _MSC_PAGELOCKWORD9_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD9 */ +#define _MSC_PAGELOCKWORD9_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD9_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD9_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD9 */ +#define MSC_PAGELOCKWORD9_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD9_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD9 */ + +/* Bit fields for MSC PAGELOCKWORD10 */ +#define _MSC_PAGELOCKWORD10_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD10 */ +#define _MSC_PAGELOCKWORD10_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD10 */ +#define _MSC_PAGELOCKWORD10_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD10_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD10_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD10 */ +#define MSC_PAGELOCKWORD10_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD10_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD10 */ + +/* Bit fields for MSC PAGELOCKWORD11 */ +#define _MSC_PAGELOCKWORD11_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD11 */ +#define _MSC_PAGELOCKWORD11_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCKWORD11 */ +#define _MSC_PAGELOCKWORD11_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD11_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD11_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD11 */ +#define MSC_PAGELOCKWORD11_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD11_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD11 */ + +/* Bit fields for MSC PAGELOCKWORD12 */ +#define _MSC_PAGELOCKWORD12_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCKWORD12 */ +#define _MSC_PAGELOCKWORD12_MASK 0x0000FFFFUL /**< Mask for MSC_PAGELOCKWORD12 */ +#define _MSC_PAGELOCKWORD12_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD12_LOCKBIT_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCKWORD12_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCKWORD12 */ +#define MSC_PAGELOCKWORD12_LOCKBIT_DEFAULT (_MSC_PAGELOCKWORD12_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCKWORD12 */ + +/** @} End of group BGM26_MSC_BitFields */ +/** @} End of group BGM26_MSC */ +/** @} End of group Parts */ + +#endif // BGM26_MSC_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_pcnt.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_pcnt.h new file mode 100644 index 0000000000..ec4c1562f3 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_pcnt.h @@ -0,0 +1,482 @@ +/**************************************************************************//** + * @file + * @brief BGM26 PCNT register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_PCNT_H +#define BGM26_PCNT_H +#define PCNT_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_PCNT PCNT + * @{ + * @brief BGM26 PCNT Register Declaration. + *****************************************************************************/ + +/** PCNT Register Declaration. */ +typedef struct pcnt_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_SET; /**< Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED1[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_CLR; /**< Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED2[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_TGL; /**< Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} PCNT_TypeDef; +/** @} End of group BGM26_PCNT */ + +/**************************************************************************//** + * @addtogroup BGM26_PCNT + * @{ + * @defgroup BGM26_PCNT_BitFields PCNT Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT IPVERSION */ +#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ +#define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ + +/* Bit fields for PCNT EN */ +#define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */ +#define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */ +#define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */ +#define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */ +#define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */ +#define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */ + +/* Bit fields for PCNT SWRST */ +#define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */ +#define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */ +#define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */ + +/* Bit fields for PCNT CFG */ +#define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */ +#define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */ +#define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */ +#define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */ +#define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */ +#define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */ +#define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */ +#define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */ +#define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */ +#define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */ +#define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */ +#define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */ +#define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */ +#define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */ +#define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */ +#define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ +#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ +#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ +#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT OVSCTRL */ +#define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */ +#define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */ +#define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT LOCK */ +#define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */ +#define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */ + +/** @} End of group BGM26_PCNT_BitFields */ +/** @} End of group BGM26_PCNT */ +/** @} End of group Parts */ + +#endif // BGM26_PCNT_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_prs.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_prs.h new file mode 100644 index 0000000000..8ed84ab75f --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_prs.h @@ -0,0 +1,2217 @@ +/**************************************************************************//** + * @file + * @brief BGM26 PRS register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_PRS_H +#define BGM26_PRS_H +#define PRS_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_PRS PRS + * @{ + * @brief BGM26 PRS Register Declaration. + *****************************************************************************/ + +/** PRS ASYNC_CH Register Group Declaration. */ +typedef struct prs_async_ch_typedef{ + __IOM uint32_t CTRL; /**< Async Channel Control Register */ +} PRS_ASYNC_CH_TypeDef; + +/** PRS SYNC_CH Register Group Declaration. */ +typedef struct prs_sync_ch_typedef{ + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +} PRS_SYNC_CH_TypeDef; + +/** PRS Register Declaration. */ +typedef struct prs_typedef{ + __IM uint32_t IPVERSION; /**< PRS IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART3_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ + uint32_t RESERVED2[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART2_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART2_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART2_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART2_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[842U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART3_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_SET; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */ + uint32_t RESERVED10[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART2_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART2_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART2_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART2_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[842U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART3_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_CLR; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */ + uint32_t RESERVED18[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART2_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART2_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART2_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART2_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[842U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART3_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART3_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_TGL; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */ + uint32_t RESERVED26[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER5_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER6_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER7_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER8_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER9_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED28[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART2_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART2_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART2_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART2_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} PRS_TypeDef; +/** @} End of group BGM26_PRS */ + +/**************************************************************************//** + * @addtogroup BGM26_PRS + * @{ + * @defgroup BGM26_PRS_BitFields PRS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ + +/* Bit fields for PRS ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ + +/* Bit fields for PRS ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ + +/* Bit fields for PRS ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_ASYNC_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_ASYNC_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_ASYNC_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH12VAL_DEFAULT (_PRS_ASYNC_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 current value */ +#define _PRS_ASYNC_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_ASYNC_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_ASYNC_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH13VAL_DEFAULT (_PRS_ASYNC_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 current value */ +#define _PRS_ASYNC_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_ASYNC_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_ASYNC_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH14VAL_DEFAULT (_PRS_ASYNC_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 current value */ +#define _PRS_ASYNC_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_ASYNC_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_ASYNC_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH15VAL_DEFAULT (_PRS_ASYNC_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ + +/* Bit fields for PRS SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ + +/* Bit fields for PRS ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ + +/* Bit fields for PRS SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ + +/* Bit fields for PRS CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ + +/* Bit fields for PRS CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ + +/* Bit fields for PRS CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_CLK */ +#define PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_RX */ +#define PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART2_TRIGGER */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define _PRS_CONSUMER_EUSART2_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_TRIGGER */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART3_CLK */ +#define _PRS_CONSUMER_EUSART3_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART3_CLK */ +#define _PRS_CONSUMER_EUSART3_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART3_CLK */ +#define _PRS_CONSUMER_EUSART3_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART3_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART3_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART3_CLK */ +#define PRS_CONSUMER_EUSART3_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART3_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART3_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART3_RX */ +#define _PRS_CONSUMER_EUSART3_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART3_RX */ +#define _PRS_CONSUMER_EUSART3_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART3_RX */ +#define _PRS_CONSUMER_EUSART3_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART3_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART3_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART3_RX */ +#define PRS_CONSUMER_EUSART3_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART3_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART3_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART3_TRIGGER */ +#define _PRS_CONSUMER_EUSART3_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART3_TRIGGER*/ +#define _PRS_CONSUMER_EUSART3_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART3_TRIGGER */ +#define _PRS_CONSUMER_EUSART3_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART3_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART3_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART3_TRIGGER*/ +#define PRS_CONSUMER_EUSART3_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART3_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART3_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ + +/* Bit fields for PRS CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ + +/* Bit fields for PRS CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_PAEN */ +#define PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_PAEN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ +#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ +#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ + +/* Bit fields for PRS CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ + +/* Bit fields for PRS CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ + +/* Bit fields for PRS CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ + +/* Bit fields for PRS CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ +#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ +#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ + +/* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ +#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ + +/* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER5_CC0 */ +#define _PRS_CONSUMER_TIMER5_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER5_CC0 */ +#define _PRS_CONSUMER_TIMER5_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER5_CC0 */ +#define _PRS_CONSUMER_TIMER5_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_CC0 */ +#define PRS_CONSUMER_TIMER5_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_CC0*/ +#define _PRS_CONSUMER_TIMER5_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_CC0 */ +#define PRS_CONSUMER_TIMER5_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER5_CC1 */ +#define _PRS_CONSUMER_TIMER5_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER5_CC1 */ +#define _PRS_CONSUMER_TIMER5_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER5_CC1 */ +#define _PRS_CONSUMER_TIMER5_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_CC1 */ +#define PRS_CONSUMER_TIMER5_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_CC1*/ +#define _PRS_CONSUMER_TIMER5_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_CC1 */ +#define PRS_CONSUMER_TIMER5_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER5_CC2 */ +#define _PRS_CONSUMER_TIMER5_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER5_CC2 */ +#define _PRS_CONSUMER_TIMER5_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER5_CC2 */ +#define _PRS_CONSUMER_TIMER5_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_CC2 */ +#define PRS_CONSUMER_TIMER5_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_CC2*/ +#define _PRS_CONSUMER_TIMER5_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER5_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_CC2 */ +#define PRS_CONSUMER_TIMER5_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER5_DTI */ +#define _PRS_CONSUMER_TIMER5_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER5_DTI */ +#define _PRS_CONSUMER_TIMER5_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER5_DTI */ +#define _PRS_CONSUMER_TIMER5_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_DTI */ +#define PRS_CONSUMER_TIMER5_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER5_DTIFS1 */ +#define _PRS_CONSUMER_TIMER5_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER5_DTIFS1*/ +#define _PRS_CONSUMER_TIMER5_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER5_DTIFS1 */ +#define _PRS_CONSUMER_TIMER5_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_DTIFS1 */ +#define PRS_CONSUMER_TIMER5_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER5_DTIFS2 */ +#define _PRS_CONSUMER_TIMER5_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER5_DTIFS2*/ +#define _PRS_CONSUMER_TIMER5_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER5_DTIFS2 */ +#define _PRS_CONSUMER_TIMER5_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER5_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER5_DTIFS2 */ +#define PRS_CONSUMER_TIMER5_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER5_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER5_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER6_CC0 */ +#define _PRS_CONSUMER_TIMER6_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER6_CC0 */ +#define _PRS_CONSUMER_TIMER6_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER6_CC0 */ +#define _PRS_CONSUMER_TIMER6_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_CC0 */ +#define PRS_CONSUMER_TIMER6_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_CC0*/ +#define _PRS_CONSUMER_TIMER6_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_CC0 */ +#define PRS_CONSUMER_TIMER6_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER6_CC1 */ +#define _PRS_CONSUMER_TIMER6_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER6_CC1 */ +#define _PRS_CONSUMER_TIMER6_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER6_CC1 */ +#define _PRS_CONSUMER_TIMER6_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_CC1 */ +#define PRS_CONSUMER_TIMER6_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_CC1*/ +#define _PRS_CONSUMER_TIMER6_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_CC1 */ +#define PRS_CONSUMER_TIMER6_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER6_CC2 */ +#define _PRS_CONSUMER_TIMER6_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER6_CC2 */ +#define _PRS_CONSUMER_TIMER6_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER6_CC2 */ +#define _PRS_CONSUMER_TIMER6_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_CC2 */ +#define PRS_CONSUMER_TIMER6_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_CC2*/ +#define _PRS_CONSUMER_TIMER6_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER6_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_CC2 */ +#define PRS_CONSUMER_TIMER6_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER6_DTI */ +#define _PRS_CONSUMER_TIMER6_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER6_DTI */ +#define _PRS_CONSUMER_TIMER6_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER6_DTI */ +#define _PRS_CONSUMER_TIMER6_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_DTI */ +#define PRS_CONSUMER_TIMER6_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER6_DTIFS1 */ +#define _PRS_CONSUMER_TIMER6_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER6_DTIFS1*/ +#define _PRS_CONSUMER_TIMER6_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER6_DTIFS1 */ +#define _PRS_CONSUMER_TIMER6_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_DTIFS1 */ +#define PRS_CONSUMER_TIMER6_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER6_DTIFS2 */ +#define _PRS_CONSUMER_TIMER6_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER6_DTIFS2*/ +#define _PRS_CONSUMER_TIMER6_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER6_DTIFS2 */ +#define _PRS_CONSUMER_TIMER6_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER6_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER6_DTIFS2 */ +#define PRS_CONSUMER_TIMER6_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER6_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER6_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER7_CC0 */ +#define _PRS_CONSUMER_TIMER7_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER7_CC0 */ +#define _PRS_CONSUMER_TIMER7_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER7_CC0 */ +#define _PRS_CONSUMER_TIMER7_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_CC0 */ +#define PRS_CONSUMER_TIMER7_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_CC0*/ +#define _PRS_CONSUMER_TIMER7_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_CC0 */ +#define PRS_CONSUMER_TIMER7_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER7_CC1 */ +#define _PRS_CONSUMER_TIMER7_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER7_CC1 */ +#define _PRS_CONSUMER_TIMER7_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER7_CC1 */ +#define _PRS_CONSUMER_TIMER7_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_CC1 */ +#define PRS_CONSUMER_TIMER7_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_CC1*/ +#define _PRS_CONSUMER_TIMER7_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_CC1 */ +#define PRS_CONSUMER_TIMER7_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER7_CC2 */ +#define _PRS_CONSUMER_TIMER7_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER7_CC2 */ +#define _PRS_CONSUMER_TIMER7_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER7_CC2 */ +#define _PRS_CONSUMER_TIMER7_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_CC2 */ +#define PRS_CONSUMER_TIMER7_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_CC2*/ +#define _PRS_CONSUMER_TIMER7_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER7_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_CC2 */ +#define PRS_CONSUMER_TIMER7_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER7_DTI */ +#define _PRS_CONSUMER_TIMER7_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER7_DTI */ +#define _PRS_CONSUMER_TIMER7_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER7_DTI */ +#define _PRS_CONSUMER_TIMER7_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_DTI */ +#define PRS_CONSUMER_TIMER7_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER7_DTIFS1 */ +#define _PRS_CONSUMER_TIMER7_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER7_DTIFS1*/ +#define _PRS_CONSUMER_TIMER7_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER7_DTIFS1 */ +#define _PRS_CONSUMER_TIMER7_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_DTIFS1 */ +#define PRS_CONSUMER_TIMER7_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER7_DTIFS2 */ +#define _PRS_CONSUMER_TIMER7_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER7_DTIFS2*/ +#define _PRS_CONSUMER_TIMER7_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER7_DTIFS2 */ +#define _PRS_CONSUMER_TIMER7_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER7_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER7_DTIFS2 */ +#define PRS_CONSUMER_TIMER7_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER7_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER7_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER8_CC0 */ +#define _PRS_CONSUMER_TIMER8_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER8_CC0 */ +#define _PRS_CONSUMER_TIMER8_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER8_CC0 */ +#define _PRS_CONSUMER_TIMER8_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_CC0 */ +#define PRS_CONSUMER_TIMER8_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_CC0*/ +#define _PRS_CONSUMER_TIMER8_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_CC0 */ +#define PRS_CONSUMER_TIMER8_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER8_CC1 */ +#define _PRS_CONSUMER_TIMER8_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER8_CC1 */ +#define _PRS_CONSUMER_TIMER8_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER8_CC1 */ +#define _PRS_CONSUMER_TIMER8_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_CC1 */ +#define PRS_CONSUMER_TIMER8_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_CC1*/ +#define _PRS_CONSUMER_TIMER8_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_CC1 */ +#define PRS_CONSUMER_TIMER8_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER8_CC2 */ +#define _PRS_CONSUMER_TIMER8_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER8_CC2 */ +#define _PRS_CONSUMER_TIMER8_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER8_CC2 */ +#define _PRS_CONSUMER_TIMER8_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_CC2 */ +#define PRS_CONSUMER_TIMER8_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_CC2*/ +#define _PRS_CONSUMER_TIMER8_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER8_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_CC2 */ +#define PRS_CONSUMER_TIMER8_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER8_DTI */ +#define _PRS_CONSUMER_TIMER8_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER8_DTI */ +#define _PRS_CONSUMER_TIMER8_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER8_DTI */ +#define _PRS_CONSUMER_TIMER8_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_DTI */ +#define PRS_CONSUMER_TIMER8_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER8_DTIFS1 */ +#define _PRS_CONSUMER_TIMER8_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER8_DTIFS1*/ +#define _PRS_CONSUMER_TIMER8_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER8_DTIFS1 */ +#define _PRS_CONSUMER_TIMER8_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_DTIFS1 */ +#define PRS_CONSUMER_TIMER8_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER8_DTIFS2 */ +#define _PRS_CONSUMER_TIMER8_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER8_DTIFS2*/ +#define _PRS_CONSUMER_TIMER8_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER8_DTIFS2 */ +#define _PRS_CONSUMER_TIMER8_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER8_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER8_DTIFS2 */ +#define PRS_CONSUMER_TIMER8_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER8_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER8_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER9_CC0 */ +#define _PRS_CONSUMER_TIMER9_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER9_CC0 */ +#define _PRS_CONSUMER_TIMER9_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER9_CC0 */ +#define _PRS_CONSUMER_TIMER9_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_CC0 */ +#define PRS_CONSUMER_TIMER9_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_CC0*/ +#define _PRS_CONSUMER_TIMER9_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_CC0 */ +#define PRS_CONSUMER_TIMER9_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER9_CC1 */ +#define _PRS_CONSUMER_TIMER9_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER9_CC1 */ +#define _PRS_CONSUMER_TIMER9_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER9_CC1 */ +#define _PRS_CONSUMER_TIMER9_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_CC1 */ +#define PRS_CONSUMER_TIMER9_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_CC1*/ +#define _PRS_CONSUMER_TIMER9_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_CC1 */ +#define PRS_CONSUMER_TIMER9_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER9_CC2 */ +#define _PRS_CONSUMER_TIMER9_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER9_CC2 */ +#define _PRS_CONSUMER_TIMER9_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER9_CC2 */ +#define _PRS_CONSUMER_TIMER9_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_CC2 */ +#define PRS_CONSUMER_TIMER9_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_CC2*/ +#define _PRS_CONSUMER_TIMER9_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER9_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_CC2 */ +#define PRS_CONSUMER_TIMER9_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER9_DTI */ +#define _PRS_CONSUMER_TIMER9_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER9_DTI */ +#define _PRS_CONSUMER_TIMER9_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER9_DTI */ +#define _PRS_CONSUMER_TIMER9_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_DTI */ +#define PRS_CONSUMER_TIMER9_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER9_DTIFS1 */ +#define _PRS_CONSUMER_TIMER9_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER9_DTIFS1*/ +#define _PRS_CONSUMER_TIMER9_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER9_DTIFS1 */ +#define _PRS_CONSUMER_TIMER9_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_DTIFS1 */ +#define PRS_CONSUMER_TIMER9_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER9_DTIFS2 */ +#define _PRS_CONSUMER_TIMER9_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER9_DTIFS2*/ +#define _PRS_CONSUMER_TIMER9_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER9_DTIFS2 */ +#define _PRS_CONSUMER_TIMER9_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER9_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER9_DTIFS2 */ +#define PRS_CONSUMER_TIMER9_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER9_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER9_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ + +/* Bit fields for PRS CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ + +/* Bit fields for PRS CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ + +/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_CLK */ +#define PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_CLK*/ + +/* Bit fields for PRS CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_IR */ +#define PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_IR*/ + +/* Bit fields for PRS CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_RX */ +#define PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_RX*/ + +/* Bit fields for PRS CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_TRIGGER*/ +#define _PRS_CONSUMER_USART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ +#define PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_USART2_CLK */ +#define _PRS_CONSUMER_USART2_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART2_CLK */ +#define _PRS_CONSUMER_USART2_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART2_CLK */ +#define _PRS_CONSUMER_USART2_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART2_CLK */ +#define PRS_CONSUMER_USART2_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART2_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART2_CLK*/ + +/* Bit fields for PRS CONSUMER_USART2_IR */ +#define _PRS_CONSUMER_USART2_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART2_IR */ +#define _PRS_CONSUMER_USART2_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART2_IR */ +#define _PRS_CONSUMER_USART2_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART2_IR */ +#define PRS_CONSUMER_USART2_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART2_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART2_IR*/ + +/* Bit fields for PRS CONSUMER_USART2_RX */ +#define _PRS_CONSUMER_USART2_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART2_RX */ +#define _PRS_CONSUMER_USART2_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART2_RX */ +#define _PRS_CONSUMER_USART2_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART2_RX */ +#define PRS_CONSUMER_USART2_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART2_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART2_RX*/ + +/* Bit fields for PRS CONSUMER_USART2_TRIGGER */ +#define _PRS_CONSUMER_USART2_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART2_TRIGGER*/ +#define _PRS_CONSUMER_USART2_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART2_TRIGGER */ +#define _PRS_CONSUMER_USART2_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART2_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART2_TRIGGER*/ +#define PRS_CONSUMER_USART2_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART2_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART2_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ +#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ +#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ + +/** @} End of group BGM26_PRS_BitFields */ +/** @} End of group BGM26_PRS */ +/** @} End of group Parts */ + +#endif // BGM26_PRS_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_prs_signals.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_prs_signals.h new file mode 100644 index 0000000000..ce803208c2 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_prs_signals.h @@ -0,0 +1,1309 @@ +/**************************************************************************//** + * @file + * @brief BGM26 PRS register signal bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_PRS_SIGNALS_H +#define BGM26_PRS_SIGNALS_H + +/** Synchronous signal sources enumeration: */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000007UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000008UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 (0x00000009UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 (0x0000000aUL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 (0x0000000bUL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 (0x0000000cUL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 (0x0000000dUL) + +/** Synchronous signal sources enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 << 8) + +/** Synchronous signals enumeration: */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER5UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER5OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER6UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER6OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER7UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER7OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER8UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER8OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER9UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER9OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC2 (0x00000004UL) + +/** Synchronous signals enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER5UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER5UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER5OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER5OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER6UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER6UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER6OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER6OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER7UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER7UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER7OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER7OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER8UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER8UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER8OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER8OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER9UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER9UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER9OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER9OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC2 << 0) + +/** Synchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_SYNC_VDAC0_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC) +#define PRS_SYNC_VDAC0_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC) +#define PRS_SYNC_VDAC1_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC) +#define PRS_SYNC_VDAC1_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC) +#define PRS_SYNC_TIMER5_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER5UF) +#define PRS_SYNC_TIMER5_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER5OF) +#define PRS_SYNC_TIMER5_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC0) +#define PRS_SYNC_TIMER5_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC1) +#define PRS_SYNC_TIMER5_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER5CC2) +#define PRS_SYNC_TIMER6_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER6UF) +#define PRS_SYNC_TIMER6_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER6OF) +#define PRS_SYNC_TIMER6_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC0) +#define PRS_SYNC_TIMER6_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC1) +#define PRS_SYNC_TIMER6_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER6CC2) +#define PRS_SYNC_TIMER7_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER7UF) +#define PRS_SYNC_TIMER7_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER7OF) +#define PRS_SYNC_TIMER7_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC0) +#define PRS_SYNC_TIMER7_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC1) +#define PRS_SYNC_TIMER7_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER7CC2) +#define PRS_SYNC_TIMER8_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER8UF) +#define PRS_SYNC_TIMER8_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER8OF) +#define PRS_SYNC_TIMER8_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC0) +#define PRS_SYNC_TIMER8_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC1) +#define PRS_SYNC_TIMER8_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER8CC2) +#define PRS_SYNC_TIMER9_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER9UF) +#define PRS_SYNC_TIMER9_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER9OF) +#define PRS_SYNC_TIMER9_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC0) +#define PRS_SYNC_TIMER9_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC1) +#define PRS_SYNC_TIMER9_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER9CC2) + +/** Asynchronous signal sources enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x00000008UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x00000009UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (0x0000000bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (0x0000000cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (0x0000000dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (0x0000000eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x0000000fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x00000010UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x00000011UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (0x00000012UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000013UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (0x00000014UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000015UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LCD (0x00000016UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000017UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000018UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x00000019UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (0x0000001aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000021UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000022UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000023UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000024UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000025UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000026UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000027UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000028UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x00000029UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x0000002fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000030UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000031UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000032UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000033UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000034UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 (0x00000035UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 (0x00000036UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 (0x00000037UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 (0x00000038UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 (0x00000039UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (0x0000003aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 (0x0000003bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 (0x0000003cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 (0x0000003dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x0000003eUL) + +/** Asynchronous signal sources enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LCD (_PRS_ASYNC_CH_CTRL_SOURCESEL_LCD << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 << 8) + +/** Asynchronous signals enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH12 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH13 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH14 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH15 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART2CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART2IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART2RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART2RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART2TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART2TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2IRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXFL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TX (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXC (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3IRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXFL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TX (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXC (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) + +/** Asynchronous signals enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH12 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH12 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH13 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH13 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH14 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH14 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH15 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH15 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART2CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART2CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART2IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART2IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART2RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART2RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART2RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART2RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART2TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART2TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART2TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART2TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2CS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2IRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2IRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3CS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3IRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3IRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) + +/** Asynchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) +#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) +#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) +#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) +#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) +#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) +#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) +#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) +#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) +#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) +#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) +#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) +#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) +#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) +#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) +#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) +#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) +#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) +#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) +#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) +#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) +#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) +#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) +#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) +#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) +#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) +#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) +#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) +#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) +#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) +#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) +#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) +#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) +#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) +#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) +#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) +#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) +#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) +#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) +#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) +#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) +#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) +#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) +#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) +#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) +#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) +#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) +#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) +#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) +#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) +#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) +#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) +#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) +#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) +#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) +#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) +#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) +#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) +#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) +#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) +#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) +#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) +#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) +#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) +#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) +#define PRS_ASYNC_MODEMH_SI (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI) +#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) +#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) +#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) +#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) +#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) +#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) +#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) +#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) +#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) +#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) +#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) +#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) +#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) +#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) +#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) +#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) +#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) +#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) +#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) +#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) +#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) +#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) +#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) +#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) +#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) +#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) +#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) +#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) +#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) +#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) +#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) +#define PRS_ASYNC_PRS_ASYNCH12 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH12) +#define PRS_ASYNC_PRS_ASYNCH13 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH13) +#define PRS_ASYNC_PRS_ASYNCH14 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH14) +#define PRS_ASYNC_PRS_ASYNCH15 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH15) +#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) +#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) +#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) +#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) +#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) +#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) +#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) +#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) +#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) +#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA) +#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID) +#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT) +#define PRS_ASYNC_ACMP1_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT) +#define PRS_ASYNC_PCNT0_DIR (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR) +#define PRS_ASYNC_PCNT0_UFOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF) +#define PRS_ASYNC_SYSRTC0_GRP0OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0) +#define PRS_ASYNC_SYSRTC0_GRP0OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1) +#define PRS_ASYNC_SYSRTC0_GRP1OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0) +#define PRS_ASYNC_SYSRTC0_GRP1OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1) +#define PRS_ASYNC_HFXO0L_STATUS (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS) +#define PRS_ASYNC_HFXO0L_STATUS1 (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1) +#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS) +#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX) +#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS) +#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV) +#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX) +#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC) +#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL) +#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL) +#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS) +#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX) +#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS) +#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV) +#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX) +#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC) +#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL) +#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL) +#define PRS_ASYNC_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF) +#define PRS_ASYNC_VDAC0L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC) +#define PRS_ASYNC_VDAC0L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM) +#define PRS_ASYNC_VDAC0L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM) +#define PRS_ASYNC_VDAC0L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC) +#define PRS_ASYNC_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF) +#define PRS_ASYNC_VDAC1L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM) +#define PRS_ASYNC_VDAC1L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM) +#define PRS_ASYNC_VDAC1L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC) +#define PRS_ASYNC_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF) +#define PRS_ASYNC_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF) +#define PRS_ASYNC_VDAC1L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC) +#define PRS_ASYNC_TIMER5_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5UF) +#define PRS_ASYNC_TIMER5_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5OF) +#define PRS_ASYNC_TIMER5_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC0) +#define PRS_ASYNC_TIMER5_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC1) +#define PRS_ASYNC_TIMER5_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER5CC2) +#define PRS_ASYNC_TIMER6_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6UF) +#define PRS_ASYNC_TIMER6_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6OF) +#define PRS_ASYNC_TIMER6_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC0) +#define PRS_ASYNC_TIMER6_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC1) +#define PRS_ASYNC_TIMER6_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER6CC2) +#define PRS_ASYNC_TIMER7_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7UF) +#define PRS_ASYNC_TIMER7_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7OF) +#define PRS_ASYNC_TIMER7_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC0) +#define PRS_ASYNC_TIMER7_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC1) +#define PRS_ASYNC_TIMER7_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER7CC2) +#define PRS_ASYNC_TIMER8_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8UF) +#define PRS_ASYNC_TIMER8_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8OF) +#define PRS_ASYNC_TIMER8_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC0) +#define PRS_ASYNC_TIMER8_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC1) +#define PRS_ASYNC_TIMER8_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER8 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER8CC2) +#define PRS_ASYNC_TIMER9_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9UF) +#define PRS_ASYNC_TIMER9_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9OF) +#define PRS_ASYNC_TIMER9_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC0) +#define PRS_ASYNC_TIMER9_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC1) +#define PRS_ASYNC_TIMER9_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER9 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER9CC2) +#define PRS_ASYNC_USART1_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS) +#define PRS_ASYNC_USART1_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX) +#define PRS_ASYNC_USART1_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS) +#define PRS_ASYNC_USART1_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA) +#define PRS_ASYNC_USART1_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX) +#define PRS_ASYNC_USART1_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC) +#define PRS_ASYNC_USART2_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 | PRS_ASYNC_CH_CTRL_SIGSEL_USART2CS) +#define PRS_ASYNC_USART2_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 | PRS_ASYNC_CH_CTRL_SIGSEL_USART2IRTX) +#define PRS_ASYNC_USART2_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 | PRS_ASYNC_CH_CTRL_SIGSEL_USART2RTS) +#define PRS_ASYNC_USART2_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 | PRS_ASYNC_CH_CTRL_SIGSEL_USART2RXDATA) +#define PRS_ASYNC_USART2_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 | PRS_ASYNC_CH_CTRL_SIGSEL_USART2TX) +#define PRS_ASYNC_USART2_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART2 | PRS_ASYNC_CH_CTRL_SIGSEL_USART2TXC) +#define PRS_ASYNC_EUSART2_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2CS) +#define PRS_ASYNC_EUSART2_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2IRDATX) +#define PRS_ASYNC_EUSART2_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RTS) +#define PRS_ASYNC_EUSART2_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXDATAV) +#define PRS_ASYNC_EUSART2_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2RXFL) +#define PRS_ASYNC_EUSART2_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TX) +#define PRS_ASYNC_EUSART2_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXC) +#define PRS_ASYNC_EUSART2_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2TXFL) +#define PRS_ASYNC_EUSART3_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3CS) +#define PRS_ASYNC_EUSART3_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3IRDATX) +#define PRS_ASYNC_EUSART3_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RTS) +#define PRS_ASYNC_EUSART3_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXDATAV) +#define PRS_ASYNC_EUSART3_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3RXFL) +#define PRS_ASYNC_EUSART3_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TX) +#define PRS_ASYNC_EUSART3_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXC) +#define PRS_ASYNC_EUSART3_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART3 | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART3TXFL) +#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) +#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) +#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) + +/** + * Asynchronous signals and sources combined and aligned with register bit fields + * without the '_ASYNCH_' infix in order for backward compatibility: + */ +#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) +#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) +#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) +#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) +#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) +#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) +#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) +#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) +#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) +#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) +#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) +#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) +#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) +#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) +#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) +#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) +#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) +#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) +#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) +#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) +#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) +#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) +#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) +#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) +#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) +#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) +#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) +#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) +#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) +#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) +#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) +#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) +#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) +#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) +#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) +#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) +#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) +#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) +#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) +#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) +#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) +#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) +#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) +#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) +#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) +#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) +#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) +#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) +#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) +#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) +#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) +#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) +#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) +#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) +#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) +#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) +#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) +#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) +#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) +#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) +#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) +#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) +#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) +#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) +#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) +#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) +#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) +#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) +#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) +#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) +#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) +#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) +#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) +#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) +#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) +#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) +#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) +#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) +#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) +#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) +#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) +#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) +#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) +#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) +#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) +#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) +#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) +#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) +#define PRS_MODEMH_SI (PRS_ASYNC_MODEMH_SI) +#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) +#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) +#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) +#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) +#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) +#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) +#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) +#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) +#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) +#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) +#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) +#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) +#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) +#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) +#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) +#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) +#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) +#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) +#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) +#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) +#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) +#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) +#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) +#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) +#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) +#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) +#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) +#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) +#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) +#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) +#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) +#define PRS_PRS_ASYNCH12 (PRS_ASYNC_PRS_ASYNCH12) +#define PRS_PRS_ASYNCH13 (PRS_ASYNC_PRS_ASYNCH13) +#define PRS_PRS_ASYNCH14 (PRS_ASYNC_PRS_ASYNCH14) +#define PRS_PRS_ASYNCH15 (PRS_ASYNC_PRS_ASYNCH15) +#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) +#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) +#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) +#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) +#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) +#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) +#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) +#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) +#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) +#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA) +#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID) +#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) +#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) +#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) +#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) +#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) +#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT) +#define PRS_ACMP1_OUT (PRS_ASYNC_ACMP1_OUT) +#define PRS_PCNT0_DIR (PRS_ASYNC_PCNT0_DIR) +#define PRS_PCNT0_UFOF (PRS_ASYNC_PCNT0_UFOF) +#define PRS_SYSRTC0_GRP0OUT0 (PRS_ASYNC_SYSRTC0_GRP0OUT0) +#define PRS_SYSRTC0_GRP0OUT1 (PRS_ASYNC_SYSRTC0_GRP0OUT1) +#define PRS_SYSRTC0_GRP1OUT0 (PRS_ASYNC_SYSRTC0_GRP1OUT0) +#define PRS_SYSRTC0_GRP1OUT1 (PRS_ASYNC_SYSRTC0_GRP1OUT1) +#define PRS_HFXO0L_STATUS (PRS_ASYNC_HFXO0L_STATUS) +#define PRS_HFXO0L_STATUS1 (PRS_ASYNC_HFXO0L_STATUS1) +#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS) +#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX) +#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS) +#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV) +#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX) +#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC) +#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL) +#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL) +#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS) +#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX) +#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS) +#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV) +#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX) +#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC) +#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL) +#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL) +#define PRS_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_VDAC0L_INTERNALTIMEROF) +#define PRS_VDAC0L_CH0DONEASYNC (PRS_ASYNC_VDAC0L_CH0DONEASYNC) +#define PRS_VDAC0L_CH1WARM (PRS_ASYNC_VDAC0L_CH1WARM) +#define PRS_VDAC0L_CH0WARM (PRS_ASYNC_VDAC0L_CH0WARM) +#define PRS_VDAC0L_CH1DONEASYNC (PRS_ASYNC_VDAC0L_CH1DONEASYNC) +#define PRS_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_VDAC0L_REFRESHTIMEROF) +#define PRS_VDAC1L_CH1WARM (PRS_ASYNC_VDAC1L_CH1WARM) +#define PRS_VDAC1L_CH0WARM (PRS_ASYNC_VDAC1L_CH0WARM) +#define PRS_VDAC1L_CH0DONEASYNC (PRS_ASYNC_VDAC1L_CH0DONEASYNC) +#define PRS_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_VDAC1L_REFRESHTIMEROF) +#define PRS_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_VDAC1L_INTERNALTIMEROF) +#define PRS_VDAC1L_CH1DONEASYNC (PRS_ASYNC_VDAC1L_CH1DONEASYNC) +#define PRS_TIMER5_UF (PRS_ASYNC_TIMER5_UF) +#define PRS_TIMER5_OF (PRS_ASYNC_TIMER5_OF) +#define PRS_TIMER5_CC0 (PRS_ASYNC_TIMER5_CC0) +#define PRS_TIMER5_CC1 (PRS_ASYNC_TIMER5_CC1) +#define PRS_TIMER5_CC2 (PRS_ASYNC_TIMER5_CC2) +#define PRS_TIMER6_UF (PRS_ASYNC_TIMER6_UF) +#define PRS_TIMER6_OF (PRS_ASYNC_TIMER6_OF) +#define PRS_TIMER6_CC0 (PRS_ASYNC_TIMER6_CC0) +#define PRS_TIMER6_CC1 (PRS_ASYNC_TIMER6_CC1) +#define PRS_TIMER6_CC2 (PRS_ASYNC_TIMER6_CC2) +#define PRS_TIMER7_UF (PRS_ASYNC_TIMER7_UF) +#define PRS_TIMER7_OF (PRS_ASYNC_TIMER7_OF) +#define PRS_TIMER7_CC0 (PRS_ASYNC_TIMER7_CC0) +#define PRS_TIMER7_CC1 (PRS_ASYNC_TIMER7_CC1) +#define PRS_TIMER7_CC2 (PRS_ASYNC_TIMER7_CC2) +#define PRS_TIMER8_UF (PRS_ASYNC_TIMER8_UF) +#define PRS_TIMER8_OF (PRS_ASYNC_TIMER8_OF) +#define PRS_TIMER8_CC0 (PRS_ASYNC_TIMER8_CC0) +#define PRS_TIMER8_CC1 (PRS_ASYNC_TIMER8_CC1) +#define PRS_TIMER8_CC2 (PRS_ASYNC_TIMER8_CC2) +#define PRS_TIMER9_UF (PRS_ASYNC_TIMER9_UF) +#define PRS_TIMER9_OF (PRS_ASYNC_TIMER9_OF) +#define PRS_TIMER9_CC0 (PRS_ASYNC_TIMER9_CC0) +#define PRS_TIMER9_CC1 (PRS_ASYNC_TIMER9_CC1) +#define PRS_TIMER9_CC2 (PRS_ASYNC_TIMER9_CC2) +#define PRS_USART1_CS (PRS_ASYNC_USART1_CS) +#define PRS_USART1_IRTX (PRS_ASYNC_USART1_IRTX) +#define PRS_USART1_RTS (PRS_ASYNC_USART1_RTS) +#define PRS_USART1_RXDATA (PRS_ASYNC_USART1_RXDATA) +#define PRS_USART1_TX (PRS_ASYNC_USART1_TX) +#define PRS_USART1_TXC (PRS_ASYNC_USART1_TXC) +#define PRS_USART2_CS (PRS_ASYNC_USART2_CS) +#define PRS_USART2_IRTX (PRS_ASYNC_USART2_IRTX) +#define PRS_USART2_RTS (PRS_ASYNC_USART2_RTS) +#define PRS_USART2_RXDATA (PRS_ASYNC_USART2_RXDATA) +#define PRS_USART2_TX (PRS_ASYNC_USART2_TX) +#define PRS_USART2_TXC (PRS_ASYNC_USART2_TXC) +#define PRS_EUSART2_CS (PRS_ASYNC_EUSART2_CS) +#define PRS_EUSART2_IRDATX (PRS_ASYNC_EUSART2_IRDATX) +#define PRS_EUSART2_RTS (PRS_ASYNC_EUSART2_RTS) +#define PRS_EUSART2_RXDATAV (PRS_ASYNC_EUSART2_RXDATAV) +#define PRS_EUSART2_RXFL (PRS_ASYNC_EUSART2_RXFL) +#define PRS_EUSART2_TX (PRS_ASYNC_EUSART2_TX) +#define PRS_EUSART2_TXC (PRS_ASYNC_EUSART2_TXC) +#define PRS_EUSART2_TXFL (PRS_ASYNC_EUSART2_TXFL) +#define PRS_EUSART3_CS (PRS_ASYNC_EUSART3_CS) +#define PRS_EUSART3_IRDATX (PRS_ASYNC_EUSART3_IRDATX) +#define PRS_EUSART3_RTS (PRS_ASYNC_EUSART3_RTS) +#define PRS_EUSART3_RXDATAV (PRS_ASYNC_EUSART3_RXDATAV) +#define PRS_EUSART3_RXFL (PRS_ASYNC_EUSART3_RXFL) +#define PRS_EUSART3_TX (PRS_ASYNC_EUSART3_TX) +#define PRS_EUSART3_TXC (PRS_ASYNC_EUSART3_TXC) +#define PRS_EUSART3_TXFL (PRS_ASYNC_EUSART3_TXFL) +#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) +#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) +#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif // BGM26_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_semailbox.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_semailbox.h new file mode 100644 index 0000000000..5024871e99 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_semailbox.h @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file + * @brief BGM26 SEMAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_SEMAILBOX_H +#define BGM26_SEMAILBOX_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_SEMAILBOX_HOST SEMAILBOX_HOST + * @{ + * @brief BGM26 SEMAILBOX_HOST Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_HOST Register Declaration. */ +typedef struct semailbox_host_typedef{ + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_HOST_TypeDef; +/** @} End of group BGM26_SEMAILBOX_HOST */ + +/**************************************************************************//** + * @addtogroup BGM26_SEMAILBOX_HOST + * @{ + * @defgroup BGM26_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ + +/* Bit fields for SEMAILBOX TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ + +/* Bit fields for SEMAILBOX RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ + +/* Bit fields for SEMAILBOX TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ + +/* Bit fields for SEMAILBOX RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ + +/* Bit fields for SEMAILBOX TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ + +/* Bit fields for SEMAILBOX RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ + +/* Bit fields for SEMAILBOX CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ + +/** @} End of group BGM26_SEMAILBOX_HOST_BitFields */ +/** @} End of group BGM26_SEMAILBOX_HOST */ +/**************************************************************************//** + * @defgroup BGM26_SEMAILBOX_APBSE SEMAILBOX_APBSE + * @{ + * @brief BGM26 SEMAILBOX_APBSE Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_APBSE Register Declaration. */ +typedef struct semailbox_apbse_typedef{ + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_APBSE_TypeDef; +/** @} End of group BGM26_SEMAILBOX_APBSE */ + +/**************************************************************************//** + * @addtogroup BGM26_SEMAILBOX_APBSE + * @{ + * @defgroup BGM26_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ + +/** @} End of group BGM26_SEMAILBOX_APBSE_BitFields */ +/** @} End of group BGM26_SEMAILBOX_APBSE */ +/** @} End of group Parts */ + +#endif // BGM26_SEMAILBOX_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_smu.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_smu.h new file mode 100644 index 0000000000..74f200b4f9 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_smu.h @@ -0,0 +1,1637 @@ +/**************************************************************************//** + * @file + * @brief BGM26 SMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_SMU_H +#define BGM26_SMU_H +#define SMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_SMU SMU + * @{ + * @brief BGM26 SMU Register Declaration. + *****************************************************************************/ + +/** SMU Register Declaration. */ +typedef struct smu_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control Settings */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< Privileged Access */ + __IOM uint32_t PPUPATD1; /**< Privileged Access */ + __IOM uint32_t PPUPATD2; /**< Privileged Access */ + uint32_t RESERVED2[5U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< Secure Access */ + __IOM uint32_t PPUSATD1; /**< Secure Access */ + __IOM uint32_t PPUSATD2; /**< Secure Access */ + uint32_t RESERVED3[53U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< Fault Status */ + __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ + __IOM uint32_t PPUPATD2_SET; /**< Privileged Access */ + uint32_t RESERVED13[5U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ + __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ + __IOM uint32_t PPUSATD2_SET; /**< Secure Access */ + uint32_t RESERVED14[53U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ + __IOM uint32_t PPUPATD2_CLR; /**< Privileged Access */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ + __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ + __IOM uint32_t PPUSATD2_CLR; /**< Secure Access */ + uint32_t RESERVED25[53U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ + __IOM uint32_t PPUPATD2_TGL; /**< Privileged Access */ + uint32_t RESERVED35[5U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ + __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ + __IOM uint32_t PPUSATD2_TGL; /**< Secure Access */ + uint32_t RESERVED36[53U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ +} SMU_TypeDef; +/** @} End of group BGM26_SMU */ + +/**************************************************************************//** + * @addtogroup BGM26_SMU + * @{ + * @defgroup BGM26_SMU_BitFields SMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ + +/* Bit fields for SMU STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ + +/* Bit fields for SMU LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 3) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 3 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x8UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_KEYSCAN (0x1UL << 10) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUPATD0_KEYSCAN_SHIFT 10 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUPATD0_KEYSCAN_MASK 0x400UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUPATD0_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_KEYSCAN_DEFAULT (_SMU_PPUPATD0_KEYSCAN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 11) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 11 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x800UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 12) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 12 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x1000UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 14) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 14 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x4000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 15) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 15 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x8000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 16) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 16 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x10000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 17) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 17 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x20000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 18) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 18 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x40000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 19) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 19 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x80000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 20) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 20 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x100000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 21) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 21 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x200000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER5 (0x1UL << 22) /**< TIMER5 Privileged Access */ +#define _SMU_PPUPATD0_TIMER5_SHIFT 22 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD0_TIMER5_MASK 0x400000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD0_TIMER5_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER5_DEFAULT (_SMU_PPUPATD0_TIMER5_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER6 (0x1UL << 23) /**< TIMER6 Privileged Access */ +#define _SMU_PPUPATD0_TIMER6_SHIFT 23 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD0_TIMER6_MASK 0x800000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD0_TIMER6_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER6_DEFAULT (_SMU_PPUPATD0_TIMER6_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER7 (0x1UL << 24) /**< TIMER7 Privileged Access */ +#define _SMU_PPUPATD0_TIMER7_SHIFT 24 /**< Shift value for SMU_TIMER7 */ +#define _SMU_PPUPATD0_TIMER7_MASK 0x1000000UL /**< Bit mask for SMU_TIMER7 */ +#define _SMU_PPUPATD0_TIMER7_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER7_DEFAULT (_SMU_PPUPATD0_TIMER7_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER8 (0x1UL << 25) /**< TIMER8 Privileged Access */ +#define _SMU_PPUPATD0_TIMER8_SHIFT 25 /**< Shift value for SMU_TIMER8 */ +#define _SMU_PPUPATD0_TIMER8_MASK 0x2000000UL /**< Bit mask for SMU_TIMER8 */ +#define _SMU_PPUPATD0_TIMER8_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER8_DEFAULT (_SMU_PPUPATD0_TIMER8_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER9 (0x1UL << 26) /**< TIMER9 Privileged Access */ +#define _SMU_PPUPATD0_TIMER9_SHIFT 26 /**< Shift value for SMU_TIMER9 */ +#define _SMU_PPUPATD0_TIMER9_MASK 0x4000000UL /**< Bit mask for SMU_TIMER9 */ +#define _SMU_PPUPATD0_TIMER9_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER9_DEFAULT (_SMU_PPUPATD0_TIMER9_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DMEM0 (0x1UL << 28) /**< DMEM0 Privileged Access */ +#define _SMU_PPUPATD0_DMEM0_SHIFT 28 /**< Shift value for SMU_DMEM0 */ +#define _SMU_PPUPATD0_DMEM0_MASK 0x10000000UL /**< Bit mask for SMU_DMEM0 */ +#define _SMU_PPUPATD0_DMEM0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DMEM0_DEFAULT (_SMU_PPUPATD0_DMEM0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DMEM1 (0x1UL << 29) /**< DMEM1 Privileged Access */ +#define _SMU_PPUPATD0_DMEM1_SHIFT 29 /**< Shift value for SMU_DMEM1 */ +#define _SMU_PPUPATD0_DMEM1_MASK 0x20000000UL /**< Bit mask for SMU_DMEM1 */ +#define _SMU_PPUPATD0_DMEM1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DMEM1_DEFAULT (_SMU_PPUPATD0_DMEM1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 30) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 30 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x40000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 31) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 31 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x80000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_BURAM (0x1UL << 0) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD1_BURAM_SHIFT 0 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD1_BURAM_MASK 0x1UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD1_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_BURAM_DEFAULT (_SMU_PPUPATD1_BURAM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_GPCRC (0x1UL << 1) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD1_GPCRC_SHIFT 1 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD1_GPCRC_MASK 0x2UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD1_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_GPCRC_DEFAULT (_SMU_PPUPATD1_GPCRC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART1 (0x1UL << 2) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD1_EUSART1_SHIFT 2 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD1_EUSART1_MASK 0x4UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART1_DEFAULT (_SMU_PPUPATD1_EUSART1_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART2 (0x1UL << 3) /**< EUSART2 Privileged Access */ +#define _SMU_PPUPATD1_EUSART2_SHIFT 3 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUPATD1_EUSART2_MASK 0x8UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUPATD1_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART2_DEFAULT (_SMU_PPUPATD1_EUSART2_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART3 (0x1UL << 4) /**< EUSART3 Privileged Access */ +#define _SMU_PPUPATD1_EUSART3_SHIFT 4 /**< Shift value for SMU_EUSART3 */ +#define _SMU_PPUPATD1_EUSART3_MASK 0x10UL /**< Bit mask for SMU_EUSART3 */ +#define _SMU_PPUPATD1_EUSART3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART3_DEFAULT (_SMU_PPUPATD1_EUSART3_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DCDC (0x1UL << 5) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD1_DCDC_SHIFT 5 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD1_DCDC_MASK 0x20UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DCDC_DEFAULT (_SMU_PPUPATD1_DCDC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HOSTMAILBOX (0x1UL << 6) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_HOSTMAILBOX_SHIFT 6 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD1_HOSTMAILBOX_MASK 0x40UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD1_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD1_HOSTMAILBOX_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 7) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD1_USART0_SHIFT 7 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 8) /**< USART1 Privileged Access */ +#define _SMU_PPUPATD1_USART1_SHIFT 8 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 9) /**< USART2 Privileged Access */ +#define _SMU_PPUPATD1_USART2_SHIFT 9 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC (0x1UL << 10) /**< SYSRTC Privileged Access */ +#define _SMU_PPUPATD1_SYSRTC_SHIFT 10 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_MASK 0x400UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC_DEFAULT (_SMU_PPUPATD1_SYSRTC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C1 (0x1UL << 11) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD1_I2C1_SHIFT 11 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD1_I2C1_MASK 0x800UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD1_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C1_DEFAULT (_SMU_PPUPATD1_I2C1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C2 (0x1UL << 12) /**< I2C2 Privileged Access */ +#define _SMU_PPUPATD1_I2C2_SHIFT 12 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD1_I2C2_MASK 0x1000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD1_I2C2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C2_DEFAULT (_SMU_PPUPATD1_I2C2_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C3 (0x1UL << 13) /**< I2C3 Privileged Access */ +#define _SMU_PPUPATD1_I2C3_SHIFT 13 /**< Shift value for SMU_I2C3 */ +#define _SMU_PPUPATD1_I2C3_MASK 0x2000UL /**< Bit mask for SMU_I2C3 */ +#define _SMU_PPUPATD1_I2C3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C3_DEFAULT (_SMU_PPUPATD1_I2C3_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD (0x1UL << 14) /**< LCD Privileged Access */ +#define _SMU_PPUPATD1_LCD_SHIFT 14 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_MASK 0x4000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD_DEFAULT (_SMU_PPUPATD1_LCD_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF (0x1UL << 15) /**< LCDRF Privileged Access */ +#define _SMU_PPUPATD1_LCDRF_SHIFT 15 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_MASK 0x8000UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF_DEFAULT (_SMU_PPUPATD1_LCDRF_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 16) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 16 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x10000UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 17) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 17 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x20000UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 18) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 18 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x40000UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 19) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 19 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x80000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 20) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 20 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x100000UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 21) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 21 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x200000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1 (0x1UL << 22) /**< ACMP1 Privileged Access */ +#define _SMU_PPUPATD1_ACMP1_SHIFT 22 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_MASK 0x400000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 23) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 23 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x800000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0 (0x1UL << 24) /**< VDAC0 Privileged Access */ +#define _SMU_PPUPATD1_VDAC0_SHIFT 24 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_MASK 0x1000000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC1 (0x1UL << 25) /**< VDAC1 Privileged Access */ +#define _SMU_PPUPATD1_VDAC1_SHIFT 25 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUPATD1_VDAC1_MASK 0x2000000UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUPATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC1_DEFAULT (_SMU_PPUPATD1_VDAC1_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT (0x1UL << 26) /**< PCNT Privileged Access */ +#define _SMU_PPUPATD1_PCNT_SHIFT 26 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_MASK 0x4000000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1 (0x1UL << 27) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUPATD1_HFRCO1_SHIFT 27 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_MASK 0x8000000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0 (0x1UL << 28) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD1_HFXO0_SHIFT 28 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_MASK 0x10000000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 29) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 29 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x20000000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 30) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 30 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x40000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 31) /**< WDOG1 Privileged Access */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 31 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x80000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x0000000FUL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x0000000FUL /**< Mask for SMU_PPUPATD2 */ +#define SMU_PPUPATD2_EUSART0 (0x1UL << 0) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD2_EUSART0_SHIFT 0 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD2_EUSART0_MASK 0x1UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD2_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD2 */ +#define SMU_PPUPATD2_EUSART0_DEFAULT (_SMU_PPUPATD2_EUSART0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD2 */ +#define SMU_PPUPATD2_SEMAILBOX (0x1UL << 1) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD2_SEMAILBOX_SHIFT 1 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD2_SEMAILBOX_MASK 0x2UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD2_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD2 */ +#define SMU_PPUPATD2_SEMAILBOX_DEFAULT (_SMU_PPUPATD2_SEMAILBOX_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD2 */ +#define SMU_PPUPATD2_AHBRADIO (0x1UL << 3) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD2_AHBRADIO_SHIFT 3 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD2_AHBRADIO_MASK 0x8UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD2_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD2 */ +#define SMU_PPUPATD2_AHBRADIO_DEFAULT (_SMU_PPUPATD2_AHBRADIO_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 3) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 3 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x8UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 5) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 7) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 8) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_KEYSCAN (0x1UL << 10) /**< KEYSCAN Secure Access */ +#define _SMU_PPUSATD0_KEYSCAN_SHIFT 10 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUSATD0_KEYSCAN_MASK 0x400UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUSATD0_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_KEYSCAN_DEFAULT (_SMU_PPUSATD0_KEYSCAN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 11) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 11 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x800UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 12) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 12 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x1000UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 13) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 14) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 14 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x4000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 15) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 15 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x8000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 16) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 16 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x10000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 17) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 17 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x20000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 18) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 18 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x40000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 19) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 19 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x80000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 20) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 20 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x100000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 21) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 21 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x200000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER5 (0x1UL << 22) /**< TIMER5 Secure Access */ +#define _SMU_PPUSATD0_TIMER5_SHIFT 22 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUSATD0_TIMER5_MASK 0x400000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUSATD0_TIMER5_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER5_DEFAULT (_SMU_PPUSATD0_TIMER5_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER6 (0x1UL << 23) /**< TIMER6 Secure Access */ +#define _SMU_PPUSATD0_TIMER6_SHIFT 23 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUSATD0_TIMER6_MASK 0x800000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUSATD0_TIMER6_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER6_DEFAULT (_SMU_PPUSATD0_TIMER6_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER7 (0x1UL << 24) /**< TIMER7 Secure Access */ +#define _SMU_PPUSATD0_TIMER7_SHIFT 24 /**< Shift value for SMU_TIMER7 */ +#define _SMU_PPUSATD0_TIMER7_MASK 0x1000000UL /**< Bit mask for SMU_TIMER7 */ +#define _SMU_PPUSATD0_TIMER7_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER7_DEFAULT (_SMU_PPUSATD0_TIMER7_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER8 (0x1UL << 25) /**< TIMER8 Secure Access */ +#define _SMU_PPUSATD0_TIMER8_SHIFT 25 /**< Shift value for SMU_TIMER8 */ +#define _SMU_PPUSATD0_TIMER8_MASK 0x2000000UL /**< Bit mask for SMU_TIMER8 */ +#define _SMU_PPUSATD0_TIMER8_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER8_DEFAULT (_SMU_PPUSATD0_TIMER8_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER9 (0x1UL << 26) /**< TIMER9 Secure Access */ +#define _SMU_PPUSATD0_TIMER9_SHIFT 26 /**< Shift value for SMU_TIMER9 */ +#define _SMU_PPUSATD0_TIMER9_MASK 0x4000000UL /**< Bit mask for SMU_TIMER9 */ +#define _SMU_PPUSATD0_TIMER9_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER9_DEFAULT (_SMU_PPUSATD0_TIMER9_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DMEM0 (0x1UL << 28) /**< DMEM0 Secure Access */ +#define _SMU_PPUSATD0_DMEM0_SHIFT 28 /**< Shift value for SMU_DMEM0 */ +#define _SMU_PPUSATD0_DMEM0_MASK 0x10000000UL /**< Bit mask for SMU_DMEM0 */ +#define _SMU_PPUSATD0_DMEM0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DMEM0_DEFAULT (_SMU_PPUSATD0_DMEM0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DMEM1 (0x1UL << 29) /**< DMEM1 Secure Access */ +#define _SMU_PPUSATD0_DMEM1_SHIFT 29 /**< Shift value for SMU_DMEM1 */ +#define _SMU_PPUSATD0_DMEM1_MASK 0x20000000UL /**< Bit mask for SMU_DMEM1 */ +#define _SMU_PPUSATD0_DMEM1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DMEM1_DEFAULT (_SMU_PPUSATD0_DMEM1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 30) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 30 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x40000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 31) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 31 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x80000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ + +/* Bit fields for SMU PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_BURAM (0x1UL << 0) /**< BURAM Secure Access */ +#define _SMU_PPUSATD1_BURAM_SHIFT 0 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD1_BURAM_MASK 0x1UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD1_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_BURAM_DEFAULT (_SMU_PPUSATD1_BURAM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_GPCRC (0x1UL << 1) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD1_GPCRC_SHIFT 1 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD1_GPCRC_MASK 0x2UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD1_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_GPCRC_DEFAULT (_SMU_PPUSATD1_GPCRC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART1 (0x1UL << 2) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD1_EUSART1_SHIFT 2 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD1_EUSART1_MASK 0x4UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART1_DEFAULT (_SMU_PPUSATD1_EUSART1_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART2 (0x1UL << 3) /**< EUSART2 Secure Access */ +#define _SMU_PPUSATD1_EUSART2_SHIFT 3 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUSATD1_EUSART2_MASK 0x8UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUSATD1_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART2_DEFAULT (_SMU_PPUSATD1_EUSART2_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART3 (0x1UL << 4) /**< EUSART3 Secure Access */ +#define _SMU_PPUSATD1_EUSART3_SHIFT 4 /**< Shift value for SMU_EUSART3 */ +#define _SMU_PPUSATD1_EUSART3_MASK 0x10UL /**< Bit mask for SMU_EUSART3 */ +#define _SMU_PPUSATD1_EUSART3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART3_DEFAULT (_SMU_PPUSATD1_EUSART3_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DCDC (0x1UL << 5) /**< DCDC Secure Access */ +#define _SMU_PPUSATD1_DCDC_SHIFT 5 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD1_DCDC_MASK 0x20UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DCDC_DEFAULT (_SMU_PPUSATD1_DCDC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HOSTMAILBOX (0x1UL << 6) /**< HOSTMAILBOX Secure Access */ +#define _SMU_PPUSATD1_HOSTMAILBOX_SHIFT 6 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD1_HOSTMAILBOX_MASK 0x40UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD1_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD1_HOSTMAILBOX_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_USART0 (0x1UL << 7) /**< USART0 Secure Access */ +#define _SMU_PPUSATD1_USART0_SHIFT 7 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD1_USART0_MASK 0x80UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD1_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_USART0_DEFAULT (_SMU_PPUSATD1_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_USART1 (0x1UL << 8) /**< USART1 Secure Access */ +#define _SMU_PPUSATD1_USART1_SHIFT 8 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUSATD1_USART1_MASK 0x100UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUSATD1_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_USART1_DEFAULT (_SMU_PPUSATD1_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_USART2 (0x1UL << 9) /**< USART2 Secure Access */ +#define _SMU_PPUSATD1_USART2_SHIFT 9 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUSATD1_USART2_MASK 0x200UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUSATD1_USART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_USART2_DEFAULT (_SMU_PPUSATD1_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC (0x1UL << 10) /**< SYSRTC Secure Access */ +#define _SMU_PPUSATD1_SYSRTC_SHIFT 10 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_MASK 0x400UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC_DEFAULT (_SMU_PPUSATD1_SYSRTC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C1 (0x1UL << 11) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD1_I2C1_SHIFT 11 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD1_I2C1_MASK 0x800UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD1_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C1_DEFAULT (_SMU_PPUSATD1_I2C1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C2 (0x1UL << 12) /**< I2C2 Secure Access */ +#define _SMU_PPUSATD1_I2C2_SHIFT 12 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUSATD1_I2C2_MASK 0x1000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUSATD1_I2C2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C2_DEFAULT (_SMU_PPUSATD1_I2C2_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C3 (0x1UL << 13) /**< I2C3 Secure Access */ +#define _SMU_PPUSATD1_I2C3_SHIFT 13 /**< Shift value for SMU_I2C3 */ +#define _SMU_PPUSATD1_I2C3_MASK 0x2000UL /**< Bit mask for SMU_I2C3 */ +#define _SMU_PPUSATD1_I2C3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C3_DEFAULT (_SMU_PPUSATD1_I2C3_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD (0x1UL << 14) /**< LCD Secure Access */ +#define _SMU_PPUSATD1_LCD_SHIFT 14 /**< Shift value for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_MASK 0x4000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD_DEFAULT (_SMU_PPUSATD1_LCD_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF (0x1UL << 15) /**< LCDRF Secure Access */ +#define _SMU_PPUSATD1_LCDRF_SHIFT 15 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_MASK 0x8000UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF_DEFAULT (_SMU_PPUSATD1_LCDRF_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 16) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 16 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x10000UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 17) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 17 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x20000UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 18) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 18 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x40000UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 19) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 19 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x80000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 20) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 20 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x100000UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 21) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 21 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x200000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1 (0x1UL << 22) /**< ACMP1 Secure Access */ +#define _SMU_PPUSATD1_ACMP1_SHIFT 22 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_MASK 0x400000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 23) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 23 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x800000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0 (0x1UL << 24) /**< VDAC0 Secure Access */ +#define _SMU_PPUSATD1_VDAC0_SHIFT 24 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_MASK 0x1000000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC1 (0x1UL << 25) /**< VDAC1 Secure Access */ +#define _SMU_PPUSATD1_VDAC1_SHIFT 25 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUSATD1_VDAC1_MASK 0x2000000UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUSATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC1_DEFAULT (_SMU_PPUSATD1_VDAC1_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT (0x1UL << 26) /**< PCNT Secure Access */ +#define _SMU_PPUSATD1_PCNT_SHIFT 26 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_MASK 0x4000000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1 (0x1UL << 27) /**< HFRCO1 Secure Access */ +#define _SMU_PPUSATD1_HFRCO1_SHIFT 27 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_MASK 0x8000000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0 (0x1UL << 28) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD1_HFXO0_SHIFT 28 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_MASK 0x10000000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 29) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 29 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x20000000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 30) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 30 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x40000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1 (0x1UL << 31) /**< WDOG1 Secure Access */ +#define _SMU_PPUSATD1_WDOG1_SHIFT 31 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_MASK 0x80000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ + +/* Bit fields for SMU PPUSATD2 */ +#define _SMU_PPUSATD2_RESETVALUE 0x0000000FUL /**< Default value for SMU_PPUSATD2 */ +#define _SMU_PPUSATD2_MASK 0x0000000FUL /**< Mask for SMU_PPUSATD2 */ +#define SMU_PPUSATD2_EUSART0 (0x1UL << 0) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD2_EUSART0_SHIFT 0 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD2_EUSART0_MASK 0x1UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD2_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD2 */ +#define SMU_PPUSATD2_EUSART0_DEFAULT (_SMU_PPUSATD2_EUSART0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD2 */ +#define SMU_PPUSATD2_SEMAILBOX (0x1UL << 1) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD2_SEMAILBOX_SHIFT 1 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD2_SEMAILBOX_MASK 0x2UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD2_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD2 */ +#define SMU_PPUSATD2_SEMAILBOX_DEFAULT (_SMU_PPUSATD2_SEMAILBOX_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD2 */ +#define SMU_PPUSATD2_AHBRADIO (0x1UL << 3) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD2_AHBRADIO_SHIFT 3 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD2_AHBRADIO_MASK 0x8UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD2_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD2 */ +#define SMU_PPUSATD2_AHBRADIO_DEFAULT (_SMU_PPUSATD2_AHBRADIO_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ + +/* Bit fields for SMU BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x000001FFUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< LDMA Privileged Mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 Privileged Mode */ +#define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 Privileged Mode */ +#define _SMU_BMPUPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA Privileged Mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ + +/* Bit fields for SMU BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x000001FFUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Secure Mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Secure Mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< LDMA Secure Mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 Secure Mode */ +#define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1 (0x1UL << 7) /**< RFECA1 Secure Mode */ +#define _SMU_BMPUSATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA Secure Mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ + +/* Bit fields for SMU BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ + +/* Bit fields for SMU BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ + +/* Bit fields for SMU ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ + +/* Bit fields for SMU ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ + +/* Bit fields for SMU ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ + +/* Bit fields for SMU ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ + +/* Bit fields for SMU ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ + +/* Bit fields for SMU ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ + +/** @} End of group BGM26_SMU_BitFields */ +/** @} End of group BGM26_SMU */ +/**************************************************************************//** + * @defgroup BGM26_SMU_CFGNS SMU_CFGNS + * @{ + * @brief BGM26 SMU_CFGNS Register Declaration. + *****************************************************************************/ + +/** SMU_CFGNS Register Declaration. */ +typedef struct smu_cfgns_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Status Register */ + __IOM uint32_t NSLOCK; /**< Lock Register */ + __IOM uint32_t NSIF; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD2; /**< Privileged Access */ + uint32_t RESERVED3[61U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Status Register */ + __IOM uint32_t NSLOCK_SET; /**< Lock Register */ + __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD2_SET; /**< Privileged Access */ + uint32_t RESERVED10[61U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Status Register */ + __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ + __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD2_CLR; /**< Privileged Access */ + uint32_t RESERVED17[61U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Status Register */ + __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ + __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD2_TGL; /**< Privileged Access */ + uint32_t RESERVED24[61U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ +} SMU_CFGNS_TypeDef; +/** @} End of group BGM26_SMU_CFGNS */ + +/**************************************************************************//** + * @addtogroup BGM26_SMU_CFGNS + * @{ + * @defgroup BGM26_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ + +/* Bit fields for SMU NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ + +/* Bit fields for SMU NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ + +/* Bit fields for SMU NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ + +/* Bit fields for SMU PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 3) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 3 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x8UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_KEYSCAN (0x1UL << 10) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUNSPATD0_KEYSCAN_SHIFT 10 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD0_KEYSCAN_MASK 0x400UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD0_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_KEYSCAN_DEFAULT (_SMU_PPUNSPATD0_KEYSCAN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 11) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 11 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x800UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 12) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 12 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x1000UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 13) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 14) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 14 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x4000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 15) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 15 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x8000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 16) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 16 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x10000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 17) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 17 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x20000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 18) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 18 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x40000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 19) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 19 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x80000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 20) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 20 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x100000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 21) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 21 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x200000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER5 (0x1UL << 22) /**< TIMER5 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER5_SHIFT 22 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUNSPATD0_TIMER5_MASK 0x400000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUNSPATD0_TIMER5_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER5_DEFAULT (_SMU_PPUNSPATD0_TIMER5_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER6 (0x1UL << 23) /**< TIMER6 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER6_SHIFT 23 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUNSPATD0_TIMER6_MASK 0x800000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUNSPATD0_TIMER6_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER6_DEFAULT (_SMU_PPUNSPATD0_TIMER6_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER7 (0x1UL << 24) /**< TIMER7 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER7_SHIFT 24 /**< Shift value for SMU_TIMER7 */ +#define _SMU_PPUNSPATD0_TIMER7_MASK 0x1000000UL /**< Bit mask for SMU_TIMER7 */ +#define _SMU_PPUNSPATD0_TIMER7_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER7_DEFAULT (_SMU_PPUNSPATD0_TIMER7_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER8 (0x1UL << 25) /**< TIMER8 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER8_SHIFT 25 /**< Shift value for SMU_TIMER8 */ +#define _SMU_PPUNSPATD0_TIMER8_MASK 0x2000000UL /**< Bit mask for SMU_TIMER8 */ +#define _SMU_PPUNSPATD0_TIMER8_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER8_DEFAULT (_SMU_PPUNSPATD0_TIMER8_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER9 (0x1UL << 26) /**< TIMER9 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER9_SHIFT 26 /**< Shift value for SMU_TIMER9 */ +#define _SMU_PPUNSPATD0_TIMER9_MASK 0x4000000UL /**< Bit mask for SMU_TIMER9 */ +#define _SMU_PPUNSPATD0_TIMER9_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER9_DEFAULT (_SMU_PPUNSPATD0_TIMER9_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DMEM0 (0x1UL << 28) /**< DMEM0 Privileged Access */ +#define _SMU_PPUNSPATD0_DMEM0_SHIFT 28 /**< Shift value for SMU_DMEM0 */ +#define _SMU_PPUNSPATD0_DMEM0_MASK 0x10000000UL /**< Bit mask for SMU_DMEM0 */ +#define _SMU_PPUNSPATD0_DMEM0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DMEM0_DEFAULT (_SMU_PPUNSPATD0_DMEM0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DMEM1 (0x1UL << 29) /**< DMEM1 Privileged Access */ +#define _SMU_PPUNSPATD0_DMEM1_SHIFT 29 /**< Shift value for SMU_DMEM1 */ +#define _SMU_PPUNSPATD0_DMEM1_MASK 0x20000000UL /**< Bit mask for SMU_DMEM1 */ +#define _SMU_PPUNSPATD0_DMEM1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DMEM1_DEFAULT (_SMU_PPUNSPATD0_DMEM1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 30) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 30 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x40000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 31) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 31 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x80000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ + +/* Bit fields for SMU PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_BURAM (0x1UL << 0) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD1_BURAM_SHIFT 0 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD1_BURAM_MASK 0x1UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD1_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_BURAM_DEFAULT (_SMU_PPUNSPATD1_BURAM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_GPCRC (0x1UL << 1) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD1_GPCRC_SHIFT 1 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD1_GPCRC_MASK 0x2UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD1_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_GPCRC_DEFAULT (_SMU_PPUNSPATD1_GPCRC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART1 (0x1UL << 2) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART1_SHIFT 2 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD1_EUSART1_MASK 0x4UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART1_DEFAULT (_SMU_PPUNSPATD1_EUSART1_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART2 (0x1UL << 3) /**< EUSART2 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART2_SHIFT 3 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUNSPATD1_EUSART2_MASK 0x8UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUNSPATD1_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART2_DEFAULT (_SMU_PPUNSPATD1_EUSART2_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART3 (0x1UL << 4) /**< EUSART3 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART3_SHIFT 4 /**< Shift value for SMU_EUSART3 */ +#define _SMU_PPUNSPATD1_EUSART3_MASK 0x10UL /**< Bit mask for SMU_EUSART3 */ +#define _SMU_PPUNSPATD1_EUSART3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART3_DEFAULT (_SMU_PPUNSPATD1_EUSART3_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DCDC (0x1UL << 5) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD1_DCDC_SHIFT 5 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD1_DCDC_MASK 0x20UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DCDC_DEFAULT (_SMU_PPUNSPATD1_DCDC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HOSTMAILBOX (0x1UL << 6) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_HOSTMAILBOX_SHIFT 6 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD1_HOSTMAILBOX_MASK 0x40UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD1_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD1_HOSTMAILBOX_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_USART0 (0x1UL << 7) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD1_USART0_SHIFT 7 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD1_USART0_MASK 0x80UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD1_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_USART0_DEFAULT (_SMU_PPUNSPATD1_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_USART1 (0x1UL << 8) /**< USART1 Privileged Access */ +#define _SMU_PPUNSPATD1_USART1_SHIFT 8 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUNSPATD1_USART1_MASK 0x100UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUNSPATD1_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_USART1_DEFAULT (_SMU_PPUNSPATD1_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_USART2 (0x1UL << 9) /**< USART2 Privileged Access */ +#define _SMU_PPUNSPATD1_USART2_SHIFT 9 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUNSPATD1_USART2_MASK 0x200UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUNSPATD1_USART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_USART2_DEFAULT (_SMU_PPUNSPATD1_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC (0x1UL << 10) /**< SYSRTC Privileged Access */ +#define _SMU_PPUNSPATD1_SYSRTC_SHIFT 10 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_MASK 0x400UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC_DEFAULT (_SMU_PPUNSPATD1_SYSRTC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C1 (0x1UL << 11) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C1_SHIFT 11 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD1_I2C1_MASK 0x800UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD1_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C1_DEFAULT (_SMU_PPUNSPATD1_I2C1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C2 (0x1UL << 12) /**< I2C2 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C2_SHIFT 12 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUNSPATD1_I2C2_MASK 0x1000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUNSPATD1_I2C2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C2_DEFAULT (_SMU_PPUNSPATD1_I2C2_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C3 (0x1UL << 13) /**< I2C3 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C3_SHIFT 13 /**< Shift value for SMU_I2C3 */ +#define _SMU_PPUNSPATD1_I2C3_MASK 0x2000UL /**< Bit mask for SMU_I2C3 */ +#define _SMU_PPUNSPATD1_I2C3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C3_DEFAULT (_SMU_PPUNSPATD1_I2C3_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD (0x1UL << 14) /**< LCD Privileged Access */ +#define _SMU_PPUNSPATD1_LCD_SHIFT 14 /**< Shift value for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_MASK 0x4000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD_DEFAULT (_SMU_PPUNSPATD1_LCD_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF (0x1UL << 15) /**< LCDRF Privileged Access */ +#define _SMU_PPUNSPATD1_LCDRF_SHIFT 15 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_MASK 0x8000UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF_DEFAULT (_SMU_PPUNSPATD1_LCDRF_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 16) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 16 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x10000UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 17) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 17 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x20000UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 18) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 18 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x40000UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 19) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 19 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x80000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 20) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 20 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x100000UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 21) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 21 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x200000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 22) /**< ACMP1 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP1_SHIFT 22 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_MASK 0x400000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 23) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 23 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x800000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 24) /**< VDAC0 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC0_SHIFT 24 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_MASK 0x1000000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC1 (0x1UL << 25) /**< VDAC1 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC1_SHIFT 25 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUNSPATD1_VDAC1_MASK 0x2000000UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUNSPATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC1_DEFAULT (_SMU_PPUNSPATD1_VDAC1_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT (0x1UL << 26) /**< PCNT Privileged Access */ +#define _SMU_PPUNSPATD1_PCNT_SHIFT 26 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_MASK 0x4000000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 27) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 27 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x8000000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 28) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD1_HFXO0_SHIFT 28 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_MASK 0x10000000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 29) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 29 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x20000000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 30) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 30 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x40000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 31) /**< WDOG1 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG1_SHIFT 31 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_MASK 0x80000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ + +/* Bit fields for SMU PPUNSPATD2 */ +#define _SMU_PPUNSPATD2_RESETVALUE 0x0000000FUL /**< Default value for SMU_PPUNSPATD2 */ +#define _SMU_PPUNSPATD2_MASK 0x0000000FUL /**< Mask for SMU_PPUNSPATD2 */ +#define SMU_PPUNSPATD2_EUSART0 (0x1UL << 0) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD2_EUSART0_SHIFT 0 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD2_EUSART0_MASK 0x1UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD2_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD2 */ +#define SMU_PPUNSPATD2_EUSART0_DEFAULT (_SMU_PPUNSPATD2_EUSART0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD2 */ +#define SMU_PPUNSPATD2_SEMAILBOX (0x1UL << 1) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD2_SEMAILBOX_SHIFT 1 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD2_SEMAILBOX_MASK 0x2UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD2_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD2 */ +#define SMU_PPUNSPATD2_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD2_SEMAILBOX_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD2 */ +#define SMU_PPUNSPATD2_AHBRADIO (0x1UL << 3) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD2_AHBRADIO_SHIFT 3 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD2_AHBRADIO_MASK 0x8UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD2_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD2 */ +#define SMU_PPUNSPATD2_AHBRADIO_DEFAULT (_SMU_PPUNSPATD2_AHBRADIO_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD2 */ + +/* Bit fields for SMU PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ + +/* Bit fields for SMU BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x000001FFUL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< LDMA Privileged Mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 Privileged Mode */ +#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 Privileged Mode */ +#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA Privileged Mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ + +/** @} End of group BGM26_SMU_CFGNS_BitFields */ +/** @} End of group BGM26_SMU_CFGNS */ +/** @} End of group Parts */ + +#endif // BGM26_SMU_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_syscfg.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_syscfg.h new file mode 100644 index 0000000000..e367ae71d3 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_syscfg.h @@ -0,0 +1,806 @@ +/**************************************************************************//** + * @file + * @brief BGM26 SYSCFG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_SYSCFG_H +#define BGM26_SYSCFG_H +#define SYSCFG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_SYSCFG SYSCFG + * @{ + * @brief BGM26 SYSCFG Register Declaration. + *****************************************************************************/ + +/** SYSCFG Register Declaration. */ +typedef struct syscfg_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV; /**< Chip Revision */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ + uint32_t RESERVED7[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ + uint32_t RESERVED8[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL; /**< RADIO SEQRAM ECC Control Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */ + uint32_t RESERVED11[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[635U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_SET; /**< Chip Revision */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ + uint32_t RESERVED17[54U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ + uint32_t RESERVED21[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ + uint32_t RESERVED22[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO SEQRAM ECC Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */ + uint32_t RESERVED25[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[635U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_CLR; /**< Chip Revision */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ + uint32_t RESERVED31[54U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ + uint32_t RESERVED35[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ + uint32_t RESERVED36[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO SEQRAM ECC Control Register */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */ + uint32_t RESERVED39[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[635U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_TGL; /**< Chip Revision */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ + uint32_t RESERVED45[54U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ + uint32_t RESERVED49[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ + uint32_t RESERVED50[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO SEQRAM ECC Control Register */ + uint32_t RESERVED52[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */ + uint32_t RESERVED53[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ +} SYSCFG_TypeDef; +/** @} End of group BGM26_SYSCFG */ + +/**************************************************************************//** + * @addtogroup BGM26_SYSCFG + * @{ + * @defgroup BGM26_SYSCFG_BitFields SYSCFG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG IPVERSION */ +#define _SYSCFG_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ +#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ + +/* Bit fields for SYSCFG IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ +#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ +#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ +#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ +#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ +#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ +#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERRIF (0x1UL << 16) /**< HOST2SRWBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_HOST2SRWBUSERRIF_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERRIF */ +#define _SYSCFG_IF_HOST2SRWBUSERRIF_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERRIF */ +#define _SYSCFG_IF_HOST2SRWBUSERRIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERRIF_DEFAULT (_SYSCFG_IF_HOST2SRWBUSERRIF_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERRIF (0x1UL << 17) /**< SRW2HOSTBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_SRW2HOSTBUSERRIF_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERRIF */ +#define _SYSCFG_IF_SRW2HOSTBUSERRIF_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERRIF */ +#define _SYSCFG_IF_SRW2HOSTBUSERRIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERRIF_DEFAULT (_SYSCFG_IF_SRW2HOSTBUSERRIF_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ + +/* Bit fields for SYSCFG IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ +#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ +#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ +#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ +#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ +#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ +#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERRIEN (0x1UL << 16) /**< HOST2SRWBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_HOST2SRWBUSERRIEN_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERRIEN */ +#define _SYSCFG_IEN_HOST2SRWBUSERRIEN_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERRIEN */ +#define _SYSCFG_IEN_HOST2SRWBUSERRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERRIEN_DEFAULT (_SYSCFG_IEN_HOST2SRWBUSERRIEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERRIEN (0x1UL << 17) /**< SRW2HOSTBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_SRW2HOSTBUSERRIEN_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERRIEN */ +#define _SYSCFG_IEN_SRW2HOSTBUSERRIEN_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERRIEN */ +#define _SYSCFG_IEN_SRW2HOSTBUSERRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERRIEN_DEFAULT (_SYSCFG_IEN_SRW2HOSTBUSERRIEN_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ + +/* Bit fields for SYSCFG CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00010013UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT 0x00000013UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ + +/* Bit fields for SYSCFG CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREV_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREV_PARTNUMBER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREV_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ + +/* Bit fields for SYSCFG CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ + +/* Bit fields for SYSCFG CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ + +/* Bit fields for SYSCFG DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK31 0x80000000UL /**< Mode BLK31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK30TO31 0xC0000000UL /**< Mode BLK30TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK29TO31 0xE0000000UL /**< Mode BLK29TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK28TO31 0xF0000000UL /**< Mode BLK28TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK27TO31 0xF8000000UL /**< Mode BLK27TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK26TO31 0xFC000000UL /**< Mode BLK26TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK25TO31 0xFE000000UL /**< Mode BLK25TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK24TO31 0xFF000000UL /**< Mode BLK24TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK23TO31 0xFF800000UL /**< Mode BLK23TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK22TO31 0xFFC00000UL /**< Mode BLK22TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK21TO31 0xFFE00000UL /**< Mode BLK21TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK20TO31 0xFFF00000UL /**< Mode BLK20TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK19TO31 0xFFF80000UL /**< Mode BLK19TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK18TO31 0xFFFC0000UL /**< Mode BLK18TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK17TO31 0xFFFE0000UL /**< Mode BLK17TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK16TO31 0xFFFF0000UL /**< Mode BLK16TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15TO31 0xFFFF8000UL /**< Mode BLK15TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO31 0xFFFFC000UL /**< Mode BLK14TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO31 0xFFFFE000UL /**< Mode BLK13TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO31 0xFFFFF000UL /**< Mode BLK12TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO31 0xFFFFF800UL /**< Mode BLK11TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO31 0xFFFFFC00UL /**< Mode BLK10TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO31 0xFFFFFE00UL /**< Mode BLK9TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO31 0xFFFFFF00UL /**< Mode BLK8TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO31 0xFFFFFF80UL /**< Mode BLK7TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO31 0xFFFFFFC0UL /**< Mode BLK6TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO31 0xFFFFFFE0UL /**< Mode BLK5TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO31 0xFFFFFFF0UL /**< Mode BLK4TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO31 0xFFFFFFF8UL /**< Mode BLK3TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO31 0xFFFFFFFCUL /**< Mode BLK2TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO31 0xFFFFFFFEUL /**< Mode BLK1TO31 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF 0xFFFFFFFFUL /**< Mode ALLOFF for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK31 << 0) /**< Shifted mode BLK31 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK30TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK30TO31 << 0) /**< Shifted mode BLK30TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK29TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK29TO31 << 0) /**< Shifted mode BLK29TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK28TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK28TO31 << 0) /**< Shifted mode BLK28TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK27TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK27TO31 << 0) /**< Shifted mode BLK27TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK26TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK26TO31 << 0) /**< Shifted mode BLK26TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK25TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK25TO31 << 0) /**< Shifted mode BLK25TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK24TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK24TO31 << 0) /**< Shifted mode BLK24TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK23TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK23TO31 << 0) /**< Shifted mode BLK23TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK22TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK22TO31 << 0) /**< Shifted mode BLK22TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK21TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK21TO31 << 0) /**< Shifted mode BLK21TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK20TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK20TO31 << 0) /**< Shifted mode BLK20TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK19TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK19TO31 << 0) /**< Shifted mode BLK19TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK18TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK18TO31 << 0) /**< Shifted mode BLK18TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK17TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK17TO31 << 0) /**< Shifted mode BLK17TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK16TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK16TO31 << 0) /**< Shifted mode BLK16TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15TO31 << 0) /**< Shifted mode BLK15TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO31 << 0) /**< Shifted mode BLK14TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO31 << 0) /**< Shifted mode BLK13TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO31 << 0) /**< Shifted mode BLK12TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO31 << 0) /**< Shifted mode BLK11TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO31 << 0) /**< Shifted mode BLK10TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO31 << 0) /**< Shifted mode BLK9TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO31 << 0) /**< Shifted mode BLK8TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO31 << 0) /**< Shifted mode BLK7TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO31 << 0) /**< Shifted mode BLK6TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO31 << 0) /**< Shifted mode BLK5TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO31 << 0) /**< Shifted mode BLK4TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO31 << 0) /**< Shifted mode BLK3TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO31 << 0) /**< Shifted mode BLK2TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO31 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO31 << 0) /**< Shifted mode BLK1TO31 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_DMEM0RETNCTRL*/ + +/* Bit fields for SYSCFG RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ + +/* Bit fields for SYSCFG RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ + +/* Bit fields for SYSCFG RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ + +/* Bit fields for SYSCFG SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ + +/* Bit fields for SYSCFG FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ + +/* Bit fields for SYSCFG ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ + +/* Bit fields for SYSCFG DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00007905UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 6 /**< Shift value for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 8 /**< Shift value for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x300UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT 10 /**< Shift value for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK 0xC00UL /**< Bit mask for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT 12 /**< Shift value for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK 0x3000UL /**< Bit mask for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT 14 /**< Shift value for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK 0xC000UL /**< Bit mask for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ + +/* Bit fields for SYSCFG ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ + +/* Bit fields for SYSCFG ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ + +/* Bit fields for SYSCFG ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ + +/* Bit fields for SYSCFG ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ +#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ + +/** @} End of group BGM26_SYSCFG_BitFields */ +/** @} End of group BGM26_SYSCFG */ +/**************************************************************************//** + * @defgroup BGM26_SYSCFG_CFGNS SYSCFG_CFGNS + * @{ + * @brief BGM26 SYSCFG_CFGNS Register Declaration. + *****************************************************************************/ + +/** SYSCFG_CFGNS Register Declaration. */ +typedef struct syscfg_cfgns_typedef{ + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED1[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[637U]; /**< Reserved for future use */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED5[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[637U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED9[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[637U]; /**< Reserved for future use */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED13[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} SYSCFG_CFGNS_TypeDef; +/** @} End of group BGM26_SYSCFG_CFGNS */ + +/**************************************************************************//** + * @addtogroup BGM26_SYSCFG_CFGNS + * @{ + * @defgroup BGM26_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ +#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ +#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ + +/* Bit fields for SYSCFG ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ +#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ + +/* Bit fields for SYSCFG ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ +#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ + +/** @} End of group BGM26_SYSCFG_CFGNS_BitFields */ +/** @} End of group BGM26_SYSCFG_CFGNS */ +/** @} End of group Parts */ + +#endif // BGM26_SYSCFG_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_sysrtc.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_sysrtc.h new file mode 100644 index 0000000000..7f8add238d --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_sysrtc.h @@ -0,0 +1,421 @@ +/**************************************************************************//** + * @file + * @brief BGM26 SYSRTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_SYSRTC_H +#define BGM26_SYSRTC_H +#define SYSRTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_SYSRTC SYSRTC + * @{ + * @brief BGM26 SYSRTC Register Declaration. + *****************************************************************************/ + +/** SYSRTC Register Declaration. */ +typedef struct sysrtc_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} SYSRTC_TypeDef; +/** @} End of group BGM26_SYSRTC */ + +/**************************************************************************//** + * @addtogroup BGM26_SYSRTC + * @{ + * @defgroup BGM26_SYSRTC_BitFields SYSRTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSRTC IPVERSION */ +#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ +#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ + +/* Bit fields for SYSRTC EN */ +#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ +#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ +#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ +#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ +#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ +#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ + +/* Bit fields for SYSRTC SWRST */ +#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ + +/* Bit fields for SYSRTC CFG */ +#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ +#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ + +/* Bit fields for SYSRTC CMD */ +#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ +#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ +#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ +#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ +#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ + +/* Bit fields for SYSRTC STATUS */ +#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ +#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ + +/* Bit fields for SYSRTC CNT */ +#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ +#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ +#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ + +/* Bit fields for SYSRTC SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ +#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ +#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ +#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ + +/* Bit fields for SYSRTC LOCK */ +#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ + +/* Bit fields for SYSRTC GRP0_IF */ +#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ + +/* Bit fields for SYSRTC GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ + +/* Bit fields for SYSRTC GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ + +/* Bit fields for SYSRTC GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ +#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ +#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ + +/* Bit fields for SYSRTC GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ +#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ + +/** @} End of group BGM26_SYSRTC_BitFields */ +/** @} End of group BGM26_SYSRTC */ +/** @} End of group Parts */ + +#endif // BGM26_SYSRTC_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_timer.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_timer.h new file mode 100644 index 0000000000..4b46acdd5a --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_timer.h @@ -0,0 +1,1020 @@ +/**************************************************************************//** + * @file + * @brief BGM26 TIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_TIMER_H +#define BGM26_TIMER_H +#define TIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_TIMER TIMER + * @{ + * @brief BGM26 TIMER Register Declaration. + *****************************************************************************/ + +/** TIMER CC Register Group Declaration. */ +typedef struct timer_cc_typedef{ + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} TIMER_CC_TypeDef; + +/** TIMER Register Declaration. */ +typedef struct timer_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; +/** @} End of group BGM26_TIMER */ + +/**************************************************************************//** + * @addtogroup BGM26_TIMER + * @{ + * @defgroup BGM26_TIMER_BitFields TIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ + +/* Bit fields for TIMER CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ + +/* Bit fields for TIMER CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ + +/* Bit fields for TIMER CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ + +/* Bit fields for TIMER CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ + +/* Bit fields for TIMER CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ + +/* Bit fields for TIMER DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ + +/* Bit fields for TIMER DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ + +/* Bit fields for TIMER DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group BGM26_TIMER_BitFields */ +/** @} End of group BGM26_TIMER */ +/** @} End of group Parts */ + +#endif // BGM26_TIMER_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_ulfrco.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ulfrco.h new file mode 100644 index 0000000000..f0ef55b249 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_ulfrco.h @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file + * @brief BGM26 ULFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_ULFRCO_H +#define BGM26_ULFRCO_H +#define ULFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_ULFRCO ULFRCO + * @{ + * @brief BGM26 ULFRCO Register Declaration. + *****************************************************************************/ + +/** ULFRCO Register Declaration. */ +typedef struct ulfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} ULFRCO_TypeDef; +/** @} End of group BGM26_ULFRCO */ + +/**************************************************************************//** + * @addtogroup BGM26_ULFRCO + * @{ + * @defgroup BGM26_ULFRCO_BitFields ULFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ULFRCO IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ + +/* Bit fields for ULFRCO STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ + +/* Bit fields for ULFRCO IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ + +/* Bit fields for ULFRCO IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ + +/** @} End of group BGM26_ULFRCO_BitFields */ +/** @} End of group BGM26_ULFRCO */ +/** @} End of group Parts */ + +#endif // BGM26_ULFRCO_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_usart.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_usart.h new file mode 100644 index 0000000000..3b08ec3e16 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_usart.h @@ -0,0 +1,1431 @@ +/**************************************************************************//** + * @file + * @brief BGM26 USART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_USART_H +#define BGM26_USART_H +#define USART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_USART USART + * @{ + * @brief BGM26 USART Register Declaration. + *****************************************************************************/ + +/** USART Register Declaration. */ +typedef struct usart_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +} USART_TypeDef; +/** @} End of group BGM26_USART */ + +/**************************************************************************//** + * @addtogroup BGM26_USART + * @{ + * @defgroup BGM26_USART_BitFields USART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for USART IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ + +/* Bit fields for USART EN */ +#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ +#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ +#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ +#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ +#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ + +/** @} End of group BGM26_USART_BitFields */ +/** @} End of group BGM26_USART */ +/** @} End of group Parts */ + +#endif // BGM26_USART_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_vdac.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_vdac.h new file mode 100644 index 0000000000..8c05377477 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_vdac.h @@ -0,0 +1,757 @@ +/**************************************************************************//** + * @file + * @brief BGM26 VDAC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_VDAC_H +#define BGM26_VDAC_H +#define VDAC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_VDAC VDAC + * @{ + * @brief BGM26 VDAC Register Declaration. + *****************************************************************************/ + +/** VDAC Register Declaration. */ +typedef struct vdac_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Module Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Config Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ + uint32_t RESERVED0[50U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[63U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Module Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Config Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ + uint32_t RESERVED5[50U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[63U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Config Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ + uint32_t RESERVED10[50U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Config Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ + uint32_t RESERVED15[50U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ +} VDAC_TypeDef; +/** @} End of group BGM26_VDAC */ + +/**************************************************************************//** + * @addtogroup BGM26_VDAC + * @{ + * @defgroup BGM26_VDAC_BitFields VDAC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC IPVERSION */ +#define _VDAC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_IPVERSION */ +#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ + +/* Bit fields for VDAC EN */ +#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ +#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ +#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ +#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ +#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ +#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ +#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ +#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ +#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ +#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ +#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ + +/* Bit fields for VDAC SWRST */ +#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ +#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ +#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ + +/* Bit fields for VDAC CFG */ +#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ +#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */ +#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ +#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ +#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ +#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ +#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ +#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ +#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ +#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ +#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ +#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ +#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ +#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ +#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ +#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ +#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ +#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ +#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ +#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ +#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ +#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CFG */ +#define _VDAC_CH0CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ +#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ +#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ +#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ + +/* Bit fields for VDAC CH1CFG */ +#define _VDAC_CH1CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ +#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ +#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ +#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ +#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ +#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ +#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ +#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ +#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0F */ +#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ +#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ +#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ +#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ + +/* Bit fields for VDAC CH1F */ +#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ +#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ +#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ +#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ + +/* Bit fields for VDAC OUTCTRL */ +#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ + +/* Bit fields for VDAC OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ + +/** @} End of group BGM26_VDAC_BitFields */ +/** @} End of group BGM26_VDAC */ +/** @} End of group Parts */ + +#endif // BGM26_VDAC_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/bgm26_wdog.h b/platform/Device/SiliconLabs/BGM26/Include/bgm26_wdog.h new file mode 100644 index 0000000000..daf546767f --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/bgm26_wdog.h @@ -0,0 +1,375 @@ +/**************************************************************************//** + * @file + * @brief BGM26 WDOG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM26_WDOG_H +#define BGM26_WDOG_H +#define WDOG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM26_WDOG WDOG + * @{ + * @brief BGM26 WDOG Register Declaration. + *****************************************************************************/ + +/** WDOG Register Declaration. */ +typedef struct wdog_typedef{ + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} WDOG_TypeDef; +/** @} End of group BGM26_WDOG */ + +/**************************************************************************//** + * @addtogroup BGM26_WDOG + * @{ + * @defgroup BGM26_WDOG_BitFields WDOG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ + +/* Bit fields for WDOG EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ +#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ + +/* Bit fields for WDOG CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ +#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/* Bit fields for WDOG LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/** @} End of group BGM26_WDOG_BitFields */ +/** @} End of group BGM26_WDOG */ +/** @} End of group Parts */ + +#endif // BGM26_WDOG_H diff --git a/platform/Device/SiliconLabs/BGM26/Include/em_device.h b/platform/Device/SiliconLabs/BGM26/Include/em_device.h new file mode 100644 index 0000000000..5337941c29 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/em_device.h @@ -0,0 +1,61 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H +#if defined(BGM260PB22VNA) +#include "bgm260pb22vna.h" + +#elif defined(BGM260PB32VNA) +#include "bgm260pb32vna.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif + +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif + +#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif +#endif /* EM_DEVICE_H */ diff --git a/platform/Device/SiliconLabs/BGM26/Include/system_bgm26.h b/platform/Device/SiliconLabs/BGM26/Include/system_bgm26.h new file mode 100644 index 0000000000..675718699a --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Include/system_bgm26.h @@ -0,0 +1,271 @@ +/**************************************************************************//** + * @file + * @brief CMSIS system header file for BGM26 + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SYSTEM_BGM26_H +#define SYSTEM_BGM26_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "sl_code_classification.h" + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup BGM26 BGM26 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ +#endif + +/*Re-direction of IRQn.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn +#else +#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn +#endif /* SL_TRUSTZONE_SECURE */ + +/*Re-direction of IRQHandler.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler +#else +#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler +#endif /* SL_TRUSTZONE_SECURE */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SecureFault_Handler(void); /**< Secure Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +/* Part Specific Interrupts */ +void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ +void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ +void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void TIMER5_IRQHandler(void); /**< TIMER5 IRQ Handler */ +void TIMER6_IRQHandler(void); /**< TIMER6 IRQ Handler */ +void TIMER7_IRQHandler(void); /**< TIMER7 IRQ Handler */ +void TIMER8_IRQHandler(void); /**< TIMER8 IRQ Handler */ +void TIMER9_IRQHandler(void); /**< TIMER9 IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ +void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ +void USART2_RX_IRQHandler(void); /**< USART2_RX IRQ Handler */ +void USART2_TX_IRQHandler(void); /**< USART2_TX IRQ Handler */ +void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ +void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ +void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ +void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ +void EUSART2_RX_IRQHandler(void); /**< EUSART2_RX IRQ Handler */ +void EUSART2_TX_IRQHandler(void); /**< EUSART2_TX IRQ Handler */ +void EUSART3_RX_IRQHandler(void); /**< EUSART3_RX IRQ Handler */ +void EUSART3_TX_IRQHandler(void); /**< EUSART3_TX IRQ Handler */ +void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ +void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ +void MPAHBRAM0_IRQHandler(void); /**< MPAHBRAM0 IRQ Handler */ +void MPAHBRAM1_IRQHandler(void); /**< MPAHBRAM1 IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ +void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ +void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void I2C2_IRQHandler(void); /**< I2C2 IRQ Handler */ +void I2C3_IRQHandler(void); /**< I2C3 IRQ Handler */ +void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ +void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ +void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ +void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void AES_IRQHandler(void); /**< AES IRQ Handler */ +void IADC_IRQHandler(void); /**< IADC IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ +void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ +void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ +void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ +void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ +void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ +void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ +void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ +void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ +void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ +void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ +void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ +void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ +void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */ +void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */ +void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */ +void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */ +void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */ +void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */ +void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */ +void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */ +void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */ +void VDAC1_IRQHandler(void); /**< VDAC1 IRQ Handler */ +void AHB2AHB0_IRQHandler(void); /**< AHB2AHB0 IRQ Handler */ +void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */ +void LCD_IRQHandler(void); /**< LCD IRQ Handler */ + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ +#endif + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHCLKGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE uint32_t SystemCoreClockGet(void) +{ + return SystemHCLKGet(); +} + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemHCLKGet(); +} + +void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFRCODPLLClockGet(void); +void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFRCOEM23ClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemULFRCOClockGet(void); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_BGM26_H */ diff --git a/platform/Device/SiliconLabs/BGM26/Source/startup_bgm26.c b/platform/Device/SiliconLabs/BGM26/Source/startup_bgm26.c new file mode 100644 index 0000000000..e2232573d4 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Source/startup_bgm26.c @@ -0,0 +1,473 @@ +/****************************************************************************** +* @file startup_bgm26.c +* @brief CMSIS-Core(M) Device Startup File for +* Device BGM26 +* @version V2.1.0 +* @date 16. December 2020 +******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "em_device.h" + +#ifdef BOOTLOADER_ENABLE +#include "api/btl_interface.h" + +#endif // BOOTLOADER_ENABLE +#ifdef SL_APP_PROPERTIES +#include "api/application_properties.h" + +#endif // SL_APP_PROPERTIES + +#define TOTAL_INTERRUPTS (16 + EXT_IRQ_COUNT) + +#ifdef BOOTLOADER_ENABLE +extern MainBootloaderTable_t mainStageTable; +extern void SystemInit2(void); + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void (*VECTOR_TABLE_Type)(void); +#endif + +#ifdef SL_APP_PROPERTIES +extern ApplicationProperties_t sl_app_properties; + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void (*VECTOR_TABLE_Type)(void); +#endif + +/*--------------------------------------------------------------------------- + * External References + *---------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +#if defined (SL_TRUSTZONE_SECURE) +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif // __ARM_FEATURE_CMSE +#endif // SL_TRUSTZONE_SECURE + +extern __NO_RETURN void __PROGRAM_START(void); + +#if defined (__START) && defined (__GNUC__) +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +void Copy_Table(); +void Zero_Table(); +#endif // __START + +/*--------------------------------------------------------------------------- + * Internal References + *---------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void); +void Default_Handler(void); + +#if defined (__GNUC__) +#ifndef __STACK_SIZE +#define __STACK_SIZE 0x00000400 +#endif // __STACK_SIZE + +#ifndef __HEAP_SIZE +#define __HEAP_SIZE 0x00000C00 +#endif // __HEAP_SIZE +#endif // __GNUC__ + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M Processor Exceptions */ +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +#ifndef SL_APP_PROPERTIES +/* Provide a dummy value for the sl_app_properties symbol. */ +void sl_app_properties(void); /* Prototype to please MISRA checkers. */ +void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + +/* Part Specific Interrupts */ +void SMU_SECURE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SMU_S_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SMU_NS_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER5_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER6_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER7_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER8_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER9_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART2_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART2_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART2_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART2_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART3_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART3_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ICACHE0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYSCFG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MPAHBRAM0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MPAHBRAM1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LFXO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ULFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMUDG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HOSTMAILBOX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ACMP1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFXO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFRCO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFRCOEM23_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AES_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void IADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DPLL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMUEFP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DCDC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KERNEL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KERNEL1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void M33CTI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void M33CTI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FPUEXH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SETAMPERHOST_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SEMBRX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SEMBTX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYSRTC_APP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYSRTC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KEYSCAN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RFECA0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RFECA1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void VDAC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AHB2AHB0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AHB2AHB1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LCD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined (__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif // __GNUC__ + +#if defined (__ICCARM__) +#pragma data_alignment=512 +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { +#elif defined(__GNUC__) +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __attribute__((aligned(512))) +__VECTOR_TABLE_ATTRIBUTE = { +#else +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { +#endif + { .topOfStack = &__INITIAL_SP }, /* Initial Stack Pointer */ + { Reset_Handler }, /* Reset Handler */ + { NMI_Handler }, /* -14 NMI Handler */ + { HardFault_Handler }, /* -13 Hard Fault Handler */ + { MemManage_Handler }, /* -12 MPU Fault Handler */ + { BusFault_Handler }, /* -11 Bus Fault Handler */ + { UsageFault_Handler }, /* -10 Usage Fault Handler */ + { SecureFault_Handler }, /* -9 Secure Fault Handler */ + { Default_Handler }, /* Reserved */ + { Default_Handler }, /* Reserved */ +#ifdef BOOTLOADER_ENABLE + { (VECTOR_TABLE_Type) & mainStageTable }, +#else + { Default_Handler }, /* Reserved */ +#endif + { SVC_Handler }, /* -5 SVCall Handler */ + { DebugMon_Handler }, /* -4 Debug Monitor Handler */ +#ifdef SL_APP_PROPERTIES + { (VECTOR_TABLE_Type) & sl_app_properties }, /* Application properties */ +#else + { sl_app_properties }, /* Application properties */ +#endif + { PendSV_Handler }, /* -2 PendSV Handler */ + { SysTick_Handler }, /* -1 SysTick Handler */ + + /* External interrupts */ + { SMU_SECURE_IRQHandler }, /* 00 = SMU_SECURE */ + { SMU_S_PRIVILEGED_IRQHandler }, /* 01 = SMU_S_PRIVILEGED */ + { SMU_NS_PRIVILEGED_IRQHandler }, /* 02 = SMU_NS_PRIVILEGED */ + { EMU_IRQHandler }, /* 03 = EMU */ + { TIMER0_IRQHandler }, /* 04 = TIMER0 */ + { TIMER1_IRQHandler }, /* 05 = TIMER1 */ + { TIMER2_IRQHandler }, /* 06 = TIMER2 */ + { TIMER3_IRQHandler }, /* 07 = TIMER3 */ + { TIMER4_IRQHandler }, /* 08 = TIMER4 */ + { TIMER5_IRQHandler }, /* 09 = TIMER5 */ + { TIMER6_IRQHandler }, /* 10 = TIMER6 */ + { TIMER7_IRQHandler }, /* 11 = TIMER7 */ + { TIMER8_IRQHandler }, /* 12 = TIMER8 */ + { TIMER9_IRQHandler }, /* 13 = TIMER9 */ + { USART0_RX_IRQHandler }, /* 14 = USART0_RX */ + { USART0_TX_IRQHandler }, /* 15 = USART0_TX */ + { USART1_RX_IRQHandler }, /* 16 = USART1_RX */ + { USART1_TX_IRQHandler }, /* 17 = USART1_TX */ + { USART2_RX_IRQHandler }, /* 18 = USART2_RX */ + { USART2_TX_IRQHandler }, /* 19 = USART2_TX */ + { EUSART0_RX_IRQHandler }, /* 20 = EUSART0_RX */ + { EUSART0_TX_IRQHandler }, /* 21 = EUSART0_TX */ + { EUSART1_RX_IRQHandler }, /* 22 = EUSART1_RX */ + { EUSART1_TX_IRQHandler }, /* 23 = EUSART1_TX */ + { EUSART2_RX_IRQHandler }, /* 24 = EUSART2_RX */ + { EUSART2_TX_IRQHandler }, /* 25 = EUSART2_TX */ + { EUSART3_RX_IRQHandler }, /* 26 = EUSART3_RX */ + { EUSART3_TX_IRQHandler }, /* 27 = EUSART3_TX */ + { Default_Handler }, /* Reserved */ + { ICACHE0_IRQHandler }, /* 29 = ICACHE0 */ + { BURTC_IRQHandler }, /* 30 = BURTC */ + { LETIMER0_IRQHandler }, /* 31 = LETIMER0 */ + { SYSCFG_IRQHandler }, /* 32 = SYSCFG */ + { MPAHBRAM0_IRQHandler }, /* 33 = MPAHBRAM0 */ + { MPAHBRAM1_IRQHandler }, /* 34 = MPAHBRAM1 */ + { LDMA_IRQHandler }, /* 35 = LDMA */ + { LFXO_IRQHandler }, /* 36 = LFXO */ + { LFRCO_IRQHandler }, /* 37 = LFRCO */ + { ULFRCO_IRQHandler }, /* 38 = ULFRCO */ + { GPIO_ODD_IRQHandler }, /* 39 = GPIO_ODD */ + { GPIO_EVEN_IRQHandler }, /* 40 = GPIO_EVEN */ + { I2C0_IRQHandler }, /* 41 = I2C0 */ + { I2C1_IRQHandler }, /* 42 = I2C1 */ + { I2C2_IRQHandler }, /* 43 = I2C2 */ + { I2C3_IRQHandler }, /* 44 = I2C3 */ + { EMUDG_IRQHandler }, /* 45 = EMUDG */ + { AGC_IRQHandler }, /* 46 = AGC */ + { BUFC_IRQHandler }, /* 47 = BUFC */ + { FRC_PRI_IRQHandler }, /* 48 = FRC_PRI */ + { FRC_IRQHandler }, /* 49 = FRC */ + { MODEM_IRQHandler }, /* 50 = MODEM */ + { PROTIMER_IRQHandler }, /* 51 = PROTIMER */ + { RAC_RSM_IRQHandler }, /* 52 = RAC_RSM */ + { RAC_SEQ_IRQHandler }, /* 53 = RAC_SEQ */ + { HOSTMAILBOX_IRQHandler }, /* 54 = HOSTMAILBOX */ + { SYNTH_IRQHandler }, /* 55 = SYNTH */ + { ACMP0_IRQHandler }, /* 56 = ACMP0 */ + { ACMP1_IRQHandler }, /* 57 = ACMP1 */ + { WDOG0_IRQHandler }, /* 58 = WDOG0 */ + { WDOG1_IRQHandler }, /* 59 = WDOG1 */ + { HFXO0_IRQHandler }, /* 60 = HFXO0 */ + { HFRCO0_IRQHandler }, /* 61 = HFRCO0 */ + { HFRCOEM23_IRQHandler }, /* 62 = HFRCOEM23 */ + { CMU_IRQHandler }, /* 63 = CMU */ + { AES_IRQHandler }, /* 64 = AES */ + { IADC_IRQHandler }, /* 65 = IADC */ + { MSC_IRQHandler }, /* 66 = MSC */ + { DPLL0_IRQHandler }, /* 67 = DPLL0 */ + { EMUEFP_IRQHandler }, /* 68 = EMUEFP */ + { DCDC_IRQHandler }, /* 69 = DCDC */ + { PCNT0_IRQHandler }, /* 70 = PCNT0 */ + { SW0_IRQHandler }, /* 71 = SW0 */ + { SW1_IRQHandler }, /* 72 = SW1 */ + { SW2_IRQHandler }, /* 73 = SW2 */ + { SW3_IRQHandler }, /* 74 = SW3 */ + { KERNEL0_IRQHandler }, /* 75 = KERNEL0 */ + { KERNEL1_IRQHandler }, /* 76 = KERNEL1 */ + { M33CTI0_IRQHandler }, /* 77 = M33CTI0 */ + { M33CTI1_IRQHandler }, /* 78 = M33CTI1 */ + { FPUEXH_IRQHandler }, /* 79 = FPUEXH */ + { SETAMPERHOST_IRQHandler }, /* 80 = SETAMPERHOST */ + { SEMBRX_IRQHandler }, /* 81 = SEMBRX */ + { SEMBTX_IRQHandler }, /* 82 = SEMBTX */ + { SYSRTC_APP_IRQHandler }, /* 83 = SYSRTC_APP */ + { SYSRTC_SEQ_IRQHandler }, /* 84 = SYSRTC_SEQ */ + { KEYSCAN_IRQHandler }, /* 85 = KEYSCAN */ + { RFECA0_IRQHandler }, /* 86 = RFECA0 */ + { RFECA1_IRQHandler }, /* 87 = RFECA1 */ + { VDAC0_IRQHandler }, /* 88 = VDAC0 */ + { VDAC1_IRQHandler }, /* 89 = VDAC1 */ + { AHB2AHB0_IRQHandler }, /* 90 = AHB2AHB0 */ + { AHB2AHB1_IRQHandler }, /* 91 = AHB2AHB1 */ + { LCD_IRQHandler }, /* 92 = LCD */ +}; + +#if defined (__GNUC__) +#pragma GCC diagnostic pop +#endif // __GNUC__ + +#if defined (__START) && defined (__GNUC__) +void Copy_Table() +{ + uint32_t *pSrc, *pDest; + extern uint32_t __etext; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + pSrc = &__etext; + pDest = &__data_start__; + + for (; pDest < &__data_end__; ) { + *pDest++ = *pSrc++; + } +} + +void Zero_Table() +{ + uint32_t *pDest; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + pDest = &__bss_start__; + + for (; pDest < &__bss_end__; ) { + *pDest++ = 0UL; + } +} +#endif // __START + +#if !defined(SL_LEGACY_LINKER) \ + && !defined(SL_RAM_LINKER) \ + && !defined(BOOTLOADER_ENABLE) +#if defined (__GNUC__) +__attribute__((optimize("no-tree-loop-distribute-patterns"))) +#endif +// Instructions are 4 bytes long +void CopyInstructions(const uint32_t *from, uint32_t *to, uint32_t num_instructions) +{ + while (num_instructions--) { + *to++ = *from++; + } +} +#if defined (__GNUC__) +void CopyToRam() +{ + extern uint32_t __lma_ramfuncs_start__; + extern uint32_t __lma_ramfuncs_end__; + extern uint32_t __ramfuncs_start__; + uint32_t num_instructions = &__lma_ramfuncs_end__ - &__lma_ramfuncs_start__; + + CopyInstructions(&__lma_ramfuncs_start__, &__ramfuncs_start__, num_instructions); +} +#elif defined (__ICCARM__) +#pragma language=save +#pragma language=extended +#pragma section="text_ram" +#pragma section="text_ram_init" +void CopyToRam(void) +{ + uint32_t num_instructions = (__section_size("text_ram") + 3) / 4; + uint32_t * from = __section_begin("text_ram_init"); + uint32_t * to = __section_begin("text_ram"); + + CopyInstructions(from, to, num_instructions); +} +#pragma language=restore +#endif +#endif + +/*--------------------------------------------------------------------------- + * Reset Handler called on controller reset + *---------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ +#if defined (SL_TRUSTZONE_SECURE) + __set_MSPLIM((uint32_t) (&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *) (&__STACK_SEAL)); +#endif // __ARM_FEATURE_CMSE +#endif // SL_TRUSTZONE_SECURE + + #ifndef __NO_SYSTEM_INIT + SystemInit(); /* CMSIS System Initialization */ + #endif + +#if !defined(SL_LEGACY_LINKER) \ + && !defined(SL_RAM_LINKER) \ + && !defined(BOOTLOADER_ENABLE) + CopyToRam(); +#endif + +#ifdef BOOTLOADER_ENABLE + SystemInit2(); +#endif // BOOTLOADER_ENABLE +#if defined (__GNUC__) && defined (__START) + Copy_Table(); + Zero_Table(); + __START(); +#else + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +#endif // __GNUC__ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif // __ARMCC_VERSION + +/*---------------------------------------------------------------------------- + * Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while (true) { + } +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif // __ARMCC_VERSION diff --git a/platform/Device/SiliconLabs/BGM26/Source/system_bgm26.c b/platform/Device/SiliconLabs/BGM26/Source/system_bgm26.c new file mode 100644 index 0000000000..f6a1598a67 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM26/Source/system_bgm26.c @@ -0,0 +1,668 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M33 system support for BGM26 devices. + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +// System oscillator frequencies. These frequencies are normally constant +// for a target, but they are made configurable in order to allow run-time +// handling of different boards. The crystal oscillator clocks can be set +// compile time to a non-default value by defining respective nFXO_FREQ +// values according to board design. By defining the nFXO_FREQ to 0, +// one indicates that the oscillator is not present, in order to save some +// SW footprint. + +#if !defined(FSRCO_FREQ) +// FSRCO frequency +#define FSRCO_FREQ (20000000UL) +#endif + +#if !defined(HFXO_FREQ) +// HFXO frequency +#define HFXO_FREQ (39000000UL) +#endif + +#if !defined(HFRCODPLL_STARTUP_FREQ) +// HFRCODPLL startup frequency +#define HFRCODPLL_STARTUP_FREQ (19000000UL) +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +// Maximum HFRCODPLL frequency +#define HFRCODPLL_MAX_FREQ (80000000UL) +#endif + +// CLKIN0 input +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) +#define CLKIN0_FREQ (0UL) +#endif + +#if !defined(LFRCO_MAX_FREQ) +// LFRCO frequency, tuned to below frequency during manufacturing. +#define LFRCO_FREQ (32768UL) +#endif + +#if !defined(ULFRCO_FREQ) +// ULFRCO frequency +#define ULFRCO_FREQ (1000UL) +#endif + +#if !defined(LFXO_FREQ) +// LFXO frequency +#define LFXO_FREQ (LFRCO_FREQ) +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// NOTE: Gecko bootloaders can't have static variable allocation. +// System HFXO clock frequency +static uint32_t SystemHFXOClock = HFXO_FREQ; +#endif + +#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// System LFXO clock frequency +static uint32_t SystemLFXOClock = LFXO_FREQ; +#endif + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +// System HFRCODPLL clock frequency +static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; + +#endif + +/*--------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *---------------------------------------------------------------------------*/ +extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if (__FPU_PRESENT == 1) + SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ + | (3U << 11U * 2U)); /* set CP11 Full Access */ +#endif + +/* Secure app takes care of moving between the security states. + * SL_TRUSTZONE_SECURE MACRO is for secure access. + * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. + * When both the MACROS are not defined, during start-up below code makes sure + * that all the peripherals are accessed from non-secure address except SMU, + * as SMU is used to configure the trustzone state of the system. */ +#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ + && defined(__TZ_PRESENT) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; + + // config SMU to Secure and other peripherals to Non-Secure. + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); +#if defined (SEMAILBOX_PRESENT) + SMU->PPUSATD2_CLR = (_SMU_PPUSATD2_MASK & ~SMU_PPUSATD2_SEMAILBOX); +#else + SMU->PPUSATD2_CLR = _SMU_PPUSATD2_MASK; +#endif + + // SAU treats all accesses as non-secure +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + __DSB(); + __ISB(); +#else + #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." +#endif // __ARM_FEATURE_CMSE + +// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +#endif //SL_TRUSTZONE_SECURE +} + +/**************************************************************************//** + * @brief + * Get current HFRCODPLL frequency. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCODPLLClockGet(void) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + return SystemHFRCODPLLClock; +#else + uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +#endif +} + +/**************************************************************************//** + * @brief + * Set HFRCODPLL frequency value. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +void SystemHFRCODPLLClockSet(uint32_t freq) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFRCODPLLClock = freq; +#else + (void) freq; // Unused parameter +#endif +} + +/***************************************************************************//** + * @brief + * Get the current system clock frequency (SYSCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * hardware configuration. + * + * @note + * This is an BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * Current system clock (SYSCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemSYSCLKGet(void) +{ + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: +#if defined(SYSTEM_NO_STATIC_MEMORY) + ret = HFXO_FREQ; +#else + ret = SystemHFXOClock; +#endif + break; +#endif + +#if (CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = FSRCO_FREQ; + break; + + default: + // Unknown clock source. + while (1) { + } + } + return ret; +} + +/***************************************************************************//** + * @brief + * Get the current system core clock frequency (HCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * The current core clock (HCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemHCLKGet(void) +{ + uint32_t presc, ret; + + ret = SystemSYSCLKGet(); + + presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; + + ret /= presc + 1U; + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + // Keep CMSIS system clock variable up-to-date + SystemCoreClock = ret; +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ + ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + // The external crystal oscillator is not present if HFXO_FREQ==0 +#if (HFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return HFXO_FREQ; +#else + return SystemHFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFXOClock = freq; + + // Update core clock frequency if HFXO is used to clock core + if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) + == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { + // This function will update the global variable + SystemHCLKGet(); + } +#else + (void) freq; // Unused parameter +#endif +} + +/**************************************************************************//** + * @brief + * Get current CLKIN0 frequency. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * CLKIN0 frequency in Hz. + *****************************************************************************/ +uint32_t SystemCLKIN0Get(void) +{ + return CLKIN0_FREQ; +} + +/**************************************************************************//** + * @brief + * Get FSRCO frequency. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * FSRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemFSRCOClockGet(void) +{ + return FSRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get current HFRCOEM23 frequency. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCOEM23 frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCOEM23ClockGet(void) +{ + uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; + + // Get oscillator frequency band + switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCOEM23->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 40000000UL; + break; + + default: + break; + } + return ret; +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + return LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + // The ULFRCO frequency is not tuned, and can be very inaccurate + return ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + // External crystal present? +#if (LFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return LFXO_FREQ; +#else + return SystemLFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a BGM26 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemLFXOClock = freq; +#else + (void) freq; // Unused parameter +#endif +} diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h index c7168b0d52..03b6e93070 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h index 7650cb7fcb..f38587c97b 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h index ae19fb2b61..92b449db91 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h index 03205757c2..247da1b2e2 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h index bc24cdb0cb..df8d9874e5 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h index 17f029338f..1a70295fa1 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h index ea8d5e3738..2f9bf3b074 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFM32PG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG22_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h index 72e3de3320..3c857e4fba 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h index 1945fc7b24..158b33018f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h index 51444605e1..fe97f9b276 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h index 24591a606c..632a8e511c 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h index 168f933335..b3d236f700 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h index 508cd5619d..3ee368ed23 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h index 1d0ffa5dbe..1746e6d817 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h index 676903923f..4f8a4fe093 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h index e97c1ceb56..791905df4d 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h index 38b9f898c1..038cf7e32e 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h index 2ae58c4fff..b43f4a8643 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h index 5fa02265f4..4d4bea3773 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h index ff412c6080..abc3748851 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h index f66f5a8922..2af1bcac9e 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h index f6a9f7548e..65cf65b9f9 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFM32PG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG22_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h index 949c6a1c91..014d4f7c7e 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h index e3607c17fe..a7e9da6f6f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h index b2dce1b9b0..4e775f9c92 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h index d671d1691c..af97a7f63a 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h index cb92d438c7..e87f0125db 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h index 21bcda419d..828c535010 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h index d1e562c5a0..6b995117f8 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFM32PG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG22_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h index 7ec4865afa..ec1cd3d9a3 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h index b66a05cb50..9b6d52f897 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h index e59c07d96b..297c055f90 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h index fb1490df20..16f3e9974f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h index 5b02f0828d..a7a5a46221 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h index a3a225a21b..34ee671f15 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h index 424c5beeb1..dbfd5938b3 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h index 47b8d46deb..8d8556678f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F128IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h index 8ad9993ba8..c64354e41f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F128IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h index ec09a7abfc..2a65d62a15 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F256IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h index 8171d749a8..92f86f8f48 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F256IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h index 41fa5a74ac..88187e2bd1 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h index a1cc4a7905..6aee6d3d0a 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h index 2891de6c6d..fad01fc5b4 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F64IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h index 34bd14a181..2f01ee690f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F64IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h b/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h index 311ca4ba1c..4a68041cf6 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h b/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h index c389f2f577..bf392a20b6 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFM32PG22 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Source/startup_efm32pg22.c b/platform/Device/SiliconLabs/EFM32PG22/Source/startup_efm32pg22.c index 6907acd857..b18a6c32e1 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Source/startup_efm32pg22.c +++ b/platform/Device/SiliconLabs/EFM32PG22/Source/startup_efm32pg22.c @@ -4,17 +4,6 @@ * Device EFM32PG22 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c b/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c index 5676aa36a5..d68d9044d5 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c +++ b/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFM32PG22 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h index ebe4334140..c12071b05c 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h index 3b424ecaab..3fdf675e43 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h index 28b5f00ccf..e0cd5a2f83 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h index 5ad8653114..96b7bdc2e8 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h index f2b8a42824..8e5f3b5c88 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h index d64fb4a93a..11f93a116e 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h index 220780accc..b12fb80318 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFM32PG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG23_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h index 51fc8bd532..c9d032444f 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h index 086d208ee6..2af1ba3d5a 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h index 9f63156461..d48bbce601 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h index 2a487c1907..569b096a15 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h index 5883cb9db8..0d966be237 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h index d28c3ed32d..ad5b5883f7 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h index cb8dbcdac6..766f21de78 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h index f6093fe187..f80c3bf8a7 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h index 22b3ae574b..3c0bb01db6 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h index 036925006e..86fc4d4c2d 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h index f74212a2c7..c8353da672 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h index 9643ebea72..a8d2222ea8 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h index f0545ffcb1..0dde9bd6b9 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h index e9a98d518f..23bcc618c1 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h index 220d58ac93..269cf63f07 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h index e7d591bfb1..1d71218514 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h index 44ae14b97d..aa697edd3c 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h index 7bfff928a1..755b15e6b4 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFM32PG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG23_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h index cd672a27dd..725eb34dac 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h index d28b53a1fd..dc1972ff3a 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h index 3f484a3502..7643c26650 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h index 24eddd7825..336949b975 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h index f8c2c25b60..7e4eea9cd5 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h index e95d6b9f86..f139791593 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h index e04a148709..ce3967ab1f 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h index 2d5e6363d4..4f6d7c07a1 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h index e2c8865ca7..8c0e6b8885 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h index bd727e7fcc..83cd676e2f 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFM32PG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG23_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h index b42a90ae40..0729b7ae25 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h index 6bb53b994e..3648e522dd 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h index 60b08899b9..c34c3b2bb0 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h index f6cb4e1166..d4f6a2d77c 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h index 844e5a9436..76215596c2 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h index e25a7b08bc..224b6138a0 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h index 244200423e..95e1f59810 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h index a802e5bd82..fdef7d622b 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h index e4d87ce8c1..e27634b2a5 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h index fadb6ab02f..36dfae4f81 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h index 5aa363720b..c7bfa29f0e 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F128IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h index 8b43c6f9a3..ad58a34d82 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F256IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h index f59cb6381a..944128b03f 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h index 0b170353a7..045b335ca7 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F64IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h index bf46ff2e6c..049a0fa6d4 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F128IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h index 3e243971b2..dacb17cf99 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F256IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h index 54e8aa638a..0e7b9add4d 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h index 1b53e6b4bb..2336a9d55a 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F64IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h index 0224a75ac1..4552cd0c4b 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F128IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h index dcb6e1dc49..08cf9246ab 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F256IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h index bd0ec7f124..8390310f45 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h index 4dab4317ed..614089959d 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F64IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h b/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h index 48166f3ae0..9c8e46469c 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h b/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h index f0f75b109a..2bf4f4c3ea 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFM32PG23 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Source/startup_efm32pg23.c b/platform/Device/SiliconLabs/EFM32PG23/Source/startup_efm32pg23.c index b577312802..f24a47f483 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Source/startup_efm32pg23.c +++ b/platform/Device/SiliconLabs/EFM32PG23/Source/startup_efm32pg23.c @@ -4,17 +4,6 @@ * Device EFM32PG23 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c b/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c index c35231609c..b6e92cb02d 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c +++ b/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFM32PG23 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_acmp.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_acmp.h index 6a51e9d5cc..50be909947 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_acmp.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_acmp.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_aes.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_aes.h index 88758c604f..fa5e1660c8 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_aes.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_aes.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_amuxcp.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_amuxcp.h index 6a0b129f01..4ad9379667 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_amuxcp.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_amuxcp.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 AMUXCP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_buram.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_buram.h index 821b472939..998654d258 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_buram.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_buram.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_burtc.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_burtc.h index 65dfe2a8f1..104c7dde48 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_burtc.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_burtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_cmu.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_cmu.h index 417ae6bc7b..2ef9353cc7 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_cmu.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_cmu.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dcdc.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dcdc.h index 4def2a6eb0..bb0c749607 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dcdc.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dcdc.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_devinfo.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_devinfo.h index 6ac47de97f..7774c406fb 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_devinfo.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_devinfo.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dma_descriptor.h index 39208626d0..eea3e3f420 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFM32PG26 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG26_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dpll.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dpll.h index a2e9103213..d756a46485 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dpll.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_dpll.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_emu.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_emu.h index bfc8cb6240..b34a2c11b6 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_emu.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_emu.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_eusart.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_eusart.h index 7c4ae3937e..1c3f84a7a6 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_eusart.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_eusart.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_fsrco.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_fsrco.h index 8bdf597225..5610cf93e2 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_fsrco.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_fsrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpcrc.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpcrc.h index 4dbaaa9689..fc068eab0e 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpcrc.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio.h index 7c04e5336c..cfece209dc 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio_port.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio_port.h index cb0c2d26d2..cf65991166 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio_port.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfrco.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfrco.h index caadbe4e39..4bf6089d9d 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfxo.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfxo.h index c7d50f8ee9..fa3f4fd5dc 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_hfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_i2c.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_i2c.h index 104605e003..d4352e753f 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_i2c.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_i2c.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_iadc.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_iadc.h index 5b94467f08..a11d327131 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_iadc.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_iadc.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_icache.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_icache.h index 256085aa59..a5d599d091 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_icache.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_icache.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_keyscan.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_keyscan.h index 7f84cd97ce..e0d6571e69 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_keyscan.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_keyscan.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcd.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcd.h index 75db2a7043..2d9d160373 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcd.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcd.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcdrf.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcdrf.h index bb9ef67f8a..eacd886049 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcdrf.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldma.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldma.h index f775db3274..b2b5ccaca8 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldma.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldma.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar.h index de915fc8e0..16f24151a6 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar_defines.h index 37de3b7051..955b03e34e 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFM32PG26 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG26_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_letimer.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_letimer.h index 800d0ad59e..68549165ab 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_letimer.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_letimer.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfrco.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfrco.h index 5666c87db8..f6d2a4394f 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfxo.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfxo.h index 9a964539c9..88b64eb13a 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_lfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mailbox.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mailbox.h index d1108e1b58..27d2e9d53d 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mpahbram.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mpahbram.h index 13030fbddc..f3eaaee3b9 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mpahbram.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_msc.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_msc.h index 27ec998363..61d277d140 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_msc.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_msc.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mvp.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mvp.h index 8dd2e7b8f8..30f830d348 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mvp.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_mvp.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_pcnt.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_pcnt.h index a40a9800bf..b83901b0b4 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_pcnt.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_pcnt.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs.h index 7c16b79600..2aaf373d52 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs_signals.h index db283f3539..8306ba959f 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFM32PG26 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG26_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_semailbox.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_semailbox.h index 18831de709..83f1094bcc 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_semailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_semailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_smu.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_smu.h index c6ca965af1..7fd89a3e45 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_smu.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_smu.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_syscfg.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_syscfg.h index 670a47db3e..11d7ff9100 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_syscfg.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_syscfg.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_sysrtc.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_sysrtc.h index dc0e4f434d..fb458a6ed0 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_sysrtc.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_timer.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_timer.h index 7b0e5cdc7f..547e11191e 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_timer.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_timer.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ulfrco.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ulfrco.h index c920e3433e..cccd38c9b3 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ulfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_usart.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_usart.h index 8d518effcd..37ba31fe8c 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_usart.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_usart.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_vdac.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_vdac.h index fb2140e8a8..79caafe08d 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_vdac.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_vdac.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_wdog.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_wdog.h index a061c9ac36..4272eda6f5 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_wdog.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26_wdog.h @@ -3,7 +3,7 @@ * @brief EFM32PG26 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512il136.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512il136.h index 56b781a2d7..5edae43446 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512il136.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512il136.h @@ -4,7 +4,7 @@ * for EFM32PG26B101F512IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512im68.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512im68.h index 477e455286..b6802909c2 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512im68.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b101f512im68.h @@ -4,7 +4,7 @@ * for EFM32PG26B101F512IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024il136.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024il136.h index 81c32615a2..45dad6e684 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024il136.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024il136.h @@ -4,7 +4,7 @@ * for EFM32PG26B301F1024IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024im68.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024im68.h index 0007b237ce..6839da5914 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024im68.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f1024im68.h @@ -4,7 +4,7 @@ * for EFM32PG26B301F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048il136.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048il136.h index cba9319fda..d1ee821d78 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048il136.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048il136.h @@ -4,7 +4,7 @@ * for EFM32PG26B301F2048IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048im68.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048im68.h index 70aad36760..de02f0e21b 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048im68.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b301f2048im68.h @@ -4,7 +4,7 @@ * for EFM32PG26B301F2048IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200il136.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200il136.h index ff67cd63f3..e57c4feec7 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200il136.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200il136.h @@ -4,7 +4,7 @@ * for EFM32PG26B500F3200IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im48.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im48.h index 7c44eb51c6..ad21edc8bc 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im48.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im48.h @@ -4,7 +4,7 @@ * for EFM32PG26B500F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im68.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im68.h index 4139800043..3289af2a88 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im68.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b500f3200im68.h @@ -4,7 +4,7 @@ * for EFM32PG26B500F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200il136.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200il136.h index 3707b02b81..747a3b28f8 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200il136.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200il136.h @@ -4,7 +4,7 @@ * for EFM32PG26B501F3200IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im48.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im48.h index 29c3c224e1..40e028f26d 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im48.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im48.h @@ -4,7 +4,7 @@ * for EFM32PG26B501F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im68.h b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im68.h index ea520ecfbc..5ede139fed 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im68.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/efm32pg26b501f3200im68.h @@ -4,7 +4,7 @@ * for EFM32PG26B501F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/em_device.h b/platform/Device/SiliconLabs/EFM32PG26/Include/em_device.h index 3e612e4de4..46b08076ff 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Include/system_efm32pg26.h b/platform/Device/SiliconLabs/EFM32PG26/Include/system_efm32pg26.h index a336362422..690d6d90cf 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Include/system_efm32pg26.h +++ b/platform/Device/SiliconLabs/EFM32PG26/Include/system_efm32pg26.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFM32PG26 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG26/Source/startup_efm32pg26.c b/platform/Device/SiliconLabs/EFM32PG26/Source/startup_efm32pg26.c index 696aa61910..bcab27ce38 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Source/startup_efm32pg26.c +++ b/platform/Device/SiliconLabs/EFM32PG26/Source/startup_efm32pg26.c @@ -4,17 +4,6 @@ * Device EFM32PG26 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFM32PG26/Source/system_efm32pg26.c b/platform/Device/SiliconLabs/EFM32PG26/Source/system_efm32pg26.c index 15dde181b4..e7e643088c 100644 --- a/platform/Device/SiliconLabs/EFM32PG26/Source/system_efm32pg26.c +++ b/platform/Device/SiliconLabs/EFM32PG26/Source/system_efm32pg26.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFM32PG26 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h index efcbdc68f1..cc62279092 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h index c453d69c5a..34afe80b46 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h index a1b926d3af..c8f241db42 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h index 379a9c5345..f91cb463a3 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h index 6ceec6e12a..54067a392a 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h index e783941115..8ee26f5981 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h index f0ea11eda8..6e3695c652 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFM32PG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG28_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h index 8aee45a5d4..afa398b622 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h index 842acbac68..5140ada523 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h index 151aa39f04..f045250be1 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h index 947a0680f8..075df42311 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h index c66d838b3b..124a6d3b00 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h index 5a90dc69eb..c5a03f3f6a 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h index f774ab8c0b..b706e33f4c 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h index e29b22eae7..3d60e0eb0b 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h index 1a04e50b2c..1de82bf853 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h index 0e8112ad91..82f603e192 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h index 1f8118d616..60b73cddbe 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h index 4c407c7541..9fe2ba7602 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h index 7046fe63ca..6ac5538e80 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h index aa50587dfc..1501d876b1 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h index ee1b3fe33d..efa1dc3351 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h index 08e0ce17e0..16ae96f8fe 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h index 140afd783f..9112313b25 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFM32PG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG28_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h index 270a102252..ffb6ea169d 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h index cac9fb7aa0..30d8ba7c1e 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h index cd1de945c7..e1b89bdea0 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h index 4cd7f96d98..39fff68c97 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h index 162e1ef78e..459c8654e5 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h index af89d3ba5f..b7873a0b70 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h index a5a4b3b254..e38b7be53e 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h index b060e0eb10..0f5a726fd8 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h index a7295d5be8..ad4174399f 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h index abbf75d932..58b6ebf314 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h index aaae2a1c8c..642a7ae36e 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFM32PG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFM32PG28_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h index 3ace1cb881..bcb8e72bf4 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h index 7810f49863..fca4862ff5 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h index 4dfd6623bb..37a7c3eaee 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h index 985c4e8215..96e0963eaf 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h index e46d7188cc..f52966c00e 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h index df2a8223d4..99a5f18dcb 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h index a90cfb9188..359d17ae93 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h index d6ecccd5fd..4167339a18 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h index bef1691f62..1dece9aaa1 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h index 2532c00a00..cfd74adee2 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h index 84aef6f139..20c7f7b70e 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B200F512IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h index a1e8cfd502..72bd648830 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B210F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h index b3a21a248b..42b0d4a35d 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B300F512IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h index 2508ac603b..b47df4c2da 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B310F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h b/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h index 2aac030ded..90023ad16d 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h b/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h index 422011a4d8..fdd63d7168 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFM32PG28 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Source/startup_efm32pg28.c b/platform/Device/SiliconLabs/EFM32PG28/Source/startup_efm32pg28.c index 4ced3c8e01..c81c8bae7b 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Source/startup_efm32pg28.c +++ b/platform/Device/SiliconLabs/EFM32PG28/Source/startup_efm32pg28.c @@ -4,17 +4,6 @@ * Device EFM32PG28 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c b/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c index 069f068a99..8fc83ce35c 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c +++ b/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFM32PG28 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h index 13a2717e07..29eb0e91ef 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h index cff939095f..116107aa04 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h index 2cc966a2c9..214d57542e 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h index 781092adfe..a1ba0ab632 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h index d266efcd4a..0cca24dcbe 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h index 45f90aefab..ea38883519 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h index 9c340090b5..56265a0f13 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h index 4415ec5f9f..6a9dbbe143 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32BG21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG21_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h index 47111ca2f5..a26fe89d5c 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h index fe1f89fdc6..b6315438b9 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h index 17d1a96865..7cf802bc6f 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h index f63c400566..b69f31e6ce 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h index cbc08d2011..239da458cf 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h index 8125370ff6..385400174a 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h index 99eaf3a580..326eab12eb 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h index ada0636818..0bb570e6ad 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h index 01d0b26793..e087b5e83c 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h index 1f8f5e17a9..4c5f8b3c11 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h index 04f8ce5ea2..d7beb11585 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h index d2ae85668c..e13185df4e 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h index 27bb300125..91374ce6fe 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h index 067215ac54..7835f3a021 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32BG21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG21_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h index 844d55e382..0143c4aa77 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h index 2212887876..021a604be3 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h index aba06f2483..3ed95cdc50 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h index b8db48f291..48132a5dea 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h index 302dc51fd6..64809d53e2 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h index 1f790d786d..72d2de1798 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h index 55702da04f..070af13b2b 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32BG21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG21_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h index aa1a68a003..8868f49f55 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h index 1b5568736e..2493d060cd 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h index ad2627e413..df1eb493f0 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h index 189805a886..85a0003849 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h index aec75a1f8a..9dda997fc2 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h index 3916492c2c..170ddd40fa 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h index 5e97250212..0292370dff 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h index 7593799f05..e5528e7fab 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h index 2c6a6b3d80..d8989940e9 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A010F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h index 10fb1ab074..9157af39fa 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A010F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h index cba991f24b..5297da2402 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A010F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h index d5b3947795..c2c44474b8 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A020F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h index 1cd85451d1..7f4cc69bc7 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A020F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h index 0bfb85a103..47353ff4e3 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A020F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h index 5a1440b04c..004f94eafb 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B010F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h index 301d3389f4..f84797e172 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B010F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h index 29e95fe3af..6537a776b5 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B010F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h index 4561517233..f422b250ca 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B020F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h index 2c20c832e2..e33cd6efa6 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B020F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h index e607034a47..d4f7122d81 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B020F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h index e2ef677953..edb19f0664 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h b/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h index ffcb0ca7b1..bb96c0808a 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG21 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Source/startup_efr32bg21.c b/platform/Device/SiliconLabs/EFR32BG21/Source/startup_efr32bg21.c index 6ba9c0a6b7..5f8d08d866 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Source/startup_efr32bg21.c +++ b/platform/Device/SiliconLabs/EFR32BG21/Source/startup_efr32bg21.c @@ -4,17 +4,6 @@ * Device EFR32BG21 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c b/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c index 82e74b1926..b83390f48a 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c +++ b/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG21 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h index 844dc23ae5..a2c414d110 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h index fc5e5a463e..5e2bb3fad8 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h index ad37acb9ef..99bca304ef 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h index 8f68415ebe..901196d646 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h index 50f4cd2c0f..2c132fceb8 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h index e37009a5c2..9d95d0844d 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h index 109a33729c..dffe7cf203 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h index 252a3a95ce..eca7ebbe7a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32BG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG22_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h index 41baffa6e1..3e6983ec8a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h index 4b9f97dd3a..2b258bb1af 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h index 5a3e7793fc..47bed125ae 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h index 8303600dc0..9376a88d9f 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h index d932a85779..86b81e49d1 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h index c76b1f88c4..fc8bc6538f 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h index 4bb6f31e06..2fa7fb3b61 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h index 2ca54e965e..54873b642e 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h index ae13da97a2..e2fb7ed921 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h index 9489efc154..a7a46a225d 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h index 1f261c5c56..44d30e32d4 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h index 953e856399..20d2b224c8 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h index 628856e0e6..c83307099b 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h index 229ce9d863..03ec56ff2a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h index 87c087dbe5..c3817ff18d 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32BG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG22_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h index 2d4c6544cc..bc04df92c7 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h index 781aeaecb9..9aaaa948a6 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h index e0f049f3a9..22dab1f2e4 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h index b7b48ee381..1f2339f159 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h index 02b3856857..f1b01732d2 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h index 0a438b4183..498de285fd 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h index d669130ede..195e4abef5 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32BG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG22_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h index c8f5d8f427..cc89b37ef0 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h index c0a14b9df7..8f964fd674 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h index 837753863f..850853879b 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h index c4f079a2e2..c1a339f5f9 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h index 25e20d999d..7c78f499e1 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h index fab9afd2c7..53573dbd50 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h index 4634b7afbf..cf05c489b5 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h index e4d27c7aa8..dcf77646b5 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h @@ -4,7 +4,7 @@ * for EFR32BG22C112F352GM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h index 43acf415d7..ae7e386c25 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h @@ -4,7 +4,7 @@ * for EFR32BG22C112F352GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h index ffebc18b0d..66d2ee5562 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h @@ -4,7 +4,7 @@ * for EFR32BG22C222F352GM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h index c15df273ed..ebe56c223a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h @@ -4,7 +4,7 @@ * for EFR32BG22C222F352GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h index 262552109e..2920f0be42 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h @@ -4,7 +4,7 @@ * for EFR32BG22C222F352GN32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h index 4a565b1ae7..d1e0ba725a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512GM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h index 88c32a5e57..6e9da767fe 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h index 075ed737c1..ddcdc92fc8 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512GN32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h index 4d5c927361..fa6b4df466 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h index a410b0ecb1..b2598411c5 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h index 7b6f14f2ee..1a7d74face 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG22E224F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h index ec47161611..cd6da63a9d 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h @@ -4,7 +4,7 @@ * for EFR32BG22E224F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h index fc21472cc1..c3664de61a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h b/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h index e971fcb7ca..ae610a2fc0 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG22 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c b/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c index ed165d80a0..43eb63700e 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c +++ b/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c @@ -4,17 +4,6 @@ * Device EFR32BG22 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c b/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c index e7273d112d..1a374a839f 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c +++ b/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG22 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h index 1ea9d656e8..03b5bff255 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h index 7d305afc82..3abbefba99 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h index 6a3b48329d..5ca6a742fa 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h index a255303194..3b652d9d0c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h index 6d4cfda2c0..8cdfc53a0c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h index d0ac99ea6e..37a655b8f6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h index 6f8b31b083..a554b9eee7 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h index 3e52ec7f7b..fb6398568c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32BG24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG24_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h index 47d84605e6..e79455f3fb 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h index 844519265b..6ee6f0f768 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h index e4d203a172..d355f4b4c7 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h index 04eaf2c547..efbb35b61e 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h index a68eb6bbce..08fc1e9bed 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h index 46f667bf41..59d9030540 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h index 5de7e8d752..caa7e02f31 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h index 8577225413..c4e4e7e5ff 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h index 50ea088380..3fcb126ebd 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h index 1a76b7c77b..09a852ca52 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h index 9b3e19388d..b3cc6b048e 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h index cab03daf18..ff1a37f31a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h index 4433f6e5ed..10597fbafc 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h index 2e62396acb..1268f129c9 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h index 41b6c92f85..c77467fe7b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h index 5bc7e86a2b..ca3eaf3b96 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32BG24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG24_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h index 18e2073f78..6c135cb623 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h index b6c124e856..555d51a2d6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h index 68f23b8e9d..92693e4ae0 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h index 683fd2c618..93c1b015ef 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h index 014ccd3f9b..b01d3b30bb 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h index 7c55fdf7e7..12ef44a13a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h index 0d3c821d98..43b5d4685c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h index 0d50003783..c9023b88e1 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h index 74b4e3a29f..23006f3cd9 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h index 291aecc923..18ba3e093f 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32BG24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG24_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h index 86c114b6b9..4da390e184 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h index 5366255728..c7836f9108 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h index 3801c62eee..948232e38a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h index e26355dd01..1a6e4d864f 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h index a32de2e703..1e8c9efaa6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h index 94015b2b1e..1dad71e6c5 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h index b8d93ad4d7..4e682efee0 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h index 3aa5f01b35..eec6bd223f 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h index 7022cc08e2..5ff20774b0 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h index 925569d163..87f80c0b66 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h index 174f90ce8a..76f1ee5ee7 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1024GJ42 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h index 6b50327f18..55ed5e5d91 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1024IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h index 92febf4f9d..7b0635e98b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h index d4f76e92bf..bd3ae478f3 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h index 06cc4b68f0..88d23df0b6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h index 3706d345be..546323bc12 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A020F1024IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h index ce983ddf61..20274ce2ac 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24A020F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h index 171d14b0c7..34ca3a4a24 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A020F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h index 6a66886d62..acaf7de8cf 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A610F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h index f57581d2a4..bc06f46cb2 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A620F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h index 66858863a0..1687e2751f 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h @@ -4,7 +4,7 @@ * for EFR32BG24B010F1024GJ42 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h index 97568a0d73..ce9cdfbf35 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B010F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h index deab051587..ccef41a539 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B010F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h index c05f528a20..4d4b96b725 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B020F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h index cd384c73e6..bb2285091b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B110F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h index ed5d9756bf..90fc3c5434 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B210F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h index 3539e88962..66418a6f0d 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B210F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h index 296a1d4f5b..cd3e1a2628 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B220F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h index 24f7310bde..56381c6577 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h @@ -4,7 +4,7 @@ * for EFR32BG24B310F1536IJ42 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h index 86ea2e58d6..4997571c44 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h @@ -4,7 +4,7 @@ * for EFR32BG24B410F1536IJ42 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h index 266a0e88bc..97d7ed5128 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B610F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h index 3556481e8f..40e0ed6d6c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B620F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h index 8f8661513b..cc8c1386a1 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h b/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h index 87c2adb75d..665afb22bc 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG24 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Source/startup_efr32bg24.c b/platform/Device/SiliconLabs/EFR32BG24/Source/startup_efr32bg24.c index 13a39f9b0b..cd813585b1 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Source/startup_efr32bg24.c +++ b/platform/Device/SiliconLabs/EFR32BG24/Source/startup_efr32bg24.c @@ -4,17 +4,6 @@ * Device EFR32BG24 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c b/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c index 5efe9f9b00..efd339d020 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c +++ b/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG24 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_acmp.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_acmp.h index fa54b49920..66fd21ced2 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_aes.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_aes.h index 39a3f22e72..4196b57d1c 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_amuxcp.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_amuxcp.h index beb14b4def..2b22b8aa2b 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_amuxcp.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_amuxcp.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 AMUXCP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_buram.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_buram.h index 8273865703..cc71876d29 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_burtc.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_burtc.h index b418122887..3059beb1a9 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_cmu.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_cmu.h index ba7fd9f19d..5bb80c7146 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dcdc.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dcdc.h index 1269a851d3..f6956b4a4b 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_devinfo.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_devinfo.h index 91ebae5b2b..f8f9a7fb8a 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dma_descriptor.h index f6c1e3a7c2..906dc42c5c 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32BG26 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG26_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dpll.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dpll.h index 9cee6ccb4c..abacfae4f0 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_emu.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_emu.h index 753ce1bff6..b9e6609485 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_eusart.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_eusart.h index 8de1c508f1..6123dd82f9 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_fsrco.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_fsrco.h index 4e1c7b02ab..edf84b6d66 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpcrc.h index 5072835de8..dae488639f 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio.h index 0cbe4ac63d..8e5162b00b 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio_port.h index 30ea90ad3c..c79da91f57 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfrco.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfrco.h index 795eba975d..014063a09c 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfxo.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfxo.h index 5a042c199d..df7406ae4b 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_i2c.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_i2c.h index 18ff1f4c59..01e34b2dba 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_iadc.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_iadc.h index c1cb31cb83..15b41c0618 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_icache.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_icache.h index c975e07d9b..065664f05c 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_keyscan.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_keyscan.h index 333d12ca0b..3326a88098 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcd.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcd.h index decbeadbdf..731841357e 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcd.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcdrf.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcdrf.h index 0f4e007798..086407ca65 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldma.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldma.h index 13713cd5d1..9e0c46c172 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar.h index 52b04fa833..1a21bbd8b1 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar_defines.h index 0a9f2a5f40..ff4d2e0449 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32BG26 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG26_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_letimer.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_letimer.h index bb208f0114..ceaecbd9a8 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfrco.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfrco.h index 98daeb1792..37fe8fea64 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfxo.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfxo.h index 0b603a7a0c..45e1b2d3fa 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mailbox.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mailbox.h index 91c675cf4a..1e5b9124c8 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mpahbram.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mpahbram.h index 3ea1c1d32f..27417f518c 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_msc.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_msc.h index c950b63633..c51dc925ad 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mvp.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mvp.h index 38c9a1a954..ba568cccbb 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mvp.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_pcnt.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_pcnt.h index 98ea2e3823..5dd33d0e20 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs.h index bee8ac223e..16c4c9bcaa 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs_signals.h index 440605b322..34e36d2b8c 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32BG26 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG26_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_semailbox.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_semailbox.h index eee662bedf..1757ab8bb4 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_smu.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_smu.h index 8907d55a5b..24b45cefdd 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_syscfg.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_syscfg.h index 075a9e78a1..b5f4d3b759 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_sysrtc.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_sysrtc.h index fdfb9fdec9..71513d4043 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_timer.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_timer.h index 252f3c12af..6dff00769a 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ulfrco.h index 9d546a447e..34d8368d21 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_usart.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_usart.h index fa92a49823..5df270b6e9 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_vdac.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_vdac.h index 7f6df517d9..c5cce7b67f 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_vdac.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_wdog.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_wdog.h index 818d6d6a0b..75dbf03b0c 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG26 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024il136.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024il136.h index 6ad52941cb..218e317468 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024il136.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024il136.h @@ -4,7 +4,7 @@ * for EFR32BG26B311F1024IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024im68.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024im68.h index e3a500a0e0..191b2106ca 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f1024im68.h @@ -4,7 +4,7 @@ * for EFR32BG26B311F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048il136.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048il136.h index da553af6ee..02d20c7b5e 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048il136.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048il136.h @@ -4,7 +4,7 @@ * for EFR32BG26B311F2048IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im48.h index 161fd20554..410f8aa4d1 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B311F2048IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im68.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im68.h index c6bf86ec71..57b46004c8 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im68.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b311f2048im68.h @@ -4,7 +4,7 @@ * for EFR32BG26B311F2048IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f1024im68.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f1024im68.h index 18b0b1d3c4..d421d11837 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f1024im68.h @@ -4,7 +4,7 @@ * for EFR32BG26B321F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im48.h index 4a115e473d..b9de6dfd08 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B321F2048IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im68.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im68.h index abbe10de57..3dcf259b4b 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im68.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b321f2048im68.h @@ -4,7 +4,7 @@ * for EFR32BG26B321F2048IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b410f3200im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b410f3200im48.h index fb44981744..65710fb181 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b410f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b410f3200im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B410F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b411f3200im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b411f3200im48.h index fd4a117b1e..9321d87c55 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b411f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b411f3200im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B411F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b420f3200im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b420f3200im48.h index a50bc7b199..2d09df958f 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b420f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b420f3200im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B420F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b421f3200im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b421f3200im48.h index 5425c07560..db5f361e7f 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b421f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b421f3200im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B421F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200il136.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200il136.h index 6194335ca4..c46ab766ed 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200il136.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200il136.h @@ -4,7 +4,7 @@ * for EFR32BG26B510F3200IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im48.h index 760d07893c..ac4972a58a 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B510F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im68.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im68.h index 62216de1ed..37632d8994 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b510f3200im68.h @@ -4,7 +4,7 @@ * for EFR32BG26B510F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200il136.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200il136.h index 28da310a7f..6f73c698c3 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200il136.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200il136.h @@ -4,7 +4,7 @@ * for EFR32BG26B511F3200IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im48.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im48.h index 544ba46350..aee3c187ec 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im48.h @@ -4,7 +4,7 @@ * for EFR32BG26B511F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im68.h b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im68.h index 23c1d4a0aa..d39d8083ee 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/efr32bg26b511f3200im68.h @@ -4,7 +4,7 @@ * for EFR32BG26B511F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG26/Include/em_device.h index 66222f2126..11ad21c2de 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Include/system_efr32bg26.h b/platform/Device/SiliconLabs/EFR32BG26/Include/system_efr32bg26.h index 1025d51cda..e0069f127a 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Include/system_efr32bg26.h +++ b/platform/Device/SiliconLabs/EFR32BG26/Include/system_efr32bg26.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG26 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG26/Source/startup_efr32bg26.c b/platform/Device/SiliconLabs/EFR32BG26/Source/startup_efr32bg26.c index 92960fe794..a2c7df0176 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Source/startup_efr32bg26.c +++ b/platform/Device/SiliconLabs/EFR32BG26/Source/startup_efr32bg26.c @@ -4,17 +4,6 @@ * Device EFR32BG26 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32BG26/Source/system_efr32bg26.c b/platform/Device/SiliconLabs/EFR32BG26/Source/system_efr32bg26.c index b3e2c2e184..713cbab8f3 100644 --- a/platform/Device/SiliconLabs/EFR32BG26/Source/system_efr32bg26.c +++ b/platform/Device/SiliconLabs/EFR32BG26/Source/system_efr32bg26.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG26 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h index a7412e55c6..4892d53c9c 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h index d7ff7de790..43c68c65b4 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h index dd085f8674..ec10ad2f06 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h index d63eb15b56..b49365123d 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h index a2e550e02c..5e893e9f36 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h index 4b1c56313c..8dcace4bcd 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h index 3d6a73525a..b193869b3b 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h index 65c83b3aad..7d5938a733 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h index 81291ebeac..181c98030b 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32BG27 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG27_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h index c47805a211..a3982937cd 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h index 28f389f036..df5b73994e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h index e3010f9f94..75f964623c 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h index 600d0b07b2..5990a4a07a 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h index 3193e5b889..adda375989 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h index e7d0e47a2a..d2589fe668 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h index 398afbadf6..d183bd4a85 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h index c3270c49bd..3eb414b684 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h index 5d4e8b4503..6c94f6e61f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h index a81a3ca245..92ab3c5541 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h index d1fe798415..4a27cdc394 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h index 358e00e0d5..1a0314e6b1 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h index 26bf71e764..ad1e96990b 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h index f57da12a2c..8dc10738f8 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h index 4423c7c623..4ff3b32e6f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h index d630adde1f..1aad680465 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32BG27 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG27_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h index 9bc3afa5d1..7b2070449a 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h index 086ac1ba50..609c52c7fc 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h index 18bd58d1bc..a15402049c 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h index 8f1e6c7f74..c1f79626d7 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h index 41f4b6eab2..7d9975022d 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h index b9b3482d51..2ecdc1e4a8 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h index 0dd71921c7..8a5fce1f13 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32BG27 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG27_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h index ee23645c35..80f5cdac91 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h index 1c36809277..debb6d3905 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 SEPUF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h index 91906d3e7c..d31c91ff93 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h index dcedb2df36..6e85ed8ddb 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h index bc81f0c675..593d9b277c 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h index 0e0b1aca7c..63267ff50f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h index 10936eab84..33bbffde69 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h index a63674e807..352add0a7e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h index dcc65ae5f1..a529d121b8 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG27C140F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h index b340f900fe..471b2833d2 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h @@ -4,7 +4,7 @@ * for EFR32BG27C140F768IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h index f0b0945913..2d66fc5394 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG27C230F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h index fb869b1425..c0b0302107 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h @@ -4,7 +4,7 @@ * for EFR32BG27C230F768IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h index f33f56db7f..ca91364261 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h @@ -4,7 +4,7 @@ * for EFR32BG27C320F768GJ39 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h index 2a47b295af..ae9ce7c6fe 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h @@ -4,7 +4,7 @@ * for EFR32BG27C320F768IJ39 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h index 03c0634f27..b72c5e5c5e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h b/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h index e5a853d99d..a17e1002a5 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG27 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Source/startup_efr32bg27.c b/platform/Device/SiliconLabs/EFR32BG27/Source/startup_efr32bg27.c index c49f3d2427..29ed474420 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Source/startup_efr32bg27.c +++ b/platform/Device/SiliconLabs/EFR32BG27/Source/startup_efr32bg27.c @@ -4,17 +4,6 @@ * Device EFR32BG27 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c b/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c index 59f7e551ab..b3b3f7395e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c +++ b/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG27 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_acmp.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_acmp.h index dcf6e0f954..e24e2c8ccc 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_aes.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_aes.h index 8f973136ad..631dd10751 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_buram.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_buram.h index 9a9f287e6d..2d09a4f0c6 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_burtc.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_burtc.h index 17dbf0dd0b..6f8dc37dd9 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h index ee643125a6..a873238a60 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dcdc.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dcdc.h index 09dffc9a55..eaf1485801 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_devinfo.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_devinfo.h index 6bbfdaedc4..ac21c6d34f 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dma_descriptor.h index 577159f04e..f267ad15ab 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32BG29 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG29_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dpll.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dpll.h index 244dbc362b..0dfba23544 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_emu.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_emu.h index 96d0c38123..d636ecb911 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_etampdet.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_etampdet.h index f456676a06..7dd3bcf99e 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_eusart.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_eusart.h index 1858d7394f..295d753d9a 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_fsrco.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_fsrco.h index 1c38e1a91d..338becec8f 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpcrc.h index a6c3559ff3..87dc9660c4 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h index 69dee19da7..42dbfc8ed5 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio_port.h index c1432a0ab9..ef658b57c1 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfrco.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfrco.h index 2f6356e5e5..9be726f391 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfxo.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfxo.h index 6492bc553d..abd6aafa62 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_i2c.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_i2c.h index abd5d9258e..ef8eb5e476 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h index 7f25c71ea3..1daf0473c5 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_icache.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_icache.h index 85fefe29f1..5500c67852 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldma.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldma.h index 877b9a364c..81ea90c6cf 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar.h index b27d962d11..901ab4f5ca 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar_defines.h index d9741baf26..023accf6c1 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32BG29 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG29_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_letimer.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_letimer.h index 363d5287c3..de0bde31ca 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfrco.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfrco.h index f29cad9dfc..dccec1ac86 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfxo.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfxo.h index 0b27a680e1..2eb0ae14cc 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_mpahbram.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_mpahbram.h index ca23dfe334..8d63338aa0 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_msc.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_msc.h index bd4e9433aa..b06840613f 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_pdm.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_pdm.h index 646255d423..b21a0bddb4 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_pdm.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs.h index c065fda752..df654161f1 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs_signals.h index 46aaaeffdb..443a1d1875 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32BG29 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32BG29_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_rtcc.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_rtcc.h index bf37da4ebc..31effc6293 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_semailbox.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_semailbox.h index 008ecd0b51..8b67e521f5 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_smu.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_smu.h index b902205718..6dc04a1418 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_syscfg.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_syscfg.h index 8014c40930..16d2cac103 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_timer.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_timer.h index 93a979d7a5..7ed7bcf915 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ulfrco.h index 55207fca98..7bdcd84370 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_usart.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_usart.h index 7d7601bf73..17ba9ffe39 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_wdog.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_wdog.h index fd3d208777..65a132976c 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG29 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b140f1024im40.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b140f1024im40.h index 343b05ddd0..60f02241e7 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b140f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b140f1024im40.h @@ -4,7 +4,7 @@ * for EFR32BG29B140F1024IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b220f1024cj45.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b220f1024cj45.h index 7363c9fc0c..ed3a7d9e8f 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b220f1024cj45.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b220f1024cj45.h @@ -4,7 +4,7 @@ * for EFR32BG29B220F1024CJ45 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b221f1024cj45.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b221f1024cj45.h index 7492dd94a9..3e7c07080d 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b221f1024cj45.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b221f1024cj45.h @@ -4,7 +4,7 @@ * for EFR32BG29B221F1024CJ45 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b230f1024cm40.h b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b230f1024cm40.h index 0be45a0f4d..49f0dd31bc 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b230f1024cm40.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b230f1024cm40.h @@ -4,7 +4,7 @@ * for EFR32BG29B230F1024CM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG29/Include/em_device.h index afe0355652..83e6c13eb4 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Include/system_efr32bg29.h b/platform/Device/SiliconLabs/EFR32BG29/Include/system_efr32bg29.h index 981c25e743..4b0e8eba68 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Include/system_efr32bg29.h +++ b/platform/Device/SiliconLabs/EFR32BG29/Include/system_efr32bg29.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG29 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG29/Source/startup_efr32bg29.c b/platform/Device/SiliconLabs/EFR32BG29/Source/startup_efr32bg29.c index 06bd561172..bd2daccd05 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Source/startup_efr32bg29.c +++ b/platform/Device/SiliconLabs/EFR32BG29/Source/startup_efr32bg29.c @@ -4,17 +4,6 @@ * Device EFR32BG29 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32BG29/Source/system_efr32bg29.c b/platform/Device/SiliconLabs/EFR32BG29/Source/system_efr32bg29.c index 3ba78ea4bc..d4369a552c 100644 --- a/platform/Device/SiliconLabs/EFR32BG29/Source/system_efr32bg29.c +++ b/platform/Device/SiliconLabs/EFR32BG29/Source/system_efr32bg29.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG29 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h index c98767cf71..ab34433a7b 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h index d4776d8da9..17d676babb 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h index d251daa211..23cd59f6a8 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h index 078d530895..64cde54b59 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h index 9ba657d388..f7e22f4f1e 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h index 528f6b9a21..413cf447da 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h index b6b5157ac2..67f68f9255 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h index 6599346360..4977111668 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32FG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG22_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h index 7790b1f214..c48dd9ed30 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h index 71893d5e26..d52050d716 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h index 7a6caeca70..5b73bee45a 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h index 005f86ef52..371ceaa105 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h index 89dcd24d0e..adc38434a8 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h index b1a46f41bd..108461e2c4 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h index 52055a2b89..d60ffac4ec 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h index 34ac96629c..3a02f3c772 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h index 934831a66c..9764b65bfc 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h index d04c2b7297..0737570ef6 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h index 4b85a16e9e..f44fe6daf2 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h index 433df2da90..de72eb21a4 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h index 4f0c01a901..a9accd0f73 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h index fee953cf7f..3f86aeb564 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h index ab056c6167..980f96c86d 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32FG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG22_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h index 5e7033217f..0b15f03e5f 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h index 7c3089f50e..fd11a68b1b 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h index b4df380251..230c962814 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h index ac3f4d32a2..ac26466102 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h index ff751a1183..568a18be8c 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h index 303f9b1af5..7aba9de597 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h index f961e7c48e..f56dbdfa99 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32FG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG22_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h index a59c30f2b0..5b0ea072fd 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h index e3f192299c..d070e06511 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h index bca07a5369..4ef7305f69 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h index 1bbb2ffde5..d9e6022e57 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h index 0496156e25..cfa2ad29f4 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h index f7a780312d..477dab18d9 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h index 2d08bb790d..55191c278d 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h index b989995d62..abc2f917ac 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F256GM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h index 88264bffae..8a3f19666c 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F256GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h index a3619080f2..5fef56db6c 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F512GM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h index ec9f7a6ab0..c76d9f8f93 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im32.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im32.h index f501821ba6..7b01ba8fff 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im32.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im32.h @@ -4,7 +4,7 @@ * for EFR32FG22E121F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im40.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im40.h index c04585449b..b7def70e59 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22e121f512im40.h @@ -4,7 +4,7 @@ * for EFR32FG22E121F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h index a2c8419b84..1070c6f39b 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h b/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h index 678fd6f2ff..47bc8d4691 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG22 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Source/startup_efr32fg22.c b/platform/Device/SiliconLabs/EFR32FG22/Source/startup_efr32fg22.c index 3c4344051e..9e6be42bcf 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Source/startup_efr32fg22.c +++ b/platform/Device/SiliconLabs/EFR32FG22/Source/startup_efr32fg22.c @@ -4,17 +4,6 @@ * Device EFR32FG22 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c b/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c index 05ab22706c..560ca53bbc 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c +++ b/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG22 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h index 5a2c6d73d7..607ccf6112 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h index e588b2f7dc..f27e1a5055 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h index 7be7745614..65174ff168 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h index 7c809e011a..a57b182646 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h index 5eb423f672..5e1db96b8f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h index 58ae29b7f5..0fce15a59a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h index 5e342a2740..3103d57409 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h index b32e19e33f..1acd4e6e92 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32FG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG23_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h index b50eb44704..e29d9389b1 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h index b3f9b7c17e..dc1c05cec0 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h index 2e7ac7ebba..4cac67014a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h index 9505eef77f..6dc395340b 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h index ca7be94c12..7230258fc7 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h index 946d9d96c7..63f6457579 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h index bb8d6a904b..a11af00107 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h index 6e26c75cfe..bd24e8e03c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h index 4c8099f957..d5e0eb82a3 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h index bf8b555f24..2a4fed94bb 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h index b3fc63cf56..5d9cd29088 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h index 377e870bd0..7a7295177c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h index 2840223688..aed5b83800 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h index 1b5985bccc..492a921a1f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h index 93b982288f..51e614d7b4 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h index 4ae59b1c65..5cfcaf2b65 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h index cb7f5bd807..89b9214d12 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h index 4f1405cd12..2b61462840 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32FG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG23_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h index 16b1bec8d7..b2e648f396 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h index 58f3c4fecd..51bb21c5f7 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h index 5e6071476d..e484454f43 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h index 9bc5e9e67e..a2453eb5a3 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h index 31e5dcc22a..dd370c7f29 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h index 86fb65434e..8542bb38f6 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h index 67b7613f67..a1ffa48c33 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h index 904f071cba..c5e5673610 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h index 960013e65f..f15f5fc7a8 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h index 135e046fe6..fe91a2a305 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h index 5c181d3101..3512768769 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32FG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG23_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h index 10f2772b6e..4b6ebf298d 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h index 908bc3596a..6bbe0de3f9 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h index 6f570789b9..fa37835efb 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h index f42a1d2ceb..ea44b4c76f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h index 166b5e0bd9..817d2f103f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h index 40ded7a263..d8916c523d 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h index 39af8ab3c1..1f9178720c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h index febcfdb365..744f8848c6 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h index 52dbc5fcc1..973127badc 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h index 2c87ec7bd5..efe04ebfe7 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h index 67ed785284..c7c8206b44 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F128GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h index 8f8e04a078..d8bde32e9d 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F256GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h index c3704274ca..62e5076080 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F256GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h index e6e5e59f20..dbc544970d 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h index b6b2d6404b..bf340afc06 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F512GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h index 93584d68b6..930a13880a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A011F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h index 762df1f4dc..0d1c186fc4 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F128GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h index edaa4e34c1..5520184826 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F256GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h index ff6c956eeb..fbd9c49714 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F256GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h index aecab965a4..93e740b579 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h index 40a509338e..f94af93aa1 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F512GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h index 86d024f817..9034df4926 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A021F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h index 8659380f73..a27b2ad282 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F128GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h index 35e47b24f9..75dc0601cd 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F512GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h index 6bf48d7230..2b8e9c50b9 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h index 6ce045ed31..1a8c1c112e 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h index 5e6fd9ce1e..9c2d08b709 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23B020F128GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h index 78b76349c7..482b0a7e43 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h @@ -4,7 +4,7 @@ * for EFR32FG23B020F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h index 15a220c192..89f78d3f89 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h @@ -4,7 +4,7 @@ * for EFR32FG23B020F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h index 7e59914872..6e989de285 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h @@ -4,7 +4,7 @@ * for EFR32FG23B021F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h index 4962cb97ec..9733e48c34 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h @@ -4,7 +4,7 @@ * for EFR32FG23B021F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h index 5d4e7c384c..7d4fe03a4d 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h b/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h index 04e9288740..c8954aa8cb 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG23 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Source/startup_efr32fg23.c b/platform/Device/SiliconLabs/EFR32FG23/Source/startup_efr32fg23.c index 045a344aa3..5a5cf6b85f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Source/startup_efr32fg23.c +++ b/platform/Device/SiliconLabs/EFR32FG23/Source/startup_efr32fg23.c @@ -4,17 +4,6 @@ * Device EFR32FG23 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c b/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c index 86f20fa131..5eec2d2bef 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c +++ b/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG23 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h index 0c7311e6c2..0bdd1d67ff 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h index 33ccc3ccee..55aa116de5 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h index 921be0cdfd..cbe05cb3c4 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h index 7ada775174..7b4732fa12 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h index f2c1c54eb6..4be44729cb 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h index 7c89c42a56..5dcc9b061b 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h index 947583bd66..80a150bcbb 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h index 84e0d8a37c..82d986fdc8 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h index 5e7f6c1c33..126f8f798f 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32FG25 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG25_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h index c6ccd721e8..216651bb63 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h index 1d182c04f5..8ce0be218f 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h index 5027f610e9..e39e7d156e 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h index 82a8aac88a..dc9526e924 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h index d543a25b50..78ddc46856 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h index f0d364a9f5..e6860935e6 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h index 4a964cb917..f27aebe332 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h index e6a2058574..3a4539e109 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h index a9545b7f63..d97b9e0a30 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h index f63a453195..838bc50c3f 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h index 0d86a13744..a22041ff0a 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h index 4dbc0a1f4d..912dd4a27d 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h index 9e7f2af0a0..04583339da 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h index 42d74f090d..3b3a4d4cf1 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h index 728f9603cc..e1e8b0f964 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h index af8ca616d5..a0f62e01be 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32FG25 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG25_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h index 0fd6b4c96c..1d75a08681 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h index 8a59de03ac..1272e55dac 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h index e04bbc6181..91e221bcdc 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h index d1bf0787ab..bc95529ac1 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h index b10ffb5ef0..d8b6366e2b 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h index 69403b9cce..7d2ecdc95b 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h index f296a2f6a4..000515329b 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h index f8127f43b6..44b8ef29b3 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h index 0c13361993..df6dd9453c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h index 25033eeff2..a1a7bfdee8 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h index 065806bc90..726003fe11 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32FG25 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG25_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h index 0bf110e05c..63759616fe 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 RFFPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h index 5a9cf5b67d..4e81213de7 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h index 7ced6268e6..7a9da77d32 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h index 88dc188faf..ea21e3af73 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h index f3aa77ee84..157ba6fea6 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h index 58e491611f..c9e4993ed8 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h index 3f82303bb0..80b439ba1a 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h index 4215ea928d..6b833d52df 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h index 441dfed485..1dead69a86 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 USB register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h index 20b423e455..6e930061a7 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 USBAHB register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h index cd386dde7b..cbbde9bbc7 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 USBPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h index e2f9972bef..51c5900fb6 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h index 5270ec5da3..e6efa37c94 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h index 3e673dd563..a3208d15a5 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A111F1152IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h index ecd5238462..b22dfdbc3e 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A121F1152IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h index 857cb4a0d0..7d5cc7bc82 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A211F1152IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h index a586b9328a..e263eca366 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A211F1920IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h index 1f26aed979..869e6120c5 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A221F1152IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h index 78cd496bca..743f15fc97 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A221F1920IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h index f27ebe75a6..a2edff0574 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B111F1152IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h index e3c826df09..ee70cdb04e 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B121F1152IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h index fc4d89ea9b..e1506a387c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B211F1920IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h index 8b69a1f464..9a7d33b3d2 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B212F1920IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h index eb0f96d3fe..f299ae098d 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B221F1920IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h index c570ce989f..cff4fd8498 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B222F1920IM56 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h index f0a71af3d7..1577b9e5e0 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h b/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h index 0cb97ac4e8..2b209be8ee 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG25 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Source/startup_efr32fg25.c b/platform/Device/SiliconLabs/EFR32FG25/Source/startup_efr32fg25.c index e365fd1f77..e11e22b58f 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Source/startup_efr32fg25.c +++ b/platform/Device/SiliconLabs/EFR32FG25/Source/startup_efr32fg25.c @@ -4,17 +4,6 @@ * Device EFR32FG25 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c b/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c index 4c4f7d0918..0bb871e5c0 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c +++ b/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG25 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h index d6a28cd3d7..af1fa415e6 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h index c2818a20db..4ffb3cdd5a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h index 1f5e3a3499..c0c8a95d07 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h index 58c10c2782..ea96a962ae 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h index ba3c3222ab..ff190f1124 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h index cd96598f41..0438915433 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h index 9128a7feb2..7092cdbd9f 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h index 405d13983c..e18b42bfdc 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32FG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG28_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h index f37f553a65..e678d0e110 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h index 08005a592b..9f69ea4202 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h index c31cf609ad..7ebb7ce5b5 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h index 771bfd4056..c8ad67df04 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h index e8eece3b1c..ce3f760580 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h index 164d83a072..f765e91d96 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h index 4b5b3c63be..f34035a06d 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h index 0ca6d015aa..454c2010a5 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h index 0793a76d5c..51aea30312 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h index 8fb709494b..83391dbdb4 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h index 8ae50d3454..bc3c588b76 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h index 2f83f7e8b5..048204b973 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h index 5bc23cd309..022d79462c 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h index 36aa122587..3c4a3cdaa0 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h index 668f68d822..6ca1148755 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h index ab85b67178..56bd22441a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h index 37d7a2c09c..878875a652 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h index dcfdbee9b7..d7f1edf0d5 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32FG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG28_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h index 5053452f2f..5ebf911197 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h index 83292c226a..5d64997e54 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h index 4accdb6b97..b50322ac36 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h index c57f9d0f3a..217fc161a6 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h index 553d1819e3..91534f613a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h index 680b9db6c7..0a444bf4ca 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h index 313ac2ce60..1a7fa8ccff 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h index 0910a69191..f9c890578c 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h index bc4970a4b5..0f94ead2a6 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h index b64ed32776..5c16b76dc8 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h index 46a2359990..6d87a51a72 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h index 37502e67e2..af174a3270 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32FG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32FG28_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h index 7beb7accde..9edd64baa8 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h index e02412d88a..505395e03e 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h index f5e19b90d0..a3113d4314 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h index 35a0e24fa7..782a57b693 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h index 26b11da369..b8e0f4d9b4 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h index c2d5f01432..8712c4f337 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h index 590bf7534e..b7c6e80a56 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h index 9e468fcc37..35e3f8001a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h index 9361d4646f..84bcd7c369 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h index dea27246b5..71d132f210 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h index 04e52a6f7d..e14ac0a764 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A010F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h index b98ae81155..3ec3195001 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A010F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h index 1bdae88780..868905ca6a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A110F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h index 547be7ed4b..57b689931a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A110F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h index b0cca6a38c..4cf85c8893 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A112F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h index 9cad45b943..f592cac46d 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A112F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h index 143dc00a9c..ee167ea670 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A120F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h index 8ed7c357d3..3cdd1b98fa 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A120F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h index 42b10d1e6c..2496fcd814 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A122F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h index 71a06b5426..90420320cc 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A122F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h index 73c41514b6..fa75d5b792 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B310F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h index 80a7adb6f6..3341de2f80 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B310F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h index 57ad08eeb2..6465d3df80 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B312F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h index e44a883963..9d24299a5a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B312F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h index 68c1163d04..3d89b985cd 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B320F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h index 433d09da43..0dab29fcbf 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B320F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h index 4cdd6db526..c464701ecb 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B322F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h index 3337ff1d58..6ad593da62 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B322F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h index fb793ff64e..6d335010b4 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h b/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h index 5859430d0d..02aed308bb 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG28 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Source/startup_efr32fg28.c b/platform/Device/SiliconLabs/EFR32FG28/Source/startup_efr32fg28.c index a60ccaea2a..1aaf96276a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Source/startup_efr32fg28.c +++ b/platform/Device/SiliconLabs/EFR32FG28/Source/startup_efr32fg28.c @@ -4,17 +4,6 @@ * Device EFR32FG28 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c b/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c index 5d62ddd49e..1c893ba805 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c +++ b/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG28 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h index 641d70c475..4ea77a672c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h index 78264b3243..70c677db60 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h index 13ae4c2c74..0d9ce43858 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h index 892b90aa79..d4de7da99f 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h index 2abb8adefb..4dd1aa4c9a 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h index ad2d35ad78..e03016a72c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h index 24ecb20123..b7192fb1b3 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h index bb08d0ce23..d592b257d2 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32MG21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG21_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h index 35351f52ff..981f7cedcc 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h index 535f89dcaa..41ec2ca150 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h index c7e3e957b7..7a5e2a5372 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h index d883bc6148..62b74222bc 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h index cc81d87ac4..4e931d5e82 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h index d9227b64ed..458102cebe 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h index 241bbb575d..34d8619697 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h index 7641b0fdbe..298e7effb6 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h index 7a95ec2aa9..fdc30fe963 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h index ebc428eb3e..ae922ce58e 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h index 6dd78fe387..face4c8ecc 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h index c838f40d88..ec18f8b8e9 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h index c9fbf46a86..a213400326 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h index 60f3ace124..dd2f457811 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32MG21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG21_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h index 6b03654d34..4178bdaa7b 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h index 252ec2e114..ff732ef7f9 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h index 1dd6befc59..2d8e208836 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h index e42cfc5e3d..6a9d3f6093 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h index f290c7c5c1..965c3c9672 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h index 6fa8c2a3ff..921939f65d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h index d8e8896b25..f5e3784066 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32MG21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG21_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h index 8324f8be76..a9f2e9f1a0 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h index 5910741d72..805061885d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h index 003d345543..7f90474d4d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h index 401f6a376b..1671f11fd5 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h index 712314e117..5728824a0f 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h index bc92a1b74e..a645c2c485 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h index 04c4fb3703..18363c1270 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h index 30f7b2c412..9a5ee03faf 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h index 2ba711606c..21dd80076c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A010F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h index 73e64bd545..8af8bc95eb 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A010F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h index 456bb9e4cf..3ec4b79581 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A010F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h index 385b11a3bb..a726f62796 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A020F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h index 04e2de6806..8da16c9649 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A020F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h index 3a6658d277..3cae8f138c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A020F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h index 1abc19cc09..ce52d7417d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B010F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h index 8dfc31f159..0de13a1797 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B010F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h index ac2eb7bb88..5b2e78363d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B010F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h index b1366c022c..a5985b864d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B020F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h index e2b5113f82..dfd44a02b7 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B020F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h index 63a9c53df3..577ac27af3 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B020F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h index 42b4490095..7f440b1042 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h index 2083f52d99..fefd454af4 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h @@ -4,7 +4,7 @@ * for RM21Z000F1024IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h b/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h index d002283b41..3b95ea0e90 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG21 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Source/startup_efr32mg21.c b/platform/Device/SiliconLabs/EFR32MG21/Source/startup_efr32mg21.c index cd213319ca..6785dd24de 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Source/startup_efr32mg21.c +++ b/platform/Device/SiliconLabs/EFR32MG21/Source/startup_efr32mg21.c @@ -4,17 +4,6 @@ * Device EFR32MG21 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c b/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c index 347d42b22d..5031c6f19b 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c +++ b/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG21 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h index 28962040d8..332aaa4dd7 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h index d1762f402f..8b70e27545 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h index 18566c9e08..bb520f4e15 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h index 223bf2bacd..6f429c28cc 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h index 21c51599f0..7d967de05c 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h index 1e0a698b69..5a8cc23c39 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h index 2c6f0d3781..c9cbd031e5 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h index 391914a3fb..5c18b07d2d 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32MG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG22_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h index 072ca642d0..bb9f002a66 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h index 8c028fca26..37ba827ca3 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h index 776ce75360..95469bce70 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h index cfdf1d25f8..22882a91a5 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h index dc429d2b4b..ac23211506 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h index 50c122f06b..6a5bad3496 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h index f483de7274..29ac9dce95 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h index b510641085..dd91ab0275 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h index 3636228712..844a4edd21 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h index 66466aba75..80d613baa8 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h index 4a05f96ef3..a37f832c17 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h index fd8f001f85..3540cfdaf4 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h index 0b5901f63f..6ad0a31e6c 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h index 891738344a..0113791ffc 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h index 54a3cd7e74..d1997ed334 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32MG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG22_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h index 696beb9d4e..b8f0590b94 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h index 3b814c7c73..47b57d530f 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h index 7a8c78d75d..f4a14de242 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h index d1c3c19c8c..fc92cbdecf 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h index 19c3a802bf..80ba7bd8e5 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h index 77ab0342c4..3ddef70b98 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h index d41df3e0f4..b32588dfbe 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32MG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG22_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h index aa8ab51f44..f5ea606231 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h index e2b110bf5e..f06835740e 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h index 46fd116af3..d9ed50da35 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h index 54abd0bbaf..102500cef7 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h index 865f98490f..d8ec2c941b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h index 6be97dcd4b..ce30834069 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h index 9c76718154..d2504bde07 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h index ed0cd79a58..c5eb86e3ee 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h @@ -4,7 +4,7 @@ * for EFR32MG22A224F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h index d11d34999a..139664e680 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h @@ -4,7 +4,7 @@ * for EFR32MG22C224F512GN32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h index 7e0849ebbf..73839df297 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG22C224F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h index 5e806b195a..1734ee9928 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h @@ -4,7 +4,7 @@ * for EFR32MG22C224F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im32.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im32.h index c44cf53505..7c328f7eb1 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG22E224F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im40.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im40.h index ff18148680..04aef1c72e 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22e224f512im40.h @@ -4,7 +4,7 @@ * for EFR32MG22E224F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h index 6312a49101..722b6b5e6c 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h b/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h index d6024f523a..9464789a63 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG22 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Source/startup_efr32mg22.c b/platform/Device/SiliconLabs/EFR32MG22/Source/startup_efr32mg22.c index f25ec065ea..374f82978b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Source/startup_efr32mg22.c +++ b/platform/Device/SiliconLabs/EFR32MG22/Source/startup_efr32mg22.c @@ -4,17 +4,6 @@ * Device EFR32MG22 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c b/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c index 8bf325b9f0..c77d189a3a 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c +++ b/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG22 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h index 68c8dbd042..59d35387d6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h index 730a34e28e..c961a7018d 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h index 9239c9f38e..778d8cf402 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h index 70a3b54e85..f71e8f7797 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h index 2c7add2e06..e037e3a72a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h index 980974e9db..394631331b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h index 4e443e421f..9626e4abc3 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h index 8dd6a7e0bc..70bbc722ef 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32MG24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG24_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h index eaca4e2ff4..1175d14a1f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h index b08ac117bf..d59df20a65 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h index b27eedc672..ad09422837 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h index 167e3c8b57..a98d91cfc3 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h index 6104ab0665..09a12481b6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h index 5599e15ecc..ca645235e6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h index 6e8ead0c2b..2d91100a19 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h index 4849c4924f..ebd1836449 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h index fe4395e1e9..e90c35052f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h index 61725da405..cf1708bb6c 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h index c2f2b6d271..ecb99e6f64 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h index 805479b571..a02553315f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h index cabc5a09f8..05e5b8b97c 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h index ac9c3795ca..40fd1a6acf 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h index 24a3cc411b..5147a9bdda 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h index 56f3178296..3203e0971e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32MG24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG24_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h index 8b8bba014a..c11c6e6e71 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h index 835c9af5c4..4384ad7055 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h index c60a4279e2..49511d1599 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h index 6a441540ce..39c9ead40b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h index 23d31a1be2..dbcecaf2b9 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h index 22b3cdf2f3..cd4155ed0f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h index dac9b9e3d0..761d9cefe8 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h index 860f1e36b7..1efb69336f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h index 85f0bd566f..73d31c5d19 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h index 31d3fb633e..8a5c094287 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32MG24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG24_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h index 5281d1e973..9de131375e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h index b77445b9fc..42afed243d 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h index dad52aae3c..1be70c02ed 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h index 7c2cb511a4..78389e9952 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h index 4e58d0a596..e6ea86e0c8 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h index d4eb788630..c2281020d2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h index 5b7fd6b99a..612bc620e6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h index 02ae799c9f..396a37a1ef 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h index d3b9d67dda..174341d5ed 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h index e671c34378..326e8504a8 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h index 8853c1a538..a91633d168 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1024IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h index 6b4c73f06d..ccced1665a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h index accbe42dc5..4b295386e7 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h index 940b3688eb..cefd7a9e58 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h index ee11fb746d..77cc7a981a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h index f6e4d3a61d..256ff0c591 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h index dd279e667e..1464c38a5a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F768IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h index 99149f9184..ae29954e87 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F768IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h index f9ff30d67b..42e6326b19 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1024IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h index 2be559fe07..dfa9d2b58e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h index 6f0d5f26bd..0e99d618ec 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h index 43f598b501..4c677c749b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h index b585e0d9ba..8abcd2c329 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h index d84181190c..d64c05a2d9 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h index 24aa683826..a64b45931c 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F768IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h index a65b4e0a4d..e64a6513c4 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A021F1024IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h index 2881a4b2e3..924ade758e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A110F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h index 594bf4ce17..278a7669ba 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A110F1536GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h index 2df0b07a7b..7f47574d66 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A111F1536GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h index af9be6669c..c55c846233 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A120F1536GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h index 72839bbc9f..1be33a559f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A121F1536GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h index 01c40ad757..2d229dfc93 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A410F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h index f152bc85bc..3bc220ede8 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A410F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h index 9752ee0809..760492a16e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A420F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h index 84b0c9d6be..96507cd684 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A420F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h index 8aa1cab11a..72d4535715 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A610F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h index 2386ea2a92..9d4efb2412 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A620F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h index e5de1c38f7..fc3d4b80d7 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B010F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h index 87f541fa8f..5e8c64d16d 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B010F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h index 8a8ca92b23..5acb45c9b9 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B010F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h index d4aa690ebc..b31250fce5 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B020F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h index a4be1726ba..c84813d832 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B020F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h index b85de32f6f..982c8ebab3 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B020F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h index b06d05d725..32be35cd9f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24B110F1536GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h index 26f3de3a2d..94b649f600 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B110F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h index 38cfacb8b6..be1c31cbc9 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B120F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h index def1a2f2b9..acca0cf8a6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B210F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h index 1d62e244fc..ad81fcde1e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B210F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h index 38d7494436..c2a4d6e61b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B220F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h index 0664ba1c24..b0e304e12a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B310F1536IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h index 0271d9a74b..37d1c2dd37 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B610F1536IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h index ebcaeabe10..7ffa249a97 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h b/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h index a9764f2d80..b5cdd40693 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG24 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c b/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c index 9757efdd24..b59b81ed43 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c +++ b/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c @@ -4,17 +4,6 @@ * Device EFR32MG24 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c b/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c index 7a8dbfd195..abe6760cce 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c +++ b/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG24 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_acmp.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_acmp.h index 586c765208..935b09b8d8 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_aes.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_aes.h index 5dc5810e16..0fa1039af7 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_amuxcp.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_amuxcp.h index 0b575db0d4..ef3c4c2641 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_amuxcp.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_amuxcp.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 AMUXCP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_buram.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_buram.h index eb1aa7503f..3baae28932 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_burtc.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_burtc.h index 31307e2e92..425fac63e4 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_cmu.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_cmu.h index 0884976aaa..003da40bf0 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dcdc.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dcdc.h index f212ff0392..c708dce1b7 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_devinfo.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_devinfo.h index 74e3698e08..34459aac50 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dma_descriptor.h index 04632b26ec..dcf8bef083 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32MG26 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG26_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dpll.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dpll.h index 419d722e5e..3967a96b0e 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_emu.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_emu.h index 6bc893a4a3..c35c60957a 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_eusart.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_eusart.h index db9da47832..f73e51de50 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_fsrco.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_fsrco.h index ab561eced1..663f4535d9 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpcrc.h index b6239bd182..778c74f869 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio.h index 2cacb4380f..961fcdf6a6 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio_port.h index 873b0af5b1..458a409c94 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfrco.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfrco.h index 01b8c4c8b0..fad20f1be4 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfxo.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfxo.h index 671d51c8d2..c4e9e78dce 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_i2c.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_i2c.h index af5ad2762e..9a9a98632d 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_iadc.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_iadc.h index 63ef5e1d75..50e8968362 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_icache.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_icache.h index 68034932e3..112614387c 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_keyscan.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_keyscan.h index 2402ca6061..e54711a196 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcd.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcd.h index 0fc63f01ba..465ed52d03 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcd.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcdrf.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcdrf.h index 0f7995a6ef..3417fe7c16 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldma.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldma.h index 5369562e20..69602e9f85 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar.h index 4f22a7e220..8bb7b0ed51 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar_defines.h index da98da24c4..500f5d6d93 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32MG26 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG26_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_letimer.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_letimer.h index bffa3a9073..e9274bfb59 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfrco.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfrco.h index 367078e275..0c0c2afb88 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfxo.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfxo.h index 4920cd311d..b0460eeef2 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mailbox.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mailbox.h index 4d17896f9d..537c0c0c3b 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mpahbram.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mpahbram.h index 912f890609..35e62dceb1 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_msc.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_msc.h index a0eef9d0ac..b34ce8d7a5 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mvp.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mvp.h index a4dc9933c4..bc19168611 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mvp.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_pcnt.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_pcnt.h index 71cb47ad96..c029acc770 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs.h index bfd73182a7..a8c0a57e84 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs_signals.h index 5a7619b5ac..b501a62ce3 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32MG26 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG26_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_semailbox.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_semailbox.h index 7931dac89b..51c7f56b18 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_smu.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_smu.h index b30f6fd1bb..3d211bddd8 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_syscfg.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_syscfg.h index 5450780f9a..e780069851 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_sysrtc.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_sysrtc.h index 4113ace6d2..7b50095dad 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_timer.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_timer.h index b996e8a0b5..4d097aa25c 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ulfrco.h index 00cae10fe1..9e35c7a294 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_usart.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_usart.h index b8f7107d3e..82d5584aa9 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_vdac.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_vdac.h index 8f372f76da..c8b73d5045 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_vdac.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_wdog.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_wdog.h index 510a69320e..6ba1612a9d 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG26 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f2048im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f2048im68.h index fb0f2751c8..ee589a5714 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f2048im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f2048im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B211F2048IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f3200im48.h index 671ab4225f..c649177d79 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b211f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B211F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f2048im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f2048im68.h index 247cffba55..e4444884c5 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f2048im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f2048im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B221F2048IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f3200im48.h index 3a52ec845a..0176fddc7c 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b221f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B221F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b311f3200il136.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b311f3200il136.h index 30a039976a..bce8053db5 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b311f3200il136.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b311f3200il136.h @@ -4,7 +4,7 @@ * for EFR32MG26B311F3200IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im48.h index 175a561eff..49efa7e38b 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B410F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im68.h index a9fb7a11e0..bc8a410108 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b410f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B410F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im48.h index 66e551f4b4..2223b3ed78 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B411F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im68.h index 94fbf59bb2..a4f3e90696 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b411f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B411F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im48.h index 78a75dc90e..187b890c87 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B420F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im68.h index 914b4575fb..95d487b93f 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b420f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B420F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im48.h index 210d366565..6978148e36 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B421F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im68.h index 8cc92b3500..fa8dfdc5e9 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b421f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B421F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200il136.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200il136.h index 040bb852b7..67a65c5184 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200il136.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200il136.h @@ -4,7 +4,7 @@ * for EFR32MG26B510F3200IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im48.h index 4b781c3cf3..843a982374 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B510F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im68.h index d8e63fc2d6..6bf1eb2ff1 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b510f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B510F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200il136.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200il136.h index 575f835669..bfa4cb9b90 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200il136.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200il136.h @@ -4,7 +4,7 @@ * for EFR32MG26B511F3200IL136 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im48.h index 24b486026d..3a7f1df572 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B511F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im68.h index 945b6084d1..bdda97daa3 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b511f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B511F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im48.h index 2a3dd0fcff..50d9fc9caa 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B520F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im68.h index abc2753434..52bf24b6be 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b520f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B520F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im48.h index cd2184451c..d49cc9ceff 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B521F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im68.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im68.h index de7c53f703..8c5e65a022 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im68.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b521f3200im68.h @@ -4,7 +4,7 @@ * for EFR32MG26B521F3200IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b610f3200im48.h b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b610f3200im48.h index e9b61f68d1..34a863ecf4 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b610f3200im48.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26b610f3200im48.h @@ -4,7 +4,7 @@ * for EFR32MG26B610F3200IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG26/Include/em_device.h index 9671210708..42a720b12a 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Include/system_efr32mg26.h b/platform/Device/SiliconLabs/EFR32MG26/Include/system_efr32mg26.h index ff5cbcbfaf..ef17628bfb 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Include/system_efr32mg26.h +++ b/platform/Device/SiliconLabs/EFR32MG26/Include/system_efr32mg26.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG26 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG26/Source/startup_efr32mg26.c b/platform/Device/SiliconLabs/EFR32MG26/Source/startup_efr32mg26.c index 1d5a9c514b..93f0a0ba4f 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Source/startup_efr32mg26.c +++ b/platform/Device/SiliconLabs/EFR32MG26/Source/startup_efr32mg26.c @@ -4,17 +4,6 @@ * Device EFR32MG26 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32MG26/Source/system_efr32mg26.c b/platform/Device/SiliconLabs/EFR32MG26/Source/system_efr32mg26.c index 552250e3dd..e065ae25f5 100644 --- a/platform/Device/SiliconLabs/EFR32MG26/Source/system_efr32mg26.c +++ b/platform/Device/SiliconLabs/EFR32MG26/Source/system_efr32mg26.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG26 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h index 2a5f43bcca..69b5f548e7 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h index 38fbbcce1c..9833bfc148 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h index 4565737eb3..80dd6444d0 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h index 1840969e9b..0c4f9d136e 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h index c550eae518..985b3841b1 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h index 0052efee4c..64101426f6 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h index 159b5ac8b9..4ebe41c570 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h index f4d59ef313..cc5938e5e3 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h index 8bc218e057..69029ce969 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32MG27 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG27_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h index 5911abc3b8..aeff2a8090 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h index d2e245bb09..21c52daeff 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h index 0e7584f118..1db59165a0 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h index a96609d219..acab9112fe 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h index 4ce1ccc632..3a816acfc5 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h index 921146a3af..4175b5968b 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h index 18f9d28f5f..c6bf3c7d2f 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h index 5cba1b1b8f..8995bb3dc4 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h index 87de4c1fe4..70895e7b72 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h index a2bd674099..a941dd534e 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h index 8b2a1601d5..52e0c86a31 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h index 6be1de9a1e..a79f0062ee 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h index d1cc42ba23..17711e9a54 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h index 202b9b86c0..538ae5c3e6 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h index c73692e7d4..a495120127 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h index 6a192b991d..c07222c5d3 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32MG27 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG27_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h index 845e275545..0ad81958ff 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h index 8d8f210917..e69aa87460 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h index 87cd2e0f58..42a4c082a3 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h index 3848bdb757..09e9b6e893 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h index f259d89d1c..d44b535604 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h index 6d3e918ea1..545b26ee4a 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h index f4fbcbf4fd..20d9db6471 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32MG27 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG27_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h index 57856ca5ed..3950e24f7a 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h index 500e6d685a..0da4249c23 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 SEPUF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h index 64dd8be5e5..265eae1b1f 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h index b0b9162565..0c7074a198 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h index 8dd231e1e5..152bfe351a 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h index 0e46bdf3e9..788477656a 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h index e671e265c6..e968f5e0c4 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h index c7911da521..53109d1325 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h index c0fb14e260..7978e33e5b 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG27C140F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h index 1877bdd2a7..25b3c7bbb2 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG27C140F768IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h index fff5f7f9d3..725cca9612 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG27C230F768IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h index a1ec37a88e..b18def92d1 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG27C230F768IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h index 5f3b12c4e6..8d4b2331e6 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h b/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h index 44b0f098f2..aefa8fbf0c 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG27 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Source/startup_efr32mg27.c b/platform/Device/SiliconLabs/EFR32MG27/Source/startup_efr32mg27.c index 35915cd41f..72ea67acf2 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Source/startup_efr32mg27.c +++ b/platform/Device/SiliconLabs/EFR32MG27/Source/startup_efr32mg27.c @@ -4,17 +4,6 @@ * Device EFR32MG27 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c b/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c index 91315531da..2068c80d83 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c +++ b/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG27 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h index e87ceef22d..e9dd793ba1 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_aes.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_aes.h index 56a3f1e2d7..e4c4bb4c9f 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_buram.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_buram.h index 929b00f636..ce817e0067 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_burtc.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_burtc.h index 94ec1878b0..9b158f0efb 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_cmu.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_cmu.h index 2444dbcd26..f7090ae7a9 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dcdc.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dcdc.h index 8bbc8b0cab..946bfa4f46 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_devinfo.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_devinfo.h index f124cda1c0..017aa54c04 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dma_descriptor.h index 9f6572a839..1bffd07b87 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32MG29 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG29_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dpll.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dpll.h index c7fa6428bd..f9072f7bb3 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_emu.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_emu.h index 4e2253c3c4..3ffc9142d8 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_etampdet.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_etampdet.h index e2089a7215..28f56c0716 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_eusart.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_eusart.h index e2775c9d3b..6ba55e6e4b 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_fsrco.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_fsrco.h index d2c8df405d..ff2d52ef9f 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpcrc.h index b7f7f14238..c7b2014d71 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio.h index 29b201a814..a4f548661a 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio_port.h index 1fac848d19..96bc5daa1f 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfrco.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfrco.h index 3e9908209c..2adc64a1d6 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfxo.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfxo.h index 1ded99f815..026ea033de 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_i2c.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_i2c.h index bae1b4e17a..a47c719f41 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_iadc.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_iadc.h index a089cd8136..0bebbd6dc5 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_icache.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_icache.h index c806119457..8975ca8230 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldma.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldma.h index d2f8b9d81c..3b31d2b030 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar.h index 024bb48158..e63d1dd5ec 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar_defines.h index f87c740c5c..9ed6eedd5f 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32MG29 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG29_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_letimer.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_letimer.h index 9c33c752b7..58f7dcea04 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfrco.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfrco.h index 2e626404b9..8a3185bd21 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfxo.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfxo.h index 9884a7cb75..522f11e0b9 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_mpahbram.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_mpahbram.h index 1874d03d5e..5e53506e1e 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_msc.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_msc.h index a519a26923..4de14e1001 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_pdm.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_pdm.h index 914fef64d7..9f5ba7f58f 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_pdm.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs.h index c0c97e9c4f..b55f216f5f 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs_signals.h index bfefad2b7d..8c9be34241 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32MG29 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MG29_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_rtcc.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_rtcc.h index ce19257f61..7e2d379d24 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_semailbox.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_semailbox.h index 887770751f..45ef821357 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_smu.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_smu.h index 131e35caa2..3b1282052d 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_syscfg.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_syscfg.h index 3a1a0ceade..1e2e6ef172 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_timer.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_timer.h index d0bd0c0dc0..0eff42fb3a 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ulfrco.h index 67041f944b..ab57c8898d 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_usart.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_usart.h index af87e1a6de..d50bb4eaa2 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_wdog.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_wdog.h index 3a063251a3..c0127437bb 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG29 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b140f1024im40.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b140f1024im40.h index 063fb38ccd..ef8a11a6c6 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b140f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b140f1024im40.h @@ -4,7 +4,7 @@ * for EFR32MG29B140F1024IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b230f1024cm40.h b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b230f1024cm40.h index 842c13fde6..d5881b57eb 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b230f1024cm40.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b230f1024cm40.h @@ -4,7 +4,7 @@ * for EFR32MG29B230F1024CM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG29/Include/em_device.h index 3f2cec628d..8c553ddd2d 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Include/system_efr32mg29.h b/platform/Device/SiliconLabs/EFR32MG29/Include/system_efr32mg29.h index 9eb90cba55..e4579839c0 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Include/system_efr32mg29.h +++ b/platform/Device/SiliconLabs/EFR32MG29/Include/system_efr32mg29.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG29 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG29/Source/startup_efr32mg29.c b/platform/Device/SiliconLabs/EFR32MG29/Source/startup_efr32mg29.c index 76cb7b5768..aec7dace5a 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Source/startup_efr32mg29.c +++ b/platform/Device/SiliconLabs/EFR32MG29/Source/startup_efr32mg29.c @@ -4,17 +4,6 @@ * Device EFR32MG29 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32MG29/Source/system_efr32mg29.c b/platform/Device/SiliconLabs/EFR32MG29/Source/system_efr32mg29.c index eac647830a..7b768a6cf5 100644 --- a/platform/Device/SiliconLabs/EFR32MG29/Source/system_efr32mg29.c +++ b/platform/Device/SiliconLabs/EFR32MG29/Source/system_efr32mg29.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG29 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h index 845a24950a..cd52e1f7f1 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h index 7f92062357..325a11751f 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h index f1ef35021f..1d0f637051 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h index 22b04ac35a..d908a49ceb 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h index b2f5da2f35..9fca4ba3e7 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h index 37c729484b..2ba66c783b 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h index f3c4ef0b07..2c953d871d 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32MR21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MR21_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h index 46e6ac94e0..a6760742d3 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h index 74bcb57ac7..fcbaf58764 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h index 049d64a644..7b3bef6a9f 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h index 4a42a4fb1d..461eae7e23 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h index 8870116edc..39aae43f31 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h index 373245033f..53e24fa9c8 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h index 0456a13de4..a202e2c540 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h index f6a8731cb3..2017741230 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h index aefbd259ad..536a4fbc22 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h index 66ad9f1def..3576136f5c 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h index b740df9617..a59200500c 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h index 1d23bc5d7a..6789e32b2e 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32MR21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MR21_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h index 748d7af5ee..8056bda4a1 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h index 58483fbca6..46e113d72e 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h index 71c6510d08..8bbbe6fc9e 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h index 7d04051770..daf9d66ff2 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h index 4d5ed512a1..a41f9c7589 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h index 99957c98e6..09367a81a8 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h index 4f538cfdbd..512a0aa7dd 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32MR21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32MR21_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h index 03fd13207f..42ddb52383 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h index 442de86cd1..e30449d027 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h index 5729b7456c..b3e444f466 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h index f7ae2a1390..b46351fed3 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h index e6181741af..b4abd4aa0c 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h index 7c0ff822c1..1a69d8ca64 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h index 5eaf65f67d..f9ff4a6eef 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h index 1df6270dbf..f5abd7b855 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h index 37582f0597..69a51e58f6 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h @@ -4,7 +4,7 @@ * for EFR32MR21A020F512IM32 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h index 7378e038ea..cc83324c80 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h b/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h index 9be2d37663..5c1067f944 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MR21 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Source/startup_efr32mr21.c b/platform/Device/SiliconLabs/EFR32MR21/Source/startup_efr32mr21.c index 8459814a1d..bc320c06a9 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Source/startup_efr32mr21.c +++ b/platform/Device/SiliconLabs/EFR32MR21/Source/startup_efr32mr21.c @@ -4,17 +4,6 @@ * Device EFR32MR21 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c b/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c index 82a6b003a2..73f1491c85 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c +++ b/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MR21 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h index b9acd04b53..7258cdb30e 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h index fc9c722e2b..dcddb139b9 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h index 0f546a2489..900406bf77 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h index c6f252a7d4..7f8b78972e 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h index aee02ec8b1..25afeab958 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h index afb68b3056..99ea03c01a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h index 3f009d7fe2..6ee9386a84 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h index 550f3c1490..8445e444f6 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32SG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32SG23_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h index e70b123523..90e5b3b2df 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h index 665f033109..22e635410a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h index 48df37e0f3..ac9a3f405b 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h index 66b6171547..2a88b7b89b 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h index ce699916e7..6a2f979ddb 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h index ab5c6021f6..3da4ea4baa 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h index d5fbba9967..d1ac7c1a37 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h index 6cdf82b001..d828bb07f1 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h index 4263aa54a9..a65f8567ac 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h index 3943aad7d7..c75d2dee5b 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h index 15622c8e1d..9f8378d582 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h index 83f8725ef8..dc84f32f95 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h index 704090c4d8..737117b7a1 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h index ef6cea2440..bf874849ba 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h index dad15c01d2..5c85dbcea7 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h index 4c7c1a0ee8..d66309d696 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h index 6c5c48dea8..e2fbc265c9 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h index be3306355b..3c36866fdd 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32SG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32SG23_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h index 02b35c07cb..85e864c5fe 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h index ac40291606..6f4bbe34db 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h index 0efacdd3ca..6cf369fd08 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h index 1220eefbbd..9611cc0293 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h index 2c797b9f4f..779b2011cb 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h index d92b1b4f06..b260dcbe04 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h index 080a6f9f7a..a986696bdb 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h index 005ee880e2..1929d24bc5 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h index 381f69b059..3dfe98fe4e 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h index bb1a80f7df..01d58d203b 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h index 53981181b8..c243adc140 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32SG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32SG23_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h index 7937e439f0..e77a2c01e0 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h index eef426d516..f92e16f864 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h index b2f59ca5b9..6944af17c8 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h index 416ff47064..402317c83c 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h index fd7e827702..404b2ba0b8 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h index e6a8139f69..b2b1c377c3 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h index 51ae707179..3dbf239746 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h index a76900c481..7b004be79b 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h index 30ada1d3fc..5599898a2a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h index 1c6a6bde1b..306365ab50 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h index a293e06261..12d72294af 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h @@ -4,7 +4,7 @@ * for EFR32SG23B020F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h index df013afc0f..74b082c779 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h @@ -4,7 +4,7 @@ * for EFR32SG23B020F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h b/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h index 1c0d5b09a1..3be9db01f0 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h b/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h index 7624ffe6ca..295a385ec1 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32SG23 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Source/startup_efr32sg23.c b/platform/Device/SiliconLabs/EFR32SG23/Source/startup_efr32sg23.c index 4971804f32..db777ca2c1 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Source/startup_efr32sg23.c +++ b/platform/Device/SiliconLabs/EFR32SG23/Source/startup_efr32sg23.c @@ -4,17 +4,6 @@ * Device EFR32SG23 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c b/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c index f758188551..1fdac65028 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c +++ b/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32SG23 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h index ec16acda4f..4e1cec6575 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h index c4b421a165..cdc211640c 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h index 26ef8f30f1..27ebc214bf 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h index 92abbef9e7..300034c75f 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h index 40d59b2977..b8397c9e1b 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h index 93a250969f..8eec409138 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h index 7ee8cfc698..4d63bbb1fa 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h index 6afc3a523a..38d643dee1 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32SG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32SG28_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h index b85f8712b0..ca8c6ab1d6 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h index 16f062b951..9407b9225c 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h index 25e0c66d84..63527e96e4 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h index 1b061523e6..c620f963cb 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h index 0ea43dcb84..72a65e9cf7 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h index 0bd85752a7..6809183c8e 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h index e008358524..e529706087 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h index 6db7452ad9..c919236fe1 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h index 86640f49a4..a6409d6a87 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h index 952712057e..5bf7f5da1d 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h index c2fb192402..fcd69a1a23 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h index fb95a815a1..e1ac5c5b88 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h index 0f202c1d9f..15e76dfeb6 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h index 13d77d1046..f5fe1dbe0f 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h index 53ece7a9b6..9dc5d317e2 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h index 56cc9b3be2..118a81b7dc 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h index 489b664620..802bff86dc 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h index 96381363e5..ba9b64ed59 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32SG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32SG28_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h index a660acb21d..e6f62df241 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h index 1a53c86d93..79986a261a 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h index a185e81b3a..acf8c5e90c 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h index e0cf631e52..021327ee06 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h index ad1067c702..5bb0edc679 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h index a0d6b47305..42efc9cd40 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h index 7884f93454..da7e471453 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h index 9fd4d6c95f..68c9139f15 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h index b5ed1626a1..74f2b53a91 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h index 3974ab38a2..d5d766d450 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h index 51d178346c..86faa6e8ac 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32SG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32SG28_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h index 1dbe2c2879..c511cffb7d 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h index f65119669f..1279662d74 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h index 60488acc13..2c4efab13c 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h index c4c995192e..ba24957022 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h index 1b35cc7379..fbb7658dab 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h index 4c97b85265..22be077fb1 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h index 7c20bf7914..41b75b9519 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h index a88dd139ca..e88aa7d34b 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h index 7db07b2257..4511d6b470 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h index 04420060fe..03e68798a0 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h index 1c4f12988c..faed820add 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h @@ -4,7 +4,7 @@ * for EFR32SG28B320F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h index 1db291d870..786f6065dd 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h @@ -4,7 +4,7 @@ * for EFR32SG28B320F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h index 9350528ce2..294c3a3921 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h @@ -4,7 +4,7 @@ * for EFR32SG28B322F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h index e96ad9e7f8..fabaa1b3da 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h @@ -4,7 +4,7 @@ * for EFR32SG28B322F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h b/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h index dfba41eecc..f094f1490e 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h b/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h index 920b820260..ba42630383 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32SG28 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Source/startup_efr32sg28.c b/platform/Device/SiliconLabs/EFR32SG28/Source/startup_efr32sg28.c index 5a7b3a2e1f..aff6ac0c03 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Source/startup_efr32sg28.c +++ b/platform/Device/SiliconLabs/EFR32SG28/Source/startup_efr32sg28.c @@ -4,17 +4,6 @@ * Device EFR32SG28 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c b/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c index 1cb536a879..516786739e 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c +++ b/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32SG28 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h index 96c92057aa..197e83a002 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h index 1aa8f207fa..5276c6ba67 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h index fe4fb54c7d..28de4359a3 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h index 5390ff393b..a3095c0335 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h index 13ee3a9d43..80063df6da 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h index 493acefe9c..4bafb1af61 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h index 7db9611d86..7e14ad6faa 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h index 9a9f5b6fca..1259b57c53 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32ZG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32ZG23_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h index 234a43d0f1..21f7f7bf05 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h index 5ada862da9..6a75d70703 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h index 956f9256ac..bcbfeab9d6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h index 1498655807..98e6b98da9 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h index d9fed2abff..c3d149066f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h index aac7b214e9..3a1e032f92 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h index 4fac32a75c..87fa298fe9 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h index 777b53a0ea..9b43f17568 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h index 0630ad9f33..ab56b7d356 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h index 064b8bf7b6..c25ca869ff 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h index 4aa2c3129d..2e2f283fcd 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h index c28c7cfb8d..d2802a9082 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h index d598f7e5f9..c333a9994a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h index f786d96988..c9c2dee4af 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h index 1e13003b3d..95d2b9c2f6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h index 0fdee72f18..2b17562034 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h index 66fd91c38f..309aa3dad6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h index 7ab7eeff2d..05c0503a2a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32ZG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32ZG23_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h index d2fe29010f..fd0ea29916 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h index c7b71b0507..18b114d342 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h index 62593ea361..e1f2163212 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h index 4b4dc2f7b2..628800eaeb 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h index 15839a223b..e5d89a2c8d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h index 234d49ac9b..f81fc2892f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h index 1ca11ffaa5..96f46c48b2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h index bd42bed174..eac8019477 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h index 418598da69..d6fc0263b0 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h index 410677b292..459a283015 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h index bbad055fcc..a02b7a0c4e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32ZG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32ZG23_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h index ae5ad6f5f3..f0ad6210fb 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h index 86bcba1c03..e570e08ecf 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h index dd1483d7ab..947898ac13 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h index dc990a512c..717980ae4a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h index b0126007d6..5fe8294661 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h index e0d479e977..2810e704b6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h index b63839088b..f4a568ac2c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h index eee5ca287e..6589ef2c01 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h index a384e3d681..4efd7bde81 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h index b00b461a79..f003418d64 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h index c97404fc4e..dcc861089f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h @@ -4,7 +4,7 @@ * for EFR32ZG23A010F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h index 080340f612..33e08a34a6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG23A010F512GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h index f4ad634990..3c258974d1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h @@ -4,7 +4,7 @@ * for EFR32ZG23A020F512GM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h index b8eb08e41a..188f3ac482 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG23A020F512GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h index 9d7d43fa85..abff105e78 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B010F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h index 5b3bfa4b05..2cd78729d6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h @@ -4,7 +4,7 @@ * for EFR32ZG23B010F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h index 7fb3d10b7c..76c2f0da3d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B011F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h index c82c12d649..87d420151d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B020F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h index 4c6fd01ae7..1c241bef0e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h @@ -4,7 +4,7 @@ * for EFR32ZG23B020F512IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h index 5017dafcf4..7239786fb8 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B021F512IM40 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h index 5d395cdd83..be8a320acc 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h index f1c27aeed4..3b2481d44f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32ZG23 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Source/startup_efr32zg23.c b/platform/Device/SiliconLabs/EFR32ZG23/Source/startup_efr32zg23.c index 19013ab770..f56781c55f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Source/startup_efr32zg23.c +++ b/platform/Device/SiliconLabs/EFR32ZG23/Source/startup_efr32zg23.c @@ -4,17 +4,6 @@ * Device EFR32ZG23 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c b/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c index 83e9fc2fe6..c3f97129f8 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c +++ b/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32ZG23 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h index c62b9d17e9..c1d244e9a2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h index 15b79e49e4..7cdd53eed2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h index 4744139660..1ae2fc2aa4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h index 09b168abef..44285f17cd 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h index b2f76ad458..1c4d775379 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h index 8befbbfa87..147661c686 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h index 08fec5485f..aa9aba14de 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h index 72442144f7..a831d38e32 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief EFR32ZG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32ZG28_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h index 21ddd93860..070f5aa363 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h index 9b1bdf4efc..b62b17b296 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h index 70ce8b9bff..5be8b03345 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h index 4ef337be47..d1d670d483 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h index 43d12ad549..30f1ccf99b 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h index 84a91b28c3..972d6a1f87 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h index 346acada67..bc7f736490 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h index 4c99b31dab..10ea71e6c3 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h index 78273f1136..23171f83b8 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h index e73c244a2f..74aad4356d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h index 4472138b15..176c67f096 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h index 75d7df2711..bd91161376 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h index d731331705..3dbd45401c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h index ccfd5b37df..467a9a93cf 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h index df4eecc4ba..1a5419707c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h index 3268b4e7d1..31233946b4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h index 0dc313effc..0882d16abe 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h index 6a6c97327c..c62346ebe6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief EFR32ZG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32ZG28_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h index 35268e436a..5290aefcee 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h index 46325cd82d..6de8c2f8b3 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h index 4c2d9f44d1..6a559d3865 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h index ea1604f1db..3cff7cc515 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h index 6b79711484..ebfc7f66d7 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h index 130c170718..0be95d42c1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h index 15ca1d3e2d..037ed3667b 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h index 046c617052..d2eeeeed43 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h index 174097b30d..478ac765c1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h index de84fd558d..2cd8526a72 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h index 02f37fa635..38afb0e838 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h index 224c14b231..a962da3fba 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h @@ -3,16 +3,28 @@ * @brief EFR32ZG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef EFR32ZG28_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h index 8f1c8b2ae4..027ce8974f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h index 223e430703..2a1199b906 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h index d727fc4b8b..355b98c2cf 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h index e655cd5596..7d997228d2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h index aca4820656..c19a71719e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h index abde7e94eb..32c5c885dd 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h index b03e0dcab7..7638ec0465 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h index ed09902350..60fbe2c14e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h index 54ebdc513f..ad966cc7da 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h index ca5e0d8383..58639de464 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h index d4cf612cd9..8e0528a990 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A110F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h index 134a0efae1..81e7820f30 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A110F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h index a6747cf374..3e3ea09bb0 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A112F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h index 629105e966..5d1861b4b6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A112F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h index f8fdb4d450..841f048eaa 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A120F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h index 059fa5baa0..74f7f446f4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A120F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h index 5c44169729..25a453239f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A122F1024GM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h index fa5d5dee30..bc879d6468 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A122F1024GM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h index 349a191f71..baf5070c6c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B310F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h index fa66ba1afc..84c32c6134 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B310F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h index 663d76af5e..6b27b5ebd3 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B312F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h index a4001c6f04..ff9eb7780c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B312F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h index 97ffcb1c96..5770b6b15c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B320F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h index b371607fd4..15fea04d8d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B320F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h index 45d9970d6c..2b3faf3333 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B322F1024IM48 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h index 2d2360ba00..8a6e81227c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B322F1024IM68 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h index 3811914940..c5ab07d3e4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h index 496f836985..21c31fea1c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32ZG28 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Source/startup_efr32zg28.c b/platform/Device/SiliconLabs/EFR32ZG28/Source/startup_efr32zg28.c index b14a2ab8e6..1fb6cfbe92 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Source/startup_efr32zg28.c +++ b/platform/Device/SiliconLabs/EFR32ZG28/Source/startup_efr32zg28.c @@ -4,17 +4,6 @@ * Device EFR32ZG28 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c b/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c index ac9a951862..93a6022faa 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c +++ b/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32ZG28 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/em_device.h b/platform/Device/SiliconLabs/FGM23/Include/em_device.h index 969b0b93e0..2dab262078 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/em_device.h +++ b/platform/Device/SiliconLabs/FGM23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h b/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h index 175b9bc319..810067c26f 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h @@ -4,7 +4,7 @@ * for FGM230SA27HGN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h b/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h index 0ad1b1352c..e3181281e2 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h @@ -4,7 +4,7 @@ * for FGM230SB27HGN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h index 84f5687738..e5c61faf62 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h @@ -3,7 +3,7 @@ * @brief FGM23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h index 7a13cf9b17..3aa1220fe1 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h @@ -3,7 +3,7 @@ * @brief FGM23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h index 5dd36d9d38..6388523f3a 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h @@ -3,7 +3,7 @@ * @brief FGM23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h index de0dad552b..a9471832e0 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h @@ -3,7 +3,7 @@ * @brief FGM23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h index 7fecfd4df0..9cabb9a528 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h @@ -3,7 +3,7 @@ * @brief FGM23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h index 8285e7e9ad..e3d835ba2d 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h @@ -3,7 +3,7 @@ * @brief FGM23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h index 91b26f3434..aca243facd 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h @@ -3,7 +3,7 @@ * @brief FGM23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h index f4b2de9751..5e9b46d037 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief FGM23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef FGM23_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h index 7c12416567..184786352e 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h @@ -3,7 +3,7 @@ * @brief FGM23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h index efdfdb4bdd..2f96b6d92b 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h @@ -3,7 +3,7 @@ * @brief FGM23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h index 323c3330a7..cbb64397ac 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h @@ -3,7 +3,7 @@ * @brief FGM23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h index e930683e48..d5d48db00e 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h @@ -3,7 +3,7 @@ * @brief FGM23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h index e50589ce92..e4a68c4d5b 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h @@ -3,7 +3,7 @@ * @brief FGM23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h index 6fcbfcf4df..ea7c7f4afe 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h @@ -3,7 +3,7 @@ * @brief FGM23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h index c65439c511..535f10313f 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h @@ -3,7 +3,7 @@ * @brief FGM23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h index d62920968c..3db80c53b7 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h @@ -3,7 +3,7 @@ * @brief FGM23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h index fa15f2d540..d7923af987 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h @@ -3,7 +3,7 @@ * @brief FGM23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h index 918c01b9ad..2faea28c92 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h @@ -3,7 +3,7 @@ * @brief FGM23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h index 816ca0b2ae..388b8468bc 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h @@ -3,7 +3,7 @@ * @brief FGM23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h index b79f5d7dad..fb3f90285a 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h @@ -3,7 +3,7 @@ * @brief FGM23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h index 89e1b2bf26..05e7ea47ef 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h @@ -3,7 +3,7 @@ * @brief FGM23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h index 1a751b1727..f52c23ba40 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h @@ -3,7 +3,7 @@ * @brief FGM23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h index 3f9048c365..3fe95ff522 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h @@ -3,7 +3,7 @@ * @brief FGM23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h index 91ddf91900..1b385e4076 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h @@ -3,7 +3,7 @@ * @brief FGM23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h index fe141d30d0..c34f569bde 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief FGM23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h index 6272e7b150..d708d3d226 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief FGM23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef FGM23_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h index 4d2e82d199..a56bddde38 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h @@ -3,7 +3,7 @@ * @brief FGM23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h index a4bdf1a7b3..1657d3ed91 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h @@ -3,7 +3,7 @@ * @brief FGM23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h index eda7bbb375..e6fb983393 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h @@ -3,7 +3,7 @@ * @brief FGM23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h index 5c944d7cf5..9104473d14 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h @@ -3,7 +3,7 @@ * @brief FGM23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h index ffd6611df6..2fbf00ec03 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h @@ -3,7 +3,7 @@ * @brief FGM23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h index eb0a3505b0..5e75192772 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h @@ -3,7 +3,7 @@ * @brief FGM23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h index 5c4db6583d..a27ed51e43 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h @@ -3,7 +3,7 @@ * @brief FGM23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h index 87c95d5187..2f23a632f1 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h @@ -3,7 +3,7 @@ * @brief FGM23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h index 157c9c58d0..7c9006a815 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief FGM23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h index a7824cb42b..d5b24d3680 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h @@ -3,7 +3,7 @@ * @brief FGM23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h index 6f02a6f414..ea47019320 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h @@ -3,16 +3,28 @@ * @brief FGM23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef FGM23_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h index b52199ca38..6af7afe81c 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h @@ -3,7 +3,7 @@ * @brief FGM23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h index b41bff86f9..ed1f3858a5 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h @@ -3,7 +3,7 @@ * @brief FGM23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h index 6a1ea2841d..e10a022255 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h @@ -3,7 +3,7 @@ * @brief FGM23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h index 99c4e85759..89bea7c2f1 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h @@ -3,7 +3,7 @@ * @brief FGM23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h index 5c6e48c5c4..5f0afeb431 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h @@ -3,7 +3,7 @@ * @brief FGM23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h index e92b35f986..049e1fa7f0 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h @@ -3,7 +3,7 @@ * @brief FGM23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h index 63f5dfdb34..8718a64562 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h @@ -3,7 +3,7 @@ * @brief FGM23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h index cd5d7447e4..42965822a1 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h @@ -3,7 +3,7 @@ * @brief FGM23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h index 5b90541aab..9590962475 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h @@ -3,7 +3,7 @@ * @brief FGM23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h index a81a4e3bf4..495922b77b 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h @@ -3,7 +3,7 @@ * @brief FGM23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h b/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h index 1546445b5f..98ede28a35 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h +++ b/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for FGM23 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Source/startup_fgm23.c b/platform/Device/SiliconLabs/FGM23/Source/startup_fgm23.c index ca9de49614..50b221f076 100644 --- a/platform/Device/SiliconLabs/FGM23/Source/startup_fgm23.c +++ b/platform/Device/SiliconLabs/FGM23/Source/startup_fgm23.c @@ -4,17 +4,6 @@ * Device FGM23 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c b/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c index fe61cee7b5..d3908bcd4d 100644 --- a/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c +++ b/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for FGM23 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/em_device.h b/platform/Device/SiliconLabs/MGM21/Include/em_device.h index d7f57be7a8..d3052e205e 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/em_device.h +++ b/platform/Device/SiliconLabs/MGM21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h index 52ac77f921..d048937917 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h @@ -4,7 +4,7 @@ * for MGM210L022JIF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h index a7307bbd68..a19e909cbb 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h @@ -4,7 +4,7 @@ * for MGM210L022JNF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h index dc91543e58..85f1a04130 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h @@ -4,7 +4,7 @@ * for MGM210LA22JIF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h index 74f9b134fb..8311650b8d 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h @@ -4,7 +4,7 @@ * for MGM210LA22JNF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h index 1e375cec63..36b847e5ed 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h @@ -4,7 +4,7 @@ * for MGM210P022JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h index 3320188b2e..590829d433 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h @@ -4,7 +4,7 @@ * for MGM210P032JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h index cb781f0cd1..b47c335646 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h @@ -4,7 +4,7 @@ * for MGM210PA22JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h index c961e0dc57..368a05399f 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h @@ -4,7 +4,7 @@ * for MGM210PA32JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h index 5e7bebeb87..8d3b7cd216 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h @@ -4,7 +4,7 @@ * for MGM210PB22JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h index 50182a41fc..2705064c86 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h @@ -4,7 +4,7 @@ * for MGM210PB32JIA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h index c2a1cfb2e1..5d094c25c7 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h @@ -4,7 +4,7 @@ * for MGM211LA02JNF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h index 1522d5e8cc..6a6614f7c9 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h @@ -3,7 +3,7 @@ * @brief MGM21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h index 2c5e54d0d0..40b5150c6d 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h @@ -3,7 +3,7 @@ * @brief MGM21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h index 24a08a939c..1cc6f18576 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h @@ -3,7 +3,7 @@ * @brief MGM21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h index c5c5b9931b..020821f602 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h @@ -3,7 +3,7 @@ * @brief MGM21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h index 486011016f..eb71faccb2 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h @@ -3,7 +3,7 @@ * @brief MGM21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h index 2563c473cd..5969553749 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h @@ -3,7 +3,7 @@ * @brief MGM21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h index d25496386f..bca7cf45d7 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h @@ -3,7 +3,7 @@ * @brief MGM21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h index 65330111d1..a7d43448cf 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief MGM21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM21_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h index 736e7d723c..6866c5b82e 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h @@ -3,7 +3,7 @@ * @brief MGM21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h index 12a5c6e4c5..e0c18418a6 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h @@ -3,7 +3,7 @@ * @brief MGM21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h index d362fa8a4d..5898d6f331 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h @@ -3,7 +3,7 @@ * @brief MGM21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h index c49bd5ef7d..55c2c870e3 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h @@ -3,7 +3,7 @@ * @brief MGM21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h index 57b7adb909..d5e6ebb941 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h @@ -3,7 +3,7 @@ * @brief MGM21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h index 549d3e5b11..5628b66b79 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h @@ -3,7 +3,7 @@ * @brief MGM21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h index 679c56eae4..5349f51c8c 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h @@ -3,7 +3,7 @@ * @brief MGM21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h index 03693b1d88..de2562c35e 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h @@ -3,7 +3,7 @@ * @brief MGM21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h index 81b4e95efd..44aa998216 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h @@ -3,7 +3,7 @@ * @brief MGM21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h index 975a1d555f..f6dcc18cf1 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h @@ -3,7 +3,7 @@ * @brief MGM21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h index 36ac31bc5a..aae3a59b37 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h @@ -3,7 +3,7 @@ * @brief MGM21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h index 1f6d449be1..ef02677351 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h @@ -3,7 +3,7 @@ * @brief MGM21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h index d946ecd5b4..cd537d7c90 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief MGM21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h index cf3fdb3a59..cc1bea7c6a 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief MGM21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM21_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h index c76a35cf15..f0c46e8825 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h @@ -3,7 +3,7 @@ * @brief MGM21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h index 4db839b64b..e9adec9fad 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h @@ -3,7 +3,7 @@ * @brief MGM21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h index be46f201f7..85d1bfd8f3 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h @@ -3,7 +3,7 @@ * @brief MGM21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h index 82e6e33391..9749afcd70 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h @@ -3,7 +3,7 @@ * @brief MGM21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h index 843a9c567e..0cd458a521 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h @@ -3,7 +3,7 @@ * @brief MGM21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h index b2d2e9179c..2193880828 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h @@ -3,7 +3,7 @@ * @brief MGM21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h index 36656c770d..c5730dccb8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h @@ -3,16 +3,28 @@ * @brief MGM21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM21_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h index 62d5f61f9d..17be847c0f 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h @@ -3,7 +3,7 @@ * @brief MGM21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h index c0a0e3901d..773b13538a 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h @@ -3,7 +3,7 @@ * @brief MGM21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h index c6e3151201..f5b52c1d89 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h @@ -3,7 +3,7 @@ * @brief MGM21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h index ec622c796a..1bef05b0b8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h @@ -3,7 +3,7 @@ * @brief MGM21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h index 86aa5cf52a..436b2f9909 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h @@ -3,7 +3,7 @@ * @brief MGM21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h index ba7a6830d5..c78b401046 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h @@ -3,7 +3,7 @@ * @brief MGM21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h index a81d6dec5f..1c55ee5ec4 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h @@ -3,7 +3,7 @@ * @brief MGM21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h index b82e2ce8d9..4aab3c5116 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h @@ -3,7 +3,7 @@ * @brief MGM21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h b/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h index e80a355fc4..49d72c6626 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h +++ b/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for MGM21 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Source/startup_mgm21.c b/platform/Device/SiliconLabs/MGM21/Source/startup_mgm21.c index d7976aa667..c36b408a43 100644 --- a/platform/Device/SiliconLabs/MGM21/Source/startup_mgm21.c +++ b/platform/Device/SiliconLabs/MGM21/Source/startup_mgm21.c @@ -4,17 +4,6 @@ * Device MGM21 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c b/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c index b021f6a315..0ffc398ae4 100644 --- a/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c +++ b/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for MGM21 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/em_device.h b/platform/Device/SiliconLabs/MGM22/Include/em_device.h index 650ec467ee..3d17501c27 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/em_device.h +++ b/platform/Device/SiliconLabs/MGM22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h b/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h index 5431f4f9f5..43a1a1d61e 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h @@ -4,7 +4,7 @@ * for MGM220PC22HNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h index 510e377696..5569f1314c 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h @@ -3,7 +3,7 @@ * @brief MGM22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h index 33b29ea659..047468ab08 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h @@ -3,7 +3,7 @@ * @brief MGM22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h index 58db09a586..793a5dfe16 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h @@ -3,7 +3,7 @@ * @brief MGM22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h index f5189e9b8c..aa43a68ec7 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h @@ -3,7 +3,7 @@ * @brief MGM22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h index 32ae968904..b481837f32 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief MGM22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h index 8f711745bf..456bab2e78 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h @@ -3,7 +3,7 @@ * @brief MGM22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h index 2bbeb8c33e..1f04f29777 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h @@ -3,7 +3,7 @@ * @brief MGM22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h index 0879ffa920..23f1a7131b 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief MGM22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM22_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h index df4c8b590c..d22e5e88ce 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h @@ -3,7 +3,7 @@ * @brief MGM22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h index 9831a355f3..f627cafc51 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h @@ -3,7 +3,7 @@ * @brief MGM22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h index 236f7e5bb9..d4aea6dbd5 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h @@ -3,7 +3,7 @@ * @brief MGM22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h index fd3e9bbcff..06307b905c 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h @@ -3,7 +3,7 @@ * @brief MGM22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h index 0116bbfbfd..5abeee95ea 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h @@ -3,7 +3,7 @@ * @brief MGM22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h index 86587ea027..afa15cddf0 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h @@ -3,7 +3,7 @@ * @brief MGM22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h index f89b0a15ce..37f29c5a27 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h @@ -3,7 +3,7 @@ * @brief MGM22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h index 811a3c922a..6866801951 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h @@ -3,7 +3,7 @@ * @brief MGM22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h index fdc8bd14c9..06f9b72707 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h @@ -3,7 +3,7 @@ * @brief MGM22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h index f254895271..efb38602c7 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h @@ -3,7 +3,7 @@ * @brief MGM22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h index c8ac9a753e..7ec580c39a 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h @@ -3,7 +3,7 @@ * @brief MGM22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h index e749d7a5dc..58c36893be 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h @@ -3,7 +3,7 @@ * @brief MGM22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h index f8341b02c3..ee255b5e5e 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h @@ -3,7 +3,7 @@ * @brief MGM22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h index 9105ebdbcc..3ff59d7087 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief MGM22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h index 40e74e265c..e76ebe16ee 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief MGM22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM22_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h index ebd18eaf2b..bf1132a099 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h @@ -3,7 +3,7 @@ * @brief MGM22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h index 5ace9eeae3..b3fa9a2d6a 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h @@ -3,7 +3,7 @@ * @brief MGM22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h index 2e50abc796..4ca4c7599d 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h @@ -3,7 +3,7 @@ * @brief MGM22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h index e70f8d870e..d82c564631 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h @@ -3,7 +3,7 @@ * @brief MGM22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h index 1aac968b4e..72df091417 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h @@ -3,7 +3,7 @@ * @brief MGM22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h index a628078dd0..5a8a07abcb 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h @@ -3,7 +3,7 @@ * @brief MGM22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h index 24d93cf284..867be4fa4d 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h @@ -3,16 +3,28 @@ * @brief MGM22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM22_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h index 5c2f4a0fa6..613d2df206 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h @@ -3,7 +3,7 @@ * @brief MGM22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h index c4a067d311..6f1a31b218 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h @@ -3,7 +3,7 @@ * @brief MGM22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h index 74c45742ef..38a298b474 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h @@ -3,7 +3,7 @@ * @brief MGM22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h index d545de2576..b6f7c09d60 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h @@ -3,7 +3,7 @@ * @brief MGM22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h index 49b83d568c..06dfdaeaed 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h @@ -3,7 +3,7 @@ * @brief MGM22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h index 08dddee7bb..a4c7fa9d01 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h @@ -3,7 +3,7 @@ * @brief MGM22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h index 314fb180f9..c034295206 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h @@ -3,7 +3,7 @@ * @brief MGM22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h b/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h index 0cc808123e..c048df35f7 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h +++ b/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for MGM22 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Source/startup_mgm22.c b/platform/Device/SiliconLabs/MGM22/Source/startup_mgm22.c index 12fd321833..f2558e2698 100644 --- a/platform/Device/SiliconLabs/MGM22/Source/startup_mgm22.c +++ b/platform/Device/SiliconLabs/MGM22/Source/startup_mgm22.c @@ -4,17 +4,6 @@ * Device MGM22 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c b/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c index 91b6efe8a1..2195291903 100644 --- a/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c +++ b/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for MGM22 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/em_device.h b/platform/Device/SiliconLabs/MGM24/Include/em_device.h index 1cd2761b3d..c6a068a902 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/em_device.h +++ b/platform/Device/SiliconLabs/MGM24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h index 1cadbf63e0..6f7bed8c19 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h @@ -4,7 +4,7 @@ * for MGM240L022RNF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h index aad6dde8c6..1f680d1a35 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h @@ -4,7 +4,7 @@ * for MGM240L022VIF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h index b8c3a6eb74..cb45fddfaa 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h @@ -4,7 +4,7 @@ * for MGM240L022VNF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h index 7751a04652..c9f37e44dc 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h @@ -4,7 +4,7 @@ * for MGM240LA22UIF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h index c652241d69..000e23dd07 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h @@ -4,7 +4,7 @@ * for MGM240LA22VIF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h index ae8d0a8aad..752f4eec19 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h @@ -4,7 +4,7 @@ * for MGM240LD22VIF ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h index d08ac5e653..064a50113e 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h @@ -4,7 +4,7 @@ * for MGM240PA22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h index 83cd60b576..3fc42334c7 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h @@ -4,7 +4,7 @@ * for MGM240PA32VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h index e6dd11bc2c..3364b5f29f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h @@ -4,7 +4,7 @@ * for MGM240PA32VNN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h index ddcf4b5fc5..57bf1fba7b 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h @@ -4,7 +4,7 @@ * for MGM240PB22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h index 4d225c6da3..a4611371fa 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h @@ -4,7 +4,7 @@ * for MGM240PB32VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h index 1e15577ffb..330bf8b8ea 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h @@ -4,7 +4,7 @@ * for MGM240PB32VNN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h index f3af4aa221..9390817c5b 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h @@ -4,7 +4,7 @@ * for MGM240SA22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h index 40264d94d4..ab69decefe 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h @@ -4,7 +4,7 @@ * for MGM240SB22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h index 72582d7525..c3c1b401eb 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h @@ -4,7 +4,7 @@ * for MGM240SD22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h index 9deaf86419..bcba52e7cb 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h @@ -3,7 +3,7 @@ * @brief MGM24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h index bf9bf0b277..95bd7f6cd0 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h @@ -3,7 +3,7 @@ * @brief MGM24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h index 67341f8f05..19d8ee931d 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h @@ -3,7 +3,7 @@ * @brief MGM24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h index ee2b94166c..75d873faff 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h @@ -3,7 +3,7 @@ * @brief MGM24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h index 73ed427f25..2fa1479eb6 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h @@ -3,7 +3,7 @@ * @brief MGM24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h index 45f317aa30..d76dca4913 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h @@ -3,7 +3,7 @@ * @brief MGM24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h index 56aa2fc562..bd3040b290 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h @@ -3,7 +3,7 @@ * @brief MGM24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h index a94f22346b..c65df55efd 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief MGM24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM24_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h index 491f5f790f..9dafdfc082 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h @@ -3,7 +3,7 @@ * @brief MGM24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h index 02703c6d2e..3cafa42b86 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h @@ -3,7 +3,7 @@ * @brief MGM24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h index 1de1eb3bc3..1c2bf943ce 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h @@ -3,7 +3,7 @@ * @brief MGM24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h index 2e62653421..a03ee1f421 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h @@ -3,7 +3,7 @@ * @brief MGM24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h index 26e528af4a..94187e7328 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h @@ -3,7 +3,7 @@ * @brief MGM24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h index 03a0800485..58a9c62996 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h @@ -3,7 +3,7 @@ * @brief MGM24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h index 9138c47417..bc38e17ea7 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h @@ -3,7 +3,7 @@ * @brief MGM24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h index 8d7263c68b..c8a47d7e45 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h @@ -3,7 +3,7 @@ * @brief MGM24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h index 556a04e75c..1c09e8cc06 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h @@ -3,7 +3,7 @@ * @brief MGM24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h index 9aefda151e..678155824a 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h @@ -3,7 +3,7 @@ * @brief MGM24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h index d76e830356..611071059f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h @@ -3,7 +3,7 @@ * @brief MGM24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h index 5876dadab2..428b050c02 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h @@ -3,7 +3,7 @@ * @brief MGM24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h index 05041cd1d7..d66eedba85 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h @@ -3,7 +3,7 @@ * @brief MGM24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h index e9a483668c..59976f0baa 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h @@ -3,7 +3,7 @@ * @brief MGM24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h index 2804fbf920..74e3dbf45e 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief MGM24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h index d6e375038c..8afa7e5246 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief MGM24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM24_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h index af0674250b..27a519c909 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h @@ -3,7 +3,7 @@ * @brief MGM24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h index 29d704d3c6..ff789b96da 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h @@ -3,7 +3,7 @@ * @brief MGM24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h index 3eca035536..4e6dc1689b 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h @@ -3,7 +3,7 @@ * @brief MGM24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h index fc9e2e3bf2..ae0c5af53b 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h @@ -3,7 +3,7 @@ * @brief MGM24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h index dd4d47853a..6c908cd1b5 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h @@ -3,7 +3,7 @@ * @brief MGM24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h index 7480734bc7..601c5a0dfc 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h @@ -3,7 +3,7 @@ * @brief MGM24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h index 3e27cc4964..29eb236784 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h @@ -3,7 +3,7 @@ * @brief MGM24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h index 41b351cb8d..3cb312bff8 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h @@ -3,7 +3,7 @@ * @brief MGM24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h index e651be095b..3dd9be5083 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h @@ -3,7 +3,7 @@ * @brief MGM24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h index 09cf4818ad..2e8a313c3c 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h @@ -3,16 +3,28 @@ * @brief MGM24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM24_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h index 5d76f9272f..f4d88d4544 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h @@ -3,7 +3,7 @@ * @brief MGM24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h index d37665fda9..382b2cd469 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h @@ -3,7 +3,7 @@ * @brief MGM24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h index e306c5ba01..2d0a67ef5c 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h @@ -3,7 +3,7 @@ * @brief MGM24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h index 84393b4927..cc094e86f1 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h @@ -3,7 +3,7 @@ * @brief MGM24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h index 537b6ee929..9b0d8db009 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h @@ -3,7 +3,7 @@ * @brief MGM24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h index 12d97d7f6c..aeee886e8f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h @@ -3,7 +3,7 @@ * @brief MGM24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h index 8a93082acb..0b7a8bbe4d 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h @@ -3,7 +3,7 @@ * @brief MGM24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h index 6c4b037ce3..1d02262920 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h @@ -3,7 +3,7 @@ * @brief MGM24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h index 6022b22d79..5706733f63 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h @@ -3,7 +3,7 @@ * @brief MGM24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h index c1aa843d31..21808476c3 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h @@ -3,7 +3,7 @@ * @brief MGM24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h b/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h index 516ca7574c..5759aa718e 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h +++ b/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for MGM24 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Source/startup_mgm24.c b/platform/Device/SiliconLabs/MGM24/Source/startup_mgm24.c index d311db3928..4669c0f931 100644 --- a/platform/Device/SiliconLabs/MGM24/Source/startup_mgm24.c +++ b/platform/Device/SiliconLabs/MGM24/Source/startup_mgm24.c @@ -4,17 +4,6 @@ * Device MGM24 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c b/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c index 7384651a09..a1be439c5a 100644 --- a/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c +++ b/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for MGM24 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/em_device.h b/platform/Device/SiliconLabs/MGM26/Include/em_device.h index 96ed420e22..00e0b7e689 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/em_device.h +++ b/platform/Device/SiliconLabs/MGM26/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -50,6 +50,15 @@ #elif defined(MGM260PB32VNN) #include "mgm260pb32vnn.h" +#elif defined(MGM260PD22VNA) +#include "mgm260pd22vna.h" + +#elif defined(MGM260PD32VNA) +#include "mgm260pd32vna.h" + +#elif defined(MGM260PD32VNN) +#include "mgm260pd32vnn.h" + #else #error "em_device.h: PART NUMBER undefined" #endif diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm260pb22vna.h b/platform/Device/SiliconLabs/MGM26/Include/mgm260pb22vna.h index 237a6f9f22..6bc3fc7a64 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm260pb22vna.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm260pb22vna.h @@ -4,7 +4,7 @@ * for MGM260PB22VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -88,7 +88,6 @@ typedef enum IRQn{ EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ - MVP_IRQn = 28, /*!< 28 EFR32 MVP Interrupt */ ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ @@ -515,8 +514,6 @@ typedef enum IRQn{ #define LFXO_COUNT 1 /** 1 LFXOs available */ #define MSC_PRESENT /** MSC is available in this part */ #define MSC_COUNT 1 /** 1 MSCs available */ -#define MVP_PRESENT /** MVP is available in this part */ -#define MVP_COUNT 1 /** 1 MVPs available */ #define PCNT_PRESENT /** PCNT is available in this part */ #define PCNT_COUNT 1 /** 1 PCNTs available */ #define PRS_PRESENT /** PRS is available in this part */ @@ -595,7 +592,6 @@ typedef enum IRQn{ #include "mgm26_hfxo.h" #include "mgm26_wdog.h" #include "mgm26_semailbox.h" -#include "mgm26_mvp.h" #include "mgm26_devinfo.h" /* Custom headers for LDMAXBAR and PRS mappings */ @@ -674,7 +670,6 @@ typedef enum IRQn{ #define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ #define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ #define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ -#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ #define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ @@ -739,7 +734,6 @@ typedef enum IRQn{ #define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ #define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ #define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ -#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ #if defined(SL_COMPONENT_CATALOG_PRESENT) #include "sl_component_catalog.h" @@ -1070,11 +1064,6 @@ typedef enum IRQn{ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) -#define MVP_BASE (MVP_S_BASE) /* MVP base address */ -#else -#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ /** @} End of group MGM260PB22VNA_Peripheral_Base */ @@ -1148,7 +1137,6 @@ typedef enum IRQn{ #define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ #define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ #define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ -#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ @@ -1213,7 +1201,6 @@ typedef enum IRQn{ #define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ #define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ #define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ -#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ @@ -1278,7 +1265,6 @@ typedef enum IRQn{ #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ #define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ #define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ -#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ /** @} End of group MGM260PB22VNA_Peripheral_Declaration */ diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vna.h b/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vna.h index 952b681b07..c686597386 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vna.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vna.h @@ -4,7 +4,7 @@ * for MGM260PB32VNA ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -88,7 +88,6 @@ typedef enum IRQn{ EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ - MVP_IRQn = 28, /*!< 28 EFR32 MVP Interrupt */ ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ @@ -513,8 +512,6 @@ typedef enum IRQn{ #define LFXO_COUNT 1 /** 1 LFXOs available */ #define MSC_PRESENT /** MSC is available in this part */ #define MSC_COUNT 1 /** 1 MSCs available */ -#define MVP_PRESENT /** MVP is available in this part */ -#define MVP_COUNT 1 /** 1 MVPs available */ #define PCNT_PRESENT /** PCNT is available in this part */ #define PCNT_COUNT 1 /** 1 PCNTs available */ #define PRS_PRESENT /** PRS is available in this part */ @@ -593,7 +590,6 @@ typedef enum IRQn{ #include "mgm26_hfxo.h" #include "mgm26_wdog.h" #include "mgm26_semailbox.h" -#include "mgm26_mvp.h" #include "mgm26_devinfo.h" /* Custom headers for LDMAXBAR and PRS mappings */ @@ -672,7 +668,6 @@ typedef enum IRQn{ #define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ #define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ #define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ -#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ #define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ @@ -737,7 +732,6 @@ typedef enum IRQn{ #define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ #define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ #define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ -#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ #if defined(SL_COMPONENT_CATALOG_PRESENT) #include "sl_component_catalog.h" @@ -1068,11 +1062,6 @@ typedef enum IRQn{ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) -#define MVP_BASE (MVP_S_BASE) /* MVP base address */ -#else -#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ /** @} End of group MGM260PB32VNA_Peripheral_Base */ @@ -1146,7 +1135,6 @@ typedef enum IRQn{ #define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ #define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ #define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ -#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ @@ -1211,7 +1199,6 @@ typedef enum IRQn{ #define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ #define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ #define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ -#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ @@ -1276,7 +1263,6 @@ typedef enum IRQn{ #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ #define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ #define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ -#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ /** @} End of group MGM260PB32VNA_Peripheral_Declaration */ diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vnn.h b/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vnn.h index c35697d03a..67686217ce 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vnn.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm260pb32vnn.h @@ -4,7 +4,7 @@ * for MGM260PB32VNN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -88,7 +88,6 @@ typedef enum IRQn{ EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ - MVP_IRQn = 28, /*!< 28 EFR32 MVP Interrupt */ ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ @@ -513,8 +512,6 @@ typedef enum IRQn{ #define LFXO_COUNT 1 /** 1 LFXOs available */ #define MSC_PRESENT /** MSC is available in this part */ #define MSC_COUNT 1 /** 1 MSCs available */ -#define MVP_PRESENT /** MVP is available in this part */ -#define MVP_COUNT 1 /** 1 MVPs available */ #define PCNT_PRESENT /** PCNT is available in this part */ #define PCNT_COUNT 1 /** 1 PCNTs available */ #define PRS_PRESENT /** PRS is available in this part */ @@ -593,7 +590,6 @@ typedef enum IRQn{ #include "mgm26_hfxo.h" #include "mgm26_wdog.h" #include "mgm26_semailbox.h" -#include "mgm26_mvp.h" #include "mgm26_devinfo.h" /* Custom headers for LDMAXBAR and PRS mappings */ @@ -672,7 +668,6 @@ typedef enum IRQn{ #define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ #define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ #define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ -#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ #define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ @@ -737,7 +732,6 @@ typedef enum IRQn{ #define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ #define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ #define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ -#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ #if defined(SL_COMPONENT_CATALOG_PRESENT) #include "sl_component_catalog.h" @@ -1068,11 +1062,6 @@ typedef enum IRQn{ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) -#define MVP_BASE (MVP_S_BASE) /* MVP base address */ -#else -#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ /** @} End of group MGM260PB32VNN_Peripheral_Base */ @@ -1146,7 +1135,6 @@ typedef enum IRQn{ #define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ #define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ #define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ -#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ @@ -1211,7 +1199,6 @@ typedef enum IRQn{ #define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ #define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ #define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ -#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ @@ -1276,7 +1263,6 @@ typedef enum IRQn{ #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ #define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ #define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ -#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ /** @} End of group MGM260PB32VNN_Peripheral_Declaration */ diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm260pd22vna.h b/platform/Device/SiliconLabs/MGM26/Include/mgm260pd22vna.h new file mode 100644 index 0000000000..1fdc12d602 --- /dev/null +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm260pd22vna.h @@ -0,0 +1,2025 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for MGM260PD22VNA + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef MGM260PD22VNA_H +#define MGM260PD22VNA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup MGM260PD22VNA MGM260PD22VNA + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** MGM26 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + TIMER5_IRQn = 9, /*!< 9 EFR32 TIMER5 Interrupt */ + TIMER6_IRQn = 10, /*!< 10 EFR32 TIMER6 Interrupt */ + TIMER7_IRQn = 11, /*!< 11 EFR32 TIMER7 Interrupt */ + TIMER8_IRQn = 12, /*!< 12 EFR32 TIMER8 Interrupt */ + TIMER9_IRQn = 13, /*!< 13 EFR32 TIMER9 Interrupt */ + USART0_RX_IRQn = 14, /*!< 14 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 15, /*!< 15 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 16, /*!< 16 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 17, /*!< 17 EFR32 USART1_TX Interrupt */ + USART2_RX_IRQn = 18, /*!< 18 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 19, /*!< 19 EFR32 USART2_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 22, /*!< 22 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 23, /*!< 23 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 24, /*!< 24 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ + EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ + EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ + MVP_IRQn = 28, /*!< 28 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 32, /*!< 32 EFR32 SYSCFG Interrupt */ + MPAHBRAM0_IRQn = 33, /*!< 33 EFR32 MPAHBRAM0 Interrupt */ + MPAHBRAM1_IRQn = 34, /*!< 34 EFR32 MPAHBRAM1 Interrupt */ + LDMA_IRQn = 35, /*!< 35 EFR32 LDMA Interrupt */ + LFXO_IRQn = 36, /*!< 36 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 37, /*!< 37 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 38, /*!< 38 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 39, /*!< 39 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 40, /*!< 40 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 41, /*!< 41 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + I2C2_IRQn = 43, /*!< 43 EFR32 I2C2 Interrupt */ + I2C3_IRQn = 44, /*!< 44 EFR32 I2C3 Interrupt */ + EMUDG_IRQn = 45, /*!< 45 EFR32 EMUDG Interrupt */ + AGC_IRQn = 46, /*!< 46 EFR32 AGC Interrupt */ + BUFC_IRQn = 47, /*!< 47 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 48, /*!< 48 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 49, /*!< 49 EFR32 FRC Interrupt */ + MODEM_IRQn = 50, /*!< 50 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 51, /*!< 51 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 52, /*!< 52 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 53, /*!< 53 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 54, /*!< 54 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 55, /*!< 55 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 56, /*!< 56 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 57, /*!< 57 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 58, /*!< 58 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 59, /*!< 59 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 60, /*!< 60 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 61, /*!< 61 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 62, /*!< 62 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 63, /*!< 63 EFR32 CMU Interrupt */ + AES_IRQn = 64, /*!< 64 EFR32 AES Interrupt */ + IADC_IRQn = 65, /*!< 65 EFR32 IADC Interrupt */ + MSC_IRQn = 66, /*!< 66 EFR32 MSC Interrupt */ + DPLL0_IRQn = 67, /*!< 67 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 68, /*!< 68 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 69, /*!< 69 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 70, /*!< 70 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 71, /*!< 71 EFR32 SW0 Interrupt */ + SW1_IRQn = 72, /*!< 72 EFR32 SW1 Interrupt */ + SW2_IRQn = 73, /*!< 73 EFR32 SW2 Interrupt */ + SW3_IRQn = 74, /*!< 74 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 75, /*!< 75 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 76, /*!< 76 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 77, /*!< 77 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 78, /*!< 78 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 79, /*!< 79 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 80, /*!< 80 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 81, /*!< 81 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 82, /*!< 82 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 83, /*!< 83 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 84, /*!< 84 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 85, /*!< 85 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 86, /*!< 86 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 87, /*!< 87 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 88, /*!< 88 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 89, /*!< 89 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 90, /*!< 90 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 91, /*!< 91 EFR32 AHB2AHB1 Interrupt */ + LCD_IRQn = 92, /*!< 92 EFR32 LCD Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup MGM260PD22VNA_Core MGM260PD22VNA Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group MGM260PD22VNA_Core */ + +/**************************************************************************//** +* @defgroup MGM260PD22VNA_Part MGM260PD22VNA Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(MGM260PD22VNA) +#define MGM260PD22VNA 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "MGM260PD22VNA" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_MODULE 1 /** Silicon Labs multi-chip module */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_6 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 6 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00320000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0831FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x16UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00320000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0831FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x16UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM0_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM0_RAM0_RAM_MEM base address */ +#define DMEM0_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM0_RAM0_RAM_MEM available address space */ +#define DMEM0_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM0_RAM0_RAM_MEM end address */ +#define DMEM0_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM0_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define DMEM1_RAM0_RAM_MEM_BASE (0x20040000UL) /** DMEM1_RAM0_RAM_MEM base address */ +#define DMEM1_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM1_RAM0_RAM_MEM available address space */ +#define DMEM1_RAM0_RAM_MEM_END (0x2007FFFFUL) /** DMEM1_RAM0_RAM_MEM end address */ +#define DMEM1_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM1_RAM0_RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for MGM260PD22VNA */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00320000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 93 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG20_PORT GPIO_PA_INDEX /**< Port of SEG20.*/ +#define LCD_SEG20_PIN 9U /**< Pin of SEG20.*/ +#define LCD_SEG26_PORT GPIO_PB_INDEX /**< Port of SEG26.*/ +#define LCD_SEG26_PIN 4U /**< Pin of SEG26.*/ +#define LCD_SEG27_PORT GPIO_PB_INDEX /**< Port of SEG27.*/ +#define LCD_SEG27_PIN 5U /**< Pin of SEG27.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 2 /** 2 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 4 /** 4 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 4 /** 4 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 10 /** 10 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 3 /** 3 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_mgm26.h" /* System Header File */ + +/** @} End of group MGM260PD22VNA_Part */ + +/**************************************************************************//** + * @defgroup MGM260PD22VNA_Peripheral_TypeDefs MGM260PD22VNA Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "mgm26_emu.h" +#include "mgm26_cmu.h" +#include "mgm26_burtc.h" +#include "mgm26_hfrco.h" +#include "mgm26_fsrco.h" +#include "mgm26_dpll.h" +#include "mgm26_lfxo.h" +#include "mgm26_lfrco.h" +#include "mgm26_ulfrco.h" +#include "mgm26_keyscan.h" +#include "mgm26_msc.h" +#include "mgm26_icache.h" +#include "mgm26_prs.h" +#include "mgm26_gpio.h" +#include "mgm26_ldma.h" +#include "mgm26_ldmaxbar.h" +#include "mgm26_timer.h" +#include "mgm26_mpahbram.h" +#include "mgm26_syscfg.h" +#include "mgm26_buram.h" +#include "mgm26_gpcrc.h" +#include "mgm26_eusart.h" +#include "mgm26_dcdc.h" +#include "mgm26_mailbox.h" +#include "mgm26_usart.h" +#include "mgm26_sysrtc.h" +#include "mgm26_i2c.h" +#include "mgm26_lcd.h" +#include "mgm26_lcdrf.h" +#include "mgm26_aes.h" +#include "mgm26_smu.h" +#include "mgm26_letimer.h" +#include "mgm26_iadc.h" +#include "mgm26_acmp.h" +#include "mgm26_amuxcp.h" +#include "mgm26_vdac.h" +#include "mgm26_pcnt.h" +#include "mgm26_hfxo.h" +#include "mgm26_wdog.h" +#include "mgm26_semailbox.h" +#include "mgm26_mvp.h" +#include "mgm26_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "mgm26_prs_signals.h" +#include "mgm26_dma_descriptor.h" +#include "mgm26_ldmaxbar_defines.h" + +/** @} End of group MGM260PD22VNA_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup MGM260PD22VNA_Peripheral_Base MGM260PD22VNA Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define BURTC_S_BASE (0x4000C000UL) /* BURTC_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define KEYSCAN_S_BASE (0x4002C000UL) /* KEYSCAN_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define TIMER5_S_BASE (0x4005C000UL) /* TIMER5_S base address */ +#define TIMER6_S_BASE (0x40060000UL) /* TIMER6_S base address */ +#define TIMER7_S_BASE (0x40064000UL) /* TIMER7_S base address */ +#define TIMER8_S_BASE (0x40068000UL) /* TIMER8_S base address */ +#define TIMER9_S_BASE (0x4006C000UL) /* TIMER9_S base address */ +#define DMEM0_S_BASE (0x40074000UL) /* DMEM0_S base address */ +#define DMEM1_S_BASE (0x40078000UL) /* DMEM1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x4007C000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x40080000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40084000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define EUSART1_S_BASE (0x4008C000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x40090000UL) /* EUSART2_S base address */ +#define EUSART3_S_BASE (0x40094000UL) /* EUSART3_S base address */ +#define DCDC_S_BASE (0x40098000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x4009C000UL) /* HOSTMAILBOX_S base address */ +#define USART0_S_BASE (0x400A0000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x400A4000UL) /* USART1_S base address */ +#define USART2_S_BASE (0x400A8000UL) /* USART2_S base address */ +#define SYSRTC0_S_BASE (0x400AC000UL) /* SYSRTC0_S base address */ +#define I2C1_S_BASE (0x400B0000UL) /* I2C1_S base address */ +#define I2C2_S_BASE (0x400B4000UL) /* I2C2_S base address */ +#define I2C3_S_BASE (0x400B8000UL) /* I2C3_S base address */ +#define LCD_S_BASE (0x400BC000UL) /* LCD_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define KEYSCAN_NS_BASE (0x5002C000UL) /* KEYSCAN_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define TIMER5_NS_BASE (0x5005C000UL) /* TIMER5_NS base address */ +#define TIMER6_NS_BASE (0x50060000UL) /* TIMER6_NS base address */ +#define TIMER7_NS_BASE (0x50064000UL) /* TIMER7_NS base address */ +#define TIMER8_NS_BASE (0x50068000UL) /* TIMER8_NS base address */ +#define TIMER9_NS_BASE (0x5006C000UL) /* TIMER9_NS base address */ +#define DMEM0_NS_BASE (0x50074000UL) /* DMEM0_NS base address */ +#define DMEM1_NS_BASE (0x50078000UL) /* DMEM1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x5007C000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x50080000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50084000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define EUSART1_NS_BASE (0x5008C000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x50090000UL) /* EUSART2_NS base address */ +#define EUSART3_NS_BASE (0x50094000UL) /* EUSART3_NS base address */ +#define DCDC_NS_BASE (0x50098000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x5009C000UL) /* HOSTMAILBOX_NS base address */ +#define USART0_NS_BASE (0x500A0000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x500A4000UL) /* USART1_NS base address */ +#define USART2_NS_BASE (0x500A8000UL) /* USART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500AC000UL) /* SYSRTC0_NS base address */ +#define I2C1_NS_BASE (0x500B0000UL) /* I2C1_NS base address */ +#define I2C2_NS_BASE (0x500B4000UL) /* I2C2_NS base address */ +#define I2C3_NS_BASE (0x500B8000UL) /* I2C3_NS base address */ +#define LCD_NS_BASE (0x500BC000UL) /* LCD_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) +#define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ +#else +#define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER5_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) +#define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ +#else +#define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER6_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) +#define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ +#else +#define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER7_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER8_S != 0))) +#define TIMER8_BASE (TIMER8_S_BASE) /* TIMER8 base address */ +#else +#define TIMER8_BASE (TIMER8_NS_BASE) /* TIMER8 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER8_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER9_S != 0))) +#define TIMER9_BASE (TIMER9_S_BASE) /* TIMER9 base address */ +#else +#define TIMER9_BASE (TIMER9_NS_BASE) /* TIMER9 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER9_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM0_S != 0))) +#define DMEM0_BASE (DMEM0_S_BASE) /* DMEM0 base address */ +#else +#define DMEM0_BASE (DMEM0_NS_BASE) /* DMEM0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM1_S != 0))) +#define DMEM1_BASE (DMEM1_S_BASE) /* DMEM1 base address */ +#else +#define DMEM1_BASE (DMEM1_NS_BASE) /* DMEM1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) +#define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ +#else +#define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) +#define USART2_BASE (USART2_S_BASE) /* USART2 base address */ +#else +#define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S) && (SL_TRUSTZONE_PERIPHERAL_I2C2_S != 0))) +#define I2C2_BASE (I2C2_S_BASE) /* I2C2 base address */ +#else +#define I2C2_BASE (I2C2_NS_BASE) /* I2C2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S) && (SL_TRUSTZONE_PERIPHERAL_I2C3_S != 0))) +#define I2C3_BASE (I2C3_S_BASE) /* I2C3 base address */ +#else +#define I2C3_BASE (I2C3_NS_BASE) /* I2C3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group MGM260PD22VNA_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup MGM260PD22VNA_Peripheral_Declaration MGM260PD22VNA Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define TIMER5_S ((TIMER_TypeDef *) TIMER5_S_BASE) /**< TIMER5_S base pointer */ +#define TIMER6_S ((TIMER_TypeDef *) TIMER6_S_BASE) /**< TIMER6_S base pointer */ +#define TIMER7_S ((TIMER_TypeDef *) TIMER7_S_BASE) /**< TIMER7_S base pointer */ +#define TIMER8_S ((TIMER_TypeDef *) TIMER8_S_BASE) /**< TIMER8_S base pointer */ +#define TIMER9_S ((TIMER_TypeDef *) TIMER9_S_BASE) /**< TIMER9_S base pointer */ +#define DMEM0_S ((MPAHBRAM_TypeDef *) DMEM0_S_BASE) /**< DMEM0_S base pointer */ +#define DMEM1_S ((MPAHBRAM_TypeDef *) DMEM1_S_BASE) /**< DMEM1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define EUSART3_S ((EUSART_TypeDef *) EUSART3_S_BASE) /**< EUSART3_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define USART2_S ((USART_TypeDef *) USART2_S_BASE) /**< USART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define I2C2_S ((I2C_TypeDef *) I2C2_S_BASE) /**< I2C2_S base pointer */ +#define I2C3_S ((I2C_TypeDef *) I2C3_S_BASE) /**< I2C3_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define TIMER5_NS ((TIMER_TypeDef *) TIMER5_NS_BASE) /**< TIMER5_NS base pointer */ +#define TIMER6_NS ((TIMER_TypeDef *) TIMER6_NS_BASE) /**< TIMER6_NS base pointer */ +#define TIMER7_NS ((TIMER_TypeDef *) TIMER7_NS_BASE) /**< TIMER7_NS base pointer */ +#define TIMER8_NS ((TIMER_TypeDef *) TIMER8_NS_BASE) /**< TIMER8_NS base pointer */ +#define TIMER9_NS ((TIMER_TypeDef *) TIMER9_NS_BASE) /**< TIMER9_NS base pointer */ +#define DMEM0_NS ((MPAHBRAM_TypeDef *) DMEM0_NS_BASE) /**< DMEM0_NS base pointer */ +#define DMEM1_NS ((MPAHBRAM_TypeDef *) DMEM1_NS_BASE) /**< DMEM1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define EUSART3_NS ((EUSART_TypeDef *) EUSART3_NS_BASE) /**< EUSART3_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define USART2_NS ((USART_TypeDef *) USART2_NS_BASE) /**< USART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define I2C2_NS ((I2C_TypeDef *) I2C2_NS_BASE) /**< I2C2_NS base pointer */ +#define I2C3_NS ((I2C_TypeDef *) I2C3_NS_BASE) /**< I2C3_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define TIMER7 ((TIMER_TypeDef *) TIMER7_BASE) /**< TIMER7 base pointer */ +#define TIMER8 ((TIMER_TypeDef *) TIMER8_BASE) /**< TIMER8 base pointer */ +#define TIMER9 ((TIMER_TypeDef *) TIMER9_BASE) /**< TIMER9 base pointer */ +#define DMEM0 ((MPAHBRAM_TypeDef *) DMEM0_BASE) /**< DMEM0 base pointer */ +#define DMEM1 ((MPAHBRAM_TypeDef *) DMEM1_BASE) /**< DMEM1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define EUSART3 ((EUSART_TypeDef *) EUSART3_BASE) /**< EUSART3 base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) /**< I2C3 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group MGM260PD22VNA_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup MGM260PD22VNA_Peripheral_Parameters MGM260PD22VNA Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x16UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x16UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x1A0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x4UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM0_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM0_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM0_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM0_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM0_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM0_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM0_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM0_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM0_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM0_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM0_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM0_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM0_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM0_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM0_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM0_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM0_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM0_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM0_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM0_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM0_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM0_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM0_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM0_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM0_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM0_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM0_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM0_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM0_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM0_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM0_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM0_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM0_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM0_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM0_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM0_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM0_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM0_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM0_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define DMEM1_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM1_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM1_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM1_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM1_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM1_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM1_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM1_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM1_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM1_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM1_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM1_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM1_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM1_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM1_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM1_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM1_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM1_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM1_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM1_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM1_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM1_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM1_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM1_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM1_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM1_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM1_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM1_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM1_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM1_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM1_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM1_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM1_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM1_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM1_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM1_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM1_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM1_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM1_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x0UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x320000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x320000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x8UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x8UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x8UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x8UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0x10UL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x8UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x8UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x8UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x8UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x10UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x10UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x10UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x10UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x28UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define TIMER5_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER5_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER5_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER5_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER5_NO_DTI 0x0UL /**> */ +#define TIMER6_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER6_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER6_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER6_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER6_NO_DTI 0x0UL /**> */ +#define TIMER7_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER7_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER7_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER7_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER7_NO_DTI 0x0UL /**> */ +#define TIMER8_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER8_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER8_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER8_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER8_NO_DTI 0x0UL /**> */ +#define TIMER9_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER9_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER9_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER9_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER9_NO_DTI 0x0UL /**> */ +#define SYSCFG_CHIP_PARTNUMBER 0x3UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART3_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART3_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define USART2_AUTOTX_REG 0x1UL /**> None */ +#define USART2_AUTOTX_REG_B 0x0UL /**> None */ +#define USART2_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART2_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART2_CLK_PRS 0x1UL /**> None */ +#define USART2_CLK_PRS_B 0x0UL /**> New Param */ +#define USART2_FLOW_CONTROL 0x1UL /**> None */ +#define USART2_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART2_I2S 0x1UL /**> None */ +#define USART2_I2S_B 0x0UL /**> New Param */ +#define USART2_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART2_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_MVDIS_FUNC 0x1UL /**> None */ +#define USART2_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART2_RX_PRS 0x1UL /**> None */ +#define USART2_RX_PRS_B 0x0UL /**> New Param */ +#define USART2_SC_AVAILABLE 0x1UL /**> None */ +#define USART2_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART2_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART2_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART2_TIMER 0x1UL /**> New Param */ +#define USART2_TIMER_B 0x0UL /**> New Param */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C2_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C2_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C3_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C3_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_OCTAPLEX 0x1UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x0UL /**> */ +#define LCD_SEG_NUM 0x28UL /**> None */ +#define LCD_SEGASCOM_SEGSTART 0x24UL /**> */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x44UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x4UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_64 0x4UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : ((n) == 3) ? EUSART3 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : ((ref) == EUSART3) ? 3 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : ((n) == 2) ? I2C2 \ + : ((n) == 3) ? I2C3 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : ((ref) == I2C2) ? 2 \ + : ((ref) == I2C3) ? 3 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : ((n) == 2) ? I2C2_DELAY \ + : ((n) == 3) ? I2C3_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : ((n) == 2) ? I2C2_DELAY_CHAIN_NUM \ + : ((n) == 3) ? I2C3_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : ((n) == 5) ? TIMER5 \ + : ((n) == 6) ? TIMER6 \ + : ((n) == 7) ? TIMER7 \ + : ((n) == 8) ? TIMER8 \ + : ((n) == 9) ? TIMER9 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : ((ref) == TIMER5) ? 5 \ + : ((ref) == TIMER6) ? 6 \ + : ((ref) == TIMER7) ? 7 \ + : ((ref) == TIMER8) ? 8 \ + : ((ref) == TIMER9) ? 9 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : ((n) == 5) ? TIMER5_CC_NUM \ + : ((n) == 6) ? TIMER6_CC_NUM \ + : ((n) == 7) ? TIMER7_CC_NUM \ + : ((n) == 8) ? TIMER8_CC_NUM \ + : ((n) == 9) ? TIMER9_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : ((n) == 5) ? TIMER5_CNTWIDTH \ + : ((n) == 6) ? TIMER6_CNTWIDTH \ + : ((n) == 7) ? TIMER7_CNTWIDTH \ + : ((n) == 8) ? TIMER8_CNTWIDTH \ + : ((n) == 9) ? TIMER9_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : ((n) == 5) ? TIMER5_DTI \ + : ((n) == 6) ? TIMER6_DTI \ + : ((n) == 7) ? TIMER7_DTI \ + : ((n) == 8) ? TIMER8_DTI \ + : ((n) == 9) ? TIMER9_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : ((n) == 5) ? TIMER5_DTI_CC_NUM \ + : ((n) == 6) ? TIMER6_DTI_CC_NUM \ + : ((n) == 7) ? TIMER7_DTI_CC_NUM \ + : ((n) == 8) ? TIMER8_DTI_CC_NUM \ + : ((n) == 9) ? TIMER9_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : ((n) == 5) ? TIMER5_NO_DTI \ + : ((n) == 6) ? TIMER6_NO_DTI \ + : ((n) == 7) ? TIMER7_NO_DTI \ + : ((n) == 8) ? TIMER8_NO_DTI \ + : ((n) == 9) ? TIMER9_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : ((n) == 2) ? USART2 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : ((ref) == USART2) ? 2 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : ((n) == 2) ? USART2_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : ((n) == 2) ? USART2_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : ((n) == 2) ? USART2_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : ((n) == 2) ? USART2_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : ((n) == 2) ? USART2_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : ((n) == 2) ? USART2_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : ((n) == 2) ? USART2_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : ((n) == 2) ? USART2_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : ((n) == 2) ? USART2_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : ((n) == 2) ? USART2_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : ((n) == 2) ? USART2_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : ((n) == 2) ? USART2_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : ((n) == 2) ? USART2_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : ((n) == 2) ? USART2_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : ((n) == 2) ? USART2_TIMER_B \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group MGM260PD22VNA_Peripheral_Parameters */ + +/** @} End of group MGM260PD22VNA */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm260pd32vna.h b/platform/Device/SiliconLabs/MGM26/Include/mgm260pd32vna.h new file mode 100644 index 0000000000..4ba97c83b1 --- /dev/null +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm260pd32vna.h @@ -0,0 +1,2023 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for MGM260PD32VNA + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef MGM260PD32VNA_H +#define MGM260PD32VNA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup MGM260PD32VNA MGM260PD32VNA + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** MGM26 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + TIMER5_IRQn = 9, /*!< 9 EFR32 TIMER5 Interrupt */ + TIMER6_IRQn = 10, /*!< 10 EFR32 TIMER6 Interrupt */ + TIMER7_IRQn = 11, /*!< 11 EFR32 TIMER7 Interrupt */ + TIMER8_IRQn = 12, /*!< 12 EFR32 TIMER8 Interrupt */ + TIMER9_IRQn = 13, /*!< 13 EFR32 TIMER9 Interrupt */ + USART0_RX_IRQn = 14, /*!< 14 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 15, /*!< 15 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 16, /*!< 16 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 17, /*!< 17 EFR32 USART1_TX Interrupt */ + USART2_RX_IRQn = 18, /*!< 18 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 19, /*!< 19 EFR32 USART2_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 22, /*!< 22 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 23, /*!< 23 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 24, /*!< 24 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ + EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ + EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ + MVP_IRQn = 28, /*!< 28 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 32, /*!< 32 EFR32 SYSCFG Interrupt */ + MPAHBRAM0_IRQn = 33, /*!< 33 EFR32 MPAHBRAM0 Interrupt */ + MPAHBRAM1_IRQn = 34, /*!< 34 EFR32 MPAHBRAM1 Interrupt */ + LDMA_IRQn = 35, /*!< 35 EFR32 LDMA Interrupt */ + LFXO_IRQn = 36, /*!< 36 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 37, /*!< 37 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 38, /*!< 38 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 39, /*!< 39 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 40, /*!< 40 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 41, /*!< 41 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + I2C2_IRQn = 43, /*!< 43 EFR32 I2C2 Interrupt */ + I2C3_IRQn = 44, /*!< 44 EFR32 I2C3 Interrupt */ + EMUDG_IRQn = 45, /*!< 45 EFR32 EMUDG Interrupt */ + AGC_IRQn = 46, /*!< 46 EFR32 AGC Interrupt */ + BUFC_IRQn = 47, /*!< 47 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 48, /*!< 48 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 49, /*!< 49 EFR32 FRC Interrupt */ + MODEM_IRQn = 50, /*!< 50 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 51, /*!< 51 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 52, /*!< 52 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 53, /*!< 53 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 54, /*!< 54 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 55, /*!< 55 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 56, /*!< 56 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 57, /*!< 57 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 58, /*!< 58 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 59, /*!< 59 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 60, /*!< 60 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 61, /*!< 61 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 62, /*!< 62 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 63, /*!< 63 EFR32 CMU Interrupt */ + AES_IRQn = 64, /*!< 64 EFR32 AES Interrupt */ + IADC_IRQn = 65, /*!< 65 EFR32 IADC Interrupt */ + MSC_IRQn = 66, /*!< 66 EFR32 MSC Interrupt */ + DPLL0_IRQn = 67, /*!< 67 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 68, /*!< 68 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 69, /*!< 69 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 70, /*!< 70 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 71, /*!< 71 EFR32 SW0 Interrupt */ + SW1_IRQn = 72, /*!< 72 EFR32 SW1 Interrupt */ + SW2_IRQn = 73, /*!< 73 EFR32 SW2 Interrupt */ + SW3_IRQn = 74, /*!< 74 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 75, /*!< 75 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 76, /*!< 76 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 77, /*!< 77 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 78, /*!< 78 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 79, /*!< 79 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 80, /*!< 80 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 81, /*!< 81 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 82, /*!< 82 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 83, /*!< 83 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 84, /*!< 84 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 85, /*!< 85 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 86, /*!< 86 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 87, /*!< 87 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 88, /*!< 88 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 89, /*!< 89 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 90, /*!< 90 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 91, /*!< 91 EFR32 AHB2AHB1 Interrupt */ + LCD_IRQn = 92, /*!< 92 EFR32 LCD Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup MGM260PD32VNA_Core MGM260PD32VNA Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group MGM260PD32VNA_Core */ + +/**************************************************************************//** +* @defgroup MGM260PD32VNA_Part MGM260PD32VNA Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(MGM260PD32VNA) +#define MGM260PD32VNA 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "MGM260PD32VNA" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_MODULE 1 /** Silicon Labs multi-chip module */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_6 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 6 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00320000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0831FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x16UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00320000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0831FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x16UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM0_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM0_RAM0_RAM_MEM base address */ +#define DMEM0_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM0_RAM0_RAM_MEM available address space */ +#define DMEM0_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM0_RAM0_RAM_MEM end address */ +#define DMEM0_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM0_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define DMEM1_RAM0_RAM_MEM_BASE (0x20040000UL) /** DMEM1_RAM0_RAM_MEM base address */ +#define DMEM1_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM1_RAM0_RAM_MEM available address space */ +#define DMEM1_RAM0_RAM_MEM_END (0x2007FFFFUL) /** DMEM1_RAM0_RAM_MEM end address */ +#define DMEM1_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM1_RAM0_RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for MGM260PD32VNA */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00320000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 93 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG20_PORT GPIO_PA_INDEX /**< Port of SEG20.*/ +#define LCD_SEG20_PIN 9U /**< Pin of SEG20.*/ +#define LCD_SEG26_PORT GPIO_PB_INDEX /**< Port of SEG26.*/ +#define LCD_SEG26_PIN 4U /**< Pin of SEG26.*/ +#define LCD_SEG27_PORT GPIO_PB_INDEX /**< Port of SEG27.*/ +#define LCD_SEG27_PIN 5U /**< Pin of SEG27.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 2 /** 2 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 4 /** 4 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 4 /** 4 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 10 /** 10 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 3 /** 3 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_mgm26.h" /* System Header File */ + +/** @} End of group MGM260PD32VNA_Part */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNA_Peripheral_TypeDefs MGM260PD32VNA Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "mgm26_emu.h" +#include "mgm26_cmu.h" +#include "mgm26_burtc.h" +#include "mgm26_hfrco.h" +#include "mgm26_fsrco.h" +#include "mgm26_dpll.h" +#include "mgm26_lfxo.h" +#include "mgm26_lfrco.h" +#include "mgm26_ulfrco.h" +#include "mgm26_keyscan.h" +#include "mgm26_msc.h" +#include "mgm26_icache.h" +#include "mgm26_prs.h" +#include "mgm26_gpio.h" +#include "mgm26_ldma.h" +#include "mgm26_ldmaxbar.h" +#include "mgm26_timer.h" +#include "mgm26_mpahbram.h" +#include "mgm26_syscfg.h" +#include "mgm26_buram.h" +#include "mgm26_gpcrc.h" +#include "mgm26_eusart.h" +#include "mgm26_dcdc.h" +#include "mgm26_mailbox.h" +#include "mgm26_usart.h" +#include "mgm26_sysrtc.h" +#include "mgm26_i2c.h" +#include "mgm26_lcd.h" +#include "mgm26_lcdrf.h" +#include "mgm26_aes.h" +#include "mgm26_smu.h" +#include "mgm26_letimer.h" +#include "mgm26_iadc.h" +#include "mgm26_acmp.h" +#include "mgm26_amuxcp.h" +#include "mgm26_vdac.h" +#include "mgm26_pcnt.h" +#include "mgm26_hfxo.h" +#include "mgm26_wdog.h" +#include "mgm26_semailbox.h" +#include "mgm26_mvp.h" +#include "mgm26_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "mgm26_prs_signals.h" +#include "mgm26_dma_descriptor.h" +#include "mgm26_ldmaxbar_defines.h" + +/** @} End of group MGM260PD32VNA_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNA_Peripheral_Base MGM260PD32VNA Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define BURTC_S_BASE (0x4000C000UL) /* BURTC_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define KEYSCAN_S_BASE (0x4002C000UL) /* KEYSCAN_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define TIMER5_S_BASE (0x4005C000UL) /* TIMER5_S base address */ +#define TIMER6_S_BASE (0x40060000UL) /* TIMER6_S base address */ +#define TIMER7_S_BASE (0x40064000UL) /* TIMER7_S base address */ +#define TIMER8_S_BASE (0x40068000UL) /* TIMER8_S base address */ +#define TIMER9_S_BASE (0x4006C000UL) /* TIMER9_S base address */ +#define DMEM0_S_BASE (0x40074000UL) /* DMEM0_S base address */ +#define DMEM1_S_BASE (0x40078000UL) /* DMEM1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x4007C000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x40080000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40084000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define EUSART1_S_BASE (0x4008C000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x40090000UL) /* EUSART2_S base address */ +#define EUSART3_S_BASE (0x40094000UL) /* EUSART3_S base address */ +#define DCDC_S_BASE (0x40098000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x4009C000UL) /* HOSTMAILBOX_S base address */ +#define USART0_S_BASE (0x400A0000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x400A4000UL) /* USART1_S base address */ +#define USART2_S_BASE (0x400A8000UL) /* USART2_S base address */ +#define SYSRTC0_S_BASE (0x400AC000UL) /* SYSRTC0_S base address */ +#define I2C1_S_BASE (0x400B0000UL) /* I2C1_S base address */ +#define I2C2_S_BASE (0x400B4000UL) /* I2C2_S base address */ +#define I2C3_S_BASE (0x400B8000UL) /* I2C3_S base address */ +#define LCD_S_BASE (0x400BC000UL) /* LCD_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define KEYSCAN_NS_BASE (0x5002C000UL) /* KEYSCAN_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define TIMER5_NS_BASE (0x5005C000UL) /* TIMER5_NS base address */ +#define TIMER6_NS_BASE (0x50060000UL) /* TIMER6_NS base address */ +#define TIMER7_NS_BASE (0x50064000UL) /* TIMER7_NS base address */ +#define TIMER8_NS_BASE (0x50068000UL) /* TIMER8_NS base address */ +#define TIMER9_NS_BASE (0x5006C000UL) /* TIMER9_NS base address */ +#define DMEM0_NS_BASE (0x50074000UL) /* DMEM0_NS base address */ +#define DMEM1_NS_BASE (0x50078000UL) /* DMEM1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x5007C000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x50080000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50084000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define EUSART1_NS_BASE (0x5008C000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x50090000UL) /* EUSART2_NS base address */ +#define EUSART3_NS_BASE (0x50094000UL) /* EUSART3_NS base address */ +#define DCDC_NS_BASE (0x50098000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x5009C000UL) /* HOSTMAILBOX_NS base address */ +#define USART0_NS_BASE (0x500A0000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x500A4000UL) /* USART1_NS base address */ +#define USART2_NS_BASE (0x500A8000UL) /* USART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500AC000UL) /* SYSRTC0_NS base address */ +#define I2C1_NS_BASE (0x500B0000UL) /* I2C1_NS base address */ +#define I2C2_NS_BASE (0x500B4000UL) /* I2C2_NS base address */ +#define I2C3_NS_BASE (0x500B8000UL) /* I2C3_NS base address */ +#define LCD_NS_BASE (0x500BC000UL) /* LCD_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) +#define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ +#else +#define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER5_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) +#define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ +#else +#define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER6_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) +#define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ +#else +#define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER7_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER8_S != 0))) +#define TIMER8_BASE (TIMER8_S_BASE) /* TIMER8 base address */ +#else +#define TIMER8_BASE (TIMER8_NS_BASE) /* TIMER8 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER8_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER9_S != 0))) +#define TIMER9_BASE (TIMER9_S_BASE) /* TIMER9 base address */ +#else +#define TIMER9_BASE (TIMER9_NS_BASE) /* TIMER9 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER9_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM0_S != 0))) +#define DMEM0_BASE (DMEM0_S_BASE) /* DMEM0 base address */ +#else +#define DMEM0_BASE (DMEM0_NS_BASE) /* DMEM0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM1_S != 0))) +#define DMEM1_BASE (DMEM1_S_BASE) /* DMEM1 base address */ +#else +#define DMEM1_BASE (DMEM1_NS_BASE) /* DMEM1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) +#define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ +#else +#define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) +#define USART2_BASE (USART2_S_BASE) /* USART2 base address */ +#else +#define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S) && (SL_TRUSTZONE_PERIPHERAL_I2C2_S != 0))) +#define I2C2_BASE (I2C2_S_BASE) /* I2C2 base address */ +#else +#define I2C2_BASE (I2C2_NS_BASE) /* I2C2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S) && (SL_TRUSTZONE_PERIPHERAL_I2C3_S != 0))) +#define I2C3_BASE (I2C3_S_BASE) /* I2C3 base address */ +#else +#define I2C3_BASE (I2C3_NS_BASE) /* I2C3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group MGM260PD32VNA_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNA_Peripheral_Declaration MGM260PD32VNA Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define TIMER5_S ((TIMER_TypeDef *) TIMER5_S_BASE) /**< TIMER5_S base pointer */ +#define TIMER6_S ((TIMER_TypeDef *) TIMER6_S_BASE) /**< TIMER6_S base pointer */ +#define TIMER7_S ((TIMER_TypeDef *) TIMER7_S_BASE) /**< TIMER7_S base pointer */ +#define TIMER8_S ((TIMER_TypeDef *) TIMER8_S_BASE) /**< TIMER8_S base pointer */ +#define TIMER9_S ((TIMER_TypeDef *) TIMER9_S_BASE) /**< TIMER9_S base pointer */ +#define DMEM0_S ((MPAHBRAM_TypeDef *) DMEM0_S_BASE) /**< DMEM0_S base pointer */ +#define DMEM1_S ((MPAHBRAM_TypeDef *) DMEM1_S_BASE) /**< DMEM1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define EUSART3_S ((EUSART_TypeDef *) EUSART3_S_BASE) /**< EUSART3_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define USART2_S ((USART_TypeDef *) USART2_S_BASE) /**< USART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define I2C2_S ((I2C_TypeDef *) I2C2_S_BASE) /**< I2C2_S base pointer */ +#define I2C3_S ((I2C_TypeDef *) I2C3_S_BASE) /**< I2C3_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define TIMER5_NS ((TIMER_TypeDef *) TIMER5_NS_BASE) /**< TIMER5_NS base pointer */ +#define TIMER6_NS ((TIMER_TypeDef *) TIMER6_NS_BASE) /**< TIMER6_NS base pointer */ +#define TIMER7_NS ((TIMER_TypeDef *) TIMER7_NS_BASE) /**< TIMER7_NS base pointer */ +#define TIMER8_NS ((TIMER_TypeDef *) TIMER8_NS_BASE) /**< TIMER8_NS base pointer */ +#define TIMER9_NS ((TIMER_TypeDef *) TIMER9_NS_BASE) /**< TIMER9_NS base pointer */ +#define DMEM0_NS ((MPAHBRAM_TypeDef *) DMEM0_NS_BASE) /**< DMEM0_NS base pointer */ +#define DMEM1_NS ((MPAHBRAM_TypeDef *) DMEM1_NS_BASE) /**< DMEM1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define EUSART3_NS ((EUSART_TypeDef *) EUSART3_NS_BASE) /**< EUSART3_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define USART2_NS ((USART_TypeDef *) USART2_NS_BASE) /**< USART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define I2C2_NS ((I2C_TypeDef *) I2C2_NS_BASE) /**< I2C2_NS base pointer */ +#define I2C3_NS ((I2C_TypeDef *) I2C3_NS_BASE) /**< I2C3_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define TIMER7 ((TIMER_TypeDef *) TIMER7_BASE) /**< TIMER7 base pointer */ +#define TIMER8 ((TIMER_TypeDef *) TIMER8_BASE) /**< TIMER8 base pointer */ +#define TIMER9 ((TIMER_TypeDef *) TIMER9_BASE) /**< TIMER9 base pointer */ +#define DMEM0 ((MPAHBRAM_TypeDef *) DMEM0_BASE) /**< DMEM0 base pointer */ +#define DMEM1 ((MPAHBRAM_TypeDef *) DMEM1_BASE) /**< DMEM1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define EUSART3 ((EUSART_TypeDef *) EUSART3_BASE) /**< EUSART3 base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) /**< I2C3 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group MGM260PD32VNA_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNA_Peripheral_Parameters MGM260PD32VNA Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x16UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x16UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x1A0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x4UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM0_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM0_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM0_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM0_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM0_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM0_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM0_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM0_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM0_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM0_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM0_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM0_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM0_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM0_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM0_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM0_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM0_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM0_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM0_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM0_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM0_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM0_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM0_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM0_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM0_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM0_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM0_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM0_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM0_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM0_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM0_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM0_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM0_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM0_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM0_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM0_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM0_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM0_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM0_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define DMEM1_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM1_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM1_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM1_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM1_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM1_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM1_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM1_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM1_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM1_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM1_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM1_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM1_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM1_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM1_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM1_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM1_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM1_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM1_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM1_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM1_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM1_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM1_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM1_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM1_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM1_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM1_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM1_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM1_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM1_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM1_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM1_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM1_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM1_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM1_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM1_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM1_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM1_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM1_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x0UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x320000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x320000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x8UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x8UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x8UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x8UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0x10UL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x8UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x8UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x8UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x8UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x10UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x10UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x10UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x10UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x28UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define TIMER5_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER5_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER5_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER5_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER5_NO_DTI 0x0UL /**> */ +#define TIMER6_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER6_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER6_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER6_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER6_NO_DTI 0x0UL /**> */ +#define TIMER7_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER7_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER7_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER7_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER7_NO_DTI 0x0UL /**> */ +#define TIMER8_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER8_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER8_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER8_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER8_NO_DTI 0x0UL /**> */ +#define TIMER9_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER9_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER9_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER9_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER9_NO_DTI 0x0UL /**> */ +#define SYSCFG_CHIP_PARTNUMBER 0x3UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART3_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART3_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define USART2_AUTOTX_REG 0x1UL /**> None */ +#define USART2_AUTOTX_REG_B 0x0UL /**> None */ +#define USART2_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART2_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART2_CLK_PRS 0x1UL /**> None */ +#define USART2_CLK_PRS_B 0x0UL /**> New Param */ +#define USART2_FLOW_CONTROL 0x1UL /**> None */ +#define USART2_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART2_I2S 0x1UL /**> None */ +#define USART2_I2S_B 0x0UL /**> New Param */ +#define USART2_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART2_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_MVDIS_FUNC 0x1UL /**> None */ +#define USART2_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART2_RX_PRS 0x1UL /**> None */ +#define USART2_RX_PRS_B 0x0UL /**> New Param */ +#define USART2_SC_AVAILABLE 0x1UL /**> None */ +#define USART2_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART2_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART2_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART2_TIMER 0x1UL /**> New Param */ +#define USART2_TIMER_B 0x0UL /**> New Param */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C2_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C2_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C3_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C3_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_OCTAPLEX 0x1UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x0UL /**> */ +#define LCD_SEG_NUM 0x28UL /**> None */ +#define LCD_SEGASCOM_SEGSTART 0x24UL /**> */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x44UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x4UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_64 0x4UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : ((n) == 3) ? EUSART3 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : ((ref) == EUSART3) ? 3 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : ((n) == 2) ? I2C2 \ + : ((n) == 3) ? I2C3 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : ((ref) == I2C2) ? 2 \ + : ((ref) == I2C3) ? 3 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : ((n) == 2) ? I2C2_DELAY \ + : ((n) == 3) ? I2C3_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : ((n) == 2) ? I2C2_DELAY_CHAIN_NUM \ + : ((n) == 3) ? I2C3_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : ((n) == 5) ? TIMER5 \ + : ((n) == 6) ? TIMER6 \ + : ((n) == 7) ? TIMER7 \ + : ((n) == 8) ? TIMER8 \ + : ((n) == 9) ? TIMER9 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : ((ref) == TIMER5) ? 5 \ + : ((ref) == TIMER6) ? 6 \ + : ((ref) == TIMER7) ? 7 \ + : ((ref) == TIMER8) ? 8 \ + : ((ref) == TIMER9) ? 9 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : ((n) == 5) ? TIMER5_CC_NUM \ + : ((n) == 6) ? TIMER6_CC_NUM \ + : ((n) == 7) ? TIMER7_CC_NUM \ + : ((n) == 8) ? TIMER8_CC_NUM \ + : ((n) == 9) ? TIMER9_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : ((n) == 5) ? TIMER5_CNTWIDTH \ + : ((n) == 6) ? TIMER6_CNTWIDTH \ + : ((n) == 7) ? TIMER7_CNTWIDTH \ + : ((n) == 8) ? TIMER8_CNTWIDTH \ + : ((n) == 9) ? TIMER9_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : ((n) == 5) ? TIMER5_DTI \ + : ((n) == 6) ? TIMER6_DTI \ + : ((n) == 7) ? TIMER7_DTI \ + : ((n) == 8) ? TIMER8_DTI \ + : ((n) == 9) ? TIMER9_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : ((n) == 5) ? TIMER5_DTI_CC_NUM \ + : ((n) == 6) ? TIMER6_DTI_CC_NUM \ + : ((n) == 7) ? TIMER7_DTI_CC_NUM \ + : ((n) == 8) ? TIMER8_DTI_CC_NUM \ + : ((n) == 9) ? TIMER9_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : ((n) == 5) ? TIMER5_NO_DTI \ + : ((n) == 6) ? TIMER6_NO_DTI \ + : ((n) == 7) ? TIMER7_NO_DTI \ + : ((n) == 8) ? TIMER8_NO_DTI \ + : ((n) == 9) ? TIMER9_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : ((n) == 2) ? USART2 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : ((ref) == USART2) ? 2 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : ((n) == 2) ? USART2_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : ((n) == 2) ? USART2_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : ((n) == 2) ? USART2_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : ((n) == 2) ? USART2_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : ((n) == 2) ? USART2_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : ((n) == 2) ? USART2_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : ((n) == 2) ? USART2_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : ((n) == 2) ? USART2_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : ((n) == 2) ? USART2_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : ((n) == 2) ? USART2_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : ((n) == 2) ? USART2_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : ((n) == 2) ? USART2_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : ((n) == 2) ? USART2_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : ((n) == 2) ? USART2_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : ((n) == 2) ? USART2_TIMER_B \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group MGM260PD32VNA_Peripheral_Parameters */ + +/** @} End of group MGM260PD32VNA */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm260pd32vnn.h b/platform/Device/SiliconLabs/MGM26/Include/mgm260pd32vnn.h new file mode 100644 index 0000000000..3b55061744 --- /dev/null +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm260pd32vnn.h @@ -0,0 +1,2023 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for MGM260PD32VNN + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef MGM260PD32VNN_H +#define MGM260PD32VNN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup MGM260PD32VNN MGM260PD32VNN + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** MGM26 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + TIMER5_IRQn = 9, /*!< 9 EFR32 TIMER5 Interrupt */ + TIMER6_IRQn = 10, /*!< 10 EFR32 TIMER6 Interrupt */ + TIMER7_IRQn = 11, /*!< 11 EFR32 TIMER7 Interrupt */ + TIMER8_IRQn = 12, /*!< 12 EFR32 TIMER8 Interrupt */ + TIMER9_IRQn = 13, /*!< 13 EFR32 TIMER9 Interrupt */ + USART0_RX_IRQn = 14, /*!< 14 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 15, /*!< 15 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 16, /*!< 16 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 17, /*!< 17 EFR32 USART1_TX Interrupt */ + USART2_RX_IRQn = 18, /*!< 18 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 19, /*!< 19 EFR32 USART2_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 22, /*!< 22 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 23, /*!< 23 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 24, /*!< 24 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 25, /*!< 25 EFR32 EUSART2_TX Interrupt */ + EUSART3_RX_IRQn = 26, /*!< 26 EFR32 EUSART3_RX Interrupt */ + EUSART3_TX_IRQn = 27, /*!< 27 EFR32 EUSART3_TX Interrupt */ + MVP_IRQn = 28, /*!< 28 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 29, /*!< 29 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 30, /*!< 30 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 31, /*!< 31 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 32, /*!< 32 EFR32 SYSCFG Interrupt */ + MPAHBRAM0_IRQn = 33, /*!< 33 EFR32 MPAHBRAM0 Interrupt */ + MPAHBRAM1_IRQn = 34, /*!< 34 EFR32 MPAHBRAM1 Interrupt */ + LDMA_IRQn = 35, /*!< 35 EFR32 LDMA Interrupt */ + LFXO_IRQn = 36, /*!< 36 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 37, /*!< 37 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 38, /*!< 38 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 39, /*!< 39 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 40, /*!< 40 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 41, /*!< 41 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + I2C2_IRQn = 43, /*!< 43 EFR32 I2C2 Interrupt */ + I2C3_IRQn = 44, /*!< 44 EFR32 I2C3 Interrupt */ + EMUDG_IRQn = 45, /*!< 45 EFR32 EMUDG Interrupt */ + AGC_IRQn = 46, /*!< 46 EFR32 AGC Interrupt */ + BUFC_IRQn = 47, /*!< 47 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 48, /*!< 48 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 49, /*!< 49 EFR32 FRC Interrupt */ + MODEM_IRQn = 50, /*!< 50 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 51, /*!< 51 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 52, /*!< 52 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 53, /*!< 53 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 54, /*!< 54 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 55, /*!< 55 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 56, /*!< 56 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 57, /*!< 57 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 58, /*!< 58 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 59, /*!< 59 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 60, /*!< 60 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 61, /*!< 61 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 62, /*!< 62 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 63, /*!< 63 EFR32 CMU Interrupt */ + AES_IRQn = 64, /*!< 64 EFR32 AES Interrupt */ + IADC_IRQn = 65, /*!< 65 EFR32 IADC Interrupt */ + MSC_IRQn = 66, /*!< 66 EFR32 MSC Interrupt */ + DPLL0_IRQn = 67, /*!< 67 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 68, /*!< 68 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 69, /*!< 69 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 70, /*!< 70 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 71, /*!< 71 EFR32 SW0 Interrupt */ + SW1_IRQn = 72, /*!< 72 EFR32 SW1 Interrupt */ + SW2_IRQn = 73, /*!< 73 EFR32 SW2 Interrupt */ + SW3_IRQn = 74, /*!< 74 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 75, /*!< 75 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 76, /*!< 76 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 77, /*!< 77 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 78, /*!< 78 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 79, /*!< 79 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 80, /*!< 80 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 81, /*!< 81 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 82, /*!< 82 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 83, /*!< 83 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 84, /*!< 84 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 85, /*!< 85 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 86, /*!< 86 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 87, /*!< 87 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 88, /*!< 88 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 89, /*!< 89 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 90, /*!< 90 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 91, /*!< 91 EFR32 AHB2AHB1 Interrupt */ + LCD_IRQn = 92, /*!< 92 EFR32 LCD Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup MGM260PD32VNN_Core MGM260PD32VNN Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group MGM260PD32VNN_Core */ + +/**************************************************************************//** +* @defgroup MGM260PD32VNN_Part MGM260PD32VNN Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(MGM260PD32VNN) +#define MGM260PD32VNN 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "MGM260PD32VNN" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_MODULE 1 /** Silicon Labs multi-chip module */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_6 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 6 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_225 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00320000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0831FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x16UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00320000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0831FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x16UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM0_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM0_RAM0_RAM_MEM base address */ +#define DMEM0_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM0_RAM0_RAM_MEM available address space */ +#define DMEM0_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM0_RAM0_RAM_MEM end address */ +#define DMEM0_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM0_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define DMEM1_RAM0_RAM_MEM_BASE (0x20040000UL) /** DMEM1_RAM0_RAM_MEM base address */ +#define DMEM1_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM1_RAM0_RAM_MEM available address space */ +#define DMEM1_RAM0_RAM_MEM_END (0x2007FFFFUL) /** DMEM1_RAM0_RAM_MEM end address */ +#define DMEM1_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM1_RAM0_RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for MGM260PD32VNN */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00320000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 93 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG20_PORT GPIO_PA_INDEX /**< Port of SEG20.*/ +#define LCD_SEG20_PIN 9U /**< Pin of SEG20.*/ +#define LCD_SEG26_PORT GPIO_PB_INDEX /**< Port of SEG26.*/ +#define LCD_SEG26_PIN 4U /**< Pin of SEG26.*/ +#define LCD_SEG27_PORT GPIO_PB_INDEX /**< Port of SEG27.*/ +#define LCD_SEG27_PIN 5U /**< Pin of SEG27.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 2 /** 2 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 4 /** 4 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 4 /** 4 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 10 /** 10 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 3 /** 3 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_mgm26.h" /* System Header File */ + +/** @} End of group MGM260PD32VNN_Part */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNN_Peripheral_TypeDefs MGM260PD32VNN Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "mgm26_emu.h" +#include "mgm26_cmu.h" +#include "mgm26_burtc.h" +#include "mgm26_hfrco.h" +#include "mgm26_fsrco.h" +#include "mgm26_dpll.h" +#include "mgm26_lfxo.h" +#include "mgm26_lfrco.h" +#include "mgm26_ulfrco.h" +#include "mgm26_keyscan.h" +#include "mgm26_msc.h" +#include "mgm26_icache.h" +#include "mgm26_prs.h" +#include "mgm26_gpio.h" +#include "mgm26_ldma.h" +#include "mgm26_ldmaxbar.h" +#include "mgm26_timer.h" +#include "mgm26_mpahbram.h" +#include "mgm26_syscfg.h" +#include "mgm26_buram.h" +#include "mgm26_gpcrc.h" +#include "mgm26_eusart.h" +#include "mgm26_dcdc.h" +#include "mgm26_mailbox.h" +#include "mgm26_usart.h" +#include "mgm26_sysrtc.h" +#include "mgm26_i2c.h" +#include "mgm26_lcd.h" +#include "mgm26_lcdrf.h" +#include "mgm26_aes.h" +#include "mgm26_smu.h" +#include "mgm26_letimer.h" +#include "mgm26_iadc.h" +#include "mgm26_acmp.h" +#include "mgm26_amuxcp.h" +#include "mgm26_vdac.h" +#include "mgm26_pcnt.h" +#include "mgm26_hfxo.h" +#include "mgm26_wdog.h" +#include "mgm26_semailbox.h" +#include "mgm26_mvp.h" +#include "mgm26_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "mgm26_prs_signals.h" +#include "mgm26_dma_descriptor.h" +#include "mgm26_ldmaxbar_defines.h" + +/** @} End of group MGM260PD32VNN_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNN_Peripheral_Base MGM260PD32VNN Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define BURTC_S_BASE (0x4000C000UL) /* BURTC_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define KEYSCAN_S_BASE (0x4002C000UL) /* KEYSCAN_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define TIMER5_S_BASE (0x4005C000UL) /* TIMER5_S base address */ +#define TIMER6_S_BASE (0x40060000UL) /* TIMER6_S base address */ +#define TIMER7_S_BASE (0x40064000UL) /* TIMER7_S base address */ +#define TIMER8_S_BASE (0x40068000UL) /* TIMER8_S base address */ +#define TIMER9_S_BASE (0x4006C000UL) /* TIMER9_S base address */ +#define DMEM0_S_BASE (0x40074000UL) /* DMEM0_S base address */ +#define DMEM1_S_BASE (0x40078000UL) /* DMEM1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x4007C000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x40080000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40084000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define EUSART1_S_BASE (0x4008C000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x40090000UL) /* EUSART2_S base address */ +#define EUSART3_S_BASE (0x40094000UL) /* EUSART3_S base address */ +#define DCDC_S_BASE (0x40098000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x4009C000UL) /* HOSTMAILBOX_S base address */ +#define USART0_S_BASE (0x400A0000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x400A4000UL) /* USART1_S base address */ +#define USART2_S_BASE (0x400A8000UL) /* USART2_S base address */ +#define SYSRTC0_S_BASE (0x400AC000UL) /* SYSRTC0_S base address */ +#define I2C1_S_BASE (0x400B0000UL) /* I2C1_S base address */ +#define I2C2_S_BASE (0x400B4000UL) /* I2C2_S base address */ +#define I2C3_S_BASE (0x400B8000UL) /* I2C3_S base address */ +#define LCD_S_BASE (0x400BC000UL) /* LCD_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define BURTC_NS_BASE (0x5000C000UL) /* BURTC_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define KEYSCAN_NS_BASE (0x5002C000UL) /* KEYSCAN_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define TIMER5_NS_BASE (0x5005C000UL) /* TIMER5_NS base address */ +#define TIMER6_NS_BASE (0x50060000UL) /* TIMER6_NS base address */ +#define TIMER7_NS_BASE (0x50064000UL) /* TIMER7_NS base address */ +#define TIMER8_NS_BASE (0x50068000UL) /* TIMER8_NS base address */ +#define TIMER9_NS_BASE (0x5006C000UL) /* TIMER9_NS base address */ +#define DMEM0_NS_BASE (0x50074000UL) /* DMEM0_NS base address */ +#define DMEM1_NS_BASE (0x50078000UL) /* DMEM1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x5007C000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x50080000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50084000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define EUSART1_NS_BASE (0x5008C000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x50090000UL) /* EUSART2_NS base address */ +#define EUSART3_NS_BASE (0x50094000UL) /* EUSART3_NS base address */ +#define DCDC_NS_BASE (0x50098000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x5009C000UL) /* HOSTMAILBOX_NS base address */ +#define USART0_NS_BASE (0x500A0000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x500A4000UL) /* USART1_NS base address */ +#define USART2_NS_BASE (0x500A8000UL) /* USART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500AC000UL) /* SYSRTC0_NS base address */ +#define I2C1_NS_BASE (0x500B0000UL) /* I2C1_NS base address */ +#define I2C2_NS_BASE (0x500B4000UL) /* I2C2_NS base address */ +#define I2C3_NS_BASE (0x500B8000UL) /* I2C3_NS base address */ +#define LCD_NS_BASE (0x500BC000UL) /* LCD_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) +#define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ +#else +#define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER5_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) +#define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ +#else +#define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER6_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) +#define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ +#else +#define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER7_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER8_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER8_S != 0))) +#define TIMER8_BASE (TIMER8_S_BASE) /* TIMER8 base address */ +#else +#define TIMER8_BASE (TIMER8_NS_BASE) /* TIMER8 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER8_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER9_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER9_S != 0))) +#define TIMER9_BASE (TIMER9_S_BASE) /* TIMER9 base address */ +#else +#define TIMER9_BASE (TIMER9_NS_BASE) /* TIMER9 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER9_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM0_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM0_S != 0))) +#define DMEM0_BASE (DMEM0_S_BASE) /* DMEM0 base address */ +#else +#define DMEM0_BASE (DMEM0_NS_BASE) /* DMEM0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM1_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM1_S != 0))) +#define DMEM1_BASE (DMEM1_S_BASE) /* DMEM1 base address */ +#else +#define DMEM1_BASE (DMEM1_NS_BASE) /* DMEM1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) +#define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ +#else +#define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) +#define USART2_BASE (USART2_S_BASE) /* USART2 base address */ +#else +#define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C2_S) && (SL_TRUSTZONE_PERIPHERAL_I2C2_S != 0))) +#define I2C2_BASE (I2C2_S_BASE) /* I2C2 base address */ +#else +#define I2C2_BASE (I2C2_NS_BASE) /* I2C2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C3_S) && (SL_TRUSTZONE_PERIPHERAL_I2C3_S != 0))) +#define I2C3_BASE (I2C3_S_BASE) /* I2C3 base address */ +#else +#define I2C3_BASE (I2C3_NS_BASE) /* I2C3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group MGM260PD32VNN_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNN_Peripheral_Declaration MGM260PD32VNN Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define TIMER5_S ((TIMER_TypeDef *) TIMER5_S_BASE) /**< TIMER5_S base pointer */ +#define TIMER6_S ((TIMER_TypeDef *) TIMER6_S_BASE) /**< TIMER6_S base pointer */ +#define TIMER7_S ((TIMER_TypeDef *) TIMER7_S_BASE) /**< TIMER7_S base pointer */ +#define TIMER8_S ((TIMER_TypeDef *) TIMER8_S_BASE) /**< TIMER8_S base pointer */ +#define TIMER9_S ((TIMER_TypeDef *) TIMER9_S_BASE) /**< TIMER9_S base pointer */ +#define DMEM0_S ((MPAHBRAM_TypeDef *) DMEM0_S_BASE) /**< DMEM0_S base pointer */ +#define DMEM1_S ((MPAHBRAM_TypeDef *) DMEM1_S_BASE) /**< DMEM1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define EUSART3_S ((EUSART_TypeDef *) EUSART3_S_BASE) /**< EUSART3_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define USART2_S ((USART_TypeDef *) USART2_S_BASE) /**< USART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define I2C2_S ((I2C_TypeDef *) I2C2_S_BASE) /**< I2C2_S base pointer */ +#define I2C3_S ((I2C_TypeDef *) I2C3_S_BASE) /**< I2C3_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define TIMER5_NS ((TIMER_TypeDef *) TIMER5_NS_BASE) /**< TIMER5_NS base pointer */ +#define TIMER6_NS ((TIMER_TypeDef *) TIMER6_NS_BASE) /**< TIMER6_NS base pointer */ +#define TIMER7_NS ((TIMER_TypeDef *) TIMER7_NS_BASE) /**< TIMER7_NS base pointer */ +#define TIMER8_NS ((TIMER_TypeDef *) TIMER8_NS_BASE) /**< TIMER8_NS base pointer */ +#define TIMER9_NS ((TIMER_TypeDef *) TIMER9_NS_BASE) /**< TIMER9_NS base pointer */ +#define DMEM0_NS ((MPAHBRAM_TypeDef *) DMEM0_NS_BASE) /**< DMEM0_NS base pointer */ +#define DMEM1_NS ((MPAHBRAM_TypeDef *) DMEM1_NS_BASE) /**< DMEM1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define EUSART3_NS ((EUSART_TypeDef *) EUSART3_NS_BASE) /**< EUSART3_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define USART2_NS ((USART_TypeDef *) USART2_NS_BASE) /**< USART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define I2C2_NS ((I2C_TypeDef *) I2C2_NS_BASE) /**< I2C2_NS base pointer */ +#define I2C3_NS ((I2C_TypeDef *) I2C3_NS_BASE) /**< I2C3_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define TIMER7 ((TIMER_TypeDef *) TIMER7_BASE) /**< TIMER7 base pointer */ +#define TIMER8 ((TIMER_TypeDef *) TIMER8_BASE) /**< TIMER8 base pointer */ +#define TIMER9 ((TIMER_TypeDef *) TIMER9_BASE) /**< TIMER9 base pointer */ +#define DMEM0 ((MPAHBRAM_TypeDef *) DMEM0_BASE) /**< DMEM0 base pointer */ +#define DMEM1 ((MPAHBRAM_TypeDef *) DMEM1_BASE) /**< DMEM1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define EUSART3 ((EUSART_TypeDef *) EUSART3_BASE) /**< EUSART3 base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) /**< I2C3 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group MGM260PD32VNN_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup MGM260PD32VNN_Peripheral_Parameters MGM260PD32VNN Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x16UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x16UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x1A0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x4UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM0_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM0_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM0_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM0_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM0_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM0_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM0_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM0_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM0_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM0_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM0_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM0_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM0_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM0_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM0_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM0_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM0_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM0_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM0_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM0_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM0_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM0_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM0_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM0_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM0_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM0_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM0_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM0_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM0_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM0_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM0_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM0_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM0_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM0_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM0_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM0_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM0_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM0_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM0_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define DMEM1_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM1_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM1_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM1_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM1_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM1_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM1_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM1_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM1_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM1_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM1_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM1_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM1_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM1_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM1_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM1_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM1_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM1_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM1_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM1_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM1_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM1_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM1_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM1_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM1_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM1_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM1_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM1_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM1_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM1_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM1_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM1_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM1_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM1_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM1_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM1_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM1_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM1_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM1_WAITSTATE_EXCLUDE 0x1UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x0UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x320000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x320000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x8UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x8UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x8UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x8UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0x10UL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x8UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x8UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x8UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x8UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x10UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x10UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU 0x8UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x10UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x10UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU 0x8UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x28UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define TIMER5_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER5_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER5_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER5_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER5_NO_DTI 0x0UL /**> */ +#define TIMER6_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER6_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER6_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER6_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER6_NO_DTI 0x0UL /**> */ +#define TIMER7_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER7_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER7_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER7_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER7_NO_DTI 0x0UL /**> */ +#define TIMER8_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER8_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER8_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER8_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER8_NO_DTI 0x0UL /**> */ +#define TIMER9_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER9_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER9_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER9_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER9_NO_DTI 0x0UL /**> */ +#define SYSCFG_CHIP_PARTNUMBER 0x3UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART3_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART3_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define USART2_AUTOTX_REG 0x1UL /**> None */ +#define USART2_AUTOTX_REG_B 0x0UL /**> None */ +#define USART2_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART2_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART2_CLK_PRS 0x1UL /**> None */ +#define USART2_CLK_PRS_B 0x0UL /**> New Param */ +#define USART2_FLOW_CONTROL 0x1UL /**> None */ +#define USART2_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART2_I2S 0x1UL /**> None */ +#define USART2_I2S_B 0x0UL /**> New Param */ +#define USART2_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART2_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_MVDIS_FUNC 0x1UL /**> None */ +#define USART2_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART2_RX_PRS 0x1UL /**> None */ +#define USART2_RX_PRS_B 0x0UL /**> New Param */ +#define USART2_SC_AVAILABLE 0x1UL /**> None */ +#define USART2_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART2_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART2_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART2_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART2_TIMER 0x1UL /**> New Param */ +#define USART2_TIMER_B 0x0UL /**> New Param */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C2_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C2_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define I2C3_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C3_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_OCTAPLEX 0x1UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x0UL /**> */ +#define LCD_SEG_NUM 0x28UL /**> None */ +#define LCD_SEGASCOM_SEGSTART 0x24UL /**> */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x44UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x4UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_64 0x4UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : ((n) == 3) ? EUSART3 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : ((ref) == EUSART3) ? 3 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : ((n) == 3) ? EUSART3_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : ((n) == 2) ? I2C2 \ + : ((n) == 3) ? I2C3 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : ((ref) == I2C2) ? 2 \ + : ((ref) == I2C3) ? 3 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : ((n) == 2) ? I2C2_DELAY \ + : ((n) == 3) ? I2C3_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : ((n) == 2) ? I2C2_DELAY_CHAIN_NUM \ + : ((n) == 3) ? I2C3_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : ((n) == 5) ? TIMER5 \ + : ((n) == 6) ? TIMER6 \ + : ((n) == 7) ? TIMER7 \ + : ((n) == 8) ? TIMER8 \ + : ((n) == 9) ? TIMER9 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : ((ref) == TIMER5) ? 5 \ + : ((ref) == TIMER6) ? 6 \ + : ((ref) == TIMER7) ? 7 \ + : ((ref) == TIMER8) ? 8 \ + : ((ref) == TIMER9) ? 9 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : ((n) == 5) ? TIMER5_CC_NUM \ + : ((n) == 6) ? TIMER6_CC_NUM \ + : ((n) == 7) ? TIMER7_CC_NUM \ + : ((n) == 8) ? TIMER8_CC_NUM \ + : ((n) == 9) ? TIMER9_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : ((n) == 5) ? TIMER5_CNTWIDTH \ + : ((n) == 6) ? TIMER6_CNTWIDTH \ + : ((n) == 7) ? TIMER7_CNTWIDTH \ + : ((n) == 8) ? TIMER8_CNTWIDTH \ + : ((n) == 9) ? TIMER9_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : ((n) == 5) ? TIMER5_DTI \ + : ((n) == 6) ? TIMER6_DTI \ + : ((n) == 7) ? TIMER7_DTI \ + : ((n) == 8) ? TIMER8_DTI \ + : ((n) == 9) ? TIMER9_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : ((n) == 5) ? TIMER5_DTI_CC_NUM \ + : ((n) == 6) ? TIMER6_DTI_CC_NUM \ + : ((n) == 7) ? TIMER7_DTI_CC_NUM \ + : ((n) == 8) ? TIMER8_DTI_CC_NUM \ + : ((n) == 9) ? TIMER9_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : ((n) == 5) ? TIMER5_NO_DTI \ + : ((n) == 6) ? TIMER6_NO_DTI \ + : ((n) == 7) ? TIMER7_NO_DTI \ + : ((n) == 8) ? TIMER8_NO_DTI \ + : ((n) == 9) ? TIMER9_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : ((n) == 2) ? USART2 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : ((ref) == USART2) ? 2 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : ((n) == 2) ? USART2_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : ((n) == 2) ? USART2_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : ((n) == 2) ? USART2_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : ((n) == 2) ? USART2_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : ((n) == 2) ? USART2_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : ((n) == 2) ? USART2_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : ((n) == 2) ? USART2_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : ((n) == 2) ? USART2_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : ((n) == 2) ? USART2_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : ((n) == 2) ? USART2_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : ((n) == 2) ? USART2_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : ((n) == 2) ? USART2_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : ((n) == 2) ? USART2_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : ((n) == 2) ? USART2_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : ((n) == 2) ? USART2_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : ((n) == 2) ? USART2_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : ((n) == 2) ? USART2_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : ((n) == 2) ? USART2_TIMER_B \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group MGM260PD32VNN_Peripheral_Parameters */ + +/** @} End of group MGM260PD32VNN */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_acmp.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_acmp.h index 16d9c852a9..6ee5801aff 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_acmp.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_acmp.h @@ -3,7 +3,7 @@ * @brief MGM26 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_aes.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_aes.h index 516083c215..c3966787dd 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_aes.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_aes.h @@ -3,7 +3,7 @@ * @brief MGM26 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_amuxcp.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_amuxcp.h index 185d8c8654..652cc99d7f 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_amuxcp.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_amuxcp.h @@ -3,7 +3,7 @@ * @brief MGM26 AMUXCP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_buram.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_buram.h index d259251642..75f0986828 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_buram.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_buram.h @@ -3,7 +3,7 @@ * @brief MGM26 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_burtc.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_burtc.h index 746685d708..75ca02041e 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_burtc.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_burtc.h @@ -3,7 +3,7 @@ * @brief MGM26 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_cmu.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_cmu.h index 87c0175526..d4ff1dc851 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_cmu.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_cmu.h @@ -3,7 +3,7 @@ * @brief MGM26 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_dcdc.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_dcdc.h index 6a429aeade..ed1926a0c8 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_dcdc.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_dcdc.h @@ -3,7 +3,7 @@ * @brief MGM26 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib @@ -149,21 +149,30 @@ typedef struct dcdc_typedef{ #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ /* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ /* Bit fields for DCDC EM01CTRL0 */ #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_devinfo.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_devinfo.h index 01b7cd2e4b..614e092037 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_devinfo.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_devinfo.h @@ -3,7 +3,7 @@ * @brief MGM26 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_dma_descriptor.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_dma_descriptor.h index 7b0203065b..cdcc2af72e 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief MGM26 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM26_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_dpll.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_dpll.h index 74abaae627..0e128eee22 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_dpll.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_dpll.h @@ -3,7 +3,7 @@ * @brief MGM26 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_emu.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_emu.h index 6d8c665bc8..5a1cb5fc6d 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_emu.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_emu.h @@ -3,7 +3,7 @@ * @brief MGM26 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_eusart.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_eusart.h index efe95c24ff..d55edf5fc8 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_eusart.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_eusart.h @@ -3,7 +3,7 @@ * @brief MGM26 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_fsrco.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_fsrco.h index fa14b75c8a..2a7c5e03cc 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_fsrco.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_fsrco.h @@ -3,7 +3,7 @@ * @brief MGM26 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpcrc.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpcrc.h index 3af510188e..9f4c1dc81c 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpcrc.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpcrc.h @@ -3,7 +3,7 @@ * @brief MGM26 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio.h index b3d9610e92..2615cb5c7d 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio.h @@ -3,7 +3,7 @@ * @brief MGM26 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio_port.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio_port.h index eb54def03d..842e103a32 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio_port.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_gpio_port.h @@ -3,7 +3,7 @@ * @brief MGM26 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfrco.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfrco.h index 5f1a694e41..6346a8f4ff 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfrco.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfrco.h @@ -3,7 +3,7 @@ * @brief MGM26 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfxo.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfxo.h index cf64b3849a..a441684e83 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfxo.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_hfxo.h @@ -3,7 +3,7 @@ * @brief MGM26 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_i2c.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_i2c.h index 702bbe4caf..4e3b7ee0ff 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_i2c.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_i2c.h @@ -3,7 +3,7 @@ * @brief MGM26 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_iadc.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_iadc.h index bcc857a0e2..456858adeb 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_iadc.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_iadc.h @@ -3,7 +3,7 @@ * @brief MGM26 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_icache.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_icache.h index 9f714fc499..0020431f5c 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_icache.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_icache.h @@ -3,7 +3,7 @@ * @brief MGM26 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_keyscan.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_keyscan.h index 77b19402f5..261b857a87 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_keyscan.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_keyscan.h @@ -3,7 +3,7 @@ * @brief MGM26 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcd.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcd.h index ae4064edfe..0a5443f85b 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcd.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcd.h @@ -3,7 +3,7 @@ * @brief MGM26 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcdrf.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcdrf.h index 4b7d818d13..2b408f2de6 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcdrf.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lcdrf.h @@ -3,7 +3,7 @@ * @brief MGM26 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldma.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldma.h index 0f30200d83..c1b83eb9fe 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldma.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldma.h @@ -3,7 +3,7 @@ * @brief MGM26 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar.h index 001074ff0f..f015f984a7 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief MGM26 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar_defines.h index 702d61d315..4cb478f5a4 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief MGM26 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM26_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_letimer.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_letimer.h index 39c7032f57..8a1b199e99 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_letimer.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_letimer.h @@ -3,7 +3,7 @@ * @brief MGM26 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfrco.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfrco.h index 53d1a88031..e2967296fc 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfrco.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfrco.h @@ -3,7 +3,7 @@ * @brief MGM26 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfxo.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfxo.h index 3c0698c5ff..c6b0ba036f 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfxo.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_lfxo.h @@ -3,7 +3,7 @@ * @brief MGM26 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_mailbox.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_mailbox.h index b48b321134..e8dc9da18f 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_mailbox.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_mailbox.h @@ -3,7 +3,7 @@ * @brief MGM26 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_mpahbram.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_mpahbram.h index c6b55cabce..9e4b1d35ce 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_mpahbram.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_mpahbram.h @@ -3,7 +3,7 @@ * @brief MGM26 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_msc.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_msc.h index f551ccf4ff..f9585c8741 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_msc.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_msc.h @@ -3,7 +3,7 @@ * @brief MGM26 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_mvp.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_mvp.h index 0634f846e5..8c5cfb4373 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_mvp.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_mvp.h @@ -3,7 +3,7 @@ * @brief MGM26 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_pcnt.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_pcnt.h index 7eff712f38..fae194946a 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_pcnt.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_pcnt.h @@ -3,7 +3,7 @@ * @brief MGM26 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs.h index bb67ea591d..50e65628be 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs.h @@ -3,7 +3,7 @@ * @brief MGM26 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs_signals.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs_signals.h index a29131382c..c0025bb762 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_prs_signals.h @@ -3,16 +3,28 @@ * @brief MGM26 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef MGM26_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_semailbox.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_semailbox.h index 1ccba3a154..70767611fb 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_semailbox.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_semailbox.h @@ -3,7 +3,7 @@ * @brief MGM26 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_smu.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_smu.h index 40c2908297..0896b17972 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_smu.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_smu.h @@ -3,7 +3,7 @@ * @brief MGM26 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_syscfg.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_syscfg.h index ba973d2849..2722b27ffd 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_syscfg.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_syscfg.h @@ -3,7 +3,7 @@ * @brief MGM26 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_sysrtc.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_sysrtc.h index 671be79b4e..9fdecf5a40 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_sysrtc.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_sysrtc.h @@ -3,7 +3,7 @@ * @brief MGM26 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_timer.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_timer.h index fa2934a208..d39aabccb0 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_timer.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_timer.h @@ -3,7 +3,7 @@ * @brief MGM26 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ulfrco.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ulfrco.h index 038423d5a7..a095569bec 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_ulfrco.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_ulfrco.h @@ -3,7 +3,7 @@ * @brief MGM26 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_usart.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_usart.h index 33473952b7..6bba18be10 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_usart.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_usart.h @@ -3,7 +3,7 @@ * @brief MGM26 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_vdac.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_vdac.h index ad39bc4e73..46039724f5 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_vdac.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_vdac.h @@ -3,7 +3,7 @@ * @brief MGM26 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/mgm26_wdog.h b/platform/Device/SiliconLabs/MGM26/Include/mgm26_wdog.h index 52463f49c1..2f045d3ca2 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/mgm26_wdog.h +++ b/platform/Device/SiliconLabs/MGM26/Include/mgm26_wdog.h @@ -3,7 +3,7 @@ * @brief MGM26 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Include/system_mgm26.h b/platform/Device/SiliconLabs/MGM26/Include/system_mgm26.h index 296e616cb3..452c546140 100644 --- a/platform/Device/SiliconLabs/MGM26/Include/system_mgm26.h +++ b/platform/Device/SiliconLabs/MGM26/Include/system_mgm26.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for MGM26 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM26/Source/startup_mgm26.c b/platform/Device/SiliconLabs/MGM26/Source/startup_mgm26.c index 04eb0010c1..7a2a176602 100644 --- a/platform/Device/SiliconLabs/MGM26/Source/startup_mgm26.c +++ b/platform/Device/SiliconLabs/MGM26/Source/startup_mgm26.c @@ -4,17 +4,6 @@ * Device MGM26 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/MGM26/Source/system_mgm26.c b/platform/Device/SiliconLabs/MGM26/Source/system_mgm26.c index d1044e90b0..e4cd2bec18 100644 --- a/platform/Device/SiliconLabs/MGM26/Source/system_mgm26.c +++ b/platform/Device/SiliconLabs/MGM26/Source/system_mgm26.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for MGM26 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/em_device.h b/platform/Device/SiliconLabs/ZGM23/Include/em_device.h index 772f3e883e..fccb7d75eb 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/em_device.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h b/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h index 19482d7d3c..8be31073f9 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for ZGM23 ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h index 405e6e4e31..633bff1446 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h @@ -4,7 +4,7 @@ * for ZGM230SA27HGN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h index 064d962609..cb8588015d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h @@ -4,7 +4,7 @@ * for ZGM230SA27HNN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h index 89e45910e8..09813c10ef 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h @@ -4,7 +4,7 @@ * for ZGM230SB27HGN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h index d5eb40d2a1..d5a37c0efe 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h @@ -4,7 +4,7 @@ * for ZGM230SB27HNN ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h index 7e2d302083..6ce2301b38 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h @@ -3,7 +3,7 @@ * @brief ZGM23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h index 2ca6ec00e9..c2037e47fa 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h @@ -3,7 +3,7 @@ * @brief ZGM23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h index ecfbd37d9b..8670a43465 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h @@ -3,7 +3,7 @@ * @brief ZGM23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h index d8ea87730b..24b939ffdf 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h @@ -3,7 +3,7 @@ * @brief ZGM23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h index 4f0e5f7d4d..63cf131e19 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h @@ -3,7 +3,7 @@ * @brief ZGM23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h index 7ef2a4ba2e..b14ed8946a 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h @@ -3,7 +3,7 @@ * @brief ZGM23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h index 2c3aee8c8e..b3d7091e37 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h @@ -3,7 +3,7 @@ * @brief ZGM23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h index c46b82b833..8aae511214 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h @@ -3,16 +3,28 @@ * @brief ZGM23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef ZGM23_DMA_DESCRIPTOR_H diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h index 2f924594bb..eb00b1fade 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h @@ -3,7 +3,7 @@ * @brief ZGM23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h index f92d32279b..c952698dea 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h @@ -3,7 +3,7 @@ * @brief ZGM23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h index 27ec9b89c4..3697e5a8ad 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h @@ -3,7 +3,7 @@ * @brief ZGM23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h index e6788915b9..f1cd282d82 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h index a486638abd..641c839ecf 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h @@ -3,7 +3,7 @@ * @brief ZGM23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h index 1c6318d93d..2379272f70 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h @@ -3,7 +3,7 @@ * @brief ZGM23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h index d1cd486b73..49f2eb0b58 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h @@ -3,7 +3,7 @@ * @brief ZGM23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h index ca5cf053f2..2a8abc2728 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h index db18c496a6..65ff0f9ce5 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h @@ -3,7 +3,7 @@ * @brief ZGM23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h index 734d243a70..3ec657362d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h @@ -3,7 +3,7 @@ * @brief ZGM23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h index 8fa841ea32..464491cfee 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h @@ -3,7 +3,7 @@ * @brief ZGM23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h index ef501f37e7..98803e1d06 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h @@ -3,7 +3,7 @@ * @brief ZGM23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h index 25d2013c03..82875384d6 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h @@ -3,7 +3,7 @@ * @brief ZGM23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h index 4a30d4166d..990c40d826 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h @@ -3,7 +3,7 @@ * @brief ZGM23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h index a67826c83c..070a2e0edf 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h @@ -3,7 +3,7 @@ * @brief ZGM23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h index 356dfdf92b..c05f4cc4cf 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h @@ -3,7 +3,7 @@ * @brief ZGM23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h index 4b96d2e236..ebb1fa22a2 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief ZGM23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h index 0d0c176a33..93ede357d1 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h @@ -3,16 +3,28 @@ * @brief ZGM23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef ZGM23_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h index 051da2e97f..d00ca80182 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h @@ -3,7 +3,7 @@ * @brief ZGM23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h index e89711ad29..3aa5fc7797 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h @@ -3,7 +3,7 @@ * @brief ZGM23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h index 22776b494f..32983373e2 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h index 7a10deb80f..0ea2cc738b 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h @@ -3,7 +3,7 @@ * @brief ZGM23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h index 5b26c3e9c1..2a78940e79 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h @@ -3,7 +3,7 @@ * @brief ZGM23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h index 8fb7a35017..8098a10c0b 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h @@ -3,7 +3,7 @@ * @brief ZGM23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h index d0e80ba7ba..10c1e9daf8 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h @@ -3,7 +3,7 @@ * @brief ZGM23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h index cc7bcb0452..35132b8ea8 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h @@ -3,7 +3,7 @@ * @brief ZGM23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h index 49e8d0c91c..cd1ff840fd 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief ZGM23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h index 135ea39058..def930dd78 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h @@ -3,7 +3,7 @@ * @brief ZGM23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h index 3baef47881..3eb3c22a12 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h @@ -3,16 +3,28 @@ * @brief ZGM23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ #ifndef ZGM23_PRS_SIGNALS_H diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h index 5ccff6b24a..cef3c0c4d6 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h @@ -3,7 +3,7 @@ * @brief ZGM23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h index dfded1d15c..b99119a375 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h @@ -3,7 +3,7 @@ * @brief ZGM23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h index 6029f4e86a..5d99b70b9e 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h @@ -3,7 +3,7 @@ * @brief ZGM23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h index 877f4803ee..82af41bdf7 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h @@ -3,7 +3,7 @@ * @brief ZGM23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h index 6eaade9f2a..3482d2c7ed 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h @@ -3,7 +3,7 @@ * @brief ZGM23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h index a5be763bb6..6dcd8f6b8f 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h @@ -3,7 +3,7 @@ * @brief ZGM23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h index 9a8bae86e2..40de74692b 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h index c130a1a94e..017f58e9ff 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h @@ -3,7 +3,7 @@ * @brief ZGM23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h index 410d5af921..39038d3e35 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h @@ -3,7 +3,7 @@ * @brief ZGM23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h index dfa557ebd1..0adf5bdd3d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h @@ -3,7 +3,7 @@ * @brief ZGM23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Source/startup_zgm23.c b/platform/Device/SiliconLabs/ZGM23/Source/startup_zgm23.c index 44fdbbbfc2..0fe9ec5c7d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Source/startup_zgm23.c +++ b/platform/Device/SiliconLabs/ZGM23/Source/startup_zgm23.c @@ -4,17 +4,6 @@ * Device ZGM23 * @version V2.1.0 * @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. diff --git a/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c b/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c index 17a0b72890..589cb937a1 100644 --- a/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c +++ b/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for ZGM23 devices. ****************************************************************************** * # License - * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/component/bgm260pb22vna.slcc b/platform/Device/component/bgm260pb22vna.slcc new file mode 100644 index 0000000000..556ef989d5 --- /dev/null +++ b/platform/Device/component/bgm260pb22vna.slcc @@ -0,0 +1,284 @@ +!!omap +- id: BGM260PB22VNA +- package: platform +- description: Silicon Labs CMSIS-Device part headers for BGM260PB22VNA. +- category: Platform|Device|BGM26 +- quality: production +- define: + - name: BGM260PB22VNA + unless: + - device_content_override + - name: SL_CODE_COMPONENT_SYSTEM + unless: + - device_content_override + value: system +- source: + - path: platform/Device/SiliconLabs/BGM26/Source/startup_bgm26.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/BGM26/Source/system_bgm26.c + unless: + - device_content_override +- include: + - file_list: + - path: bgm260pb22vna.h + - path: bgm26_acmp.h + - path: bgm26_aes.h + - path: bgm26_amuxcp.h + - path: bgm26_buram.h + - path: bgm26_burtc.h + - path: bgm26_cmu.h + - path: bgm26_dcdc.h + - path: bgm26_devinfo.h + - path: bgm26_dma_descriptor.h + - path: bgm26_dpll.h + - path: bgm26_emu.h + - path: bgm26_eusart.h + - path: bgm26_fsrco.h + - path: bgm26_gpcrc.h + - path: bgm26_gpio.h + - path: bgm26_gpio_port.h + - path: bgm26_hfrco.h + - path: bgm26_hfxo.h + - path: bgm26_i2c.h + - path: bgm26_iadc.h + - path: bgm26_icache.h + - path: bgm26_keyscan.h + - path: bgm26_lcd.h + - path: bgm26_lcdrf.h + - path: bgm26_ldma.h + - path: bgm26_ldmaxbar.h + - path: bgm26_ldmaxbar_defines.h + - path: bgm26_letimer.h + - path: bgm26_lfrco.h + - path: bgm26_lfxo.h + - path: bgm26_mailbox.h + - path: bgm26_mpahbram.h + - path: bgm26_msc.h + - path: bgm26_pcnt.h + - path: bgm26_prs.h + - path: bgm26_prs_signals.h + - path: bgm26_semailbox.h + - path: bgm26_smu.h + - path: bgm26_syscfg.h + - path: bgm26_sysrtc.h + - path: bgm26_timer.h + - path: bgm26_ulfrco.h + - path: bgm26_usart.h + - path: bgm26_vdac.h + - path: bgm26_wdog.h + - path: em_device.h + - path: system_bgm26.h + path: platform/Device/SiliconLabs/BGM26/Include/ + unless: + - device_content_override +- provides: + - name: bgm260pb22vna + - name: device + - name: device_efx + - name: device_series_2 + - name: device_sdid_225 + - name: device_generic_family_efr32xg26 + - name: device_family_bgm26 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_is_module + - name: hardware_board_has_hfxo_freq_40mhz + - name: hardware_board_has_hfxo + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_10dbm + - name: device_pa_0dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dmem0 + - name: device_has_dmem1 + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_eusart2 + - name: device_has_eusart3 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_i2c2 + - name: device_has_i2c3 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_lcd + - name: device_has_lcdrf + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_timer5 + - name: device_has_timer6 + - name: device_has_timer7 + - name: device_has_timer8 + - name: device_has_timer9 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_usart1 + - name: device_has_usart2 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_vdac1 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_2g4hz + - name: device_supports_rail + - name: device_no_rail_api + - name: device_supports_bluetooth + - name: device_supports_bluetooth_iq_sampling + - name: device_supports_bluetooth_antenna_switching + - name: device_supports_bluetooth_coded_phy + - name: device_supports_bluetooth_cte + - name: device_supports_connect + - name: device_compute_basic +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core + - name: code_classification + - name: component_catalog + - name: BGM260PB22VNA_config +- template_contribution: + - name: device_opn + value: BGM260PB22VNA + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: bgm26 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 3276800 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 524288 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_a + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_b + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_c + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_d + - name: code_classification_components + value: system +- tag: + - device:opn:bgm260pb22vna +- toolchain_settings: + - option: device_opn + value: bgm260pb22vna + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/225/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 3276800 + start: 134217728 + type: non-volatile + - name: RAM + size: 524288 + start: 536870912 + type: volatile + opn: bgm260pb22vna + sbom: + license: Zlib diff --git a/platform/Device/component/bgm260pb32vna.slcc b/platform/Device/component/bgm260pb32vna.slcc new file mode 100644 index 0000000000..ce99e84ab3 --- /dev/null +++ b/platform/Device/component/bgm260pb32vna.slcc @@ -0,0 +1,283 @@ +!!omap +- id: BGM260PB32VNA +- package: platform +- description: Silicon Labs CMSIS-Device part headers for BGM260PB32VNA. +- category: Platform|Device|BGM26 +- quality: production +- define: + - name: BGM260PB32VNA + unless: + - device_content_override + - name: SL_CODE_COMPONENT_SYSTEM + unless: + - device_content_override + value: system +- source: + - path: platform/Device/SiliconLabs/BGM26/Source/startup_bgm26.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/BGM26/Source/system_bgm26.c + unless: + - device_content_override +- include: + - file_list: + - path: bgm260pb32vna.h + - path: bgm26_acmp.h + - path: bgm26_aes.h + - path: bgm26_amuxcp.h + - path: bgm26_buram.h + - path: bgm26_burtc.h + - path: bgm26_cmu.h + - path: bgm26_dcdc.h + - path: bgm26_devinfo.h + - path: bgm26_dma_descriptor.h + - path: bgm26_dpll.h + - path: bgm26_emu.h + - path: bgm26_eusart.h + - path: bgm26_fsrco.h + - path: bgm26_gpcrc.h + - path: bgm26_gpio.h + - path: bgm26_gpio_port.h + - path: bgm26_hfrco.h + - path: bgm26_hfxo.h + - path: bgm26_i2c.h + - path: bgm26_iadc.h + - path: bgm26_icache.h + - path: bgm26_keyscan.h + - path: bgm26_lcd.h + - path: bgm26_lcdrf.h + - path: bgm26_ldma.h + - path: bgm26_ldmaxbar.h + - path: bgm26_ldmaxbar_defines.h + - path: bgm26_letimer.h + - path: bgm26_lfrco.h + - path: bgm26_lfxo.h + - path: bgm26_mailbox.h + - path: bgm26_mpahbram.h + - path: bgm26_msc.h + - path: bgm26_pcnt.h + - path: bgm26_prs.h + - path: bgm26_prs_signals.h + - path: bgm26_semailbox.h + - path: bgm26_smu.h + - path: bgm26_syscfg.h + - path: bgm26_sysrtc.h + - path: bgm26_timer.h + - path: bgm26_ulfrco.h + - path: bgm26_usart.h + - path: bgm26_vdac.h + - path: bgm26_wdog.h + - path: em_device.h + - path: system_bgm26.h + path: platform/Device/SiliconLabs/BGM26/Include/ + unless: + - device_content_override +- provides: + - name: bgm260pb32vna + - name: device + - name: device_efx + - name: device_series_2 + - name: device_sdid_225 + - name: device_generic_family_efr32xg26 + - name: device_family_bgm26 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_is_module + - name: hardware_board_has_hfxo_freq_40mhz + - name: hardware_board_has_hfxo + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_20dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dmem0 + - name: device_has_dmem1 + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_eusart2 + - name: device_has_eusart3 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_i2c2 + - name: device_has_i2c3 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_lcd + - name: device_has_lcdrf + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_timer5 + - name: device_has_timer6 + - name: device_has_timer7 + - name: device_has_timer8 + - name: device_has_timer9 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_usart1 + - name: device_has_usart2 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_vdac1 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_2g4hz + - name: device_supports_rail + - name: device_no_rail_api + - name: device_supports_bluetooth + - name: device_supports_bluetooth_iq_sampling + - name: device_supports_bluetooth_antenna_switching + - name: device_supports_bluetooth_coded_phy + - name: device_supports_bluetooth_cte + - name: device_supports_connect + - name: device_compute_basic +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core + - name: code_classification + - name: component_catalog + - name: BGM260PB32VNA_config +- template_contribution: + - name: device_opn + value: BGM260PB32VNA + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: bgm26 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 3276800 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 524288 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_a + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_b + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_c + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_d + - name: code_classification_components + value: system +- tag: + - device:opn:bgm260pb32vna +- toolchain_settings: + - option: device_opn + value: bgm260pb32vna + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/225/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 3276800 + start: 134217728 + type: non-volatile + - name: RAM + size: 524288 + start: 536870912 + type: volatile + opn: bgm260pb32vna + sbom: + license: Zlib diff --git a/platform/Device/component/mgm260pb22vna.slcc b/platform/Device/component/mgm260pb22vna.slcc index f9e76c99dd..db3f11e921 100644 --- a/platform/Device/component/mgm260pb22vna.slcc +++ b/platform/Device/component/mgm260pb22vna.slcc @@ -3,7 +3,7 @@ - package: platform - description: Silicon Labs CMSIS-Device part headers for MGM260PB22VNA. - category: Platform|Device|MGM26 -- quality: evaluation +- quality: production - define: - name: MGM260PB22VNA unless: @@ -56,7 +56,6 @@ - path: mgm26_mailbox.h - path: mgm26_mpahbram.h - path: mgm26_msc.h - - path: mgm26_mvp.h - path: mgm26_pcnt.h - path: mgm26_prs.h - path: mgm26_prs_signals.h @@ -143,7 +142,6 @@ - name: device_has_lfrco - name: device_has_lfxo - name: device_has_msc - - name: device_has_mvp - name: device_has_pcnt - name: device_has_pcnt0 - name: device_has_prs @@ -192,7 +190,7 @@ - name: device_supports_bluetooth_coded_phy - name: device_supports_bluetooth_cte - name: device_supports_connect - - name: device_compute_mvp + - name: device_compute_basic - recommends: - id: trustzone_unaware - requires: diff --git a/platform/Device/component/mgm260pb32vna.slcc b/platform/Device/component/mgm260pb32vna.slcc index 5dac0ef7bd..5045463dfd 100644 --- a/platform/Device/component/mgm260pb32vna.slcc +++ b/platform/Device/component/mgm260pb32vna.slcc @@ -3,7 +3,7 @@ - package: platform - description: Silicon Labs CMSIS-Device part headers for MGM260PB32VNA. - category: Platform|Device|MGM26 -- quality: evaluation +- quality: production - define: - name: MGM260PB32VNA unless: @@ -56,7 +56,6 @@ - path: mgm26_mailbox.h - path: mgm26_mpahbram.h - path: mgm26_msc.h - - path: mgm26_mvp.h - path: mgm26_pcnt.h - path: mgm26_prs.h - path: mgm26_prs_signals.h @@ -142,7 +141,6 @@ - name: device_has_lfrco - name: device_has_lfxo - name: device_has_msc - - name: device_has_mvp - name: device_has_pcnt - name: device_has_pcnt0 - name: device_has_prs @@ -191,7 +189,7 @@ - name: device_supports_bluetooth_coded_phy - name: device_supports_bluetooth_cte - name: device_supports_connect - - name: device_compute_mvp + - name: device_compute_basic - recommends: - id: trustzone_unaware - requires: diff --git a/platform/Device/component/mgm260pb32vnn.slcc b/platform/Device/component/mgm260pb32vnn.slcc index 5ccfedd94c..5481ad7470 100644 --- a/platform/Device/component/mgm260pb32vnn.slcc +++ b/platform/Device/component/mgm260pb32vnn.slcc @@ -3,7 +3,7 @@ - package: platform - description: Silicon Labs CMSIS-Device part headers for MGM260PB32VNN. - category: Platform|Device|MGM26 -- quality: evaluation +- quality: production - define: - name: MGM260PB32VNN unless: @@ -56,7 +56,6 @@ - path: mgm26_mailbox.h - path: mgm26_mpahbram.h - path: mgm26_msc.h - - path: mgm26_mvp.h - path: mgm26_pcnt.h - path: mgm26_prs.h - path: mgm26_prs_signals.h @@ -142,7 +141,6 @@ - name: device_has_lfrco - name: device_has_lfxo - name: device_has_msc - - name: device_has_mvp - name: device_has_pcnt - name: device_has_pcnt0 - name: device_has_prs @@ -191,7 +189,7 @@ - name: device_supports_bluetooth_coded_phy - name: device_supports_bluetooth_cte - name: device_supports_connect - - name: device_compute_mvp + - name: device_compute_basic - recommends: - id: trustzone_unaware - requires: diff --git a/platform/Device/component/mgm260pd22vna.slcc b/platform/Device/component/mgm260pd22vna.slcc new file mode 100644 index 0000000000..2a7c4b5a55 --- /dev/null +++ b/platform/Device/component/mgm260pd22vna.slcc @@ -0,0 +1,288 @@ +!!omap +- id: MGM260PD22VNA +- package: platform +- description: Silicon Labs CMSIS-Device part headers for MGM260PD22VNA. +- category: Platform|Device|MGM26 +- quality: production +- define: + - name: MGM260PD22VNA + unless: + - device_content_override + - name: SL_CODE_COMPONENT_SYSTEM + unless: + - device_content_override + value: system +- source: + - path: platform/Device/SiliconLabs/MGM26/Source/startup_mgm26.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/MGM26/Source/system_mgm26.c + unless: + - device_content_override +- include: + - file_list: + - path: mgm260pd22vna.h + - path: em_device.h + - path: mgm26_acmp.h + - path: mgm26_aes.h + - path: mgm26_amuxcp.h + - path: mgm26_buram.h + - path: mgm26_burtc.h + - path: mgm26_cmu.h + - path: mgm26_dcdc.h + - path: mgm26_devinfo.h + - path: mgm26_dma_descriptor.h + - path: mgm26_dpll.h + - path: mgm26_emu.h + - path: mgm26_eusart.h + - path: mgm26_fsrco.h + - path: mgm26_gpcrc.h + - path: mgm26_gpio.h + - path: mgm26_gpio_port.h + - path: mgm26_hfrco.h + - path: mgm26_hfxo.h + - path: mgm26_i2c.h + - path: mgm26_iadc.h + - path: mgm26_icache.h + - path: mgm26_keyscan.h + - path: mgm26_lcd.h + - path: mgm26_lcdrf.h + - path: mgm26_ldma.h + - path: mgm26_ldmaxbar.h + - path: mgm26_ldmaxbar_defines.h + - path: mgm26_letimer.h + - path: mgm26_lfrco.h + - path: mgm26_lfxo.h + - path: mgm26_mailbox.h + - path: mgm26_mpahbram.h + - path: mgm26_msc.h + - path: mgm26_mvp.h + - path: mgm26_pcnt.h + - path: mgm26_prs.h + - path: mgm26_prs_signals.h + - path: mgm26_semailbox.h + - path: mgm26_smu.h + - path: mgm26_syscfg.h + - path: mgm26_sysrtc.h + - path: mgm26_timer.h + - path: mgm26_ulfrco.h + - path: mgm26_usart.h + - path: mgm26_vdac.h + - path: mgm26_wdog.h + - path: system_mgm26.h + path: platform/Device/SiliconLabs/MGM26/Include/ + unless: + - device_content_override +- provides: + - name: mgm260pd22vna + - name: device + - name: device_efx + - name: device_series_2 + - name: device_sdid_225 + - name: device_generic_family_efr32xg26 + - name: device_family_mgm26 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_is_module + - name: hardware_board_has_hfxo_freq_40mhz + - name: hardware_board_has_hfxo + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_10dbm + - name: device_pa_0dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dmem0 + - name: device_has_dmem1 + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_eusart2 + - name: device_has_eusart3 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_i2c2 + - name: device_has_i2c3 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_lcd + - name: device_has_lcdrf + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_mvp + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_timer5 + - name: device_has_timer6 + - name: device_has_timer7 + - name: device_has_timer8 + - name: device_has_timer9 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_usart1 + - name: device_has_usart2 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_vdac1 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_2g4hz + - name: device_supports_rail + - name: device_supports_rail_stack + - name: device_supports_zigbee + - name: device_supports_thread + - name: device_supports_bluetooth + - name: device_supports_bluetooth_iq_sampling + - name: device_supports_bluetooth_antenna_switching + - name: device_supports_bluetooth_coded_phy + - name: device_supports_bluetooth_cte + - name: device_supports_connect + - name: device_compute_mvp +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core + - name: code_classification + - name: component_catalog + - name: MGM260PD22VNA_config +- template_contribution: + - name: device_opn + value: MGM260PD22VNA + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: mgm26 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 3276800 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 524288 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_a + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_b + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_c + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_d + - name: code_classification_components + value: system +- tag: + - device:opn:mgm260pd22vna +- toolchain_settings: + - option: device_opn + value: mgm260pd22vna + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/225/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 3276800 + start: 134217728 + type: non-volatile + - name: RAM + size: 524288 + start: 536870912 + type: volatile + opn: mgm260pd22vna + sbom: + license: Zlib diff --git a/platform/Device/component/mgm260pd32vna.slcc b/platform/Device/component/mgm260pd32vna.slcc new file mode 100644 index 0000000000..c0681e1a1e --- /dev/null +++ b/platform/Device/component/mgm260pd32vna.slcc @@ -0,0 +1,287 @@ +!!omap +- id: MGM260PD32VNA +- package: platform +- description: Silicon Labs CMSIS-Device part headers for MGM260PD32VNA. +- category: Platform|Device|MGM26 +- quality: production +- define: + - name: MGM260PD32VNA + unless: + - device_content_override + - name: SL_CODE_COMPONENT_SYSTEM + unless: + - device_content_override + value: system +- source: + - path: platform/Device/SiliconLabs/MGM26/Source/startup_mgm26.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/MGM26/Source/system_mgm26.c + unless: + - device_content_override +- include: + - file_list: + - path: mgm260pd32vna.h + - path: em_device.h + - path: mgm26_acmp.h + - path: mgm26_aes.h + - path: mgm26_amuxcp.h + - path: mgm26_buram.h + - path: mgm26_burtc.h + - path: mgm26_cmu.h + - path: mgm26_dcdc.h + - path: mgm26_devinfo.h + - path: mgm26_dma_descriptor.h + - path: mgm26_dpll.h + - path: mgm26_emu.h + - path: mgm26_eusart.h + - path: mgm26_fsrco.h + - path: mgm26_gpcrc.h + - path: mgm26_gpio.h + - path: mgm26_gpio_port.h + - path: mgm26_hfrco.h + - path: mgm26_hfxo.h + - path: mgm26_i2c.h + - path: mgm26_iadc.h + - path: mgm26_icache.h + - path: mgm26_keyscan.h + - path: mgm26_lcd.h + - path: mgm26_lcdrf.h + - path: mgm26_ldma.h + - path: mgm26_ldmaxbar.h + - path: mgm26_ldmaxbar_defines.h + - path: mgm26_letimer.h + - path: mgm26_lfrco.h + - path: mgm26_lfxo.h + - path: mgm26_mailbox.h + - path: mgm26_mpahbram.h + - path: mgm26_msc.h + - path: mgm26_mvp.h + - path: mgm26_pcnt.h + - path: mgm26_prs.h + - path: mgm26_prs_signals.h + - path: mgm26_semailbox.h + - path: mgm26_smu.h + - path: mgm26_syscfg.h + - path: mgm26_sysrtc.h + - path: mgm26_timer.h + - path: mgm26_ulfrco.h + - path: mgm26_usart.h + - path: mgm26_vdac.h + - path: mgm26_wdog.h + - path: system_mgm26.h + path: platform/Device/SiliconLabs/MGM26/Include/ + unless: + - device_content_override +- provides: + - name: mgm260pd32vna + - name: device + - name: device_efx + - name: device_series_2 + - name: device_sdid_225 + - name: device_generic_family_efr32xg26 + - name: device_family_mgm26 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_is_module + - name: hardware_board_has_hfxo_freq_40mhz + - name: hardware_board_has_hfxo + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_20dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dmem0 + - name: device_has_dmem1 + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_eusart2 + - name: device_has_eusart3 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_i2c2 + - name: device_has_i2c3 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_lcd + - name: device_has_lcdrf + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_mvp + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_timer5 + - name: device_has_timer6 + - name: device_has_timer7 + - name: device_has_timer8 + - name: device_has_timer9 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_usart1 + - name: device_has_usart2 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_vdac1 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_2g4hz + - name: device_supports_rail + - name: device_supports_rail_stack + - name: device_supports_zigbee + - name: device_supports_thread + - name: device_supports_bluetooth + - name: device_supports_bluetooth_iq_sampling + - name: device_supports_bluetooth_antenna_switching + - name: device_supports_bluetooth_coded_phy + - name: device_supports_bluetooth_cte + - name: device_supports_connect + - name: device_compute_mvp +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core + - name: code_classification + - name: component_catalog + - name: MGM260PD32VNA_config +- template_contribution: + - name: device_opn + value: MGM260PD32VNA + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: mgm26 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 3276800 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 524288 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_a + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_b + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_c + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_d + - name: code_classification_components + value: system +- tag: + - device:opn:mgm260pd32vna +- toolchain_settings: + - option: device_opn + value: mgm260pd32vna + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/225/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 3276800 + start: 134217728 + type: non-volatile + - name: RAM + size: 524288 + start: 536870912 + type: volatile + opn: mgm260pd32vna + sbom: + license: Zlib diff --git a/platform/Device/component/mgm260pd32vnn.slcc b/platform/Device/component/mgm260pd32vnn.slcc new file mode 100644 index 0000000000..ae16d5a892 --- /dev/null +++ b/platform/Device/component/mgm260pd32vnn.slcc @@ -0,0 +1,287 @@ +!!omap +- id: MGM260PD32VNN +- package: platform +- description: Silicon Labs CMSIS-Device part headers for MGM260PD32VNN. +- category: Platform|Device|MGM26 +- quality: production +- define: + - name: MGM260PD32VNN + unless: + - device_content_override + - name: SL_CODE_COMPONENT_SYSTEM + unless: + - device_content_override + value: system +- source: + - path: platform/Device/SiliconLabs/MGM26/Source/startup_mgm26.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/MGM26/Source/system_mgm26.c + unless: + - device_content_override +- include: + - file_list: + - path: mgm260pd32vnn.h + - path: em_device.h + - path: mgm26_acmp.h + - path: mgm26_aes.h + - path: mgm26_amuxcp.h + - path: mgm26_buram.h + - path: mgm26_burtc.h + - path: mgm26_cmu.h + - path: mgm26_dcdc.h + - path: mgm26_devinfo.h + - path: mgm26_dma_descriptor.h + - path: mgm26_dpll.h + - path: mgm26_emu.h + - path: mgm26_eusart.h + - path: mgm26_fsrco.h + - path: mgm26_gpcrc.h + - path: mgm26_gpio.h + - path: mgm26_gpio_port.h + - path: mgm26_hfrco.h + - path: mgm26_hfxo.h + - path: mgm26_i2c.h + - path: mgm26_iadc.h + - path: mgm26_icache.h + - path: mgm26_keyscan.h + - path: mgm26_lcd.h + - path: mgm26_lcdrf.h + - path: mgm26_ldma.h + - path: mgm26_ldmaxbar.h + - path: mgm26_ldmaxbar_defines.h + - path: mgm26_letimer.h + - path: mgm26_lfrco.h + - path: mgm26_lfxo.h + - path: mgm26_mailbox.h + - path: mgm26_mpahbram.h + - path: mgm26_msc.h + - path: mgm26_mvp.h + - path: mgm26_pcnt.h + - path: mgm26_prs.h + - path: mgm26_prs_signals.h + - path: mgm26_semailbox.h + - path: mgm26_smu.h + - path: mgm26_syscfg.h + - path: mgm26_sysrtc.h + - path: mgm26_timer.h + - path: mgm26_ulfrco.h + - path: mgm26_usart.h + - path: mgm26_vdac.h + - path: mgm26_wdog.h + - path: system_mgm26.h + path: platform/Device/SiliconLabs/MGM26/Include/ + unless: + - device_content_override +- provides: + - name: mgm260pd32vnn + - name: device + - name: device_efx + - name: device_series_2 + - name: device_sdid_225 + - name: device_generic_family_efr32xg26 + - name: device_family_mgm26 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_is_module + - name: hardware_board_has_hfxo_freq_40mhz + - name: hardware_board_has_hfxo + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_20dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dmem0 + - name: device_has_dmem1 + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_eusart2 + - name: device_has_eusart3 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_i2c2 + - name: device_has_i2c3 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_lcd + - name: device_has_lcdrf + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_mvp + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_timer5 + - name: device_has_timer6 + - name: device_has_timer7 + - name: device_has_timer8 + - name: device_has_timer9 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_usart1 + - name: device_has_usart2 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_vdac1 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_2g4hz + - name: device_supports_rail + - name: device_supports_rail_stack + - name: device_supports_zigbee + - name: device_supports_thread + - name: device_supports_bluetooth + - name: device_supports_bluetooth_iq_sampling + - name: device_supports_bluetooth_antenna_switching + - name: device_supports_bluetooth_coded_phy + - name: device_supports_bluetooth_cte + - name: device_supports_connect + - name: device_compute_mvp +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core + - name: code_classification + - name: component_catalog + - name: MGM260PD32VNN_config +- template_contribution: + - name: device_opn + value: MGM260PD32VNN + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: mgm26 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 3276800 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 524288 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_a + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_b + - name: device_gpio_port_pin_info + value: + count: '10' + mask: '0x03FF' + name: gpio_port_c + - name: device_gpio_port_pin_info + value: + count: '6' + mask: '0x003F' + name: gpio_port_d + - name: code_classification_components + value: system +- tag: + - device:opn:mgm260pd32vnn +- toolchain_settings: + - option: device_opn + value: mgm260pd32vnn + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/225/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 3276800 + start: 134217728 + type: non-volatile + - name: RAM + size: 524288 + start: 536870912 + type: volatile + opn: mgm260pd32vnn + sbom: + license: Zlib diff --git a/platform/bootloader/api/btl_interface.c b/platform/bootloader/api/btl_interface.c index 054222d256..97e0302c05 100644 --- a/platform/bootloader/api/btl_interface.c +++ b/platform/bootloader/api/btl_interface.c @@ -421,7 +421,7 @@ bool bootloader_getUpgradeLocation(uint32_t *location) uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) >> BOOTLOADER_VERSION_MINOR_SHIFT); - if (blMajorVersion == 2UL && blMinorVersion >= 1UL) { + if (blMajorVersion > 2UL || (blMajorVersion == 2UL && blMinorVersion >= 1UL)) { *location = mainBootloaderTable->getUpgradeLocation(); return true; } diff --git a/platform/bootloader/api/btl_interface_storage.c b/platform/bootloader/api/btl_interface_storage.c index 259ca09f6a..16ee57a43e 100644 --- a/platform/bootloader/api/btl_interface_storage.c +++ b/platform/bootloader/api/btl_interface_storage.c @@ -16,6 +16,8 @@ ******************************************************************************/ #include "btl_interface.h" +#include "btl_internal_flash.h" +#include // ----------------------------------------------------------------------------- // Defines @@ -38,6 +40,36 @@ static Bootloader_PPUSATDnCLKENnState_t blPPUSATDnCLKENnState = { 0 }; // ----------------------------------------------------------------------------- // Functions +static bool verifyAddressRange(uint32_t address, + uint32_t length) +{ + // Flash starts at FLASH_BASE, and is FLASH_SIZE large + if ((length > FLASH_SIZE) +#if (FLASH_BASE > 0x0UL) + || (address < FLASH_BASE) +#endif + || (address > FLASH_BASE + FLASH_SIZE)) { + return false; + } + + if ((address + length) <= FLASH_BASE + FLASH_SIZE) { + return true; + } else { + return false; + } +} + +static bool verifyErased(uint32_t address, + uint32_t length) +{ + for (uint32_t i = 0; i < length; i += 4) { + if (*(uint32_t *)(address + i) != 0xFFFFFFFF) { + return false; + } + } + return true; +} + void bootloader_getStorageInfo(BootloaderStorageInformation_t *info) { if (!bootloader_pointerValid(mainBootloaderTable) @@ -70,20 +102,53 @@ int32_t bootloader_readStorage(uint32_t slotId, uint8_t *buffer, size_t length) { - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; + int32_t retVal; + BootloaderStorageInformation_t storageInfo; + BootloaderStorageSlot_t storageSlot; + + //Check for the storageType of the device + bootloader_getStorageInfo(&storageInfo); + + if (storageInfo.storageType == INTERNAL_FLASH) { + // Ensure slot is valid + if (slotId >= storageInfo.numStorageSlots) { + return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT; + } + + retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + + // Ensure address is within slot + if ((offset + length > storageSlot.length) \ + || (offset > storageSlot.length) \ + || (length > storageSlot.length)) { + return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + + // Address range is valid; read data + retVal = bootloader_readRawStorage(storageSlot.address + offset, + buffer, + length); } + //END OF INTERNAL_FLASH + else { + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - int32_t retVal = mainBootloaderTable->storage->read(slotId, offset, buffer, length); + retVal = mainBootloaderTable->storage->read(slotId, offset, buffer, length); -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); + #endif + } return retVal; } @@ -93,20 +158,50 @@ int32_t bootloader_writeStorage(uint32_t slotId, uint8_t *buffer, size_t length) { - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } + int32_t retVal; + BootloaderStorageInformation_t storageInfo; + BootloaderStorageSlot_t storageSlot; -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + //Check for the storageType of the device + bootloader_getStorageInfo(&storageInfo); - int32_t retVal = mainBootloaderTable->storage->write(slotId, offset, buffer, length); + if (storageInfo.storageType == INTERNAL_FLASH) { + // Ensure slot is valid + if (slotId >= storageInfo.numStorageSlots) { + return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT; + } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + + // Ensure address is within slot + if ((offset + length > storageSlot.length) \ + || (offset > storageSlot.length) \ + || (length > storageSlot.length)) { + return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + + retVal = bootloader_writeRawStorage(storageSlot.address + offset, + buffer, + length); + } else { + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + retVal = mainBootloaderTable->storage->write(slotId, offset, buffer, length); + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + } return retVal; } @@ -200,20 +295,41 @@ int32_t bootloader_eraseWriteStorage(uint32_t slotId, int32_t bootloader_eraseStorageSlot(uint32_t slotId) { - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } + int32_t retVal; + BootloaderStorageInformation_t storageInfo; + BootloaderStorageSlot_t storageSlot; -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + //Check for the storageType of the device + bootloader_getStorageInfo(&storageInfo); - int32_t retVal = mainBootloaderTable->storage->erase(slotId); + if (storageInfo.storageType == INTERNAL_FLASH) { + // Ensure slot is valid + if (slotId >= storageInfo.numStorageSlots) { + return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT; + } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + + retVal = bootloader_eraseRawStorage(storageSlot.address, storageSlot.length); + } else { + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + retVal = mainBootloaderTable->storage->erase(slotId); + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + } return retVal; } @@ -486,19 +602,36 @@ int32_t bootloader_readRawStorage(uint32_t address, uint8_t *buffer, size_t length) { - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + int32_t retVal; + BootloaderStorageInformation_t storageInfo; - int32_t retVal = mainBootloaderTable->storage->readRaw(address, buffer, length); + //Check for the storageType of the device + bootloader_getStorageInfo(&storageInfo); -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + if (storageInfo.storageType == INTERNAL_FLASH) { + // Ensure address is is within flash + if (!verifyAddressRange(address, length)) { + return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + + memcpy(buffer, (void *)address, length); + + retVal = BOOTLOADER_OK; + } else { + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + retVal = mainBootloaderTable->storage->readRaw(address, buffer, length); + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + } return retVal; } @@ -507,20 +640,44 @@ int32_t bootloader_writeRawStorage(uint32_t address, uint8_t *buffer, size_t length) { - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } + int32_t retVal; + BootloaderStorageInformation_t storageInfo; -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + //Check for the storageType of the device + bootloader_getStorageInfo(&storageInfo); - int32_t retVal = mainBootloaderTable->storage->writeRaw(address, buffer, length); + if (storageInfo.storageType == INTERNAL_FLASH) { + // Ensure address is is within chip + if (!verifyAddressRange(address, length)) { + return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + // Ensure space is empty + if (!verifyErased(address, length)) { + return BOOTLOADER_ERROR_STORAGE_NEEDS_ERASE; + } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + if (flash_writeBuffer(address, buffer, length)) { + retVal = BOOTLOADER_OK; + } else { + retVal = BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + //END OF INTERNAL FLASH + } else { + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + retVal = mainBootloaderTable->storage->writeRaw(address, buffer, length); + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + } return retVal; } @@ -554,23 +711,59 @@ int32_t bootloader_getAllocatedDMAChannel(void) int32_t bootloader_eraseRawStorage(uint32_t address, size_t length) { - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } + int32_t retVal; + BootloaderStorageInformation_t storageInfo; -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + //Check for the storageType of the device + bootloader_getStorageInfo(&storageInfo); - int32_t retVal = mainBootloaderTable->storage->eraseRaw(address, length); + if (storageInfo.storageType == INTERNAL_FLASH) { + // Ensure erase covers an integer number of pages + if (length % FLASH_PAGE_SIZE) { + return BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN; + } + // Ensure erase is page aligned + if (address % FLASH_PAGE_SIZE) { + return BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN; + } + // Ensure address is is within flash + if (!verifyAddressRange(address, length)) { + return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + bool ret = false; + + do { + ret = flash_erasePage(address); + address += FLASH_PAGE_SIZE; + length -= FLASH_PAGE_SIZE; + } while (length > 0 && ret); + + if (ret) { + retVal = BOOTLOADER_OK; + } else { + retVal = BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + } else { + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + retVal = mainBootloaderTable->storage->eraseRaw(address, length); + + #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); + #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + } return retVal; } + #if defined(__GNUC__) #pragma GCC diagnostic pop #endif diff --git a/platform/bootloader/bootloader_production_demos.xml b/platform/bootloader/bootloader_production_demos.xml index 20c63304aa..7ced3012dc 100644 --- a/platform/bootloader/bootloader_production_demos.xml +++ b/platform/bootloader/bootloader_production_demos.xml @@ -6,7 +6,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -28,7 +28,7 @@ - + @@ -39,7 +39,7 @@ - + @@ -50,7 +50,7 @@ - + @@ -61,7 +61,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -116,7 +116,7 @@ - + @@ -127,7 +127,7 @@ - + @@ -138,7 +138,7 @@ - + @@ -149,7 +149,7 @@ - + @@ -160,7 +160,7 @@ - + @@ -171,7 +171,7 @@ - + @@ -182,7 +182,7 @@ - + @@ -193,7 +193,7 @@ - + @@ -204,7 +204,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -226,7 +226,7 @@ - + @@ -237,7 +237,7 @@ - + @@ -248,7 +248,7 @@ - + @@ -259,7 +259,7 @@ - + @@ -270,7 +270,7 @@ - + @@ -281,7 +281,7 @@ - + diff --git a/platform/bootloader/bootloader_production_templates.xml b/platform/bootloader/bootloader_production_templates.xml index 3e8001379a..344716aad9 100644 --- a/platform/bootloader/bootloader_production_templates.xml +++ b/platform/bootloader/bootloader_production_templates.xml @@ -6,7 +6,7 @@ - + @@ -22,7 +22,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -54,7 +54,7 @@ - + @@ -70,7 +70,7 @@ - + @@ -85,7 +85,7 @@ - + @@ -100,7 +100,7 @@ - + @@ -115,7 +115,7 @@ - + @@ -130,7 +130,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -160,7 +160,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -190,7 +190,7 @@ - + @@ -205,7 +205,7 @@ - + @@ -220,7 +220,7 @@ - + @@ -235,7 +235,7 @@ - + @@ -250,7 +250,7 @@ - + @@ -265,7 +265,7 @@ - + @@ -280,7 +280,7 @@ - + @@ -295,7 +295,7 @@ - + @@ -310,7 +310,7 @@ - + diff --git a/platform/bootloader/component/bootloader_interface_s2.slcc b/platform/bootloader/component/bootloader_interface_s2.slcc index cc0cf331c9..c08f95ceda 100644 --- a/platform/bootloader/component/bootloader_interface_s2.slcc +++ b/platform/bootloader/component/bootloader_interface_s2.slcc @@ -16,8 +16,12 @@ source: condition: [trustzone_secure] - path: platform/bootloader/api/btl_interface_ns.c condition: [trustzone_nonsecure] + - path: platform/bootloader/core/flash/btl_internal_flash.c + include: - - path: platform/bootloader + - path: platform/bootloader + file_list: + - path: core/btl_util.h - path: platform/bootloader/api file_list: - path: application_properties.h @@ -26,6 +30,9 @@ include: - path: btl_interface_parser.h - path: btl_interface_storage.h - path: btl_reset_info.h + - path: platform/bootloader/core/flash/ + file_list: + - path: btl_internal_flash.h provides: - name: bootloader_interface_common condition: [device_series_2] @@ -107,8 +114,7 @@ template_contribution: - name: bootloader_size value: 73728 condition: [apploader] - unless: [trustzone_secure, trustzone_nonsecure] - + unless: [trustzone_secure, trustzone_nonsecure] documentation: docset: mcu-bootloader document: group-Interface diff --git a/platform/bootloader/component/scripts/bootloader_storage_validation.lua b/platform/bootloader/component/scripts/bootloader_storage_validation.lua index 650943dde8..33ecf3025c 100644 --- a/platform/bootloader/component/scripts/bootloader_storage_validation.lua +++ b/platform/bootloader/component/scripts/bootloader_storage_validation.lua @@ -35,12 +35,12 @@ if (not slc.is_selected("bootloader_spiflash_storage")) and (not slc.is_selected do -- Check alignment for all enabled slots if isSlotEnabled[slotID] == "1" then - if tonumber(slotStartAddress[slotID],10) % flash_page_size ~= 0 then + if tonumber(slotStartAddress[slotID]) % flash_page_size ~= 0 then validation.warning('Slot '.. tostring(tonumber(slotID-1)) .. " is not page aligned. Try aligning the slot start address to a " .. tostring(flash_page_size) .. "bytes boundary", validation.target_for_project()) end - if tonumber(slotSizes[slotID],10) % flash_page_size ~= 0 then + if tonumber(slotSizes[slotID]) % flash_page_size ~= 0 then validation.warning('Slot size for slot '.. tostring(tonumber(slotID-1)) .. " is not page aligned. Try aligning the slot size to a " .. tostring(flash_page_size) .. "bytes boundary", validation.target_for_project()) @@ -55,15 +55,15 @@ if slot_overlap.value == "0" then if (slot0_enable.value == "1") and (slot1_enable.value == "1") then -- slot 0 and slot 1 are enabled -- Conditions to detect potential overlaps b/w slot0 and slot1 - if tonumber(slot1_start_addr.value,10) == tonumber(slot0_start_addr.value,10) then + if tonumber(slot1_start_addr.value) == tonumber(slot0_start_addr.value) then validation.error('Overlap detected between slot0 and slot1', validation.target_for_project()) end - if (tonumber(slot1_start_addr.value,10) > (tonumber(slot0_start_addr.value,10))) and ((tonumber(slot0_start_addr.value,10) + tonumber(slot0_size.value,10)) > tonumber(slot1_start_addr.value,10)) then + if (tonumber(slot1_start_addr.value) > (tonumber(slot0_start_addr.value))) and ((tonumber(slot0_start_addr.value) + tonumber(slot0_size.value)) > tonumber(slot1_start_addr.value)) then validation.error('Overlap detected between storage slot 0 and slot 1',validation.target_for_project()) end - if ((tonumber(slot0_start_addr.value,10)) > (tonumber(slot1_start_addr.value,10))) and ((tonumber(slot1_start_addr.value,10) + tonumber(slot1_size.value,10)) > tonumber(slot0_start_addr.value,10)) then + if ((tonumber(slot0_start_addr.value)) > (tonumber(slot1_start_addr.value))) and ((tonumber(slot1_start_addr.value) + tonumber(slot1_size.value)) > tonumber(slot0_start_addr.value)) then validation.error('Overlap detected between storage slot 0 and slot 1',validation.target_for_project()) end end @@ -71,28 +71,28 @@ if slot_overlap.value == "0" then if slot0_enable.value == "1" and slot1_enable.value == "1" and slot2_enable.value == "1" then -- slot 0,slot 1 and slot 2 are enabled -- Conditions to detect potential overlaps b/w slot1 and slot2 - if tonumber(slot1_start_addr.value,10) == tonumber(slot2_start_addr.value,10) then + if tonumber(slot1_start_addr.value) == tonumber(slot2_start_addr.value) then validation.error('Overlap detected between storage slot 1 and slot 2',validation.target_for_project()) end - if ((tonumber(slot2_start_addr.value,10)) > (tonumber(slot1_start_addr.value,10))) and ((tonumber(slot1_start_addr.value,10) + tonumber(slot1_size.value,10)) > tonumber(slot2_start_addr.value,10)) then + if ((tonumber(slot2_start_addr.value)) > (tonumber(slot1_start_addr.value))) and ((tonumber(slot1_start_addr.value) + tonumber(slot1_size.value)) > tonumber(slot2_start_addr.value)) then validation.error('Overlap detected between storage slot 1 and slot 2',validation.target_for_project()) end - if ((tonumber(slot1_start_addr.value,10)) > (tonumber(slot2_start_addr.value,10))) and ((tonumber(slot2_start_addr.value,10) + tonumber(slot2_size.value,10)) > tonumber(slot1_start_addr.value,10)) then + if ((tonumber(slot1_start_addr.value)) > (tonumber(slot2_start_addr.value))) and ((tonumber(slot2_start_addr.value) + tonumber(slot2_size.value)) > tonumber(slot1_start_addr.value)) then validation.error('Overlap detected between storage slot 1 and slot 2',validation.target_for_project()) end -- Conditions to detect potential overlaps b/w slot0 and slot2 - if tonumber(slot0_start_addr.value,10) == tonumber(slot2_start_addr.value,10) then + if tonumber(slot0_start_addr.value) == tonumber(slot2_start_addr.value) then validation.error('Overlap detected between storage slot 0 and slot 2',validation.target_for_project()) end - if ((tonumber(slot2_start_addr.value,10)) > (tonumber(slot0_start_addr.value,10))) and ((tonumber(slot0_start_addr.value,10) + tonumber(slot0_size.value,10)) > tonumber(slot2_start_addr.value,10)) then + if ((tonumber(slot2_start_addr.value)) > (tonumber(slot0_start_addr.value))) and ((tonumber(slot0_start_addr.value) + tonumber(slot0_size.value)) > tonumber(slot2_start_addr.value)) then validation.error('Overlap detected between storage slot 0 and slot 2',validation.target_for_project()) end - if ((tonumber(slot0_start_addr.value,10)) > (tonumber(slot2_start_addr.value,10))) and ((tonumber(slot2_start_addr.value,10) + tonumber(slot2_size.value,10)) > tonumber(slot0_start_addr.value,10)) then + if ((tonumber(slot0_start_addr.value)) > (tonumber(slot2_start_addr.value))) and ((tonumber(slot2_start_addr.value) + tonumber(slot2_size.value)) > tonumber(slot0_start_addr.value)) then validation.error('Overlap detected between storage slot 0 and slot 2',validation.target_for_project()) end end diff --git a/platform/bootloader/config/btl_config.h b/platform/bootloader/config/btl_config.h index 2cd5cf06c3..847dfb66b1 100644 --- a/platform/bootloader/config/btl_config.h +++ b/platform/bootloader/config/btl_config.h @@ -41,7 +41,7 @@ MISRAC_ENABLE #endif #ifndef BOOTLOADER_VERSION_MAIN_CUSTOMER -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 #endif #define BOOTLOADER_VERSION_MAIN (BOOTLOADER_VERSION_MAIN_MAJOR << 24 \ diff --git a/platform/bootloader/config/device_sdid_205/apploader/btl_core_cfg.h b/platform/bootloader/config/device_sdid_205/apploader/btl_core_cfg.h index 6a956620b0..df88d592be 100644 --- a/platform/bootloader/config/device_sdid_205/apploader/btl_core_cfg.h +++ b/platform/bootloader/config/device_sdid_205/apploader/btl_core_cfg.h @@ -103,7 +103,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/device_sdid_205/apploader/btl_core_s_cfg.h b/platform/bootloader/config/device_sdid_205/apploader/btl_core_s_cfg.h index 87ef7a2f47..9176b41972 100644 --- a/platform/bootloader/config/device_sdid_205/apploader/btl_core_s_cfg.h +++ b/platform/bootloader/config/device_sdid_205/apploader/btl_core_s_cfg.h @@ -93,7 +93,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/device_sdid_205/btl_core_cfg.h b/platform/bootloader/config/device_sdid_205/btl_core_cfg.h index 75850f1798..d11c411f4a 100644 --- a/platform/bootloader/config/device_sdid_205/btl_core_cfg.h +++ b/platform/bootloader/config/device_sdid_205/btl_core_cfg.h @@ -114,7 +114,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/device_sdid_205/btl_core_s_cfg.h b/platform/bootloader/config/device_sdid_205/btl_core_s_cfg.h index 59e6d91c49..389994e86d 100644 --- a/platform/bootloader/config/device_sdid_205/btl_core_s_cfg.h +++ b/platform/bootloader/config/device_sdid_205/btl_core_s_cfg.h @@ -93,7 +93,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/device_series_2/apploader/btl_core_cfg.h b/platform/bootloader/config/device_series_2/apploader/btl_core_cfg.h index 58590c6e59..0803776055 100644 --- a/platform/bootloader/config/device_series_2/apploader/btl_core_cfg.h +++ b/platform/bootloader/config/device_series_2/apploader/btl_core_cfg.h @@ -103,7 +103,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/device_series_2/apploader/btl_core_s_cfg.h b/platform/bootloader/config/device_series_2/apploader/btl_core_s_cfg.h index d591d663eb..1c1af3994d 100644 --- a/platform/bootloader/config/device_series_2/apploader/btl_core_s_cfg.h +++ b/platform/bootloader/config/device_series_2/apploader/btl_core_s_cfg.h @@ -98,7 +98,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/device_series_2/btl_core_cfg.h b/platform/bootloader/config/device_series_2/btl_core_cfg.h index c60b190aca..1d898da56d 100644 --- a/platform/bootloader/config/device_series_2/btl_core_cfg.h +++ b/platform/bootloader/config/device_series_2/btl_core_cfg.h @@ -114,7 +114,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/device_series_2/btl_core_s_cfg.h b/platform/bootloader/config/device_series_2/btl_core_s_cfg.h index db07bff633..3bec97fb6f 100644 --- a/platform/bootloader/config/device_series_2/btl_core_s_cfg.h +++ b/platform/bootloader/config/device_series_2/btl_core_s_cfg.h @@ -98,7 +98,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 #define USE_CUSTOM_APP_SIZE 0 diff --git a/platform/bootloader/parser/delta_dfu/lib/gcc/cortex-m33/lib/libddfu-patch.a b/platform/bootloader/parser/delta_dfu/lib/gcc/cortex-m33/lib/libddfu-patch.a index 5318db709a..1cec45a9d3 100644 --- a/platform/bootloader/parser/delta_dfu/lib/gcc/cortex-m33/lib/libddfu-patch.a +++ b/platform/bootloader/parser/delta_dfu/lib/gcc/cortex-m33/lib/libddfu-patch.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:42c6f6c015817c0d8415927f3ece3d4a049e6a640e2a5fe7f73f29e9bcbe134c +oid sha256:a8db66e7e5d09f736078d0582e7835f261c1f7e48f2bc72fd978ce0455a49207 size 4692 diff --git a/platform/bootloader/parser/delta_dfu/lib/iar/cortex-m33/lib/libddfu-patch.a b/platform/bootloader/parser/delta_dfu/lib/iar/cortex-m33/lib/libddfu-patch.a index 4a333e040a..cbff20c47a 100644 --- a/platform/bootloader/parser/delta_dfu/lib/iar/cortex-m33/lib/libddfu-patch.a +++ b/platform/bootloader/parser/delta_dfu/lib/iar/cortex-m33/lib/libddfu-patch.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e88d439e066214103925aec6b910b0b616ba30da4b13f6a428300495b7b018ff +oid sha256:47b711db4a70a99c2aee874d59be6f6762906722d30d5cdb4fce021ba3b3d5b2 size 15228 diff --git a/platform/common/inc/sl_platform_version.h b/platform/common/inc/sl_platform_version.h index bc24389436..88611c9ccc 100644 --- a/platform/common/inc/sl_platform_version.h +++ b/platform/common/inc/sl_platform_version.h @@ -32,7 +32,7 @@ #define SL_PLATFORM_MAJOR_VERSION 5 #define SL_PLATFORM_MINOR_VERSION 1 -#define SL_PLATFORM_PATCH_VERSION 0 +#define SL_PLATFORM_PATCH_VERSION 1 #define SL_PLATFORM_VERSION ((SL_PLATFORM_MAJOR_VERSION << 8) \ | (SL_PLATFORM_MINOR_VERSION << 4) \ diff --git a/platform/common/toolchain/cortexm/gcc/s30/linkerfile.ld.jinja b/platform/common/toolchain/cortexm/gcc/s30/linkerfile.ld.jinja index af53fa8cdf..910b86e213 100644 --- a/platform/common/toolchain/cortexm/gcc/s30/linkerfile.ld.jinja +++ b/platform/common/toolchain/cortexm/gcc/s30/linkerfile.ld.jinja @@ -73,18 +73,64 @@ {%- endif %} {%- endif %} -{% if axip_region0_flash_size_overhead is defined %} -{%- set flash_size = flash_size - axip_region0_flash_size_overhead | sum %} -{%- if memory_flash_size is defined %} - {%- set memory_flash_size = memory_flash_size - axip_region0_flash_size_overhead | sum %} +{#- + Code Region 0 is usually the bootloader region. The default logical size is 32kb. +#} +{%- if axip_region0_enabled is defined %} + {%- if code_region0_size is defined %} + {%- set logical_code_region0_size = code_region0_size | first %} + {%- else %} + {%- set logical_code_region0_size = 32768 %} + {%- endif %} + {%- set logical_code_region0_size = ((logical_code_region0_size // 32768) * 32768) %} + + {#- + With AXiP enabled, every 8 logical pages effectively uses 9 physical pages. + #} + {%- set physical_code_region0_size = ((9 * logical_code_region0_size) // 8) %} + {%- set region0_axip_overhead = physical_code_region0_size - logical_code_region0_size %} {%- endif %} + +{#- + Code Region 1 is usually the app region. The default logical size depends on + the part's flash size. Those default sizes are defined in the lookup table below. +#} +{%- if axip_region1_enabled is defined %} + {%- if code_region1_size is defined %} + {%- set logical_code_region1_size = code_region1_size | first %} + {%- else %} + + {#- + Code Region 1 size's look-up table. + #} + {%- if (flash_size == 1900544) %} {#- 2MB #} + {%- set logical_code_region1_size = 884736 %} + {%- elif (flash_size == 2949120) %} {#- 3MB #} + {%- set logical_code_region1_size = 1441792 %} + {%- elif (flash_size == 3997696) %} {#- 4MB #} + {%- set logical_code_region1_size = 2031616 %} + {%- else %} + {%- set logical_code_region1_size = 2031616 %} + {%- endif %} + + {%- endif %} + {%- set logical_code_region1_size = ((logical_code_region1_size // 32768) * 32768) %} + + {#- + With AXiP enabled, every 8 logical pages effectively uses 9 physical pages. + #} + {%- set physical_code_region1_size = ((9 * logical_code_region1_size) // 8) %} + {%- set region1_axip_overhead = physical_code_region1_size - logical_code_region1_size %} {%- endif %} -{% if axip_region1_flash_size_overhead is defined %} -{%- set flash_size = flash_size - axip_region1_flash_size_overhead | sum %} -{%- if memory_flash_size is defined %} - {%- set memory_flash_size = memory_flash_size - axip_region1_flash_size_overhead | sum %} +{#- + Reduce the available flash size taking the Code Regions' AXiP overhead into account. +#} +{%- if region0_axip_overhead is defined %} + {%- set flash_size = flash_size - region0_axip_overhead %} {%- endif %} +{%- if region1_axip_overhead is defined %} + {%- set flash_size = flash_size - region1_axip_overhead %} {%- endif %} {#- @@ -137,6 +183,11 @@ {%- endif %} {%- endif %} +{%- if static_tokens_enable is defined %} + {%- set flash_lockbits_size = lockbits_size | first %} + {%- set app_flash_size = app_flash_size - flash_lockbits_size %} +{%- endif %} + {% if tz_non_secure_execution is defined %} {%- set app_flash_start_offset = app_flash_start - flash_addr %} {#- @@ -154,6 +205,13 @@ {%- set app_flash_size = app_flash_size - secure_app_flash_size %} {%- endif %} +{% if matter_certificate_store is defined %} + {#- + Currently matter certificates are stored at manufacturing time in the last flash page. + #} + {%- set app_flash_size = app_flash_size - flash_page_size %} +{%- endif %} + {%- set rtt = 0 %} {%- if linker_rtt_section is defined %} {%- set rtt = 1 %} diff --git a/platform/common/toolchain/cortexm/iar/s30/linkerfile.icf.jinja b/platform/common/toolchain/cortexm/iar/s30/linkerfile.icf.jinja index 6466d979bd..0d050993b3 100644 --- a/platform/common/toolchain/cortexm/iar/s30/linkerfile.icf.jinja +++ b/platform/common/toolchain/cortexm/iar/s30/linkerfile.icf.jinja @@ -43,6 +43,66 @@ {%- endif %} {%- endif %} +{#- + Code Region 0 is usually the bootloader region. The default logical size is 32kb. +#} +{%- if axip_region0_enabled is defined %} + {%- if code_region0_size is defined %} + {%- set logical_code_region0_size = code_region0_size | first %} + {%- else %} + {%- set logical_code_region0_size = 32768 %} + {%- endif %} + {%- set logical_code_region0_size = ((logical_code_region0_size // 32768) * 32768) %} + + {#- + With AXiP enabled, every 8 logical pages effectively uses 9 physical pages. + #} + {%- set physical_code_region0_size = ((9 * logical_code_region0_size) // 8) %} + {%- set region0_axip_overhead = physical_code_region0_size - logical_code_region0_size %} +{%- endif %} + +{#- + Code Region 1 is usually the app region. The default logical size depends on + the part's flash size. Those default sizes are defined in the lookup table below. +#} +{%- if axip_region1_enabled is defined %} + {%- if code_region1_size is defined %} + {%- set logical_code_region1_size = code_region1_size | first %} + {%- else %} + + {#- + Code Region 1 size's look-up table. + #} + {%- if (flash_size == 1900544) %} {#- 2MB #} + {%- set logical_code_region1_size = 884736 %} + {%- elif (flash_size == 2949120) %} {#- 3MB #} + {%- set logical_code_region1_size = 1441792 %} + {%- elif (flash_size == 3997696) %} {#- 4MB #} + {%- set logical_code_region1_size = 2031616 %} + {%- else %} + {%- set logical_code_region1_size = 2031616 %} + {%- endif %} + + {%- endif %} + {%- set logical_code_region1_size = ((logical_code_region1_size // 32768) * 32768) %} + + {#- + With AXiP enabled, every 8 logical pages effectively uses 9 physical pages. + #} + {%- set physical_code_region1_size = ((9 * logical_code_region1_size) // 8) %} + {%- set region1_axip_overhead = physical_code_region1_size - logical_code_region1_size %} +{%- endif %} + +{#- + Reduce the available flash size taking the Code Regions' AXiP overhead into account. +#} +{%- if region0_axip_overhead is defined %} + {%- set flash_size = flash_size - region0_axip_overhead %} +{%- endif %} +{%- if region1_axip_overhead is defined %} + {%- set flash_size = flash_size - region1_axip_overhead %} +{%- endif %} + {#- Application specific sizes. Here we start to calculate the application view of the physical memory. @@ -101,6 +161,18 @@ {%- set app_flash_size = app_flash_size - secure_app_flash_size %} {%- endif %} +{%- if static_tokens_enable is defined %} + {%- set flash_lockbits_size = lockbits_size | first %} + {%- set app_flash_size = app_flash_size - flash_lockbits_size %} +{%- endif %} + +{% if matter_certificate_store is defined %} + {#- + Currently matter certificates are stored at manufacturing time in the last flash page. + #} + {%- set app_flash_size = app_flash_size - flash_page_size %} +{%- endif %} + /*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ diff --git a/platform/common/toolchain/toolchains.slct b/platform/common/toolchain/toolchains.slct index dc4d4f5dfc..9487fbefd3 100644 --- a/platform/common/toolchain/toolchains.slct +++ b/platform/common/toolchain/toolchains.slct @@ -190,27 +190,13 @@ exporter: disabled: [] cmse: enabled: - - tool: makefile.arm.gcc.compiler - option: misc - action: append - value: "-mcmse" - - tool: com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.compiler.base - option: com.silabs.gnu.c.compiler.option.misc.otherlist - action: append - value: "-mcmse" - - tool: com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base - option: com.silabs.gnu.cpp.compiler.option.misc.otherlist - action: append - value: "-mcmse" - - tool: iar.ewp.arm.compiler - option: IExtraOptions - action: append - value: "--cmse" - - tool: iar.arm.toolchain.compiler.v5.4.1 - option: iar.arm.toolchain.compiler.option.additionalUserOptions - action: append - value: "--cmse" - disabled: [] + - tool: compiler + option: secure_code + value: true + disabled: + - tool: compiler + option: secure_code + value: false nano_c_libs: enabled: - tool: makefile.arm.gcc.compiler diff --git a/platform/documentation/release-highlights.txt b/platform/documentation/release-highlights.txt index b8c8b606e8..0d5fc8d292 100644 --- a/platform/documentation/release-highlights.txt +++ b/platform/documentation/release-highlights.txt @@ -1,15 +1,12 @@ -Platform 5.1.0 +Platform 5.1.1 - CMSIS Device - - Added support for new EFR32xG27 OPN, EFR32xG26 OPN's, Module OPN's(MGM260PB22VNA2,MGM260PB32VNA2,MGM260PB32VNN2) + - Added support for xGM260 modules - CPC - - Experimental support of NETLINK-SDIO interface on the SiWx917m platform + - Fixed a potential security vulnerability. - Security - - Mbed TLS upgraded to latest version 3.6.2 + - Targeted quality improvements and bug fixes. - Boards and External Devices - - Added support for board OPN's BRD2709A, BRD2711A, BRD4350A, BRD4351A, BRD4412A, BRD4413A. -- RAIL 5.1.0 - - Added support for Bluetooth Low Energy (BLE) Channel Sounding (CS) on the EFR32xG24. - This feature enables accurate distance measurement between two devices when used with the Silicon Labs BLE stack and distance measurement libraries. - - Added support for Concurrent listening feature on the EFR32xG26 part. - - Added support for 1 Mbps and 2 Mbps custom 802.15.4 SUN PHYs on the EFR32xG26 part. + - Added support for BRD2505A, BRD2713A, BRD4120A, BRD4121A, BRD4402C, BRD4403C +- RAIL 5.1.1 + - Added support for the xGM260P modules diff --git a/platform/driver/pwm/src/sl_pwm.c b/platform/driver/pwm/src/sl_pwm.c index babab2d2f4..9ff32d70fb 100644 --- a/platform/driver/pwm/src/sl_pwm.c +++ b/platform/driver/pwm/src/sl_pwm.c @@ -322,7 +322,7 @@ uint8_t sl_pwm_get_duty_cycle(sl_pwm_instance_t *pwm) uint32_t compare = TIMER_CaptureGet(pwm->timer, pwm->channel); #else uint32_t top = sl_hal_timer_get_top(pwm->timer); - uint32_t compare = sl_hal_timer_channel_get_capture(pwm->timer, pwm->channel); + uint32_t compare = sl_hal_timer_channel_get_compare(pwm->timer, pwm->channel); #endif uint8_t percent = (uint8_t)((compare * 100) / top); diff --git a/platform/emdrv/component/nvm3_crypto_se.slcc b/platform/emdrv/component/nvm3_crypto_se.slcc new file mode 100644 index 0000000000..bee3107e1e --- /dev/null +++ b/platform/emdrv/component/nvm3_crypto_se.slcc @@ -0,0 +1,23 @@ +id: nvm3_crypto_se +label: NVM3 HAL for SE crypto +package: platform +description: > + NVM3 crypto HAL for crypto HW on SE subsystem. +category: Services|NVM3 +quality: production +metadata: + sbom: + license: Zlib +source: + - path: platform/emdrv/nvm3/src/nvm3_hal_crypto_se.c + unless: [trustzone_nonsecure] +include: + - path: platform/emdrv/nvm3/inc + file_list: + - path: nvm3_hal_crypto.h + - path: nvm3_hal_crypto_handle.h + unless: [trustzone_nonsecure] +provides: + - name: nvm3_crypto_se +requires: + - name: se_manager diff --git a/platform/emdrv/component/nvm3_default.slcc b/platform/emdrv/component/nvm3_default.slcc index ad523d10d8..39ef0c2b32 100644 --- a/platform/emdrv/component/nvm3_default.slcc +++ b/platform/emdrv/component/nvm3_default.slcc @@ -39,7 +39,7 @@ template_contribution: event: platform_init include: nvm3_default.h handler: nvm3_initDefault - priority: 9999 + priority: 9998 condition: [device_efx] unless: [trustzone_secure] documentation: diff --git a/platform/emdrv/component/nvm3_optimization_enable.slcc b/platform/emdrv/component/nvm3_optimization_enable.slcc index 9eac6bfa6b..e61b75a114 100644 --- a/platform/emdrv/component/nvm3_optimization_enable.slcc +++ b/platform/emdrv/component/nvm3_optimization_enable.slcc @@ -2,7 +2,7 @@ id: nvm3_optimization_enable label: NVM3 enable optimization package: platform description: > - Enabling this component improves the NVM3 init time and object lookup time. + This component improves the NVM3 initialization and object lookup time. Code size increases ~1248 bytes with NVM3 optimization enabled. category: Services|NVM3 quality: production diff --git a/platform/emdrv/component/nvm3_secure.slcc b/platform/emdrv/component/nvm3_secure.slcc new file mode 100644 index 0000000000..8e84226347 --- /dev/null +++ b/platform/emdrv/component/nvm3_secure.slcc @@ -0,0 +1,16 @@ +id: nvm3_secure +label: NVM3 enable security +package: platform +description: > + The NVM3 secure component enables secure reads/writes for the NVM3 data. +category: Services|NVM3 +quality: production +metadata: + sbom: + license: Zlib +define: + - name: NVM3_SECURITY +provides: + - name: nvm3_secure +requires: + - name: nvm3_crypto_se diff --git a/platform/emdrv/component/nvm3_source.slcc b/platform/emdrv/component/nvm3_source.slcc index cba2660e56..6969d5d54f 100644 --- a/platform/emdrv/component/nvm3_source.slcc +++ b/platform/emdrv/component/nvm3_source.slcc @@ -81,6 +81,8 @@ requires: condition: [device_efx] - name: "nvm3_optimization" condition: [device_efx] + - name: "nvm3_secure" + condition: [device_series_3] recommends: - id: "nvm3_optimization_disable" condition: [device_series_2] diff --git a/platform/emdrv/nvm3/inc/nvm3_generic.h b/platform/emdrv/nvm3/inc/nvm3_generic.h index cbc9450f4b..ca9ce913ec 100644 --- a/platform/emdrv/nvm3/inc/nvm3_generic.h +++ b/platform/emdrv/nvm3/inc/nvm3_generic.h @@ -87,7 +87,7 @@ extern "C" { /***************************************************************************//** * @brief Definitions of NVM3 constraints. ******************************************************************************/ -#define NVM3_MIN_PAGE_SIZE 512U ///< The minimum page size supported +#define NVM3_MIN_PAGE_SIZE 4096U ///< The minimum page size supported #define NVM3_MAX_OBJECT_SIZE_LOW_LIMIT 204U ///< The minimum value for the maximum object size #define NVM3_MAX_OBJECT_SIZE_HIGH_LIMIT 4096U ///< The maximum value for the maximum object size #define NVM3_MAX_OBJECT_SIZE_DEFAULT 1900U ///< The default value for the maximum object size @@ -762,11 +762,16 @@ __STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) found by searching the NVM. The search will start at the last stored object and search all the way to the oldest object. If the object is found, the cache is updated accordingly. + NVM3 Optimization improves the NVM3 initialization and object lookup time. + Code size increases ~1248 bytes with NVM3 Optimization enabled. NVM3 driver provides + a means to enable or disable Optimization from Simplicity Studio UC. The application must allocate and support data for the cache. See the @ref nvm3_open function for more details. The size of each cache element is one uint32_t and one pointer giving a total of 8 bytes (2 words) - pr. entry for EFM32 and EFR32 devices. + per entry for EFM32 and EFR32 devices. With Optimization enabled, the size of each + cache element is two uint32_t and one pointer giving a total of 12 bytes (3 words) + per entry. @note The cache is fully initialized by @ref nvm3_open() and automatically updated by any subsequent write, read, or delete function call. @@ -791,11 +796,12 @@ __STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) for IAR and ARM GCC. The maximum stack usage measured was 420 bytes for IAR, and 472 bytes for ARM GCC builds. The unit test used to validate the stack usage has a 10% margin and uses a stack limit of 462 bytes for IAR - and 520 for ARM GCC. The maximum stack usage measured was 715 bytes for ARM - GCC builds with security. The unit test used to validate the stack usage has - a 10% margin and uses a stack limit of 794 bytes for ARM GCC with security. - Note that the actual stack usage is a little different on the Cortex - M0 Plus, M3, M4, and M33 with NVM3 source. + and 520 bytes for ARM GCC. The maximum stack usage measured on SIXX device was + 540 bytes for IAR, and 520 bytes for ARM GCC builds with security. The unit + test used to validate the stack usage has a 10% margin and uses a stack + limit of 600 bytes for IAR and 576 bytes for ARM GCC builds with security. + Note that the actual stack usage is a little different on the Cortex M4 and M33 + with NVM3 source. # The API {#nvm3_api} The NVM3 API is defined in the nvm3.h file. The application code @@ -860,7 +866,7 @@ __STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) -# NVM area size must be a multiple of the page size. The minimum required NVM size is dependent on both the NVM page size and the - NVM3_MAX_OBJECT_SIZE value. For a device with 2 kB page size and typical + NVM3_MAX_OBJECT_SIZE value. For a device with 4 kB page size and typical values for NVM3_MAX_OBJECT_SIZE, the following is the minimum required number of pages: - For NVM3_MAX_OBJECT_SIZE=208: 3 pages @@ -943,21 +949,28 @@ __STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) @n The "driver" for external Flash is selected by setting the halHandle in the nvm3_open initialization structure to point to nvm3_halFlashHandle. - @n All data objects are authenticated + encrypted using AES-GCM mode and - counter objects are stored in plain. NVM3 encryption key is stored in SE - MTP region. Reading the external memory alone will not give access to the - unencrypted data objects. + # Securing Objects in External Flash {#nvm3_support_secure_storage} + All data objects are authenticated + encrypted using AES-GCM mode and + counter objects are stored in plain. Each data object which is securely stored + in external flash has a size overhead of 8 bytes. NVM3 uses device generated key + for crypto operations. Reading the external memory directly (without using NVM3) + will not give access to the unencrypted data objects. @n HAL for crypto is added to have the flexibility to use available crypto which can be selected by setting the halCryptoHandle in the nvm3_open initialization structure to point to desired crypto handle. + @n NVM3 crypto key will be changed if "device erase" is triggered on a debug + locked part, which will also clean up the NVM3 from the memory. In this case, + if previously stored NVM3 data is reloaded to the same device, NVM3 data read + will fail as NVM3 crypto key has changed. + # NVM3 Source code {#nvm3_source_code} - The NVM3 source code can be compiled for Cortex M0, M3, M4, and M33 with either - Arm GCC or IAR toolchains. In addition, the NVM3 driver provides a means to - securely store and retrieve the objects in external Flash using authenticated - encryption. Objects in internal Flash need not be encrypted, while objects - in external Flash must always be encrypted. + The NVM3 source code can be compiled for Cortex M4 and M33 with either ARM GCC + or IAR toolchains. In addition, the NVM3 driver provides a means to securely + store and retrieve the objects in external Flash using authenticated encryption. + Objects in internal Flash need not be encrypted, while objects in external Flash + must always be encrypted. # Storage Capacity {#nvm3_capacity} Basic storage is defined as the size of on instance of all objects, including @@ -972,15 +985,6 @@ __STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) with enough flash pages to put the maximum allowed basic storage significantly higher than the actual basic storage. - ## Max Allowed Basic Storage with 8 kB page size - | Flash pages | Total size (bytes) | Max allowed basic storage (bytes) | | | | - |-------------------------------|--------------------------------------|-----------------------------------------|-------------------------------------|--------------------------------------|--------------------------------------| - | | | Max object size = 204 bytes | Max object size = 254 bytes | Max object size = 1900 bytes | Max object size = 4096 bytes | - | 3 | 24516 | 7748 | 7648 | 4356 | 0 | - | 4 | 32688 | 15920 | 15820 | 12528 | 8136 | - | 5 | 40860 | 24092 | 23992 | 20700 | 16308 | - | 6 | 49032 | 32264 | 32164 | 28872 | 24480 | - ## Max Allowed Basic Storage with 4 kB page size | Flash pages | Total size (bytes) | Max allowed basic storage (bytes) | | | | |-------------------------------|--------------------------------------|-----------------------------------------|-------------------------------------|--------------------------------------|--------------------------------------| @@ -994,6 +998,15 @@ __STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) | 9 | 36684 | 28108 | 28008 | 24716 | 20324 | | 10 | 40760 | 32184 | 32084 | 28792 | 24400 | +## Max Allowed Basic Storage with 8 kB page size + | Flash pages | Total size (bytes) | Max allowed basic storage (bytes) | | | | + |-------------------------------|--------------------------------------|-----------------------------------------|-------------------------------------|--------------------------------------|--------------------------------------| + | | | Max object size = 204 bytes | Max object size = 254 bytes | Max object size = 1900 bytes | Max object size = 4096 bytes | + | 3 | 24516 | 7748 | 7648 | 4356 | 0 | + | 4 | 32688 | 15920 | 15820 | 12528 | 8136 | + | 5 | 40860 | 24092 | 23992 | 20700 | 16308 | + | 6 | 49032 | 32264 | 32164 | 28872 | 24480 | + # Default Instance {#nvm3_default} Several NVM3 instances can be created on a device and live independently of each other, but to save memory, it is usually desirable to use only one NVM3 instance as each diff --git a/platform/emdrv/nvm3/inc/nvm3_hal_crypto.h b/platform/emdrv/nvm3/inc/nvm3_hal_crypto.h new file mode 100644 index 0000000000..bf08d7e3f7 --- /dev/null +++ b/platform/emdrv/nvm3/inc/nvm3_hal_crypto.h @@ -0,0 +1,208 @@ +/***************************************************************************//** + * @file + * @brief Crypto HAL for NVM3 driver + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_HAL_CRYPTO_H +#define NVM3_HAL_CRYPTO_H + +#include "sl_status.h" + +#ifdef NVM3_HOST_BUILD +#include "nvm3_hal_host.h" +#else +#include "sl_assert.h" +#include "sl_common.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup nvm3halcrypto NVM3 HAL CRYPTO + * @brief NVM3 Crypto Hardware Abstraction Layer + * @{ + * @details + * This module provides the interface to the NVM. By having all NVM access + * functions in a separate file, it is possible to support different hardware + * by substituting the functions in this module. + * + * @note These functions are used by the NVM3 and should not be used by + * any applications. + ******************************************************************************/ + +/****************************************************************************** + ****************************** MACROS ********************************** + *****************************************************************************/ + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#define nvm3_halCryptoInit(halCrypto) ((halCrypto)->init()) +#define nvm3_halCryptoGenRandNum(halCrypto, a, b) ((halCrypto)->genRandNum((a), (b))) +#define nvm3_halCryptoEncrypt(halCrypto, a, b, c, d, e, f, g, h) ((halCrypto)->encrypt((a), (b), (c), (d), (e), (f), (g), (h))) +#define nvm3_halCryptoDecrypt(halCrypto, a, b, c, d, e, f, g, h) ((halCrypto)->decrypt((a), (b), (c), (d), (e), (f), (g), (h))) + +/// @endcond + +/****************************************************************************** + ****************************** TYPEDEFS ********************************** + *****************************************************************************/ + +typedef enum { + NVM3_HAL_CRYPTO_ALGO_NONE = 0, + NVM3_HAL_CRYPTO_ALGO_AEAD = 1, + NVM3_HAL_CRYPTO_ALGO_ENC = 2 +} nvm3_halCryptoAlgo_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Init the NVM3 HAL Crypto for usage. + * + * @details + * This function must be run at initialization, before any other functions + * are called. It is used to initialize the crypto before any crypto + * functionality can be accessed. + * + * @return + * The result of the crypto init call. + * @ref SL_STATUS_OK on success or a NVM3 @ref sl_status_t on failure. + ******************************************************************************/ +typedef sl_status_t (*nvm3_HalCryptoInit_t)(void); + +/***************************************************************************//** + * @brief + * This function is used to generate random number. + * + * @param[in] outputSize + * The length of the random number to be generated in number of bytes. + * + * @param[out] output + * A pointer to the random number generated. + * + * @return + * The result of the random number generator operation. + * @ref SL_STATUS_OK on success or a NVM3 @ref sl_status_t on failure. + ******************************************************************************/ +typedef sl_status_t (*nvm3_HalCryptoGenRandNum_t)(uint8_t *output, size_t outputSize); + +/***************************************************************************//** + * @brief + * This function is used to perform encryption/authenticated encryption on + * NVM data. + * + * @param[in] nonce + * A pointer to the nonce value. + * + * @param[in] aad + * A pointer to the additional data to authenticate. + * + * @param[in] aadLen + * The length of the additional data to authenticate in number of bytes. + * + * @param[in] plainData + * A pointer to plain data to encrypt. + * + * @param[in] plainDataLen + * The length of the plain data in number of bytes. + * + * @param[out] cipherData + * A pointer to encrypted data. + * + * @param[out] tag + * A pointer to the tag. + * + * @param[in] cryptoAlgo + * Crypto algorithm to use. + * + * @return + * The result of the encryption operation. + * @ref SL_STATUS_OK on success or a NVM3 @ref sl_status_t on failure. + ******************************************************************************/ +typedef sl_status_t (*nvm3_HalCryptoEncrypt_t)(const uint8_t *nonce, const uint8_t *aad, size_t aadLen, const uint8_t *plainData, size_t plainDataLen, uint8_t *cipherData, uint8_t *tag, nvm3_halCryptoAlgo_t cryptoAlgo); + +/***************************************************************************//** + * @brief + * This function is used to perform decryption/authenticated decryption + * of NVM data. + * + * @param[in] nonce + * A pointer to the nonce value. + * + * @param[in] aad + * A pointer to the additional data to authenticate. + * + * @param[in] aadLen + * The length of the additional data to authenticate in number of bytes. + * + * @param[in] cipherData + * A pointer to encrypted data to decrypt. + * + * @param[in] cipherDataLen + * The length of the encrypted data in number of bytes. + * + * @param[out] plainData + * A pointer to decrypted data. + * + * @param[in] tag + * A pointer to the tag to verify. + * + * @param[in] cryptoAlgo + * Crypto algorithm to use. + * + * @return + * The result of the decryption operation. + * @ref SL_STATUS_OK on success or a NVM3 @ref sl_status_t on failure. + ******************************************************************************/ +typedef sl_status_t (*nvm3_HalCryptoDecrypt_t)(const uint8_t *nonce, const uint8_t *aad, size_t aadLen, const uint8_t *cipherData, size_t cipherDataLen, uint8_t *plainData, const uint8_t *tag, nvm3_halCryptoAlgo_t cryptoAlgo); + +/// @brief The HAL Crypto handle definition. +typedef struct { + nvm3_HalCryptoInit_t init; ///< Pointer to the init function + nvm3_HalCryptoGenRandNum_t genRandNum; ///< Pointer to the random number generator function + nvm3_HalCryptoEncrypt_t encrypt; ///< Pointer to the encryption function + nvm3_HalCryptoDecrypt_t decrypt; ///< Pointer to the decryption function +} nvm3_HalCryptoHandle_t; + +/** @} (end addtogroup nvm3halcrypto) */ +/** @} (end addtogroup nvm3) */ + +#ifdef __cplusplus +} +#endif + +#endif /* NVM_CRYPTO_HAL_H */ diff --git a/platform/emdrv/nvm3/inc/nvm3_hal_crypto_handle.h b/platform/emdrv/nvm3/inc/nvm3_hal_crypto_handle.h new file mode 100644 index 0000000000..8d47c03550 --- /dev/null +++ b/platform/emdrv/nvm3/inc/nvm3_hal_crypto_handle.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Crypto HAL for NVM3 driver + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_HAL_CRYPTO_HANDLE_H +#define NVM3_HAL_CRYPTO_HANDLE_H + +#include "nvm3_hal_crypto.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup nvm3halCrypto + * @{ + * @details + * This module provides the NVM3 interface to crypto. + * + * @note The features available through the handle are used by the NVM3 and + * should not be used directly by any applications. + ******************************************************************************/ + +/******************************************************************************* + *************************** GLOBAL VARIABLES ****************************** + ******************************************************************************/ + +extern const nvm3_HalCryptoHandle_t nvm3_halCryptoHandle; ///< The HAL crypto handle. + +/** @} (end addtogroup nvm3halCrypto) */ +/** @} (end addtogroup nvm3) */ + +#ifdef __cplusplus +} +#endif + +#endif /* NVM3_HAL_CRYPTO_HANDLE_H */ diff --git a/platform/emdrv/nvm3/src/nvm3_hal_crypto_se.c b/platform/emdrv/nvm3/src/nvm3_hal_crypto_se.c new file mode 100644 index 0000000000..934853a72e --- /dev/null +++ b/platform/emdrv/nvm3/src/nvm3_hal_crypto_se.c @@ -0,0 +1,219 @@ +/***************************************************************************//** + * @file + * @brief HAL SE Crypto implementation for Non-Volatile Memory driver + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "nvm3.h" +#include "nvm3_hal_crypto_handle.h" +#include "sl_se_manager.h" +#include "sl_se_manager_entropy.h" +#include "sl_se_manager_cipher.h" + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup nvm3halcrypto + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +static sl_se_key_descriptor_t nvm3_gcm_key_desc; + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialize key descriptor for NVM3 crypto operations. + ******************************************************************************/ +static void nvm3_keyDescInit(void) +{ + nvm3_gcm_key_desc.type = SL_SE_KEY_TYPE_AES_128; + nvm3_gcm_key_desc.size = 16; + nvm3_gcm_key_desc.storage.method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE; + nvm3_gcm_key_desc.flags = SL_SE_KEY_FLAG_IS_DEVICE_GENERATED; + nvm3_gcm_key_desc.storage.location.slot = SL_SE_KEY_SLOT_NVM3_KEY; +} + +/***************************************************************************//** + * Validate crypto parameters. + ******************************************************************************/ +static sl_status_t nvm3_validateCryptoParams(const uint8_t *nonce, + const uint8_t *aad, + size_t aadLen, + const uint8_t *inData, + size_t inDataLen, + uint8_t *outData, + const uint8_t *tag, + nvm3_halCryptoAlgo_t cryptoAlgo) +{ + if (cryptoAlgo != NVM3_HAL_CRYPTO_ALGO_AEAD) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((nonce == NULL) + || (aad == NULL && aadLen > 0) + || (inData == NULL && inDataLen > 0) + || (outData == NULL) + || (tag == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + return SL_STATUS_OK; +} + +/** @endcond */ + +/***************************************************************************//** + * SE manager initialization. + ******************************************************************************/ +static sl_status_t nvm3_halCryptoSeInit(void) +{ + // Initialize the SE manager + if (sl_se_init() != SL_STATUS_OK) { + return SL_STATUS_NVM3_CRYPTO_INIT_FAILED; + } + // Initialize key descriptor for NVM3 crypto operations + nvm3_keyDescInit(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Generate true random number. + ******************************************************************************/ +static sl_status_t nvm3_halCryptoSeGenRandNum(uint8_t *output, size_t outputSize) +{ + sl_se_command_context_t cmd_ctx; + sl_se_init_command_context(&cmd_ctx); + if (sl_se_get_random(&cmd_ctx, output, outputSize) != SL_STATUS_OK) { + return SL_STATUS_NVM3_RANDOM_NUM_GENERATION_FAILED; + } + return SL_STATUS_OK; +} + +/***************************************************************************//** + * SE crypto encryption operation. + ******************************************************************************/ +static sl_status_t nvm3_halCryptoSeEncrypt(const uint8_t *nonce, + const uint8_t *aad, + size_t aadLen, + const uint8_t *plainData, + size_t plainDataLen, + uint8_t *cipherData, + uint8_t *tag, + nvm3_halCryptoAlgo_t cryptoAlgo) +{ + if (nvm3_validateCryptoParams(nonce, + aad, + aadLen, + plainData, + plainDataLen, + cipherData, + tag, + cryptoAlgo) != SL_STATUS_OK) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_se_command_context_t cmd_ctx; + sl_se_init_command_context(&cmd_ctx); + if (sl_se_gcm_crypt_and_tag(&cmd_ctx, + &nvm3_gcm_key_desc, + SL_SE_ENCRYPT, + plainDataLen, + nonce, + NVM3_NONCE_SIZE, + aad, + aadLen, + plainData, + cipherData, + NVM3_GCM_TAG_SIZE, + tag) != SL_STATUS_OK) { + return SL_STATUS_NVM3_ENCRYPTION_FAILED; + } + return SL_STATUS_OK; +} + +/***************************************************************************//** + * SE crypto decryption operation. + ******************************************************************************/ +static sl_status_t nvm3_halCryptoSeDecrypt(const uint8_t *nonce, + const uint8_t *aad, + size_t aadLen, + const uint8_t *cipherData, + size_t cipherDataLen, + uint8_t *plainData, + const uint8_t *tag, + nvm3_halCryptoAlgo_t cryptoAlgo) +{ + if (nvm3_validateCryptoParams(nonce, + aad, + aadLen, + cipherData, + cipherDataLen, + plainData, + tag, + cryptoAlgo) != SL_STATUS_OK) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_se_command_context_t cmd_ctx; + sl_se_init_command_context(&cmd_ctx); + if (sl_se_gcm_auth_decrypt(&cmd_ctx, + &nvm3_gcm_key_desc, + cipherDataLen, + nonce, + NVM3_NONCE_SIZE, + aad, + aadLen, + cipherData, + plainData, + NVM3_GCM_TAG_SIZE, + tag) != SL_STATUS_OK) { + return SL_STATUS_SECURITY_DECRYPT_ERROR; + } + return SL_STATUS_OK; +} + +/******************************************************************************* + *************************** GLOBAL VARIABLES ****************************** + ******************************************************************************/ + +const nvm3_HalCryptoHandle_t nvm3_halCryptoHandle = { + .init = nvm3_halCryptoSeInit, ///< Set the init function + .genRandNum = nvm3_halCryptoSeGenRandNum, ///< Set the random num generator function + .encrypt = nvm3_halCryptoSeEncrypt, ///< Set the encryption function + .decrypt = nvm3_halCryptoSeDecrypt, ///< Set the decryption function +}; + +/** @} (end addtogroup nvm3halcrypto) */ +/** @} (end addtogroup nvm3) */ diff --git a/platform/emdrv/nvm3/src/nvm3_lock.c b/platform/emdrv/nvm3/src/nvm3_lock.c index 65896909ba..3e88fbd9ae 100644 --- a/platform/emdrv/nvm3/src/nvm3_lock.c +++ b/platform/emdrv/nvm3/src/nvm3_lock.c @@ -60,11 +60,9 @@ #ifdef NVM3_HOST_BUILD static int lockCount = 0; /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -#elif defined(SL_CATALOG_KERNEL_PRESENT) -static osMutexId_t nvm3_mutex; ///< NVM3 Lock Mutex - +#elif defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2) +static osMutexId_t nvm3_mutex; ///< NVM3 Lock Mutex #define NVM3_ERROR_ASSERT() do { EFM_ASSERT(false); } while (0) - #else CORE_DECLARE_IRQ_STATE; /// @endcond @@ -106,7 +104,7 @@ const size_t nvm3_objHandleSize = sizeof(nvm3_Obj_t); ******************************************************************************/ SL_WEAK void nvm3_lockCreateMutex(void) { -#if defined(SL_CATALOG_KERNEL_PRESENT) +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2) if (nvm3_mutex == NULL) { const osMutexAttr_t mutex_attr = { " NVM3 Mutex", @@ -133,7 +131,9 @@ SL_WEAK void nvm3_lockBegin(void) { #ifdef NVM3_HOST_BUILD lockCount++; -#elif defined(SL_CATALOG_KERNEL_PRESENT) +// In apps running on micrium OS on Ser2, the app is acquiring the mutex within +// a critical section while invoking bootloader APIs +#elif defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2) /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN osStatus_t os_status = osError; // Bypass the lock if kernel is not running @@ -167,7 +167,7 @@ SL_WEAK void nvm3_lockEnd(void) nvm3_tracePrint(NVM3_TRACE_LEVEL_ERROR, "NVM3 ERROR - lockEnd: invalid lock count.\n"); } lockCount--; -#elif defined(SL_CATALOG_KERNEL_PRESENT) +#elif defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2) osStatus_t os_status = osError; // Bypass the lock if kernel is not running if (osKernelGetState() == osKernelRunning) { diff --git a/platform/emlib/inc/em_iadc.h b/platform/emlib/inc/em_iadc.h index 36e505906c..2b62fa2bf2 100644 --- a/platform/emlib/inc/em_iadc.h +++ b/platform/emlib/inc/em_iadc.h @@ -327,6 +327,14 @@ typedef enum { /** Vddio2 / 4 */ iadcPosInputVddio2 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) | 3, +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + /** Vbat /4 */ + iadcPosInputVbat = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vss */ + iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, #else /** Vss */ iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) diff --git a/platform/hwconf_data/hwconfig.hwdata b/platform/hwconf_data/hwconfig.hwdata index bbed5a924f..8bd98cacb1 100644 --- a/platform/hwconf_data/hwconfig.hwdata +++ b/platform/hwconf_data/hwconfig.hwdata @@ -1,151 +1,155 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + + diff --git a/platform/peripheral/inc/sl_hal_system_generic.h b/platform/peripheral/inc/sl_hal_system_generic.h index 27c6f62c78..27b7fcad38 100644 --- a/platform/peripheral/inc/sl_hal_system_generic.h +++ b/platform/peripheral/inc/sl_hal_system_generic.h @@ -189,12 +189,15 @@ uint32_t sl_hal_system_get_hfrcodpll_band_calibration(uint32_t frequency); /***************************************************************************//** * @brief - * Get a factory calibration value for HFRCOCEM23 oscillator. + * Get a factory calibration value for HFRCOEM23 oscillator. + * + * @param [in] + * HFRCOEM23 frequency for which to retrieve calibration. * * @return * HFRCOEM23 calibration value. ******************************************************************************/ -uint32_t sl_hal_system_get_hfrcoem23_calibration(void); +uint32_t sl_hal_system_get_hfrcoem23_calibration(uint32_t frequency); /***************************************************************************//** * @brief diff --git a/platform/peripheral/src/sl_hal_system.c b/platform/peripheral/src/sl_hal_system.c index baa23e80d2..d2f085249e 100644 --- a/platform/peripheral/src/sl_hal_system.c +++ b/platform/peripheral/src/sl_hal_system.c @@ -301,15 +301,27 @@ uint32_t sl_hal_system_get_hfrcodpll_band_calibration(uint32_t frequency) /***************************************************************************//** * Get a factory calibration value for HFRCOCEM23 oscillator. ******************************************************************************/ -uint32_t sl_hal_system_get_hfrcoem23_calibration(void) +uint32_t sl_hal_system_get_hfrcoem23_calibration(uint32_t frequency) { #if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) sl_status_t status; sl_se_command_context_t se_command_ctx; sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); - uint32_t offset = DEVINFO_GP_HFRCOEM23DEFAULT_OFFSET; + uint32_t offset; uint32_t calibration_value = 0; + // Determine offset based on HFRCOEM23 frequency. + if (frequency == 40000000UL) { +#if defined(DEVINFO_GP_HFRCOEM2340MHZ_OFFSET) + offset = DEVINFO_GP_HFRCOEM2340MHZ_OFFSET; +#else + // Default to 20Mhz. + offset = DEVINFO_GP_HFRCOEM23DEFAULT_OFFSET; +#endif + } else { + offset = DEVINFO_GP_HFRCOEM23DEFAULT_OFFSET; + } + // Initialize command context status = sl_se_init_command_context(&se_command_ctx); if (status != SL_STATUS_OK) { @@ -324,6 +336,7 @@ uint32_t sl_hal_system_get_hfrcoem23_calibration(void) return calibration_value; #else + (void)frequency; return 0; #endif } diff --git a/platform/radio/efr32_multiphy_configurator/__pycache__/ConfigurationWrapper.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/__pycache__/ConfigurationWrapper.cpython-310.pyc deleted file mode 100644 index f9d52b88fe..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/__pycache__/ConfigurationWrapper.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/__pycache__/set_pymath_paths.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/__pycache__/set_pymath_paths.cpython-310.pyc deleted file mode 100644 index 47ff6a802f..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/__pycache__/set_pymath_paths.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/common/__pycache__/__init__.cpython-310.pyc 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b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg21/revA0/static/interface/__pycache__/iregmapregister.cpython-310.pyc deleted file mode 100644 index 71c8612e91..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg21/revA0/static/interface/__pycache__/iregmapregister.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg21/revC0/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg21/revC0/device.py index 837dca4560..248e338eec 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg21/revC0/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg21/revC0/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32X21X000F1024XM32_RevC0, self).__init__(rmio, label, 'EFR32X21X000F1024XM32', - RM_SVD_Info('EFR32X21X000F1024XM32_SEQ.svd', 'a979e38e49509667c5870af5781b4503')) + RM_SVD_Info('EFR32X21X000F1024XM32_SEQ.svd', '041764f23fda98d332119fd94d64ff4a')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index bc193ea72f..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/__pycache__/factory.cpython-310.pyc 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/revB2/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/revB2/device.py index 8878fad032..810ae2e79d 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/revB2/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg22/revB2/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG22X000F512IM32_RevB2, self).__init__(rmio, label, 'EFR32XG22X000F512IM32', - RM_SVD_Info('EFR32XG22X000F512IM32_SEQ.svd', '52ad1957944ebbe49ef918711e138087')) + RM_SVD_Info('EFR32XG22X000F512IM32_SEQ.svd', 'f3ea5edc9b2133de551b44dad2b89a56')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/__pycache__/excluded_regs.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/__pycache__/excluded_regs.cpython-310.pyc deleted file mode 100644 index 2ed26c01f4..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/__pycache__/excluded_regs.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/device.py index 89d4bf0da5..eb4308797b 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG23A000F512GM40_RevA2, self).__init__(rmio, label, 'EFR32XG23A000F512GM40', - RM_SVD_Info('EFR32XG23A000F512GM40_SEQ.svd', '7e38df7f5f8ef434e11d56f0d16c95e2')) + RM_SVD_Info('EFR32XG23A000F512GM40_SEQ.svd', '206324afaa04ddd54daedf34b1d8ddb6')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/static/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/static/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 0d11745003..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg23/revA2/static/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg24/revA1/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg24/revA1/device.py index 5de66a4d59..c569815b91 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg24/revA1/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg24/revA1/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG24XFULL_RevA1, self).__init__(rmio, label, 'EFR32XG24XFULL', - RM_SVD_Info('EFR32XG24XFULL_SEQ.svd', 'f21b7adaba85a0a0c0f869c3cd136a54')) + RM_SVD_Info('EFR32XG24XFULL_SEQ.svd', '34430b25d09903162371638e55f365a3')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_field.py index 0082b54dec..84b352f49e 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_field.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_field.py @@ -154,6 +154,36 @@ def __init__(self, register): self.__dict__['zz_frozen'] = True +class RM_Field_SUNOFDM_RXCFG1_PSDU_CE_MODE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SUNOFDM_RXCFG1_PSDU_CE_MODE, self).__init__(register, + 'PSDU_CE_MODE', 'SUNOFDM.RXCFG1.PSDU_CE_MODE', 'read-write', + u"", + 13, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SUNOFDM_RXCFG1_PHR_CE_MODE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SUNOFDM_RXCFG1_PHR_CE_MODE, self).__init__(register, + 'PHR_CE_MODE', 'SUNOFDM.RXCFG1.PHR_CE_MODE', 'read-write', + u"", + 14, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SUNOFDM_RXCFG1_FRCMAXSPEED(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SUNOFDM_RXCFG1_FRCMAXSPEED, self).__init__(register, + 'FRCMAXSPEED', 'SUNOFDM.RXCFG1.FRCMAXSPEED', 'read-write', + u"", + 15, 1) + self.__dict__['zz_frozen'] = True + + class RM_Field_SUNOFDM_RXCFG2_RSSISETPOINT(Base_RM_Field): def __init__(self, register): self.__dict__['zz_frozen'] = False @@ -184,6 +214,16 @@ def __init__(self, register): self.__dict__['zz_frozen'] = True +class RM_Field_SUNOFDM_COLLDET_BGDIS(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SUNOFDM_COLLDET_BGDIS, self).__init__(register, + 'BGDIS', 'SUNOFDM.COLLDET.BGDIS', 'read-write', + u"", + 6, 1) + self.__dict__['zz_frozen'] = True + + class RM_Field_SUNOFDM_AFC_AFCMIXERRATIOGAIN(Base_RM_Field): def __init__(self, register): self.__dict__['zz_frozen'] = False diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_register.py index 23e37a52ae..589fee5fc8 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_register.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/SUNOFDM_register.py @@ -72,7 +72,7 @@ def __init__(self, rmio, label): 0xb500fc00, 0x00C, 'RXCFG1', 'SUNOFDM.RXCFG1', 'read-write', u"", - 0x00000000, 0x00001FFF, + 0x00000000, 0x0000FFFF, 0x00001000, 0x00002000, 0x00003000) @@ -88,6 +88,12 @@ def __init__(self, rmio, label): self.zz_fdict['EXTCOARSEFREQ'] = self.EXTCOARSEFREQ self.GIRECOMB = RM_Field_SUNOFDM_RXCFG1_GIRECOMB(self) self.zz_fdict['GIRECOMB'] = self.GIRECOMB + self.PSDU_CE_MODE = RM_Field_SUNOFDM_RXCFG1_PSDU_CE_MODE(self) + self.zz_fdict['PSDU_CE_MODE'] = self.PSDU_CE_MODE + self.PHR_CE_MODE = RM_Field_SUNOFDM_RXCFG1_PHR_CE_MODE(self) + self.zz_fdict['PHR_CE_MODE'] = self.PHR_CE_MODE + self.FRCMAXSPEED = RM_Field_SUNOFDM_RXCFG1_FRCMAXSPEED(self) + self.zz_fdict['FRCMAXSPEED'] = self.FRCMAXSPEED self.__dict__['zz_frozen'] = True @@ -114,7 +120,7 @@ def __init__(self, rmio, label): 0xb500fc00, 0x014, 'COLLDET', 'SUNOFDM.COLLDET', 'read-write', u"", - 0x00000014, 0x0000003F, + 0x00000014, 0x0000007F, 0x00001000, 0x00002000, 0x00003000) @@ -122,6 +128,8 @@ def __init__(self, rmio, label): self.zz_fdict['COLLDET'] = self.COLLDET self.COLLDETTHR = RM_Field_SUNOFDM_COLLDET_COLLDETTHR(self) self.zz_fdict['COLLDETTHR'] = self.COLLDETTHR + self.BGDIS = RM_Field_SUNOFDM_COLLDET_BGDIS(self) + self.zz_fdict['BGDIS'] = self.BGDIS self.__dict__['zz_frozen'] = True diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/device.py index 8f1c8c45d4..dddcc517bc 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg25/revA1/device.py @@ -129,7 +129,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG25XFULL_RevA1, self).__init__(rmio, label, 'EFR32XG25XFULL', - RM_SVD_Info('EFR32XG25XFULL_SEQ.svd', 'f5fdab6fa89ed101762a26438b1ff165')) + RM_SVD_Info('EFR32XG25XFULL_SEQ.svd', '9ad4be299dc74c428fdc5ebbefa724ba')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/__pycache__/excluded_regs.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/__pycache__/excluded_regs.cpython-310.pyc deleted file mode 100644 index 47a3cfeb80..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/__pycache__/excluded_regs.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/device.py index d1d7f658c2..d32c48b548 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG26XFULL_RevA1, self).__init__(rmio, label, 'EFR32XG26XFULL', - RM_SVD_Info('EFR32XG26XFULL_SEQ.svd', 'be9d07edd4c311150c365b5e053af86a')) + RM_SVD_Info('EFR32XG26XFULL_SEQ.svd', '73e3afd8f3b14149c897def8addb14d3')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/static/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/static/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 9d6dfbadc7..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg26/revA1/static/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg27/revA1/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg27/revA1/device.py index bc129ecfe8..c3fce7cbb4 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg27/revA1/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg27/revA1/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG27XFULL_RevA1, self).__init__(rmio, label, 'EFR32XG27XFULL', - RM_SVD_Info('EFR32XG27XFULL_SEQ.svd', '00d842ff61f02fd9148f88a7bb0d6d3d')) + RM_SVD_Info('EFR32XG27XFULL_SEQ.svd', '6e6aad5a38898616fb00e2509a2fde54')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/__pycache__/excluded_regs.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/__pycache__/excluded_regs.cpython-310.pyc deleted file mode 100644 index 10dbd3fe5c..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/__pycache__/excluded_regs.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/device.py index 5f7822357a..b4c5194cf5 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG28XFULL_RevA0, self).__init__(rmio, label, 'EFR32XG28XFULL', - RM_SVD_Info('EFR32XG28XFULL_SEQ.svd', '9c1b4a0d87ebfcfe7a9debf2ac74111f')) + RM_SVD_Info('EFR32XG28XFULL_SEQ.svd', 'fe127f8798bd80c7cc22b888e4443c5a')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/static/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/static/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 4a24d9d3ac..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg28/revA0/static/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg29/revA0/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg29/revA0/device.py index 07bd203b02..ef8f29e081 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg29/revA0/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/efr32xg29/revA0/device.py @@ -113,7 +113,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_EFR32XG29XFULL_RevA0, self).__init__(rmio, label, 'EFR32XG29XFULL', - RM_SVD_Info('EFR32XG29XFULL_SEQ.svd', '4b474f31813b61fcd39ce2ccbb4fc742')) + RM_SVD_Info('EFR32XG29XFULL_SEQ.svd', '937b6798d60da07b355abc93f34de019')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS diff --git 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a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ.py deleted file mode 100644 index 242b481fe6..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ.py +++ /dev/null @@ -1,32 +0,0 @@ - -# -*- coding: utf-8 -*- - -__all__ = [ 'RM_Peripheral_SEQ' ] - -from . static import Base_RM_Peripheral -from . SEQ_register import * - -class RM_Peripheral_SEQ(Base_RM_Peripheral): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Peripheral_SEQ, self).__init__(rmio, label, - 0xA0000000, 'SEQ', - u"", - []) - self.MMDDENOMINIT_CALC = RM_Register_SEQ_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) - self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC - self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) - self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED - self.MODINDEX_CALC = RM_Register_SEQ_MODINDEX_CALC(self.zz_rmio, self.zz_label) - self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC - self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) - self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED - self.SPARE4 = RM_Register_SEQ_SPARE4(self.zz_rmio, self.zz_label) - self.zz_rdict['SPARE4'] = self.SPARE4 - self.MODEMINFO = RM_Register_SEQ_MODEMINFO(self.zz_rmio, self.zz_label) - self.zz_rdict['MODEMINFO'] = self.MODEMINFO - self.MISC = RM_Register_SEQ_MISC(self.zz_rmio, self.zz_label) - self.zz_rdict['MISC'] = self.MISC - self.PHYINFO = RM_Register_SEQ_PHYINFO(self.zz_rmio, self.zz_label) - self.zz_rdict['PHYINFO'] = self.PHYINFO - self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS.py new file mode 100644 index 0000000000..93059165ab --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS.py @@ -0,0 +1,32 @@ + +# -*- coding: utf-8 -*- + +__all__ = [ 'RM_Peripheral_SEQ_NS' ] + +from . static import Base_RM_Peripheral +from . SEQ_NS_register import * + +class RM_Peripheral_SEQ_NS(Base_RM_Peripheral): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Peripheral_SEQ_NS, self).__init__(rmio, label, + 0xB0000000, 'SEQ_NS', + u"", + []) + self.MMDDENOMINIT_CALC = RM_Register_SEQ_NS_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC + self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED + self.MODINDEX_CALC = RM_Register_SEQ_NS_MODINDEX_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC + self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED + self.SPARE4 = RM_Register_SEQ_NS_SPARE4(self.zz_rmio, self.zz_label) + self.zz_rdict['SPARE4'] = self.SPARE4 + self.MODEMINFO = RM_Register_SEQ_NS_MODEMINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['MODEMINFO'] = self.MODEMINFO + self.MISC = RM_Register_SEQ_NS_MISC(self.zz_rmio, self.zz_label) + self.zz_rdict['MISC'] = self.MISC + self.PHYINFO = RM_Register_SEQ_NS_PHYINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['PHYINFO'] = self.PHYINFO + self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS_field.py new file mode 100644 index 0000000000..d576504640 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS_field.py @@ -0,0 +1,366 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Field + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_NS.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_NS.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_NS.MODINDEX_CALC.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_NS.MODINDEX_CALC.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_NS.MODINDEX_CALC.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_NS.MODINDEX_CALC.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_NS.MODINDEX_CALC.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_NS.MODINDEX_CALC.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_SPARE4_SPARE4(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_SPARE4_SPARE4, self).__init__(register, + 'SPARE4', 'SEQ_NS.SPARE4.SPARE4', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN, self).__init__(register, + 'LEGACY_EN', 'SEQ_NS.MODEMINFO.LEGACY_EN', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE0, self).__init__(register, + 'SPARE0', 'SEQ_NS.MODEMINFO.SPARE0', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_TRECS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_TRECS_EN, self).__init__(register, + 'TRECS_EN', 'SEQ_NS.MODEMINFO.TRECS_EN', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_BCR_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_BCR_EN, self).__init__(register, + 'BCR_EN', 'SEQ_NS.MODEMINFO.BCR_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN, self).__init__(register, + 'COHERENT_EN', 'SEQ_NS.MODEMINFO.COHERENT_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN, self).__init__(register, + 'LONGRANGE_EN', 'SEQ_NS.MODEMINFO.LONGRANGE_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN, self).__init__(register, + 'ENHDSSS_EN', 'SEQ_NS.MODEMINFO.ENHDSSS_EN', 'read-write', + u"", + 6, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE1, self).__init__(register, + 'SPARE1', 'SEQ_NS.MODEMINFO.SPARE1', 'read-write', + u"", + 7, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN, self).__init__(register, + 'SOFTMODEM_EN', 'SEQ_NS.MODEMINFO.SOFTMODEM_EN', 'read-write', + u"", + 8, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_BTC_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_BTC_EN, self).__init__(register, + 'BTC_EN', 'SEQ_NS.MODEMINFO.BTC_EN', 'read-write', + u"", + 9, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE2, self).__init__(register, + 'SPARE2', 'SEQ_NS.MODEMINFO.SPARE2', 'read-write', + u"", + 10, 22) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED10(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED10, self).__init__(register, + 'RESERVED10', 'SEQ_NS.MISC.RESERVED10', 'read-write', + u"", + 10, 2) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN, self).__init__(register, + 'SYNTH_MODE_TX00D_EN', 'SEQ_NS.MISC.SYNTH_MODE_TX00D_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ_NS.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ_NS.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED2, self).__init__(register, + 'RESERVED2', 'SEQ_NS.MISC.RESERVED2', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED1, self).__init__(register, + 'RESERVED1', 'SEQ_NS.MISC.RESERVED1', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED0, self).__init__(register, + 'RESERVED0', 'SEQ_NS.MISC.RESERVED0', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_PHYINFO_ADDRESS(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_PHYINFO_ADDRESS, self).__init__(register, + 'ADDRESS', 'SEQ_NS.PHYINFO.ADDRESS', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS_register.py new file mode 100644 index 0000000000..9750742d78 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_NS_register.py @@ -0,0 +1,191 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Register +from . SEQ_NS_field import * + + +class RM_Register_SEQ_NS_MMDDENOMINIT_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MMDDENOMINIT_CALC, self).__init__(rmio, label, + 0xb0000000, 0x000, + 'MMDDENOMINIT_CALC', 'SEQ_NS.MMDDENOMINIT_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, + 0xb0000000, 0x004, + 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODINDEX_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODINDEX_CALC, self).__init__(rmio, label, + 0xb0000000, 0x008, + 'MODINDEX_CALC', 'SEQ_NS.MODINDEX_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, + 0xb0000000, 0x00C, + 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_SPARE4(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_SPARE4, self).__init__(rmio, label, + 0xb0000000, 0x010, + 'SPARE4', 'SEQ_NS.SPARE4', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.SPARE4 = RM_Field_SEQ_NS_SPARE4_SPARE4(self) + self.zz_fdict['SPARE4'] = self.SPARE4 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODEMINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODEMINFO, self).__init__(rmio, label, + 0xb0000000, 0x014, + 'MODEMINFO', 'SEQ_NS.MODEMINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.LEGACY_EN = RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN(self) + self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN + self.SPARE0 = RM_Field_SEQ_NS_MODEMINFO_SPARE0(self) + self.zz_fdict['SPARE0'] = self.SPARE0 + self.TRECS_EN = RM_Field_SEQ_NS_MODEMINFO_TRECS_EN(self) + self.zz_fdict['TRECS_EN'] = self.TRECS_EN + self.BCR_EN = RM_Field_SEQ_NS_MODEMINFO_BCR_EN(self) + self.zz_fdict['BCR_EN'] = self.BCR_EN + self.COHERENT_EN = RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN(self) + self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN + self.LONGRANGE_EN = RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN(self) + self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN + self.ENHDSSS_EN = RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN(self) + self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN + self.SPARE1 = RM_Field_SEQ_NS_MODEMINFO_SPARE1(self) + self.zz_fdict['SPARE1'] = self.SPARE1 + self.SOFTMODEM_EN = RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN(self) + self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN + self.BTC_EN = RM_Field_SEQ_NS_MODEMINFO_BTC_EN(self) + self.zz_fdict['BTC_EN'] = self.BTC_EN + self.SPARE2 = RM_Field_SEQ_NS_MODEMINFO_SPARE2(self) + self.zz_fdict['SPARE2'] = self.SPARE2 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MISC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MISC, self).__init__(rmio, label, + 0xb0000000, 0x018, + 'MISC', 'SEQ_NS.MISC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.RESERVED10 = RM_Field_SEQ_NS_MISC_RESERVED10(self) + self.zz_fdict['RESERVED10'] = self.RESERVED10 + self.SYNTH_MODE_TX00D_EN = RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN(self) + self.zz_fdict['SYNTH_MODE_TX00D_EN'] = self.SYNTH_MODE_TX00D_EN + self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN + self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN + self.RESERVED2 = RM_Field_SEQ_NS_MISC_RESERVED2(self) + self.zz_fdict['RESERVED2'] = self.RESERVED2 + self.RESERVED1 = RM_Field_SEQ_NS_MISC_RESERVED1(self) + self.zz_fdict['RESERVED1'] = self.RESERVED1 + self.RESERVED0 = RM_Field_SEQ_NS_MISC_RESERVED0(self) + self.zz_fdict['RESERVED0'] = self.RESERVED0 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_PHYINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_PHYINFO, self).__init__(rmio, label, + 0xb0000000, 0x01C, + 'PHYINFO', 'SEQ_NS.PHYINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.ADDRESS = RM_Field_SEQ_NS_PHYINFO_ADDRESS(self) + self.zz_fdict['ADDRESS'] = self.ADDRESS + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S.py new file mode 100644 index 0000000000..a7646c6d63 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S.py @@ -0,0 +1,32 @@ + +# -*- coding: utf-8 -*- + +__all__ = [ 'RM_Peripheral_SEQ_S' ] + +from . static import Base_RM_Peripheral +from . SEQ_S_register import * + +class RM_Peripheral_SEQ_S(Base_RM_Peripheral): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Peripheral_SEQ_S, self).__init__(rmio, label, + 0xA0000000, 'SEQ_S', + u"", + []) + self.MMDDENOMINIT_CALC = RM_Register_SEQ_S_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC + self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED + self.MODINDEX_CALC = RM_Register_SEQ_S_MODINDEX_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC + self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED + self.SPARE4 = RM_Register_SEQ_S_SPARE4(self.zz_rmio, self.zz_label) + self.zz_rdict['SPARE4'] = self.SPARE4 + self.MODEMINFO = RM_Register_SEQ_S_MODEMINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['MODEMINFO'] = self.MODEMINFO + self.MISC = RM_Register_SEQ_S_MISC(self.zz_rmio, self.zz_label) + self.zz_rdict['MISC'] = self.MISC + self.PHYINFO = RM_Register_SEQ_S_PHYINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['PHYINFO'] = self.PHYINFO + self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S_field.py new file mode 100644 index 0000000000..a40b470b26 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S_field.py @@ -0,0 +1,366 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Field + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_S.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_S.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_S.MODINDEX_CALC.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_S.MODINDEX_CALC.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_S.MODINDEX_CALC.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_S.MODINDEX_CALC.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_S.MODINDEX_CALC.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_S.MODINDEX_CALC.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_SPARE4_SPARE4(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_SPARE4_SPARE4, self).__init__(register, + 'SPARE4', 'SEQ_S.SPARE4.SPARE4', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_LEGACY_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_LEGACY_EN, self).__init__(register, + 'LEGACY_EN', 'SEQ_S.MODEMINFO.LEGACY_EN', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE0, self).__init__(register, + 'SPARE0', 'SEQ_S.MODEMINFO.SPARE0', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_TRECS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_TRECS_EN, self).__init__(register, + 'TRECS_EN', 'SEQ_S.MODEMINFO.TRECS_EN', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_BCR_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_BCR_EN, self).__init__(register, + 'BCR_EN', 'SEQ_S.MODEMINFO.BCR_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_COHERENT_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_COHERENT_EN, self).__init__(register, + 'COHERENT_EN', 'SEQ_S.MODEMINFO.COHERENT_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN, self).__init__(register, + 'LONGRANGE_EN', 'SEQ_S.MODEMINFO.LONGRANGE_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN, self).__init__(register, + 'ENHDSSS_EN', 'SEQ_S.MODEMINFO.ENHDSSS_EN', 'read-write', + u"", + 6, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE1, self).__init__(register, + 'SPARE1', 'SEQ_S.MODEMINFO.SPARE1', 'read-write', + u"", + 7, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN, self).__init__(register, + 'SOFTMODEM_EN', 'SEQ_S.MODEMINFO.SOFTMODEM_EN', 'read-write', + u"", + 8, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_BTC_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_BTC_EN, self).__init__(register, + 'BTC_EN', 'SEQ_S.MODEMINFO.BTC_EN', 'read-write', + u"", + 9, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE2, self).__init__(register, + 'SPARE2', 'SEQ_S.MODEMINFO.SPARE2', 'read-write', + u"", + 10, 22) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED10(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED10, self).__init__(register, + 'RESERVED10', 'SEQ_S.MISC.RESERVED10', 'read-write', + u"", + 10, 2) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN, self).__init__(register, + 'SYNTH_MODE_TX00D_EN', 'SEQ_S.MISC.SYNTH_MODE_TX00D_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ_S.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ_S.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED2, self).__init__(register, + 'RESERVED2', 'SEQ_S.MISC.RESERVED2', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED1, self).__init__(register, + 'RESERVED1', 'SEQ_S.MISC.RESERVED1', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED0, self).__init__(register, + 'RESERVED0', 'SEQ_S.MISC.RESERVED0', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_PHYINFO_ADDRESS(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_PHYINFO_ADDRESS, self).__init__(register, + 'ADDRESS', 'SEQ_S.PHYINFO.ADDRESS', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S_register.py new file mode 100644 index 0000000000..f506b7e389 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_S_register.py @@ -0,0 +1,191 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Register +from . SEQ_S_field import * + + +class RM_Register_SEQ_S_MMDDENOMINIT_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MMDDENOMINIT_CALC, self).__init__(rmio, label, + 0xa0000000, 0x000, + 'MMDDENOMINIT_CALC', 'SEQ_S.MMDDENOMINIT_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, + 0xa0000000, 0x004, + 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODINDEX_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODINDEX_CALC, self).__init__(rmio, label, + 0xa0000000, 0x008, + 'MODINDEX_CALC', 'SEQ_S.MODINDEX_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, + 0xa0000000, 0x00C, + 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_SPARE4(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_SPARE4, self).__init__(rmio, label, + 0xa0000000, 0x010, + 'SPARE4', 'SEQ_S.SPARE4', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.SPARE4 = RM_Field_SEQ_S_SPARE4_SPARE4(self) + self.zz_fdict['SPARE4'] = self.SPARE4 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODEMINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODEMINFO, self).__init__(rmio, label, + 0xa0000000, 0x014, + 'MODEMINFO', 'SEQ_S.MODEMINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.LEGACY_EN = RM_Field_SEQ_S_MODEMINFO_LEGACY_EN(self) + self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN + self.SPARE0 = RM_Field_SEQ_S_MODEMINFO_SPARE0(self) + self.zz_fdict['SPARE0'] = self.SPARE0 + self.TRECS_EN = RM_Field_SEQ_S_MODEMINFO_TRECS_EN(self) + self.zz_fdict['TRECS_EN'] = self.TRECS_EN + self.BCR_EN = RM_Field_SEQ_S_MODEMINFO_BCR_EN(self) + self.zz_fdict['BCR_EN'] = self.BCR_EN + self.COHERENT_EN = RM_Field_SEQ_S_MODEMINFO_COHERENT_EN(self) + self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN + self.LONGRANGE_EN = RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN(self) + self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN + self.ENHDSSS_EN = RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN(self) + self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN + self.SPARE1 = RM_Field_SEQ_S_MODEMINFO_SPARE1(self) + self.zz_fdict['SPARE1'] = self.SPARE1 + self.SOFTMODEM_EN = RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN(self) + self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN + self.BTC_EN = RM_Field_SEQ_S_MODEMINFO_BTC_EN(self) + self.zz_fdict['BTC_EN'] = self.BTC_EN + self.SPARE2 = RM_Field_SEQ_S_MODEMINFO_SPARE2(self) + self.zz_fdict['SPARE2'] = self.SPARE2 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MISC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MISC, self).__init__(rmio, label, + 0xa0000000, 0x018, + 'MISC', 'SEQ_S.MISC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.RESERVED10 = RM_Field_SEQ_S_MISC_RESERVED10(self) + self.zz_fdict['RESERVED10'] = self.RESERVED10 + self.SYNTH_MODE_TX00D_EN = RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN(self) + self.zz_fdict['SYNTH_MODE_TX00D_EN'] = self.SYNTH_MODE_TX00D_EN + self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN + self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN + self.RESERVED2 = RM_Field_SEQ_S_MISC_RESERVED2(self) + self.zz_fdict['RESERVED2'] = self.RESERVED2 + self.RESERVED1 = RM_Field_SEQ_S_MISC_RESERVED1(self) + self.zz_fdict['RESERVED1'] = self.RESERVED1 + self.RESERVED0 = RM_Field_SEQ_S_MISC_RESERVED0(self) + self.zz_fdict['RESERVED0'] = self.RESERVED0 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_PHYINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_PHYINFO, self).__init__(rmio, label, + 0xa0000000, 0x01C, + 'PHYINFO', 'SEQ_S.PHYINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.ADDRESS = RM_Field_SEQ_S_PHYINFO_ADDRESS(self) + self.zz_fdict['ADDRESS'] = self.ADDRESS + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_field.py deleted file mode 100644 index 06656c939c..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_field.py +++ /dev/null @@ -1,356 +0,0 @@ - -# -*- coding: utf-8 -*- - -from . static import Base_RM_Field - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, - 'DENOMINIT0', 'SEQ.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', - u"", - 0, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, - 'DENOMINIT1', 'SEQ.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', - u"", - 9, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, - 'DENOMINIT0', 'SEQ.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', - u"", - 0, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, - 'DENOMINIT1', 'SEQ.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', - u"", - 9, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXM, self).__init__(register, - 'MODINDEXM', 'SEQ.MODINDEX_CALC.MODINDEXM', 'read-write', - u"", - 0, 8) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE, self).__init__(register, - 'MODINDEXE', 'SEQ.MODINDEX_CALC.MODINDEXE', 'read-write', - u"", - 8, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_FREQGAINE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_FREQGAINE, self).__init__(register, - 'FREQGAINE', 'SEQ.MODINDEX_CALC.FREQGAINE', 'read-write', - u"", - 13, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_FREQGAINM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_FREQGAINM, self).__init__(register, - 'FREQGAINM', 'SEQ.MODINDEX_CALC.FREQGAINM', 'read-write', - u"", - 16, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, - 'AMMODINDEXM', 'SEQ.MODINDEX_CALC.AMMODINDEXM', 'read-write', - u"", - 19, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, - 'AMMODINDEXE', 'SEQ.MODINDEX_CALC.AMMODINDEXE', 'read-write', - u"", - 24, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, - 'MODINDEXM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', - u"", - 0, 8) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, - 'MODINDEXE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', - u"", - 8, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, - 'FREQGAINE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', - u"", - 13, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, - 'FREQGAINM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', - u"", - 16, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, - 'AMMODINDEXM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', - u"", - 19, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, - 'AMMODINDEXE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', - u"", - 24, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_SPARE4_SPARE4(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_SPARE4_SPARE4, self).__init__(register, - 'SPARE4', 'SEQ.SPARE4.SPARE4', 'read-write', - u"", - 0, 32) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_LEGACY_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_LEGACY_EN, self).__init__(register, - 'LEGACY_EN', 'SEQ.MODEMINFO.LEGACY_EN', 'read-write', - u"", - 0, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE0, self).__init__(register, - 'SPARE0', 'SEQ.MODEMINFO.SPARE0', 'read-write', - u"", - 1, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_TRECS_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_TRECS_EN, self).__init__(register, - 'TRECS_EN', 'SEQ.MODEMINFO.TRECS_EN', 'read-write', - u"", - 2, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_BCR_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_BCR_EN, self).__init__(register, - 'BCR_EN', 'SEQ.MODEMINFO.BCR_EN', 'read-write', - u"", - 3, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_COHERENT_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_COHERENT_EN, self).__init__(register, - 'COHERENT_EN', 'SEQ.MODEMINFO.COHERENT_EN', 'read-write', - u"", - 4, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_LONGRANGE_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_LONGRANGE_EN, self).__init__(register, - 'LONGRANGE_EN', 'SEQ.MODEMINFO.LONGRANGE_EN', 'read-write', - u"", - 5, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_ENHDSSS_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_ENHDSSS_EN, self).__init__(register, - 'ENHDSSS_EN', 'SEQ.MODEMINFO.ENHDSSS_EN', 'read-write', - u"", - 6, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE1, self).__init__(register, - 'SPARE1', 'SEQ.MODEMINFO.SPARE1', 'read-write', - u"", - 7, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN, self).__init__(register, - 'SOFTMODEM_EN', 'SEQ.MODEMINFO.SOFTMODEM_EN', 'read-write', - u"", - 8, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_BTC_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_BTC_EN, self).__init__(register, - 'BTC_EN', 'SEQ.MODEMINFO.BTC_EN', 'read-write', - u"", - 9, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE2(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE2, self).__init__(register, - 'SPARE2', 'SEQ.MODEMINFO.SPARE2', 'read-write', - u"", - 10, 22) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED10(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED10, self).__init__(register, - 'RESERVED10', 'SEQ.MISC.RESERVED10', 'read-write', - u"", - 10, 2) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, - 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', - u"", - 4, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, - 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', - u"", - 3, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED2(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED2, self).__init__(register, - 'RESERVED2', 'SEQ.MISC.RESERVED2', 'read-write', - u"", - 2, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED1, self).__init__(register, - 'RESERVED1', 'SEQ.MISC.RESERVED1', 'read-write', - u"", - 1, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED0, self).__init__(register, - 'RESERVED0', 'SEQ.MISC.RESERVED0', 'read-write', - u"", - 0, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_PHYINFO_ADDRESS(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_PHYINFO_ADDRESS, self).__init__(register, - 'ADDRESS', 'SEQ.PHYINFO.ADDRESS', 'read-write', - u"", - 0, 32) - self.__dict__['zz_frozen'] = True - - diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_register.py deleted file mode 100644 index f4a745a31d..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/SEQ_register.py +++ /dev/null @@ -1,189 +0,0 @@ - -# -*- coding: utf-8 -*- - -from . static import Base_RM_Register -from . SEQ_field import * - - -class RM_Register_SEQ_MMDDENOMINIT_CALC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MMDDENOMINIT_CALC, self).__init__(rmio, label, - 0xa0000000, 0x000, - 'MMDDENOMINIT_CALC', 'SEQ.MMDDENOMINIT_CALC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.DENOMINIT0 = RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0(self) - self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 - self.DENOMINIT1 = RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1(self) - self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, - 0xa0000000, 0x004, - 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ.MMDDENOMINIT_CALC_DOUBLED', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.DENOMINIT0 = RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) - self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 - self.DENOMINIT1 = RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) - self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODINDEX_CALC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODINDEX_CALC, self).__init__(rmio, label, - 0xa0000000, 0x008, - 'MODINDEX_CALC', 'SEQ.MODINDEX_CALC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.MODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXM(self) - self.zz_fdict['MODINDEXM'] = self.MODINDEXM - self.MODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE(self) - self.zz_fdict['MODINDEXE'] = self.MODINDEXE - self.FREQGAINE = RM_Field_SEQ_MODINDEX_CALC_FREQGAINE(self) - self.zz_fdict['FREQGAINE'] = self.FREQGAINE - self.FREQGAINM = RM_Field_SEQ_MODINDEX_CALC_FREQGAINM(self) - self.zz_fdict['FREQGAINM'] = self.FREQGAINM - self.AMMODINDEXM = RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM(self) - self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM - self.AMMODINDEXE = RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE(self) - self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, - 0xa0000000, 0x00C, - 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.MODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) - self.zz_fdict['MODINDEXM'] = self.MODINDEXM - self.MODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) - self.zz_fdict['MODINDEXE'] = self.MODINDEXE - self.FREQGAINE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) - self.zz_fdict['FREQGAINE'] = self.FREQGAINE - self.FREQGAINM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) - self.zz_fdict['FREQGAINM'] = self.FREQGAINM - self.AMMODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) - self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM - self.AMMODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) - self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_SPARE4(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_SPARE4, self).__init__(rmio, label, - 0xa0000000, 0x010, - 'SPARE4', 'SEQ.SPARE4', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.SPARE4 = RM_Field_SEQ_SPARE4_SPARE4(self) - self.zz_fdict['SPARE4'] = self.SPARE4 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODEMINFO(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODEMINFO, self).__init__(rmio, label, - 0xa0000000, 0x014, - 'MODEMINFO', 'SEQ.MODEMINFO', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.LEGACY_EN = RM_Field_SEQ_MODEMINFO_LEGACY_EN(self) - self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN - self.SPARE0 = RM_Field_SEQ_MODEMINFO_SPARE0(self) - self.zz_fdict['SPARE0'] = self.SPARE0 - self.TRECS_EN = RM_Field_SEQ_MODEMINFO_TRECS_EN(self) - self.zz_fdict['TRECS_EN'] = self.TRECS_EN - self.BCR_EN = RM_Field_SEQ_MODEMINFO_BCR_EN(self) - self.zz_fdict['BCR_EN'] = self.BCR_EN - self.COHERENT_EN = RM_Field_SEQ_MODEMINFO_COHERENT_EN(self) - self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN - self.LONGRANGE_EN = RM_Field_SEQ_MODEMINFO_LONGRANGE_EN(self) - self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN - self.ENHDSSS_EN = RM_Field_SEQ_MODEMINFO_ENHDSSS_EN(self) - self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN - self.SPARE1 = RM_Field_SEQ_MODEMINFO_SPARE1(self) - self.zz_fdict['SPARE1'] = self.SPARE1 - self.SOFTMODEM_EN = RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN(self) - self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN - self.BTC_EN = RM_Field_SEQ_MODEMINFO_BTC_EN(self) - self.zz_fdict['BTC_EN'] = self.BTC_EN - self.SPARE2 = RM_Field_SEQ_MODEMINFO_SPARE2(self) - self.zz_fdict['SPARE2'] = self.SPARE2 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MISC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MISC, self).__init__(rmio, label, - 0xa0000000, 0x018, - 'MISC', 'SEQ.MISC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.RESERVED10 = RM_Field_SEQ_MISC_RESERVED10(self) - self.zz_fdict['RESERVED10'] = self.RESERVED10 - self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN(self) - self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN - self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN(self) - self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN - self.RESERVED2 = RM_Field_SEQ_MISC_RESERVED2(self) - self.zz_fdict['RESERVED2'] = self.RESERVED2 - self.RESERVED1 = RM_Field_SEQ_MISC_RESERVED1(self) - self.zz_fdict['RESERVED1'] = self.RESERVED1 - self.RESERVED0 = RM_Field_SEQ_MISC_RESERVED0(self) - self.zz_fdict['RESERVED0'] = self.RESERVED0 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_PHYINFO(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_PHYINFO, self).__init__(rmio, label, - 0xa0000000, 0x01C, - 'PHYINFO', 'SEQ.PHYINFO', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.ADDRESS = RM_Field_SEQ_PHYINFO_ADDRESS(self) - self.zz_fdict['ADDRESS'] = self.ADDRESS - self.__dict__['zz_frozen'] = True - - diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/device.py index 7815f8e5d9..8e405e6d3d 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA0/device.py @@ -35,7 +35,8 @@ from . RAC_S import * from . RFCRC_NS import * from . RFCRC_S import * -from . SEQ import * +from . SEQ_NS import * +from . SEQ_S import * from . SYNTH_NS import * from . SYNTH_S import * @@ -113,7 +114,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_SIXG301XFULL_RevA0, self).__init__(rmio, label, 'SIXG301XFULL', - RM_SVD_Info('SIXG301XFULL_SEQ.svd', '29b658b42da0f8d838cb8778b74ae57a')) + RM_SVD_Info('SIXG301XFULL_SEQ.svd', '014c0f66318de0c5fafe6261faa8f1d8')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS @@ -135,8 +136,10 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.zz_pdict['RFCRC_NS'] = self.RFCRC_NS self.RFCRC_S = RM_Peripheral_RFCRC_S(self.zz_rmio, self.zz_label) self.zz_pdict['RFCRC_S'] = self.RFCRC_S - self.SEQ = RM_Peripheral_SEQ(self.zz_rmio, self.zz_label) - self.zz_pdict['SEQ'] = self.SEQ + self.SEQ_NS = RM_Peripheral_SEQ_NS(self.zz_rmio, self.zz_label) + self.zz_pdict['SEQ_NS'] = self.SEQ_NS + self.SEQ_S = RM_Peripheral_SEQ_S(self.zz_rmio, self.zz_label) + self.zz_pdict['SEQ_S'] = self.SEQ_S self.SYNTH_NS = RM_Peripheral_SYNTH_NS(self.zz_rmio, self.zz_label) self.zz_pdict['SYNTH_NS'] = self.SYNTH_NS self.SYNTH_S = RM_Peripheral_SYNTH_S(self.zz_rmio, self.zz_label) @@ -148,6 +151,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.MODEM = self.MODEM_S self.RAC = self.RAC_S self.RFCRC = self.RFCRC_S + self.SEQ = self.SEQ_S self.SYNTH = self.SYNTH_S pass elif default_tz_access_mode == RM_TrustZone_Access_Mode.TZ_NONSECURE: @@ -156,6 +160,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.MODEM = self.MODEM_NS self.RAC = self.RAC_NS self.RFCRC = self.RFCRC_NS + self.SEQ = self.SEQ_NS self.SYNTH = self.SYNTH_NS pass diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ.py deleted file mode 100644 index 242b481fe6..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ.py +++ /dev/null @@ -1,32 +0,0 @@ - -# -*- coding: utf-8 -*- - -__all__ = [ 'RM_Peripheral_SEQ' ] - -from . static import Base_RM_Peripheral -from . SEQ_register import * - -class RM_Peripheral_SEQ(Base_RM_Peripheral): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Peripheral_SEQ, self).__init__(rmio, label, - 0xA0000000, 'SEQ', - u"", - []) - self.MMDDENOMINIT_CALC = RM_Register_SEQ_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) - self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC - self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) - self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED - self.MODINDEX_CALC = RM_Register_SEQ_MODINDEX_CALC(self.zz_rmio, self.zz_label) - self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC - self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) - self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED - self.SPARE4 = RM_Register_SEQ_SPARE4(self.zz_rmio, self.zz_label) - self.zz_rdict['SPARE4'] = self.SPARE4 - self.MODEMINFO = RM_Register_SEQ_MODEMINFO(self.zz_rmio, self.zz_label) - self.zz_rdict['MODEMINFO'] = self.MODEMINFO - self.MISC = RM_Register_SEQ_MISC(self.zz_rmio, self.zz_label) - self.zz_rdict['MISC'] = self.MISC - self.PHYINFO = RM_Register_SEQ_PHYINFO(self.zz_rmio, self.zz_label) - self.zz_rdict['PHYINFO'] = self.PHYINFO - self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS.py new file mode 100644 index 0000000000..93059165ab --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS.py @@ -0,0 +1,32 @@ + +# -*- coding: utf-8 -*- + +__all__ = [ 'RM_Peripheral_SEQ_NS' ] + +from . static import Base_RM_Peripheral +from . SEQ_NS_register import * + +class RM_Peripheral_SEQ_NS(Base_RM_Peripheral): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Peripheral_SEQ_NS, self).__init__(rmio, label, + 0xB0000000, 'SEQ_NS', + u"", + []) + self.MMDDENOMINIT_CALC = RM_Register_SEQ_NS_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC + self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED + self.MODINDEX_CALC = RM_Register_SEQ_NS_MODINDEX_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC + self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED + self.SPARE4 = RM_Register_SEQ_NS_SPARE4(self.zz_rmio, self.zz_label) + self.zz_rdict['SPARE4'] = self.SPARE4 + self.MODEMINFO = RM_Register_SEQ_NS_MODEMINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['MODEMINFO'] = self.MODEMINFO + self.MISC = RM_Register_SEQ_NS_MISC(self.zz_rmio, self.zz_label) + self.zz_rdict['MISC'] = self.MISC + self.PHYINFO = RM_Register_SEQ_NS_PHYINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['PHYINFO'] = self.PHYINFO + self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS_field.py new file mode 100644 index 0000000000..d576504640 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS_field.py @@ -0,0 +1,366 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Field + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_NS.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_NS.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_NS.MODINDEX_CALC.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_NS.MODINDEX_CALC.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_NS.MODINDEX_CALC.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_NS.MODINDEX_CALC.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_NS.MODINDEX_CALC.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_NS.MODINDEX_CALC.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_SPARE4_SPARE4(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_SPARE4_SPARE4, self).__init__(register, + 'SPARE4', 'SEQ_NS.SPARE4.SPARE4', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN, self).__init__(register, + 'LEGACY_EN', 'SEQ_NS.MODEMINFO.LEGACY_EN', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE0, self).__init__(register, + 'SPARE0', 'SEQ_NS.MODEMINFO.SPARE0', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_TRECS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_TRECS_EN, self).__init__(register, + 'TRECS_EN', 'SEQ_NS.MODEMINFO.TRECS_EN', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_BCR_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_BCR_EN, self).__init__(register, + 'BCR_EN', 'SEQ_NS.MODEMINFO.BCR_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN, self).__init__(register, + 'COHERENT_EN', 'SEQ_NS.MODEMINFO.COHERENT_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN, self).__init__(register, + 'LONGRANGE_EN', 'SEQ_NS.MODEMINFO.LONGRANGE_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN, self).__init__(register, + 'ENHDSSS_EN', 'SEQ_NS.MODEMINFO.ENHDSSS_EN', 'read-write', + u"", + 6, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE1, self).__init__(register, + 'SPARE1', 'SEQ_NS.MODEMINFO.SPARE1', 'read-write', + u"", + 7, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN, self).__init__(register, + 'SOFTMODEM_EN', 'SEQ_NS.MODEMINFO.SOFTMODEM_EN', 'read-write', + u"", + 8, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_BTC_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_BTC_EN, self).__init__(register, + 'BTC_EN', 'SEQ_NS.MODEMINFO.BTC_EN', 'read-write', + u"", + 9, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE2, self).__init__(register, + 'SPARE2', 'SEQ_NS.MODEMINFO.SPARE2', 'read-write', + u"", + 10, 22) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED10(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED10, self).__init__(register, + 'RESERVED10', 'SEQ_NS.MISC.RESERVED10', 'read-write', + u"", + 10, 2) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN, self).__init__(register, + 'SYNTH_MODE_TX00D_EN', 'SEQ_NS.MISC.SYNTH_MODE_TX00D_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ_NS.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ_NS.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED2, self).__init__(register, + 'RESERVED2', 'SEQ_NS.MISC.RESERVED2', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED1, self).__init__(register, + 'RESERVED1', 'SEQ_NS.MISC.RESERVED1', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED0, self).__init__(register, + 'RESERVED0', 'SEQ_NS.MISC.RESERVED0', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_PHYINFO_ADDRESS(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_PHYINFO_ADDRESS, self).__init__(register, + 'ADDRESS', 'SEQ_NS.PHYINFO.ADDRESS', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS_register.py new file mode 100644 index 0000000000..9750742d78 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_NS_register.py @@ -0,0 +1,191 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Register +from . SEQ_NS_field import * + + +class RM_Register_SEQ_NS_MMDDENOMINIT_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MMDDENOMINIT_CALC, self).__init__(rmio, label, + 0xb0000000, 0x000, + 'MMDDENOMINIT_CALC', 'SEQ_NS.MMDDENOMINIT_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, + 0xb0000000, 0x004, + 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODINDEX_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODINDEX_CALC, self).__init__(rmio, label, + 0xb0000000, 0x008, + 'MODINDEX_CALC', 'SEQ_NS.MODINDEX_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, + 0xb0000000, 0x00C, + 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_SPARE4(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_SPARE4, self).__init__(rmio, label, + 0xb0000000, 0x010, + 'SPARE4', 'SEQ_NS.SPARE4', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.SPARE4 = RM_Field_SEQ_NS_SPARE4_SPARE4(self) + self.zz_fdict['SPARE4'] = self.SPARE4 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODEMINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODEMINFO, self).__init__(rmio, label, + 0xb0000000, 0x014, + 'MODEMINFO', 'SEQ_NS.MODEMINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.LEGACY_EN = RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN(self) + self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN + self.SPARE0 = RM_Field_SEQ_NS_MODEMINFO_SPARE0(self) + self.zz_fdict['SPARE0'] = self.SPARE0 + self.TRECS_EN = RM_Field_SEQ_NS_MODEMINFO_TRECS_EN(self) + self.zz_fdict['TRECS_EN'] = self.TRECS_EN + self.BCR_EN = RM_Field_SEQ_NS_MODEMINFO_BCR_EN(self) + self.zz_fdict['BCR_EN'] = self.BCR_EN + self.COHERENT_EN = RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN(self) + self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN + self.LONGRANGE_EN = RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN(self) + self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN + self.ENHDSSS_EN = RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN(self) + self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN + self.SPARE1 = RM_Field_SEQ_NS_MODEMINFO_SPARE1(self) + self.zz_fdict['SPARE1'] = self.SPARE1 + self.SOFTMODEM_EN = RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN(self) + self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN + self.BTC_EN = RM_Field_SEQ_NS_MODEMINFO_BTC_EN(self) + self.zz_fdict['BTC_EN'] = self.BTC_EN + self.SPARE2 = RM_Field_SEQ_NS_MODEMINFO_SPARE2(self) + self.zz_fdict['SPARE2'] = self.SPARE2 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MISC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MISC, self).__init__(rmio, label, + 0xb0000000, 0x018, + 'MISC', 'SEQ_NS.MISC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.RESERVED10 = RM_Field_SEQ_NS_MISC_RESERVED10(self) + self.zz_fdict['RESERVED10'] = self.RESERVED10 + self.SYNTH_MODE_TX00D_EN = RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN(self) + self.zz_fdict['SYNTH_MODE_TX00D_EN'] = self.SYNTH_MODE_TX00D_EN + self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN + self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN + self.RESERVED2 = RM_Field_SEQ_NS_MISC_RESERVED2(self) + self.zz_fdict['RESERVED2'] = self.RESERVED2 + self.RESERVED1 = RM_Field_SEQ_NS_MISC_RESERVED1(self) + self.zz_fdict['RESERVED1'] = self.RESERVED1 + self.RESERVED0 = RM_Field_SEQ_NS_MISC_RESERVED0(self) + self.zz_fdict['RESERVED0'] = self.RESERVED0 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_PHYINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_PHYINFO, self).__init__(rmio, label, + 0xb0000000, 0x01C, + 'PHYINFO', 'SEQ_NS.PHYINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.ADDRESS = RM_Field_SEQ_NS_PHYINFO_ADDRESS(self) + self.zz_fdict['ADDRESS'] = self.ADDRESS + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S.py new file mode 100644 index 0000000000..a7646c6d63 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S.py @@ -0,0 +1,32 @@ + +# -*- coding: utf-8 -*- + +__all__ = [ 'RM_Peripheral_SEQ_S' ] + +from . static import Base_RM_Peripheral +from . SEQ_S_register import * + +class RM_Peripheral_SEQ_S(Base_RM_Peripheral): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Peripheral_SEQ_S, self).__init__(rmio, label, + 0xA0000000, 'SEQ_S', + u"", + []) + self.MMDDENOMINIT_CALC = RM_Register_SEQ_S_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC + self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED + self.MODINDEX_CALC = RM_Register_SEQ_S_MODINDEX_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC + self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED + self.SPARE4 = RM_Register_SEQ_S_SPARE4(self.zz_rmio, self.zz_label) + self.zz_rdict['SPARE4'] = self.SPARE4 + self.MODEMINFO = RM_Register_SEQ_S_MODEMINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['MODEMINFO'] = self.MODEMINFO + self.MISC = RM_Register_SEQ_S_MISC(self.zz_rmio, self.zz_label) + self.zz_rdict['MISC'] = self.MISC + self.PHYINFO = RM_Register_SEQ_S_PHYINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['PHYINFO'] = self.PHYINFO + self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S_field.py new file mode 100644 index 0000000000..a40b470b26 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S_field.py @@ -0,0 +1,366 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Field + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_S.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_S.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_S.MODINDEX_CALC.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_S.MODINDEX_CALC.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_S.MODINDEX_CALC.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_S.MODINDEX_CALC.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_S.MODINDEX_CALC.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_S.MODINDEX_CALC.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_SPARE4_SPARE4(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_SPARE4_SPARE4, self).__init__(register, + 'SPARE4', 'SEQ_S.SPARE4.SPARE4', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_LEGACY_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_LEGACY_EN, self).__init__(register, + 'LEGACY_EN', 'SEQ_S.MODEMINFO.LEGACY_EN', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE0, self).__init__(register, + 'SPARE0', 'SEQ_S.MODEMINFO.SPARE0', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_TRECS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_TRECS_EN, self).__init__(register, + 'TRECS_EN', 'SEQ_S.MODEMINFO.TRECS_EN', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_BCR_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_BCR_EN, self).__init__(register, + 'BCR_EN', 'SEQ_S.MODEMINFO.BCR_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_COHERENT_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_COHERENT_EN, self).__init__(register, + 'COHERENT_EN', 'SEQ_S.MODEMINFO.COHERENT_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN, self).__init__(register, + 'LONGRANGE_EN', 'SEQ_S.MODEMINFO.LONGRANGE_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN, self).__init__(register, + 'ENHDSSS_EN', 'SEQ_S.MODEMINFO.ENHDSSS_EN', 'read-write', + u"", + 6, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE1, self).__init__(register, + 'SPARE1', 'SEQ_S.MODEMINFO.SPARE1', 'read-write', + u"", + 7, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN, self).__init__(register, + 'SOFTMODEM_EN', 'SEQ_S.MODEMINFO.SOFTMODEM_EN', 'read-write', + u"", + 8, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_BTC_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_BTC_EN, self).__init__(register, + 'BTC_EN', 'SEQ_S.MODEMINFO.BTC_EN', 'read-write', + u"", + 9, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE2, self).__init__(register, + 'SPARE2', 'SEQ_S.MODEMINFO.SPARE2', 'read-write', + u"", + 10, 22) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED10(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED10, self).__init__(register, + 'RESERVED10', 'SEQ_S.MISC.RESERVED10', 'read-write', + u"", + 10, 2) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN, self).__init__(register, + 'SYNTH_MODE_TX00D_EN', 'SEQ_S.MISC.SYNTH_MODE_TX00D_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ_S.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ_S.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED2, self).__init__(register, + 'RESERVED2', 'SEQ_S.MISC.RESERVED2', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED1, self).__init__(register, + 'RESERVED1', 'SEQ_S.MISC.RESERVED1', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED0, self).__init__(register, + 'RESERVED0', 'SEQ_S.MISC.RESERVED0', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_PHYINFO_ADDRESS(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_PHYINFO_ADDRESS, self).__init__(register, + 'ADDRESS', 'SEQ_S.PHYINFO.ADDRESS', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S_register.py new file mode 100644 index 0000000000..f506b7e389 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_S_register.py @@ -0,0 +1,191 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Register +from . SEQ_S_field import * + + +class RM_Register_SEQ_S_MMDDENOMINIT_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MMDDENOMINIT_CALC, self).__init__(rmio, label, + 0xa0000000, 0x000, + 'MMDDENOMINIT_CALC', 'SEQ_S.MMDDENOMINIT_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, + 0xa0000000, 0x004, + 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODINDEX_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODINDEX_CALC, self).__init__(rmio, label, + 0xa0000000, 0x008, + 'MODINDEX_CALC', 'SEQ_S.MODINDEX_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, + 0xa0000000, 0x00C, + 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_SPARE4(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_SPARE4, self).__init__(rmio, label, + 0xa0000000, 0x010, + 'SPARE4', 'SEQ_S.SPARE4', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.SPARE4 = RM_Field_SEQ_S_SPARE4_SPARE4(self) + self.zz_fdict['SPARE4'] = self.SPARE4 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODEMINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODEMINFO, self).__init__(rmio, label, + 0xa0000000, 0x014, + 'MODEMINFO', 'SEQ_S.MODEMINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.LEGACY_EN = RM_Field_SEQ_S_MODEMINFO_LEGACY_EN(self) + self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN + self.SPARE0 = RM_Field_SEQ_S_MODEMINFO_SPARE0(self) + self.zz_fdict['SPARE0'] = self.SPARE0 + self.TRECS_EN = RM_Field_SEQ_S_MODEMINFO_TRECS_EN(self) + self.zz_fdict['TRECS_EN'] = self.TRECS_EN + self.BCR_EN = RM_Field_SEQ_S_MODEMINFO_BCR_EN(self) + self.zz_fdict['BCR_EN'] = self.BCR_EN + self.COHERENT_EN = RM_Field_SEQ_S_MODEMINFO_COHERENT_EN(self) + self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN + self.LONGRANGE_EN = RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN(self) + self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN + self.ENHDSSS_EN = RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN(self) + self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN + self.SPARE1 = RM_Field_SEQ_S_MODEMINFO_SPARE1(self) + self.zz_fdict['SPARE1'] = self.SPARE1 + self.SOFTMODEM_EN = RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN(self) + self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN + self.BTC_EN = RM_Field_SEQ_S_MODEMINFO_BTC_EN(self) + self.zz_fdict['BTC_EN'] = self.BTC_EN + self.SPARE2 = RM_Field_SEQ_S_MODEMINFO_SPARE2(self) + self.zz_fdict['SPARE2'] = self.SPARE2 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MISC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MISC, self).__init__(rmio, label, + 0xa0000000, 0x018, + 'MISC', 'SEQ_S.MISC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.RESERVED10 = RM_Field_SEQ_S_MISC_RESERVED10(self) + self.zz_fdict['RESERVED10'] = self.RESERVED10 + self.SYNTH_MODE_TX00D_EN = RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN(self) + self.zz_fdict['SYNTH_MODE_TX00D_EN'] = self.SYNTH_MODE_TX00D_EN + self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN + self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN + self.RESERVED2 = RM_Field_SEQ_S_MISC_RESERVED2(self) + self.zz_fdict['RESERVED2'] = self.RESERVED2 + self.RESERVED1 = RM_Field_SEQ_S_MISC_RESERVED1(self) + self.zz_fdict['RESERVED1'] = self.RESERVED1 + self.RESERVED0 = RM_Field_SEQ_S_MISC_RESERVED0(self) + self.zz_fdict['RESERVED0'] = self.RESERVED0 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_PHYINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_PHYINFO, self).__init__(rmio, label, + 0xa0000000, 0x01C, + 'PHYINFO', 'SEQ_S.PHYINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.ADDRESS = RM_Field_SEQ_S_PHYINFO_ADDRESS(self) + self.zz_fdict['ADDRESS'] = self.ADDRESS + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_field.py deleted file mode 100644 index 06656c939c..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_field.py +++ /dev/null @@ -1,356 +0,0 @@ - -# -*- coding: utf-8 -*- - -from . static import Base_RM_Field - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, - 'DENOMINIT0', 'SEQ.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', - u"", - 0, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, - 'DENOMINIT1', 'SEQ.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', - u"", - 9, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, - 'DENOMINIT0', 'SEQ.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', - u"", - 0, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, - 'DENOMINIT1', 'SEQ.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', - u"", - 9, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXM, self).__init__(register, - 'MODINDEXM', 'SEQ.MODINDEX_CALC.MODINDEXM', 'read-write', - u"", - 0, 8) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE, self).__init__(register, - 'MODINDEXE', 'SEQ.MODINDEX_CALC.MODINDEXE', 'read-write', - u"", - 8, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_FREQGAINE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_FREQGAINE, self).__init__(register, - 'FREQGAINE', 'SEQ.MODINDEX_CALC.FREQGAINE', 'read-write', - u"", - 13, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_FREQGAINM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_FREQGAINM, self).__init__(register, - 'FREQGAINM', 'SEQ.MODINDEX_CALC.FREQGAINM', 'read-write', - u"", - 16, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, - 'AMMODINDEXM', 'SEQ.MODINDEX_CALC.AMMODINDEXM', 'read-write', - u"", - 19, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, - 'AMMODINDEXE', 'SEQ.MODINDEX_CALC.AMMODINDEXE', 'read-write', - u"", - 24, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, - 'MODINDEXM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', - u"", - 0, 8) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, - 'MODINDEXE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', - u"", - 8, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, - 'FREQGAINE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', - u"", - 13, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, - 'FREQGAINM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', - u"", - 16, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, - 'AMMODINDEXM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', - u"", - 19, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, - 'AMMODINDEXE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', - u"", - 24, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_SPARE4_SPARE4(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_SPARE4_SPARE4, self).__init__(register, - 'SPARE4', 'SEQ.SPARE4.SPARE4', 'read-write', - u"", - 0, 32) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_LEGACY_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_LEGACY_EN, self).__init__(register, - 'LEGACY_EN', 'SEQ.MODEMINFO.LEGACY_EN', 'read-write', - u"", - 0, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE0, self).__init__(register, - 'SPARE0', 'SEQ.MODEMINFO.SPARE0', 'read-write', - u"", - 1, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_TRECS_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_TRECS_EN, self).__init__(register, - 'TRECS_EN', 'SEQ.MODEMINFO.TRECS_EN', 'read-write', - u"", - 2, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_BCR_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_BCR_EN, self).__init__(register, - 'BCR_EN', 'SEQ.MODEMINFO.BCR_EN', 'read-write', - u"", - 3, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_COHERENT_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_COHERENT_EN, self).__init__(register, - 'COHERENT_EN', 'SEQ.MODEMINFO.COHERENT_EN', 'read-write', - u"", - 4, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_LONGRANGE_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_LONGRANGE_EN, self).__init__(register, - 'LONGRANGE_EN', 'SEQ.MODEMINFO.LONGRANGE_EN', 'read-write', - u"", - 5, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_ENHDSSS_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_ENHDSSS_EN, self).__init__(register, - 'ENHDSSS_EN', 'SEQ.MODEMINFO.ENHDSSS_EN', 'read-write', - u"", - 6, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE1, self).__init__(register, - 'SPARE1', 'SEQ.MODEMINFO.SPARE1', 'read-write', - u"", - 7, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN, self).__init__(register, - 'SOFTMODEM_EN', 'SEQ.MODEMINFO.SOFTMODEM_EN', 'read-write', - u"", - 8, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_BTC_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_BTC_EN, self).__init__(register, - 'BTC_EN', 'SEQ.MODEMINFO.BTC_EN', 'read-write', - u"", - 9, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE2(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE2, self).__init__(register, - 'SPARE2', 'SEQ.MODEMINFO.SPARE2', 'read-write', - u"", - 10, 22) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED10(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED10, self).__init__(register, - 'RESERVED10', 'SEQ.MISC.RESERVED10', 'read-write', - u"", - 10, 2) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, - 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', - u"", - 4, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, - 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', - u"", - 3, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED2(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED2, self).__init__(register, - 'RESERVED2', 'SEQ.MISC.RESERVED2', 'read-write', - u"", - 2, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED1, self).__init__(register, - 'RESERVED1', 'SEQ.MISC.RESERVED1', 'read-write', - u"", - 1, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED0, self).__init__(register, - 'RESERVED0', 'SEQ.MISC.RESERVED0', 'read-write', - u"", - 0, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_PHYINFO_ADDRESS(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_PHYINFO_ADDRESS, self).__init__(register, - 'ADDRESS', 'SEQ.PHYINFO.ADDRESS', 'read-write', - u"", - 0, 32) - self.__dict__['zz_frozen'] = True - - diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_register.py deleted file mode 100644 index f4a745a31d..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/SEQ_register.py +++ /dev/null @@ -1,189 +0,0 @@ - -# -*- coding: utf-8 -*- - -from . static import Base_RM_Register -from . SEQ_field import * - - -class RM_Register_SEQ_MMDDENOMINIT_CALC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MMDDENOMINIT_CALC, self).__init__(rmio, label, - 0xa0000000, 0x000, - 'MMDDENOMINIT_CALC', 'SEQ.MMDDENOMINIT_CALC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.DENOMINIT0 = RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0(self) - self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 - self.DENOMINIT1 = RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1(self) - self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, - 0xa0000000, 0x004, - 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ.MMDDENOMINIT_CALC_DOUBLED', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.DENOMINIT0 = RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) - self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 - self.DENOMINIT1 = RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) - self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODINDEX_CALC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODINDEX_CALC, self).__init__(rmio, label, - 0xa0000000, 0x008, - 'MODINDEX_CALC', 'SEQ.MODINDEX_CALC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.MODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXM(self) - self.zz_fdict['MODINDEXM'] = self.MODINDEXM - self.MODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE(self) - self.zz_fdict['MODINDEXE'] = self.MODINDEXE - self.FREQGAINE = RM_Field_SEQ_MODINDEX_CALC_FREQGAINE(self) - self.zz_fdict['FREQGAINE'] = self.FREQGAINE - self.FREQGAINM = RM_Field_SEQ_MODINDEX_CALC_FREQGAINM(self) - self.zz_fdict['FREQGAINM'] = self.FREQGAINM - self.AMMODINDEXM = RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM(self) - self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM - self.AMMODINDEXE = RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE(self) - self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, - 0xa0000000, 0x00C, - 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.MODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) - self.zz_fdict['MODINDEXM'] = self.MODINDEXM - self.MODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) - self.zz_fdict['MODINDEXE'] = self.MODINDEXE - self.FREQGAINE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) - self.zz_fdict['FREQGAINE'] = self.FREQGAINE - self.FREQGAINM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) - self.zz_fdict['FREQGAINM'] = self.FREQGAINM - self.AMMODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) - self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM - self.AMMODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) - self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_SPARE4(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_SPARE4, self).__init__(rmio, label, - 0xa0000000, 0x010, - 'SPARE4', 'SEQ.SPARE4', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.SPARE4 = RM_Field_SEQ_SPARE4_SPARE4(self) - self.zz_fdict['SPARE4'] = self.SPARE4 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODEMINFO(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODEMINFO, self).__init__(rmio, label, - 0xa0000000, 0x014, - 'MODEMINFO', 'SEQ.MODEMINFO', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.LEGACY_EN = RM_Field_SEQ_MODEMINFO_LEGACY_EN(self) - self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN - self.SPARE0 = RM_Field_SEQ_MODEMINFO_SPARE0(self) - self.zz_fdict['SPARE0'] = self.SPARE0 - self.TRECS_EN = RM_Field_SEQ_MODEMINFO_TRECS_EN(self) - self.zz_fdict['TRECS_EN'] = self.TRECS_EN - self.BCR_EN = RM_Field_SEQ_MODEMINFO_BCR_EN(self) - self.zz_fdict['BCR_EN'] = self.BCR_EN - self.COHERENT_EN = RM_Field_SEQ_MODEMINFO_COHERENT_EN(self) - self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN - self.LONGRANGE_EN = RM_Field_SEQ_MODEMINFO_LONGRANGE_EN(self) - self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN - self.ENHDSSS_EN = RM_Field_SEQ_MODEMINFO_ENHDSSS_EN(self) - self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN - self.SPARE1 = RM_Field_SEQ_MODEMINFO_SPARE1(self) - self.zz_fdict['SPARE1'] = self.SPARE1 - self.SOFTMODEM_EN = RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN(self) - self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN - self.BTC_EN = RM_Field_SEQ_MODEMINFO_BTC_EN(self) - self.zz_fdict['BTC_EN'] = self.BTC_EN - self.SPARE2 = RM_Field_SEQ_MODEMINFO_SPARE2(self) - self.zz_fdict['SPARE2'] = self.SPARE2 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MISC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MISC, self).__init__(rmio, label, - 0xa0000000, 0x018, - 'MISC', 'SEQ.MISC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.RESERVED10 = RM_Field_SEQ_MISC_RESERVED10(self) - self.zz_fdict['RESERVED10'] = self.RESERVED10 - self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN(self) - self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN - self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN(self) - self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN - self.RESERVED2 = RM_Field_SEQ_MISC_RESERVED2(self) - self.zz_fdict['RESERVED2'] = self.RESERVED2 - self.RESERVED1 = RM_Field_SEQ_MISC_RESERVED1(self) - self.zz_fdict['RESERVED1'] = self.RESERVED1 - self.RESERVED0 = RM_Field_SEQ_MISC_RESERVED0(self) - self.zz_fdict['RESERVED0'] = self.RESERVED0 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_PHYINFO(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_PHYINFO, self).__init__(rmio, label, - 0xa0000000, 0x01C, - 'PHYINFO', 'SEQ.PHYINFO', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.ADDRESS = RM_Field_SEQ_PHYINFO_ADDRESS(self) - self.zz_fdict['ADDRESS'] = self.ADDRESS - self.__dict__['zz_frozen'] = True - - diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/device.py index ba934f139e..4108ee9548 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revA1/device.py @@ -35,7 +35,8 @@ from . RAC_S import * from . RFCRC_NS import * from . RFCRC_S import * -from . SEQ import * +from . SEQ_NS import * +from . SEQ_S import * from . SYNTH_NS import * from . SYNTH_S import * @@ -113,7 +114,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_SIXG301XFULL_RevA1, self).__init__(rmio, label, 'SIXG301XFULL', - RM_SVD_Info('SIXG301XFULL_SEQ.svd', '29b658b42da0f8d838cb8778b74ae57a')) + RM_SVD_Info('SIXG301XFULL_SEQ.svd', '014c0f66318de0c5fafe6261faa8f1d8')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS @@ -135,8 +136,10 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.zz_pdict['RFCRC_NS'] = self.RFCRC_NS self.RFCRC_S = RM_Peripheral_RFCRC_S(self.zz_rmio, self.zz_label) self.zz_pdict['RFCRC_S'] = self.RFCRC_S - self.SEQ = RM_Peripheral_SEQ(self.zz_rmio, self.zz_label) - self.zz_pdict['SEQ'] = self.SEQ + self.SEQ_NS = RM_Peripheral_SEQ_NS(self.zz_rmio, self.zz_label) + self.zz_pdict['SEQ_NS'] = self.SEQ_NS + self.SEQ_S = RM_Peripheral_SEQ_S(self.zz_rmio, self.zz_label) + self.zz_pdict['SEQ_S'] = self.SEQ_S self.SYNTH_NS = RM_Peripheral_SYNTH_NS(self.zz_rmio, self.zz_label) self.zz_pdict['SYNTH_NS'] = self.SYNTH_NS self.SYNTH_S = RM_Peripheral_SYNTH_S(self.zz_rmio, self.zz_label) @@ -148,6 +151,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.MODEM = self.MODEM_S self.RAC = self.RAC_S self.RFCRC = self.RFCRC_S + self.SEQ = self.SEQ_S self.SYNTH = self.SYNTH_S pass elif default_tz_access_mode == RM_TrustZone_Access_Mode.TZ_NONSECURE: @@ -156,6 +160,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.MODEM = self.MODEM_NS self.RAC = self.RAC_NS self.RFCRC = self.RFCRC_NS + self.SEQ = self.SEQ_NS self.SYNTH = self.SYNTH_NS pass diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ.py deleted file mode 100644 index 242b481fe6..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ.py +++ /dev/null @@ -1,32 +0,0 @@ - -# -*- coding: utf-8 -*- - -__all__ = [ 'RM_Peripheral_SEQ' ] - -from . static import Base_RM_Peripheral -from . SEQ_register import * - -class RM_Peripheral_SEQ(Base_RM_Peripheral): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Peripheral_SEQ, self).__init__(rmio, label, - 0xA0000000, 'SEQ', - u"", - []) - self.MMDDENOMINIT_CALC = RM_Register_SEQ_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) - self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC - self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) - self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED - self.MODINDEX_CALC = RM_Register_SEQ_MODINDEX_CALC(self.zz_rmio, self.zz_label) - self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC - self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) - self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED - self.SPARE4 = RM_Register_SEQ_SPARE4(self.zz_rmio, self.zz_label) - self.zz_rdict['SPARE4'] = self.SPARE4 - self.MODEMINFO = RM_Register_SEQ_MODEMINFO(self.zz_rmio, self.zz_label) - self.zz_rdict['MODEMINFO'] = self.MODEMINFO - self.MISC = RM_Register_SEQ_MISC(self.zz_rmio, self.zz_label) - self.zz_rdict['MISC'] = self.MISC - self.PHYINFO = RM_Register_SEQ_PHYINFO(self.zz_rmio, self.zz_label) - self.zz_rdict['PHYINFO'] = self.PHYINFO - self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS.py new file mode 100644 index 0000000000..270da9960d --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS.py @@ -0,0 +1,32 @@ + +# -*- coding: utf-8 -*- + +__all__ = [ 'RM_Peripheral_SEQ_NS' ] + +from . static import Base_RM_Peripheral +from . SEQ_NS_register import * + +class RM_Peripheral_SEQ_NS(Base_RM_Peripheral): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Peripheral_SEQ_NS, self).__init__(rmio, label, + 0xA0000000, 'SEQ_NS', + u"", + []) + self.MMDDENOMINIT_CALC = RM_Register_SEQ_NS_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC + self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED + self.MODINDEX_CALC = RM_Register_SEQ_NS_MODINDEX_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC + self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED + self.SPARE4 = RM_Register_SEQ_NS_SPARE4(self.zz_rmio, self.zz_label) + self.zz_rdict['SPARE4'] = self.SPARE4 + self.MODEMINFO = RM_Register_SEQ_NS_MODEMINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['MODEMINFO'] = self.MODEMINFO + self.MISC = RM_Register_SEQ_NS_MISC(self.zz_rmio, self.zz_label) + self.zz_rdict['MISC'] = self.MISC + self.PHYINFO = RM_Register_SEQ_NS_PHYINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['PHYINFO'] = self.PHYINFO + self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS_field.py new file mode 100644 index 0000000000..d576504640 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS_field.py @@ -0,0 +1,366 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Field + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_NS.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_NS.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_NS.MODINDEX_CALC.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_NS.MODINDEX_CALC.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_NS.MODINDEX_CALC.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_NS.MODINDEX_CALC.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_NS.MODINDEX_CALC.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_NS.MODINDEX_CALC.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_SPARE4_SPARE4(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_SPARE4_SPARE4, self).__init__(register, + 'SPARE4', 'SEQ_NS.SPARE4.SPARE4', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN, self).__init__(register, + 'LEGACY_EN', 'SEQ_NS.MODEMINFO.LEGACY_EN', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE0, self).__init__(register, + 'SPARE0', 'SEQ_NS.MODEMINFO.SPARE0', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_TRECS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_TRECS_EN, self).__init__(register, + 'TRECS_EN', 'SEQ_NS.MODEMINFO.TRECS_EN', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_BCR_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_BCR_EN, self).__init__(register, + 'BCR_EN', 'SEQ_NS.MODEMINFO.BCR_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN, self).__init__(register, + 'COHERENT_EN', 'SEQ_NS.MODEMINFO.COHERENT_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN, self).__init__(register, + 'LONGRANGE_EN', 'SEQ_NS.MODEMINFO.LONGRANGE_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN, self).__init__(register, + 'ENHDSSS_EN', 'SEQ_NS.MODEMINFO.ENHDSSS_EN', 'read-write', + u"", + 6, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE1, self).__init__(register, + 'SPARE1', 'SEQ_NS.MODEMINFO.SPARE1', 'read-write', + u"", + 7, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN, self).__init__(register, + 'SOFTMODEM_EN', 'SEQ_NS.MODEMINFO.SOFTMODEM_EN', 'read-write', + u"", + 8, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_BTC_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_BTC_EN, self).__init__(register, + 'BTC_EN', 'SEQ_NS.MODEMINFO.BTC_EN', 'read-write', + u"", + 9, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MODEMINFO_SPARE2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MODEMINFO_SPARE2, self).__init__(register, + 'SPARE2', 'SEQ_NS.MODEMINFO.SPARE2', 'read-write', + u"", + 10, 22) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED10(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED10, self).__init__(register, + 'RESERVED10', 'SEQ_NS.MISC.RESERVED10', 'read-write', + u"", + 10, 2) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN, self).__init__(register, + 'SYNTH_MODE_TX00D_EN', 'SEQ_NS.MISC.SYNTH_MODE_TX00D_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ_NS.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ_NS.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED2, self).__init__(register, + 'RESERVED2', 'SEQ_NS.MISC.RESERVED2', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED1, self).__init__(register, + 'RESERVED1', 'SEQ_NS.MISC.RESERVED1', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_MISC_RESERVED0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_MISC_RESERVED0, self).__init__(register, + 'RESERVED0', 'SEQ_NS.MISC.RESERVED0', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_NS_PHYINFO_ADDRESS(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_NS_PHYINFO_ADDRESS, self).__init__(register, + 'ADDRESS', 'SEQ_NS.PHYINFO.ADDRESS', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS_register.py new file mode 100644 index 0000000000..0f2b136512 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_NS_register.py @@ -0,0 +1,191 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Register +from . SEQ_NS_field import * + + +class RM_Register_SEQ_NS_MMDDENOMINIT_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MMDDENOMINIT_CALC, self).__init__(rmio, label, + 0xa0000000, 0x000, + 'MMDDENOMINIT_CALC', 'SEQ_NS.MMDDENOMINIT_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, + 0xa0000000, 0x004, + 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ_NS.MMDDENOMINIT_CALC_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_NS_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODINDEX_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODINDEX_CALC, self).__init__(rmio, label, + 0xa0000000, 0x008, + 'MODINDEX_CALC', 'SEQ_NS.MODINDEX_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_NS_MODINDEX_CALC_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, + 0xa0000000, 0x00C, + 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ_NS.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_NS_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_SPARE4(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_SPARE4, self).__init__(rmio, label, + 0xa0000000, 0x010, + 'SPARE4', 'SEQ_NS.SPARE4', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.SPARE4 = RM_Field_SEQ_NS_SPARE4_SPARE4(self) + self.zz_fdict['SPARE4'] = self.SPARE4 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MODEMINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MODEMINFO, self).__init__(rmio, label, + 0xa0000000, 0x014, + 'MODEMINFO', 'SEQ_NS.MODEMINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.LEGACY_EN = RM_Field_SEQ_NS_MODEMINFO_LEGACY_EN(self) + self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN + self.SPARE0 = RM_Field_SEQ_NS_MODEMINFO_SPARE0(self) + self.zz_fdict['SPARE0'] = self.SPARE0 + self.TRECS_EN = RM_Field_SEQ_NS_MODEMINFO_TRECS_EN(self) + self.zz_fdict['TRECS_EN'] = self.TRECS_EN + self.BCR_EN = RM_Field_SEQ_NS_MODEMINFO_BCR_EN(self) + self.zz_fdict['BCR_EN'] = self.BCR_EN + self.COHERENT_EN = RM_Field_SEQ_NS_MODEMINFO_COHERENT_EN(self) + self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN + self.LONGRANGE_EN = RM_Field_SEQ_NS_MODEMINFO_LONGRANGE_EN(self) + self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN + self.ENHDSSS_EN = RM_Field_SEQ_NS_MODEMINFO_ENHDSSS_EN(self) + self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN + self.SPARE1 = RM_Field_SEQ_NS_MODEMINFO_SPARE1(self) + self.zz_fdict['SPARE1'] = self.SPARE1 + self.SOFTMODEM_EN = RM_Field_SEQ_NS_MODEMINFO_SOFTMODEM_EN(self) + self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN + self.BTC_EN = RM_Field_SEQ_NS_MODEMINFO_BTC_EN(self) + self.zz_fdict['BTC_EN'] = self.BTC_EN + self.SPARE2 = RM_Field_SEQ_NS_MODEMINFO_SPARE2(self) + self.zz_fdict['SPARE2'] = self.SPARE2 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_MISC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_MISC, self).__init__(rmio, label, + 0xa0000000, 0x018, + 'MISC', 'SEQ_NS.MISC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.RESERVED10 = RM_Field_SEQ_NS_MISC_RESERVED10(self) + self.zz_fdict['RESERVED10'] = self.RESERVED10 + self.SYNTH_MODE_TX00D_EN = RM_Field_SEQ_NS_MISC_SYNTH_MODE_TX00D_EN(self) + self.zz_fdict['SYNTH_MODE_TX00D_EN'] = self.SYNTH_MODE_TX00D_EN + self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_NS_MISC_IFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN + self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_NS_MISC_RFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN + self.RESERVED2 = RM_Field_SEQ_NS_MISC_RESERVED2(self) + self.zz_fdict['RESERVED2'] = self.RESERVED2 + self.RESERVED1 = RM_Field_SEQ_NS_MISC_RESERVED1(self) + self.zz_fdict['RESERVED1'] = self.RESERVED1 + self.RESERVED0 = RM_Field_SEQ_NS_MISC_RESERVED0(self) + self.zz_fdict['RESERVED0'] = self.RESERVED0 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_NS_PHYINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_NS_PHYINFO, self).__init__(rmio, label, + 0xa0000000, 0x01C, + 'PHYINFO', 'SEQ_NS.PHYINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.ADDRESS = RM_Field_SEQ_NS_PHYINFO_ADDRESS(self) + self.zz_fdict['ADDRESS'] = self.ADDRESS + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S.py new file mode 100644 index 0000000000..79d59161df --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S.py @@ -0,0 +1,32 @@ + +# -*- coding: utf-8 -*- + +__all__ = [ 'RM_Peripheral_SEQ_S' ] + +from . static import Base_RM_Peripheral +from . SEQ_S_register import * + +class RM_Peripheral_SEQ_S(Base_RM_Peripheral): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Peripheral_SEQ_S, self).__init__(rmio, label, + 0xB0000000, 'SEQ_S', + u"", + []) + self.MMDDENOMINIT_CALC = RM_Register_SEQ_S_MMDDENOMINIT_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC'] = self.MMDDENOMINIT_CALC + self.MMDDENOMINIT_CALC_DOUBLED = RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MMDDENOMINIT_CALC_DOUBLED'] = self.MMDDENOMINIT_CALC_DOUBLED + self.MODINDEX_CALC = RM_Register_SEQ_S_MODINDEX_CALC(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC'] = self.MODINDEX_CALC + self.MODINDEX_CALC_MODINDEXE_DOUBLED = RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED(self.zz_rmio, self.zz_label) + self.zz_rdict['MODINDEX_CALC_MODINDEXE_DOUBLED'] = self.MODINDEX_CALC_MODINDEXE_DOUBLED + self.SPARE4 = RM_Register_SEQ_S_SPARE4(self.zz_rmio, self.zz_label) + self.zz_rdict['SPARE4'] = self.SPARE4 + self.MODEMINFO = RM_Register_SEQ_S_MODEMINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['MODEMINFO'] = self.MODEMINFO + self.MISC = RM_Register_SEQ_S_MISC(self.zz_rmio, self.zz_label) + self.zz_rdict['MISC'] = self.MISC + self.PHYINFO = RM_Register_SEQ_S_PHYINFO(self.zz_rmio, self.zz_label) + self.zz_rdict['PHYINFO'] = self.PHYINFO + self.__dict__['zz_frozen'] = True \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S_field.py new file mode 100644 index 0000000000..a40b470b26 --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S_field.py @@ -0,0 +1,366 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Field + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_S.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_S.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, + 'DENOMINIT0', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', + u"", + 0, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, + 'DENOMINIT1', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', + u"", + 9, 9) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_S.MODINDEX_CALC.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_S.MODINDEX_CALC.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_S.MODINDEX_CALC.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_S.MODINDEX_CALC.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_S.MODINDEX_CALC.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_S.MODINDEX_CALC.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, + 'MODINDEXM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', + u"", + 0, 8) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, + 'MODINDEXE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', + u"", + 8, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, + 'FREQGAINE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', + u"", + 13, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, + 'FREQGAINM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', + u"", + 16, 3) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, + 'AMMODINDEXM', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', + u"", + 19, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, + 'AMMODINDEXE', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', + u"", + 24, 5) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_SPARE4_SPARE4(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_SPARE4_SPARE4, self).__init__(register, + 'SPARE4', 'SEQ_S.SPARE4.SPARE4', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_LEGACY_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_LEGACY_EN, self).__init__(register, + 'LEGACY_EN', 'SEQ_S.MODEMINFO.LEGACY_EN', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE0, self).__init__(register, + 'SPARE0', 'SEQ_S.MODEMINFO.SPARE0', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_TRECS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_TRECS_EN, self).__init__(register, + 'TRECS_EN', 'SEQ_S.MODEMINFO.TRECS_EN', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_BCR_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_BCR_EN, self).__init__(register, + 'BCR_EN', 'SEQ_S.MODEMINFO.BCR_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_COHERENT_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_COHERENT_EN, self).__init__(register, + 'COHERENT_EN', 'SEQ_S.MODEMINFO.COHERENT_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN, self).__init__(register, + 'LONGRANGE_EN', 'SEQ_S.MODEMINFO.LONGRANGE_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN, self).__init__(register, + 'ENHDSSS_EN', 'SEQ_S.MODEMINFO.ENHDSSS_EN', 'read-write', + u"", + 6, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE1, self).__init__(register, + 'SPARE1', 'SEQ_S.MODEMINFO.SPARE1', 'read-write', + u"", + 7, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN, self).__init__(register, + 'SOFTMODEM_EN', 'SEQ_S.MODEMINFO.SOFTMODEM_EN', 'read-write', + u"", + 8, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_BTC_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_BTC_EN, self).__init__(register, + 'BTC_EN', 'SEQ_S.MODEMINFO.BTC_EN', 'read-write', + u"", + 9, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MODEMINFO_SPARE2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MODEMINFO_SPARE2, self).__init__(register, + 'SPARE2', 'SEQ_S.MODEMINFO.SPARE2', 'read-write', + u"", + 10, 22) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED10(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED10, self).__init__(register, + 'RESERVED10', 'SEQ_S.MISC.RESERVED10', 'read-write', + u"", + 10, 2) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN, self).__init__(register, + 'SYNTH_MODE_TX00D_EN', 'SEQ_S.MISC.SYNTH_MODE_TX00D_EN', 'read-write', + u"", + 5, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ_S.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 4, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, + 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ_S.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', + u"", + 3, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED2(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED2, self).__init__(register, + 'RESERVED2', 'SEQ_S.MISC.RESERVED2', 'read-write', + u"", + 2, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED1(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED1, self).__init__(register, + 'RESERVED1', 'SEQ_S.MISC.RESERVED1', 'read-write', + u"", + 1, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_MISC_RESERVED0(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_MISC_RESERVED0, self).__init__(register, + 'RESERVED0', 'SEQ_S.MISC.RESERVED0', 'read-write', + u"", + 0, 1) + self.__dict__['zz_frozen'] = True + + +class RM_Field_SEQ_S_PHYINFO_ADDRESS(Base_RM_Field): + def __init__(self, register): + self.__dict__['zz_frozen'] = False + super(RM_Field_SEQ_S_PHYINFO_ADDRESS, self).__init__(register, + 'ADDRESS', 'SEQ_S.PHYINFO.ADDRESS', 'read-write', + u"", + 0, 32) + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S_register.py new file mode 100644 index 0000000000..21e9f4467f --- /dev/null +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_S_register.py @@ -0,0 +1,191 @@ + +# -*- coding: utf-8 -*- + +from . static import Base_RM_Register +from . SEQ_S_field import * + + +class RM_Register_SEQ_S_MMDDENOMINIT_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MMDDENOMINIT_CALC, self).__init__(rmio, label, + 0xb0000000, 0x000, + 'MMDDENOMINIT_CALC', 'SEQ_S.MMDDENOMINIT_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, + 0xb0000000, 0x004, + 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ_S.MMDDENOMINIT_CALC_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.DENOMINIT0 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) + self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 + self.DENOMINIT1 = RM_Field_SEQ_S_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) + self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODINDEX_CALC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODINDEX_CALC, self).__init__(rmio, label, + 0xb0000000, 0x008, + 'MODINDEX_CALC', 'SEQ_S.MODINDEX_CALC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_S_MODINDEX_CALC_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, + 0xb0000000, 0x00C, + 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ_S.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.MODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) + self.zz_fdict['MODINDEXM'] = self.MODINDEXM + self.MODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) + self.zz_fdict['MODINDEXE'] = self.MODINDEXE + self.FREQGAINE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) + self.zz_fdict['FREQGAINE'] = self.FREQGAINE + self.FREQGAINM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) + self.zz_fdict['FREQGAINM'] = self.FREQGAINM + self.AMMODINDEXM = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) + self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM + self.AMMODINDEXE = RM_Field_SEQ_S_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) + self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_SPARE4(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_SPARE4, self).__init__(rmio, label, + 0xb0000000, 0x010, + 'SPARE4', 'SEQ_S.SPARE4', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.SPARE4 = RM_Field_SEQ_S_SPARE4_SPARE4(self) + self.zz_fdict['SPARE4'] = self.SPARE4 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MODEMINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MODEMINFO, self).__init__(rmio, label, + 0xb0000000, 0x014, + 'MODEMINFO', 'SEQ_S.MODEMINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.LEGACY_EN = RM_Field_SEQ_S_MODEMINFO_LEGACY_EN(self) + self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN + self.SPARE0 = RM_Field_SEQ_S_MODEMINFO_SPARE0(self) + self.zz_fdict['SPARE0'] = self.SPARE0 + self.TRECS_EN = RM_Field_SEQ_S_MODEMINFO_TRECS_EN(self) + self.zz_fdict['TRECS_EN'] = self.TRECS_EN + self.BCR_EN = RM_Field_SEQ_S_MODEMINFO_BCR_EN(self) + self.zz_fdict['BCR_EN'] = self.BCR_EN + self.COHERENT_EN = RM_Field_SEQ_S_MODEMINFO_COHERENT_EN(self) + self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN + self.LONGRANGE_EN = RM_Field_SEQ_S_MODEMINFO_LONGRANGE_EN(self) + self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN + self.ENHDSSS_EN = RM_Field_SEQ_S_MODEMINFO_ENHDSSS_EN(self) + self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN + self.SPARE1 = RM_Field_SEQ_S_MODEMINFO_SPARE1(self) + self.zz_fdict['SPARE1'] = self.SPARE1 + self.SOFTMODEM_EN = RM_Field_SEQ_S_MODEMINFO_SOFTMODEM_EN(self) + self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN + self.BTC_EN = RM_Field_SEQ_S_MODEMINFO_BTC_EN(self) + self.zz_fdict['BTC_EN'] = self.BTC_EN + self.SPARE2 = RM_Field_SEQ_S_MODEMINFO_SPARE2(self) + self.zz_fdict['SPARE2'] = self.SPARE2 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_MISC(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_MISC, self).__init__(rmio, label, + 0xb0000000, 0x018, + 'MISC', 'SEQ_S.MISC', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.RESERVED10 = RM_Field_SEQ_S_MISC_RESERVED10(self) + self.zz_fdict['RESERVED10'] = self.RESERVED10 + self.SYNTH_MODE_TX00D_EN = RM_Field_SEQ_S_MISC_SYNTH_MODE_TX00D_EN(self) + self.zz_fdict['SYNTH_MODE_TX00D_EN'] = self.SYNTH_MODE_TX00D_EN + self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_S_MISC_IFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN + self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_S_MISC_RFPKDOFF_AFTER_FRAME_EN(self) + self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN + self.RESERVED2 = RM_Field_SEQ_S_MISC_RESERVED2(self) + self.zz_fdict['RESERVED2'] = self.RESERVED2 + self.RESERVED1 = RM_Field_SEQ_S_MISC_RESERVED1(self) + self.zz_fdict['RESERVED1'] = self.RESERVED1 + self.RESERVED0 = RM_Field_SEQ_S_MISC_RESERVED0(self) + self.zz_fdict['RESERVED0'] = self.RESERVED0 + self.__dict__['zz_frozen'] = True + + +class RM_Register_SEQ_S_PHYINFO(Base_RM_Register): + def __init__(self, rmio, label): + self.__dict__['zz_frozen'] = False + super(RM_Register_SEQ_S_PHYINFO, self).__init__(rmio, label, + 0xb0000000, 0x01C, + 'PHYINFO', 'SEQ_S.PHYINFO', 'read-write', + u"", + 0x00000000, 0x00000000, + 0x00001000, 0x00002000, + 0x00003000) + + self.ADDRESS = RM_Field_SEQ_S_PHYINFO_ADDRESS(self) + self.zz_fdict['ADDRESS'] = self.ADDRESS + self.__dict__['zz_frozen'] = True + + diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_field.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_field.py deleted file mode 100644 index 06656c939c..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_field.py +++ /dev/null @@ -1,356 +0,0 @@ - -# -*- coding: utf-8 -*- - -from . static import Base_RM_Field - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0, self).__init__(register, - 'DENOMINIT0', 'SEQ.MMDDENOMINIT_CALC.DENOMINIT0', 'read-write', - u"", - 0, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1, self).__init__(register, - 'DENOMINIT1', 'SEQ.MMDDENOMINIT_CALC.DENOMINIT1', 'read-write', - u"", - 9, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, self).__init__(register, - 'DENOMINIT0', 'SEQ.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT0', 'read-write', - u"", - 0, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, self).__init__(register, - 'DENOMINIT1', 'SEQ.MMDDENOMINIT_CALC_DOUBLED.DENOMINIT1', 'read-write', - u"", - 9, 9) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXM, self).__init__(register, - 'MODINDEXM', 'SEQ.MODINDEX_CALC.MODINDEXM', 'read-write', - u"", - 0, 8) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE, self).__init__(register, - 'MODINDEXE', 'SEQ.MODINDEX_CALC.MODINDEXE', 'read-write', - u"", - 8, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_FREQGAINE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_FREQGAINE, self).__init__(register, - 'FREQGAINE', 'SEQ.MODINDEX_CALC.FREQGAINE', 'read-write', - u"", - 13, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_FREQGAINM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_FREQGAINM, self).__init__(register, - 'FREQGAINM', 'SEQ.MODINDEX_CALC.FREQGAINM', 'read-write', - u"", - 16, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM, self).__init__(register, - 'AMMODINDEXM', 'SEQ.MODINDEX_CALC.AMMODINDEXM', 'read-write', - u"", - 19, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE, self).__init__(register, - 'AMMODINDEXE', 'SEQ.MODINDEX_CALC.AMMODINDEXE', 'read-write', - u"", - 24, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, self).__init__(register, - 'MODINDEXM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM', 'read-write', - u"", - 0, 8) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE, self).__init__(register, - 'MODINDEXE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXE', 'read-write', - u"", - 8, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, self).__init__(register, - 'FREQGAINE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', 'read-write', - u"", - 13, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, self).__init__(register, - 'FREQGAINM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', 'read-write', - u"", - 16, 3) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM, self).__init__(register, - 'AMMODINDEXM', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXM', 'read-write', - u"", - 19, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE, self).__init__(register, - 'AMMODINDEXE', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.AMMODINDEXE', 'read-write', - u"", - 24, 5) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_SPARE4_SPARE4(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_SPARE4_SPARE4, self).__init__(register, - 'SPARE4', 'SEQ.SPARE4.SPARE4', 'read-write', - u"", - 0, 32) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_LEGACY_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_LEGACY_EN, self).__init__(register, - 'LEGACY_EN', 'SEQ.MODEMINFO.LEGACY_EN', 'read-write', - u"", - 0, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE0, self).__init__(register, - 'SPARE0', 'SEQ.MODEMINFO.SPARE0', 'read-write', - u"", - 1, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_TRECS_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_TRECS_EN, self).__init__(register, - 'TRECS_EN', 'SEQ.MODEMINFO.TRECS_EN', 'read-write', - u"", - 2, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_BCR_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_BCR_EN, self).__init__(register, - 'BCR_EN', 'SEQ.MODEMINFO.BCR_EN', 'read-write', - u"", - 3, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_COHERENT_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_COHERENT_EN, self).__init__(register, - 'COHERENT_EN', 'SEQ.MODEMINFO.COHERENT_EN', 'read-write', - u"", - 4, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_LONGRANGE_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_LONGRANGE_EN, self).__init__(register, - 'LONGRANGE_EN', 'SEQ.MODEMINFO.LONGRANGE_EN', 'read-write', - u"", - 5, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_ENHDSSS_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_ENHDSSS_EN, self).__init__(register, - 'ENHDSSS_EN', 'SEQ.MODEMINFO.ENHDSSS_EN', 'read-write', - u"", - 6, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE1, self).__init__(register, - 'SPARE1', 'SEQ.MODEMINFO.SPARE1', 'read-write', - u"", - 7, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN, self).__init__(register, - 'SOFTMODEM_EN', 'SEQ.MODEMINFO.SOFTMODEM_EN', 'read-write', - u"", - 8, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_BTC_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_BTC_EN, self).__init__(register, - 'BTC_EN', 'SEQ.MODEMINFO.BTC_EN', 'read-write', - u"", - 9, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MODEMINFO_SPARE2(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MODEMINFO_SPARE2, self).__init__(register, - 'SPARE2', 'SEQ.MODEMINFO.SPARE2', 'read-write', - u"", - 10, 22) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED10(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED10, self).__init__(register, - 'RESERVED10', 'SEQ.MISC.RESERVED10', 'read-write', - u"", - 10, 2) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN, self).__init__(register, - 'IFPKDOFF_AFTER_FRAME_EN', 'SEQ.MISC.IFPKDOFF_AFTER_FRAME_EN', 'read-write', - u"", - 4, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN, self).__init__(register, - 'RFPKDOFF_AFTER_FRAME_EN', 'SEQ.MISC.RFPKDOFF_AFTER_FRAME_EN', 'read-write', - u"", - 3, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED2(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED2, self).__init__(register, - 'RESERVED2', 'SEQ.MISC.RESERVED2', 'read-write', - u"", - 2, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED1(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED1, self).__init__(register, - 'RESERVED1', 'SEQ.MISC.RESERVED1', 'read-write', - u"", - 1, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_MISC_RESERVED0(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_MISC_RESERVED0, self).__init__(register, - 'RESERVED0', 'SEQ.MISC.RESERVED0', 'read-write', - u"", - 0, 1) - self.__dict__['zz_frozen'] = True - - -class RM_Field_SEQ_PHYINFO_ADDRESS(Base_RM_Field): - def __init__(self, register): - self.__dict__['zz_frozen'] = False - super(RM_Field_SEQ_PHYINFO_ADDRESS, self).__init__(register, - 'ADDRESS', 'SEQ.PHYINFO.ADDRESS', 'read-write', - u"", - 0, 32) - self.__dict__['zz_frozen'] = True - - diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_register.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_register.py deleted file mode 100644 index f4a745a31d..0000000000 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/SEQ_register.py +++ /dev/null @@ -1,189 +0,0 @@ - -# -*- coding: utf-8 -*- - -from . static import Base_RM_Register -from . SEQ_field import * - - -class RM_Register_SEQ_MMDDENOMINIT_CALC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MMDDENOMINIT_CALC, self).__init__(rmio, label, - 0xa0000000, 0x000, - 'MMDDENOMINIT_CALC', 'SEQ.MMDDENOMINIT_CALC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.DENOMINIT0 = RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT0(self) - self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 - self.DENOMINIT1 = RM_Field_SEQ_MMDDENOMINIT_CALC_DENOMINIT1(self) - self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MMDDENOMINIT_CALC_DOUBLED, self).__init__(rmio, label, - 0xa0000000, 0x004, - 'MMDDENOMINIT_CALC_DOUBLED', 'SEQ.MMDDENOMINIT_CALC_DOUBLED', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.DENOMINIT0 = RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0(self) - self.zz_fdict['DENOMINIT0'] = self.DENOMINIT0 - self.DENOMINIT1 = RM_Field_SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1(self) - self.zz_fdict['DENOMINIT1'] = self.DENOMINIT1 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODINDEX_CALC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODINDEX_CALC, self).__init__(rmio, label, - 0xa0000000, 0x008, - 'MODINDEX_CALC', 'SEQ.MODINDEX_CALC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.MODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXM(self) - self.zz_fdict['MODINDEXM'] = self.MODINDEXM - self.MODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE(self) - self.zz_fdict['MODINDEXE'] = self.MODINDEXE - self.FREQGAINE = RM_Field_SEQ_MODINDEX_CALC_FREQGAINE(self) - self.zz_fdict['FREQGAINE'] = self.FREQGAINE - self.FREQGAINM = RM_Field_SEQ_MODINDEX_CALC_FREQGAINM(self) - self.zz_fdict['FREQGAINM'] = self.FREQGAINM - self.AMMODINDEXM = RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXM(self) - self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM - self.AMMODINDEXE = RM_Field_SEQ_MODINDEX_CALC_AMMODINDEXE(self) - self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED, self).__init__(rmio, label, - 0xa0000000, 0x00C, - 'MODINDEX_CALC_MODINDEXE_DOUBLED', 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.MODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM(self) - self.zz_fdict['MODINDEXM'] = self.MODINDEXM - self.MODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXE(self) - self.zz_fdict['MODINDEXE'] = self.MODINDEXE - self.FREQGAINE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE(self) - self.zz_fdict['FREQGAINE'] = self.FREQGAINE - self.FREQGAINM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM(self) - self.zz_fdict['FREQGAINM'] = self.FREQGAINM - self.AMMODINDEXM = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXM(self) - self.zz_fdict['AMMODINDEXM'] = self.AMMODINDEXM - self.AMMODINDEXE = RM_Field_SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_AMMODINDEXE(self) - self.zz_fdict['AMMODINDEXE'] = self.AMMODINDEXE - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_SPARE4(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_SPARE4, self).__init__(rmio, label, - 0xa0000000, 0x010, - 'SPARE4', 'SEQ.SPARE4', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.SPARE4 = RM_Field_SEQ_SPARE4_SPARE4(self) - self.zz_fdict['SPARE4'] = self.SPARE4 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MODEMINFO(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MODEMINFO, self).__init__(rmio, label, - 0xa0000000, 0x014, - 'MODEMINFO', 'SEQ.MODEMINFO', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.LEGACY_EN = RM_Field_SEQ_MODEMINFO_LEGACY_EN(self) - self.zz_fdict['LEGACY_EN'] = self.LEGACY_EN - self.SPARE0 = RM_Field_SEQ_MODEMINFO_SPARE0(self) - self.zz_fdict['SPARE0'] = self.SPARE0 - self.TRECS_EN = RM_Field_SEQ_MODEMINFO_TRECS_EN(self) - self.zz_fdict['TRECS_EN'] = self.TRECS_EN - self.BCR_EN = RM_Field_SEQ_MODEMINFO_BCR_EN(self) - self.zz_fdict['BCR_EN'] = self.BCR_EN - self.COHERENT_EN = RM_Field_SEQ_MODEMINFO_COHERENT_EN(self) - self.zz_fdict['COHERENT_EN'] = self.COHERENT_EN - self.LONGRANGE_EN = RM_Field_SEQ_MODEMINFO_LONGRANGE_EN(self) - self.zz_fdict['LONGRANGE_EN'] = self.LONGRANGE_EN - self.ENHDSSS_EN = RM_Field_SEQ_MODEMINFO_ENHDSSS_EN(self) - self.zz_fdict['ENHDSSS_EN'] = self.ENHDSSS_EN - self.SPARE1 = RM_Field_SEQ_MODEMINFO_SPARE1(self) - self.zz_fdict['SPARE1'] = self.SPARE1 - self.SOFTMODEM_EN = RM_Field_SEQ_MODEMINFO_SOFTMODEM_EN(self) - self.zz_fdict['SOFTMODEM_EN'] = self.SOFTMODEM_EN - self.BTC_EN = RM_Field_SEQ_MODEMINFO_BTC_EN(self) - self.zz_fdict['BTC_EN'] = self.BTC_EN - self.SPARE2 = RM_Field_SEQ_MODEMINFO_SPARE2(self) - self.zz_fdict['SPARE2'] = self.SPARE2 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_MISC(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_MISC, self).__init__(rmio, label, - 0xa0000000, 0x018, - 'MISC', 'SEQ.MISC', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.RESERVED10 = RM_Field_SEQ_MISC_RESERVED10(self) - self.zz_fdict['RESERVED10'] = self.RESERVED10 - self.IFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_MISC_IFPKDOFF_AFTER_FRAME_EN(self) - self.zz_fdict['IFPKDOFF_AFTER_FRAME_EN'] = self.IFPKDOFF_AFTER_FRAME_EN - self.RFPKDOFF_AFTER_FRAME_EN = RM_Field_SEQ_MISC_RFPKDOFF_AFTER_FRAME_EN(self) - self.zz_fdict['RFPKDOFF_AFTER_FRAME_EN'] = self.RFPKDOFF_AFTER_FRAME_EN - self.RESERVED2 = RM_Field_SEQ_MISC_RESERVED2(self) - self.zz_fdict['RESERVED2'] = self.RESERVED2 - self.RESERVED1 = RM_Field_SEQ_MISC_RESERVED1(self) - self.zz_fdict['RESERVED1'] = self.RESERVED1 - self.RESERVED0 = RM_Field_SEQ_MISC_RESERVED0(self) - self.zz_fdict['RESERVED0'] = self.RESERVED0 - self.__dict__['zz_frozen'] = True - - -class RM_Register_SEQ_PHYINFO(Base_RM_Register): - def __init__(self, rmio, label): - self.__dict__['zz_frozen'] = False - super(RM_Register_SEQ_PHYINFO, self).__init__(rmio, label, - 0xa0000000, 0x01C, - 'PHYINFO', 'SEQ.PHYINFO', 'read-write', - u"", - 0x00000000, 0x00000000, - 0x00001000, 0x00002000, - 0x00003000) - - self.ADDRESS = RM_Field_SEQ_PHYINFO_ADDRESS(self) - self.zz_fdict['ADDRESS'] = self.ADDRESS - self.__dict__['zz_frozen'] = True - - diff --git a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/device.py b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/device.py index 034a8cdc27..799817c653 100644 --- a/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/device.py +++ b/platform/radio/efr32_multiphy_configurator/host_py_rm_studio_internal/full/sixg301/revB0/device.py @@ -35,7 +35,8 @@ from . RAC_S import * from . RFCRC_NS import * from . RFCRC_S import * -from . SEQ import * +from . SEQ_NS import * +from . SEQ_S import * from . SYNTH_NS import * from . SYNTH_S import * @@ -113,7 +114,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.__dict__['zz_frozen'] = False super(RM_Device_SIXG301XFULL_RevB0, self).__init__(rmio, label, 'SIXG301XFULL', - RM_SVD_Info('SIXG301XFULL_SEQ.svd', 'b0e132779c58ced80388bd67cafddad6')) + RM_SVD_Info('SIXG301XFULL_SEQ.svd', 'ef5cf72defcc982fa828dbdc6be9e05b')) self.AGC_NS = RM_Peripheral_AGC_NS(self.zz_rmio, self.zz_label) self.zz_pdict['AGC_NS'] = self.AGC_NS @@ -135,8 +136,10 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.zz_pdict['RFCRC_NS'] = self.RFCRC_NS self.RFCRC_S = RM_Peripheral_RFCRC_S(self.zz_rmio, self.zz_label) self.zz_pdict['RFCRC_S'] = self.RFCRC_S - self.SEQ = RM_Peripheral_SEQ(self.zz_rmio, self.zz_label) - self.zz_pdict['SEQ'] = self.SEQ + self.SEQ_NS = RM_Peripheral_SEQ_NS(self.zz_rmio, self.zz_label) + self.zz_pdict['SEQ_NS'] = self.SEQ_NS + self.SEQ_S = RM_Peripheral_SEQ_S(self.zz_rmio, self.zz_label) + self.zz_pdict['SEQ_S'] = self.SEQ_S self.SYNTH_NS = RM_Peripheral_SYNTH_NS(self.zz_rmio, self.zz_label) self.zz_pdict['SYNTH_NS'] = self.SYNTH_NS self.SYNTH_S = RM_Peripheral_SYNTH_S(self.zz_rmio, self.zz_label) @@ -148,6 +151,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.MODEM = self.MODEM_S self.RAC = self.RAC_S self.RFCRC = self.RFCRC_S + self.SEQ = self.SEQ_S self.SYNTH = self.SYNTH_S pass elif default_tz_access_mode == RM_TrustZone_Access_Mode.TZ_NONSECURE: @@ -156,6 +160,7 @@ def __init__(self, rmio=None, label='offline_rm', default_tz_access_mode=RM_Trus self.MODEM = self.MODEM_NS self.RAC = self.RAC_NS self.RFCRC = self.RFCRC_NS + self.SEQ = self.SEQ_NS self.SYNTH = self.SYNTH_NS pass diff --git a/platform/radio/efr32_multiphy_configurator/pro2_chip_configurator/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pro2_chip_configurator/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 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--git a/platform/radio/efr32_multiphy_configurator/pycalcmodel/core/reg_model.py b/platform/radio/efr32_multiphy_configurator/pycalcmodel/core/reg_model.py index f76988c9fa..67296b33e9 100644 --- a/platform/radio/efr32_multiphy_configurator/pycalcmodel/core/reg_model.py +++ b/platform/radio/efr32_multiphy_configurator/pycalcmodel/core/reg_model.py @@ -16,7 +16,10 @@ def get_reg_model(cls, part_family, part_revision=None): else: if part_family.upper() in RM_ALL_PART_FAMILY_NAMES: #Add to reg model - if part_revision == 'ANY' or part_family.upper() in RM_S1_PART_FAMILY_NAMES or part_family.upper() in RM_S2_PART_FAMILY_NAMES: + if (part_revision == 'ANY' + or part_family.upper() in RM_S1_PART_FAMILY_NAMES + or part_family.upper() in RM_S2_PART_FAMILY_NAMES + or part_family.upper() in ["RAINIER"]): cls._reg_model_dict[part_family] = RM_Factory(part_family.upper())() else: cls._reg_model_dict[part_family] = RM_Factory(part_family.upper(), part_revision)() diff --git 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differ diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/isc_import/MultiPHYStudioPropFileImport.py b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/isc_import/MultiPHYStudioPropFileImport.py index 60edc7250d..94089ef7a2 100644 --- a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/isc_import/MultiPHYStudioPropFileImport.py +++ b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/isc_import/MultiPHYStudioPropFileImport.py @@ -16,7 +16,7 @@ class MultiPHYStudioPropFileImport(object): def __init__(self): pass - def run(self, radioconf_filename, output_directory, output_filename=None, internal=False, secondary=False, sign=False): + def run(self, radioconf_filename, output_directory, output_filename=None, internal=False, secondary=False, sign=False, wifi_script=False, wifi_script_seqacc=False): xml_string = self.parse_file(radioconf_filename) # print xml_string @@ -35,7 +35,7 @@ def run(self, radioconf_filename, output_directory, output_filename=None, intern ModelDiff.process_diffs(multi_phy_model) if int(multi_phy_model.status_code) != ModelDiffCodes.UNKNOWN_ERROR.value: - RAILScriptsWrapper.run_rail_scripts(multi_phy_model, output_filename=output_filename, internal=internal, secondary=secondary, sign=sign) + RAILScriptsWrapper.run_rail_scripts(multi_phy_model, output_filename=output_filename, internal=internal, secondary=secondary, sign=sign, wifi_script=wifi_script, wifi_script_seqacc=wifi_script_seqacc) # Renaming the files for uniqueness for file in multi_phy_model.output_files.file: diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/multi_phy_configuration_model/__pycache__/Bindings.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/multi_phy_configuration_model/__pycache__/Bindings.cpython-310.pyc deleted file mode 100644 index f16dfb3686..0000000000 Binary files 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deleted file mode 100644 index b05dfd1529..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/multi_phy_configuration_model/__pycache__/rail_scripts_wrapper.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/multi_phy_configuration_model/rail_scripts_wrapper.py b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/multi_phy_configuration_model/rail_scripts_wrapper.py index afe420be36..c6a1ed188b 100644 --- a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/multi_phy_configuration_model/rail_scripts_wrapper.py +++ b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/multi_phy_configuration_model/rail_scripts_wrapper.py @@ -11,8 +11,8 @@ class RAILScriptsWrapper(object): rail_signature_function = None @staticmethod - def run_rail_scripts(multi_phy_model, generate_debug_yaml=False, output_filename="rail_config", internal=False, secondary=False, sign=False): - railAdapter = RAILAdapter(mphyConfig=multi_phy_model, adapter_name=multi_phy_model.rail_adapter_version) + def run_rail_scripts(multi_phy_model, generate_debug_yaml=False, output_filename="rail_config", internal=False, secondary=False, sign=False, wifi_script=False, wifi_script_seqacc=False): + railAdapter = RAILAdapter(mphyConfig=multi_phy_model, adapter_name=multi_phy_model.rail_adapter_version, wifi_script=wifi_script, wifi_script_seqacc=wifi_script_seqacc) railAdapter.populateModel() if railAdapter._railModelPopulated == False: @@ -55,9 +55,10 @@ def run_rail_scripts(multi_phy_model, generate_debug_yaml=False, output_filename rail_config_c = generator.render(generator.template_path_c) multi_phy_model.output_files.file.append(fileType("{}.c".format(output_filename), rail_config_c)) - railtest_generator = RailTest_rmrConfigGenerator(railAdapter) - rail_railtest_commands = railtest_generator.render(railtest_generator.template_path_railtest) - multi_phy_model.output_files.file.append(fileType("rail_test_commands.txt", rail_railtest_commands)) + if wifi_script is False and wifi_script_seqacc is False : + railtest_generator = RailTest_rmrConfigGenerator(railAdapter) + rail_railtest_commands = railtest_generator.render(railtest_generator.template_path_railtest) + multi_phy_model.output_files.file.append(fileType("rail_test_commands.txt", rail_railtest_commands)) @staticmethod def dump_output_files(multi_phy_model, output_path): diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 56a7d3b3fc..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/model_diff.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/model_diff.cpython-310.pyc deleted file mode 100644 index b36081d943..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/model_diff.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/model_diff_codes.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/model_diff_codes.cpython-310.pyc deleted file mode 100644 index f34b2c6881..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/__pycache__/model_diff_codes.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/model_diff.py b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/model_diff.py index 58a0b30f08..55853eca7a 100644 --- a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/model_diff.py +++ b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_diff_tool/model_diff.py @@ -49,7 +49,10 @@ def process_diffs(multi_phy_model, skip_running_radio_config_on_channel=False): channel_config_entry_registers = dict() # Init dictionary # Create default register model for the part_family - if multi_phy_model.part_revision == 'ANY' or multi_phy_model.part_family.upper() in RM_S1_PART_FAMILY_NAMES or multi_phy_model.part_family.upper() in RM_S2_PART_FAMILY_NAMES: + if (multi_phy_model.part_revision == 'ANY' + or multi_phy_model.part_family.upper() in RM_S1_PART_FAMILY_NAMES + or multi_phy_model.part_family.upper() in RM_S2_PART_FAMILY_NAMES + or multi_phy_model.part_family.upper() in ["RAINIER"]): register_model = RM_Factory(multi_phy_model.part_family.upper())() else: register_model = RM_Factory(multi_phy_model.part_family.upper(), multi_phy_model.part_revision)() diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_model_to_xml/__pycache__/Bindings.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_model_to_xml/__pycache__/Bindings.cpython-310.pyc deleted file mode 100644 index 67053b8d94..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_model_to_xml/__pycache__/Bindings.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_model_to_xml/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pylib_multi_phy_model/register_model_to_xml/__pycache__/__init__.cpython-310.pyc deleted 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a/platform/radio/efr32_multiphy_configurator/pyradioconfig/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/__pycache__/_version.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/__pycache__/_version.cpython-310.pyc deleted file mode 100644 index 0034d7ca23..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/__pycache__/_version.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/_version.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/_version.py index 82fe104ee4..d3e556b793 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/_version.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/_version.py @@ -1,3 +1,4 @@ -__version__ = '2404.4.5' +__version__ = '2404.5.3' + diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/calculator_model_framework/Utils/ModelChecking.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/calculator_model_framework/Utils/ModelChecking.py index 815704e4cc..e24a05d7f9 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/calculator_model_framework/Utils/ModelChecking.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/calculator_model_framework/Utils/ModelChecking.py @@ -85,7 +85,10 @@ def check_regs(model, ignore_missing_info=True): else: phy_name = model.phy.name #Get the regmap object just once for the part (much more efficient than looping) - if model.part_revision == 'ANY' or part_family.upper() in RM_S1_PART_FAMILY_NAMES or part_family.upper() in RM_S2_PART_FAMILY_NAMES: + if (model.part_revision == 'ANY' + or part_family.upper() in RM_S1_PART_FAMILY_NAMES + or part_family.upper() in RM_S2_PART_FAMILY_NAMES + or part_family.upper() in ["RAINIER"]): regmap_obj = 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b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/calculators/calc_demodulator.py index 586829b208..311b8887a2 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/calculators/calc_demodulator.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/calculators/calc_demodulator.py @@ -1365,4 +1365,4 @@ def calc_src2_denominator(self, model): def calc_dec0_values_available(self, model): # EFR32 90nm parts (Dumbo, Jumbo, Nerio, Nixi) always allow all rates to be available model.vars.input_decimation_filter_allow_dec3.value = 1 - model.vars.input_decimation_filter_allow_dec8.value = 1 + model.vars.input_decimation_filter_allow_dec8.value = 1 \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/phys/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/phys/__pycache__/__init__.cpython-310.pyc deleted file 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a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/profiles/__pycache__/sol_regs.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/profiles/rainier_regs.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/profiles/rainier_regs.py index 6737e63543..edfeca8f4f 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/profiles/rainier_regs.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/profiles/rainier_regs.py @@ -103,6 +103,7 @@ def build_modem_regs_rainier(model, profile): profile.outputs.append(ModelOutput(model.vars.MODEM_DIGMIXCTRL_DSSSCFECOMBO, '', ModelOutputType.SVD_REG_FIELD, readable_name='MODEM.DIGMIXCTRL.DSSSCFECOMBO')) profile.outputs.append(ModelOutput(model.vars.MODEM_SYNC3_SYNC3, '', ModelOutputType.SVD_REG_FIELD, readable_name='MODEM.SYNC3.SYNC3')) + profile.outputs.append(ModelOutput(model.vars.MODEM_SRCCHF_CHMUTETIMER, '', ModelOutputType.SVD_REG_FIELD, readable_name='MODEM.SRCCHF.CHMUTETIMER')) profile.outputs.append(ModelOutput(model.vars.MODEM_EHDSSSCTRL_DSSSPMTIMEOUT, '', ModelOutputType.SVD_REG_FIELD, readable_name='MODEM.EHDSSSCTRL.DSSSPMTIMEOUT')) profile.outputs.append(ModelOutput(model.vars.MODEM_EHDSSSCTRL_DSSSFRMTIMEOUT, '', ModelOutputType.SVD_REG_FIELD, readable_name='MODEM.EHDSSSCTRL.DSSSFRMTIMEOUT')) @@ -251,6 +252,9 @@ def build_modem_regs_rainier(model, profile): profile.outputs.append(ModelOutput(model.vars.SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_MODINDEXM, '', ModelOutputType.SVD_REG_FIELD,readable_name='SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.MODINDEXM')) profile.outputs.append(ModelOutput(model.vars.SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, '', ModelOutputType.SVD_REG_FIELD,readable_name='SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE')) profile.outputs.append(ModelOutput(model.vars.SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, '', ModelOutputType.SVD_REG_FIELD,readable_name='SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM')) + profile.outputs.append(ModelOutput(model.vars.SEQ_MISC_SYNTH_MODE_TX00D_EN, '', ModelOutputType.SVD_REG_FIELD,readable_name='SEQ.MISC.SYNTH_MODE_TX00D_EN')) + profile.outputs.append(ModelOutput(model.vars.MODEM_SPARE_SPARE, '', ModelOutputType.SVD_REG_FIELD, readable_name='MODEM.SPARE.SPARE')) + ## Synth_IF Series 3 Reigsters def build_synth_regs_s3(model, profile): ## LPF @@ -357,6 +361,46 @@ def build_synth_regs_s3(model, profile): # profile.outputs.append(ModelOutput(model.vars.RAC_SYMMDCTRL_SYMMDSEL56STG, '', ModelOutputType.SVD_REG_FIELD, readable_name='RAC.SYMMDCTRL.SYMMDSEL56STG')) # profile.outputs.append(ModelOutput(model.vars.RAC_SYMMDCTRL_SYMMDSEL56STGTX, '', ModelOutputType.SVD_REG_FIELD, readable_name='RAC.SYMMDCTRL.SYMMDSEL56STGTX')) + + # DTIMLOSS feature for fast switch PHY optimization. See https://jira.silabs.com/browse/MCUW_RADIO_CFG-2525 + profile.outputs.append(ModelOutput(model.vars.MODEM_TRECSCFG_DTIMLOSSEN, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.TRECSCFG.DTIMLOSSEN')) + profile.outputs.append(ModelOutput(model.vars.MODEM_TRECSCFG_DTIMLOSSTHD, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.TRECSCFG.DTIMLOSSTHD')) + + # TODO: Add to lpwh72000 and lpwh74000 when available in register map + if not (model.part_family.upper() == 'RAINIER' and model.part_revision in ['A0', 'A1', 'A2']): + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_FASTCWDETECTEN, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.FASTCWDETECTEN')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_FASTSUPERCHIPEN, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.FASTSUPERCHIPEN')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_FASTNARROWPULSEEN, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.FASTNARROWPULSEEN')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_EYEOPENINGMODE, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.EYEOPENINGMODE')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_CWDETECTSTARTWINDOW, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.CWDETECTSTARTWINDOW')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_CWDETECTTHRESHOLD, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.CWDETECTTHRESHOLD')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_SUPERCHIPSTARTWINDOW, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.SUPERCHIPSTARTWINDOW')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_NPULSEFIXEDTHRESHOLD, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.NPULSEFIXEDTHRESHOLD')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_NPULSETHRESHADJEN, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.NPULSETHRESHADJEN')) + profile.outputs.append( + ModelOutput(model.vars.MODEM_SIFASTDETECTCTRL_NPULSETHRESHADJ, '', ModelOutputType.SVD_REG_FIELD, + readable_name='MODEM.SIFASTDETECTCTRL.NPULSETHRESHADJ')) + def build_syctrl_regs_s3(model, profile): profile.outputs.append(ModelOutput(model.vars.RAC_SYCTRL0_SYVCOTRIMIPTAT, '', ModelOutputType.SVD_REG_FIELD, readable_name='RAC.SYCTRL0.SYVCOTRIMIPTAT')) profile.outputs.append(ModelOutput(model.vars.RAC_SYCTRL0_SYVCOTRIMIBIAS, '', ModelOutputType.SVD_REG_FIELD, readable_name='RAC.SYCTRL0.SYVCOTRIMIBIAS')) diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/common/utils/__pycache__/__init__.cpython-310.pyc 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b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/calculators/calc_global.py index efcc484f5e..4c90cc1f34 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/calculators/calc_global.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/calculators/calc_global.py @@ -23,6 +23,7 @@ def buildVariables(self, model): # Add register groups self._add_SHAPING_regs(model) + self._add_PREDIST_regs(model) # Internal variable self._addModelVariable(model, 'src1', int, ModelVariableFormat.DECIMAL) @@ -163,10 +164,6 @@ def _add_common_regs(self, model): self._addModelRegister(model, 'MODEM.CTRL0.DUALCORROPTDIS', int, ModelVariableFormat.HEX) self._addModelRegister(model, 'MODEM.CTRL4.SOFTDSSSMODE', int, ModelVariableFormat.HEX) - self._addModelRegister(model, 'MODEM.CTRL4.PREDISTRST', int, ModelVariableFormat.HEX) - self._addModelRegister(model, 'MODEM.CTRL4.PREDISTAVG', int, ModelVariableFormat.HEX) - self._addModelRegister(model, 'MODEM.CTRL4.PREDISTDEB', int, ModelVariableFormat.HEX) - self._addModelRegister(model, 'MODEM.CTRL4.PREDISTGAIN', int, ModelVariableFormat.HEX) self._addModelRegister(model, 'MODEM.CTRL5.DSSSCTD' , int, ModelVariableFormat.HEX ) self._addModelRegister(model, 'MODEM.CTRL5.BBSS' , int, ModelVariableFormat.HEX ) @@ -288,3 +285,9 @@ def _add_common_regs(self, model): self._addModelRegister(model, 'SEQ.BBSS_GROUP_1.BBSS_LEVEL_LOW', int, ModelVariableFormat.HEX) self._addModelRegister(model, 'SEQ.BBSS_GROUP_1.BBSS_HYSTERESIS', int, ModelVariableFormat.HEX) self._addModelRegister(model, 'SEQ.BBSS_GROUP_1.IIR_SHIFT', int, ModelVariableFormat.HEX) + + def _add_PREDIST_regs(self, model): + self._addModelRegister(model, 'MODEM.CTRL4.PREDISTRST', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.CTRL4.PREDISTAVG', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.CTRL4.PREDISTDEB', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.CTRL4.PREDISTGAIN', int, ModelVariableFormat.HEX) \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/calculators/calc_wisun.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/calculators/calc_wisun.py index 56863f979f..b7759e9366 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/calculators/calc_wisun.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/calculators/calc_wisun.py @@ -44,7 +44,7 @@ def buildVariables(self, model): ['IN', 0x05, 'India'], ['MX', 0x06, 'Mexico'], ['BZ', 0x07, 'Brazil'], - ['AZ_NZ', 0x08, 'Australia and New Zealand'], + ['AU_NZ', 0x08, 'Australia and New Zealand'], ['KR', 0x09, 'Korea'], ['PH', 0x0A, 'Philippines'], ['MY', 0x0B, 'Malaysia'], @@ -224,7 +224,7 @@ def calc_wisun_freq_spacing(self, model): error = True base_frequency_hz = 902.2e6 channel_spacing_hz = 200e3 - elif wisun_reg_domain == reg_domain_enum.AZ_NZ: + elif wisun_reg_domain == reg_domain_enum.AU_NZ: if wisun_operating_class == 1: base_frequency_hz = 915.2e6 channel_spacing_hz = 200e3 diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/__pycache__/Phys_connect.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/__pycache__/Phys_connect.cpython-310.pyc deleted file mode 100644 index 7459eb817e..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/__pycache__/Phys_connect.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 718df92842..0000000000 Binary files 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a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/__pycache__/phys_studio_wisun_han.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_0.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_0.py index 90a4f3de8c..6836bf04d8 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_0.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_0.py @@ -338,34 +338,34 @@ def PHY_IEEE802154_WISUN_915MHz_2GFSK_300kbps_5_BZ(self, model, phy_name=None): phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - ### AZ_NZ Region PHYs From Wi-SUN FAN 1.0 Spec### + ### AU_NZ Region PHYs From Wi-SUN FAN 1.0 Spec### # Operating Class 1 - def PHY_IEEE802154_WISUN_915MHz_2GFSK_50kbps_1b_AZ_NZ(self, model, phy_name=None): - params = WisunFanChannelParams('AZ_NZ', 1, 'Mode1b', 200000, 915200000, 'AZ_NZ-915MHz') + def PHY_IEEE802154_WISUN_915MHz_2GFSK_50kbps_1b_AU_NZ(self, model, phy_name=None): + params = WisunFanChannelParams('AU_NZ', 1, 'Mode1b', 200000, 915200000, 'AU_NZ-915MHz') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_IEEE802154_WISUN_915MHz_2GFSK_100kbps_2a_AZ_NZ(self, model, phy_name=None): - params = WisunFanChannelParams('AZ_NZ', 1, 'Mode2a', 200000, 915200000, 'AZ_NZ-915MHz') + def PHY_IEEE802154_WISUN_915MHz_2GFSK_100kbps_2a_AU_NZ(self, model, phy_name=None): + params = WisunFanChannelParams('AU_NZ', 1, 'Mode2a', 200000, 915200000, 'AU_NZ-915MHz') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy # Operating Class 2 - def PHY_IEEE802154_WISUN_915MHz_2GFSK_150kbps_3_AZ_NZ(self, model, phy_name=None): - params = WisunFanChannelParams('AZ_NZ', 2, 'Mode3', 400000, 915400000, 'AZ_NZ-915MHz') + def PHY_IEEE802154_WISUN_915MHz_2GFSK_150kbps_3_AU_NZ(self, model, phy_name=None): + params = WisunFanChannelParams('AU_NZ', 2, 'Mode3', 400000, 915400000, 'AU_NZ-915MHz') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_IEEE802154_WISUN_915MHz_2GFSK_200kbps_4a_AZ_NZ(self, model, phy_name=None): - params = WisunFanChannelParams('AZ_NZ', 2, 'Mode4a', 400000, 915400000, 'AZ_NZ-915MHz') + def PHY_IEEE802154_WISUN_915MHz_2GFSK_200kbps_4a_AU_NZ(self, model, phy_name=None): + params = WisunFanChannelParams('AU_NZ', 2, 'Mode4a', 400000, 915400000, 'AU_NZ-915MHz') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_IEEE802154_WISUN_915MHz_2GFSK_300kbps_5_AZ_NZ(self, model, phy_name=None): - params = WisunFanChannelParams('AZ_NZ', 2, 'Mode5', 400000, 915400000, 'AZ_NZ-915MHz') + def PHY_IEEE802154_WISUN_915MHz_2GFSK_300kbps_5_AU_NZ(self, model, phy_name=None): + params = WisunFanChannelParams('AU_NZ', 2, 'Mode5', 400000, 915400000, 'AU_NZ-915MHz') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1.py index 8850cb9ad3..3dc3242315 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1.py @@ -219,13 +219,13 @@ def PHY_WISUN_FAN_1v1_866MHz_Plan40_2FSK_3_IN(self, model, phy_name=None): ### SG Region PHYs From Wi-SUN FAN 1.1 Spec### - # ChanPlanID 38 - def PHY_WISUN_FAN_1v1_867MHz_Plan38_2FSK_4a_SG(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('SG', 6, 38, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode4a (2FSK 200kbps mi=0.5)') + # ChanPlanID 43 + def PHY_WISUN_FAN_1v1_867MHz_Plan43_2FSK_4a_SG(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('SG', 6, 43, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode4a (2FSK 200kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_867MHz_Plan38_2FSK_5_SG(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('SG', 8, 38, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode5 (2FSK 300kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_867MHz_Plan43_2FSK_5_SG(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('SG', 8, 43, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode5 (2FSK 300kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1_virtual.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1_virtual.py index 3e762d38eb..e6c8e9eeb4 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1_virtual.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/phys/phys_studio_wisun_fan_1_1_virtual.py @@ -6,28 +6,28 @@ @do_not_inherit_phys class PhysStudioWisunFan1v1VirtualJumbo(PhysStudioWisunFan1v1Jumbo): - def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_1b_AZ_NZ(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('AZ_NZ', 0x02, 48, 200000, 915200000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode1b (2FSK 50kbps mi=1.0)') + def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_1b_AU_NZ(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('AU_NZ', 0x02, 48, 200000, 915200000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode1b (2FSK 50kbps mi=1.0)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_2a_AZ_NZ(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('AZ_NZ', 0x03, 48, 200000, 915200000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode2a (2FSK 100kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_2a_AU_NZ(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('AU_NZ', 0x03, 48, 200000, 915200000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode2a (2FSK 100kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_3_AZ_NZ(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('AZ_NZ', 0x05, 49, 400000, 915400000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode3 (2FSK 150kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_3_AU_NZ(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('AU_NZ', 0x05, 49, 400000, 915400000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode3 (2FSK 150kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_4a_AZ_NZ(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('AZ_NZ', 0x06, 49, 400000, 915400000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode4a (2FSK 200kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_4a_AU_NZ(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('AU_NZ', 0x06, 49, 400000, 915400000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode4a (2FSK 200kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_5_AZ_NZ(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('AZ_NZ', 0x08, 49, 400000, 915400000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode5 (2FSK 300kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_5_AU_NZ(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('AU_NZ', 0x08, 49, 400000, 915400000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode5 (2FSK 300kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy @@ -45,32 +45,7 @@ def PHY_WISUN_FAN_1v1_920MHz_Plan128_2FSK_3_CN(self, model, phy_name=None): params = WisunFan1v1ChannelParamsJumbo('CN', 0x05, 128, 250000, 920625000, 'Wi-SUN FAN, CN 920-924 MHz, Mode3 (2FSK 150kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan144_2FSK_1b_CN(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('CN', 0x02, 144, 200000, 779200000, 'Wi-SUN FAN, CN 779-787 MHz, Mode1b (2FSK 50kbps mi=1.0)') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan144_2FSK_2a_CN(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('CN', 0x03, 144, 200000, 779200000, 'Wi-SUN FAN, CN 779-787 MHz, Mode2a (2FSK 100kbps mi=0.5)') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan145_2FSK_3_CN(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('CN', 0x05, 145, 400000, 779400000, 'Wi-SUN FAN, CN 779-787 MHz, Mode3 (2FSK 150kbps mi=0.5)') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan145_2FSK_4a_CN(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('CN', 0x06, 145, 400000, 779400000, 'Wi-SUN FAN, CN 779-787 MHz, Mode4a (2FSK 200kbps mi=0.5)') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan145_2FSK_5_CN(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('CN', 0x08, 145, 400000, 779400000, 'Wi-SUN FAN, CN 779-787 MHz, Mode5 (2FSK 300kbps mi=0.5)') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - + def PHY_WISUN_FAN_1v1_470MHz_Plan160_2FSK_1b_CN(self, model, phy_name=None): params = WisunFan1v1ChannelParamsJumbo('CN', 0x02, 160, 200000, 470200000, 'Wi-SUN FAN, CN 470-510 MHz, Mode1b (2FSK 50kbps mi=1.0)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) @@ -172,17 +147,17 @@ def PHY_WISUN_FAN_1v1_919MHz_Plan80_2FSK_2a_MY(self, model, phy_name=None): return phy def PHY_WISUN_FAN_1v1_919MHz_Plan81_2FSK_3_MY(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('MY', 0x05, 81, 400000, 919400000, 'Wi-SUN FAN, MY 919-923 MHz, Mode3 (2FSK 150kbps mi=0.5)') + params = WisunFan1v1ChannelParamsJumbo('MY', 0x05, 81, 400000, 919200000, 'Wi-SUN FAN, MY 919-923 MHz, Mode3 (2FSK 150kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy def PHY_WISUN_FAN_1v1_919MHz_Plan81_2FSK_4a_MY(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('MY', 0x06, 81, 400000, 919400000, 'Wi-SUN FAN, MY 919-923 MHz, Mode4a (2FSK 200kbps mi=0.5)') + params = WisunFan1v1ChannelParamsJumbo('MY', 0x06, 81, 400000, 919200000, 'Wi-SUN FAN, MY 919-923 MHz, Mode4a (2FSK 200kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy def PHY_WISUN_FAN_1v1_919MHz_Plan81_2FSK_5_MY(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('MY', 0x08, 81, 400000, 919400000, 'Wi-SUN FAN, MY 919-923 MHz, Mode5 (2FSK 300kbps mi=0.5)') + params = WisunFan1v1ChannelParamsJumbo('MY', 0x08, 81, 400000, 919200000, 'Wi-SUN FAN, MY 919-923 MHz, Mode5 (2FSK 300kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy @@ -211,18 +186,18 @@ def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_5_PH(self, model, phy_name=None): phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_866MHz_Plan32_2FSK_1a_SG(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('SG', 0x01, 32, 100000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode1a (2FSK 50kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_866MHz_Plan41_2FSK_1a_SG(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('SG', 0x01, 41, 100000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode1a (2FSK 50kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_866MHz_Plan33_2FSK_2a_SG(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('SG', 0x03, 33, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode2a (2FSK 100kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_866MHz_Plan42_2FSK_2a_SG(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('SG', 0x03, 42, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode2a (2FSK 100kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_866MHz_Plan33_2FSK_3_SG(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('SG', 0x05, 33, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode3 (2FSK 150kbps mi=0.5)') + def PHY_WISUN_FAN_1v1_866MHz_Plan42_2FSK_3_SG(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('SG', 0x05, 42, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode3 (2FSK 150kbps mi=0.5)') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/profiles/__pycache__/Profile_LongRange.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/profiles/__pycache__/Profile_LongRange.cpython-310.pyc deleted file mode 100644 index 682b1db530..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/profiles/__pycache__/Profile_LongRange.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/profiles/__pycache__/__init__.cpython-310.pyc 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b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/profiles/profile_wisun_fan_1_1.py index 157993686b..f1ffd3380a 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/profiles/profile_wisun_fan_1_1.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/jumbo/profiles/profile_wisun_fan_1_1.py @@ -39,6 +39,9 @@ class ProfileWisunFan1v1Jumbo(IProfile): 38: chplan_id_params('Plan38_863M_870M_400k', 863.5e6, 400e3), 39: chplan_id_params('Plan39_865M_868M_100k', 865.1e6, 100e3), 40: chplan_id_params('Plan40_865M_868M_200k', 865.1e6, 200e3), + 41: chplan_id_params('Plan41_863M_870M_100k', 866.1e6, 100e3), + 42: chplan_id_params('Plan42_863M_870M_200k', 866.1e6, 200e3), + 43: chplan_id_params('Plan43_863M_876M_400k', 866.3e6, 400e3), 48: chplan_id_params('Plan48_915M_928M_200k', 915.2e6, 200e3), 49: chplan_id_params('Plan49_915M_928M_400k', 915.4e6, 400e3), 64: chplan_id_params('Plan64_920M_925M_200k', 920.2e6, 200e3), diff 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a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/filters/__pycache__/phy_filters.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/filters/__pycache__/phy_filters.cpython-310.pyc deleted file mode 100644 index d877f7d83d..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/filters/__pycache__/phy_filters.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/phys/Phys_RAIL_Base_Standard_BLE.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/phys/Phys_RAIL_Base_Standard_BLE.py index b8538f7cfa..4ba04eed25 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/phys/Phys_RAIL_Base_Standard_BLE.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/phys/Phys_RAIL_Base_Standard_BLE.py @@ -2,4 +2,13 @@ class PhysRailBaseStandardBluetoothLeLion(PhysRailBaseStandardBluetoothLeLeopard): - pass \ No newline at end of file + + def PHY_Bluetooth_LongRange_nodsa_125kbps(self, model, phy_name=None): + phy = super().PHY_Bluetooth_LongRange_dsa_125kbps(model, phy_name=phy_name) + phy.profile_outputs.MODEM_LONGRANGE_LRBLEDSA.override = 0 + return phy + + def PHY_Bluetooth_LongRange_nodsa_500kbps(self, model, phy_name=None): + phy = super().PHY_Bluetooth_LongRange_dsa_500kbps(model, phy_name=phy_name) + phy.profile_outputs.MODEM_LONGRANGE_LRBLEDSA.override = 0 + return phy \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/phys/__pycache__/Phys_Datasheet.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/phys/__pycache__/Phys_Datasheet.cpython-310.pyc deleted file mode 100644 index 5e8060a791..0000000000 Binary files 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a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/phys/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/profiles/Profile_BLE.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/profiles/Profile_BLE.py index 520e642447..e7c650efc2 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/profiles/Profile_BLE.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/lion/profiles/Profile_BLE.py @@ -15,4 +15,22 @@ def __init__(self): self._family = "lion" def build_register_profile_outputs(self, model, profile): - build_modem_regs_lion(model, profile) \ No newline at end of file + build_modem_regs_lion(model, profile) + + def _build_feature_settings(self, model): + ble_feature = model.profile.inputs.ble_feature.var_value + + if ble_feature == model.vars.ble_feature.var_enum.LE_1M: + self._copy_model_variables_from_phy(model, 'PHY_Bluetooth_LE_Viterbi_noDSA') + elif ble_feature == model.vars.ble_feature.var_enum.LE_2M: + self._copy_model_variables_from_phy(model, 'PHY_Bluetooth_LE_2M_Viterbi_noDSA_fullrate') + elif ble_feature == model.vars.ble_feature.var_enum.CODED_125K: + self._copy_model_variables_from_phy(model, 'PHY_Bluetooth_LongRange_nodsa_125kbps') + elif ble_feature == model.vars.ble_feature.var_enum.CODED_500K: + self._copy_model_variables_from_phy(model, 'PHY_Bluetooth_LongRange_nodsa_500kbps') + elif ble_feature == model.vars.ble_feature.var_enum.AOX_1M: + self._copy_model_variables_from_phy(model, 'PHY_Bluetooth_LE_Viterbi_noDSA_fullrate') + elif ble_feature == model.vars.ble_feature.var_enum.AOX_2M: + self._copy_model_variables_from_phy(model, 'PHY_Bluetooth_LE_2M_Viterbi_noDSA_fullrate') + elif ble_feature == model.vars.ble_feature.var_enum.CONCURRENT: + self._copy_model_variables_from_phy(model, 'PHY_Bluetooth_1M_Concurrent') \ No newline at end of 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b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/filters/__pycache__/phy_filters.cpython-310.pyc deleted file mode 100644 index e06d32eab8..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/filters/__pycache__/phy_filters.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/Phys_Studio_Sigfox_TX.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/Phys_Studio_Sigfox_TX.py index 4a075e294f..33e582bc23 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/Phys_Studio_Sigfox_TX.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/Phys_Studio_Sigfox_TX.py @@ -11,6 +11,7 @@ def PHY_Sigfox_868MHz_DBPSK_100bps_TXOnly(self, model, phy_name=None): phy.profile_inputs.xtal_frequency_hz.value = 39_000_000 phy.profile_inputs.base_frequency_hz.value = 868_034_000 phy.profile_inputs.channel_spacing_hz.value = 100 + phy.profile_inputs.fixed_length_size.value = 16 return phy @@ -23,6 +24,7 @@ def PHY_Sigfox_915MHz_DBPSK_600bps_TXOnly(self, model, phy_name=None): phy.profile_inputs.xtal_frequency_hz.value = 39_000_000 phy.profile_inputs.base_frequency_hz.value = 905_104_000 phy.profile_inputs.channel_spacing_hz.value = 100 + phy.profile_inputs.fixed_length_size.value = 16 return phy diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/__pycache__/Phys_Default.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/__pycache__/Phys_Default.cpython-310.pyc deleted file mode 100644 index 0877e08dcc..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/__pycache__/Phys_Default.cpython-310.pyc and /dev/null differ diff --git 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diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/__pycache__/phys_studio_wisun_han.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/__pycache__/phys_studio_wisun_han.cpython-310.pyc deleted file mode 100644 index b3af5f04ff..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/__pycache__/phys_studio_wisun_han.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1.py index d5f9da94d3..77773b31c6 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1.py @@ -220,13 +220,13 @@ def PHY_WISUN_FAN_1v1_866MHz_Plan40_2FSK_3_IN_FEC(self, model, phy_name=None): ### SG Region PHYs From Wi-SUN FAN 1.1 Spec### - # ChanPlanID 38 - def PHY_WISUN_FAN_1v1_867MHz_Plan38_2FSK_4a_SG_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('SG', 22, 38, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode4a (2FSK 200kbps mi=0.5), FEC') + # ChanPlanID 43 + def PHY_WISUN_FAN_1v1_867MHz_Plan43_2FSK_4a_SG_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('SG', 22, 43, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode4a (2FSK 200kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_867MHz_Plan38_2FSK_5_SG_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsJumbo('SG', 24, 38, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode5 (2FSK 300kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_867MHz_Plan43_2FSK_5_SG_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsJumbo('SG', 24, 43, 400000, 866300000, 'Wi-SUN FAN, SG 865-867 MHz, Mode5 (2FSK 300kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1_virtual.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1_virtual.py index 8ec7a7eda7..5b1b87c1d6 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1_virtual.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/phys/phys_studio_wisun_fan_1_1_virtual.py @@ -8,28 +8,28 @@ class PhysStudioWisunFan1v1VirtualOcelot(PhysStudioWisunFan1v1VirtualJumbo): def _set_xtal_frequency(self, model, phy): phy.profile_inputs.xtal_frequency_hz.value = 39000000 - def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_1b_AZ_NZ_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('AZ_NZ', 0x12, 48, 200000, 915200000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode1b (2FSK 50kbps mi=1.0), FEC') + def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_1b_AU_NZ_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('AU_NZ', 0x12, 48, 200000, 915200000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode1b (2FSK 50kbps mi=1.0), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_2a_AZ_NZ_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('AZ_NZ', 0x13, 48, 200000, 915200000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode2a (2FSK 100kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_915MHz_Plan48_2FSK_2a_AU_NZ_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('AU_NZ', 0x13, 48, 200000, 915200000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode2a (2FSK 100kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_3_AZ_NZ_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('AZ_NZ', 0x15, 49, 400000, 915400000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode3 (2FSK 150kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_3_AU_NZ_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('AU_NZ', 0x15, 49, 400000, 915400000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode3 (2FSK 150kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_4a_AZ_NZ_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('AZ_NZ', 0x16, 49, 400000, 915400000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode4a (2FSK 200kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_4a_AU_NZ_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('AU_NZ', 0x16, 49, 400000, 915400000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode4a (2FSK 200kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_5_AZ_NZ_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('AZ_NZ', 0x18, 49, 400000, 915400000, 'Wi-SUN FAN, AZ_NZ 915-928 MHz, Mode5 (2FSK 300kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_5_AU_NZ_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('AU_NZ', 0x18, 49, 400000, 915400000, 'Wi-SUN FAN, AU_NZ 915-928 MHz, Mode5 (2FSK 300kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy @@ -48,31 +48,6 @@ def PHY_WISUN_FAN_1v1_920MHz_Plan128_2FSK_3_CN_FEC(self, model, phy_name=None): phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_779MHz_Plan144_2FSK_1b_CN_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('CN', 0x12, 144, 200000, 779200000, 'Wi-SUN FAN, CN 779-787 MHz, Mode1b (2FSK 50kbps mi=1.0), FEC') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan144_2FSK_2a_CN_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('CN', 0x13, 144, 200000, 779200000, 'Wi-SUN FAN, CN 779-787 MHz, Mode2a (2FSK 100kbps mi=0.5), FEC') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan145_2FSK_3_CN_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('CN', 0x15, 145, 400000, 779400000, 'Wi-SUN FAN, CN 779-787 MHz, Mode3 (2FSK 150kbps mi=0.5), FEC') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan145_2FSK_4a_CN_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('CN', 0x16, 145, 400000, 779400000, 'Wi-SUN FAN, CN 779-787 MHz, Mode4a (2FSK 200kbps mi=0.5), FEC') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - - def PHY_WISUN_FAN_1v1_779MHz_Plan145_2FSK_5_CN_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('CN', 0x18, 145, 400000, 779400000, 'Wi-SUN FAN, CN 779-787 MHz, Mode5 (2FSK 300kbps mi=0.5), FEC') - phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) - return phy - def PHY_WISUN_FAN_1v1_470MHz_Plan160_2FSK_1b_CN_FEC(self, model, phy_name=None): params = WisunFan1v1ChannelParamsOcelot('CN', 0x12, 160, 200000, 470200000, 'Wi-SUN FAN, CN 470-510 MHz, Mode1b (2FSK 50kbps mi=1.0), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) @@ -174,17 +149,17 @@ def PHY_WISUN_FAN_1v1_919MHz_Plan80_2FSK_2a_MY_FEC(self, model, phy_name=None): return phy def PHY_WISUN_FAN_1v1_919MHz_Plan81_2FSK_3_MY_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('MY', 0x15, 81, 400000, 919400000, 'Wi-SUN FAN, MY 919-923 MHz, Mode3 (2FSK 150kbps mi=0.5), FEC') + params = WisunFan1v1ChannelParamsOcelot('MY', 0x15, 81, 400000, 919200000, 'Wi-SUN FAN, MY 919-923 MHz, Mode3 (2FSK 150kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy def PHY_WISUN_FAN_1v1_919MHz_Plan81_2FSK_4a_MY_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('MY', 0x16, 81, 400000, 919400000, 'Wi-SUN FAN, MY 919-923 MHz, Mode4a (2FSK 200kbps mi=0.5), FEC') + params = WisunFan1v1ChannelParamsOcelot('MY', 0x16, 81, 400000, 919200000, 'Wi-SUN FAN, MY 919-923 MHz, Mode4a (2FSK 200kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy def PHY_WISUN_FAN_1v1_919MHz_Plan81_2FSK_5_MY_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('MY', 0x18, 81, 400000, 919400000, 'Wi-SUN FAN, MY 919-923 MHz, Mode5 (2FSK 300kbps mi=0.5), FEC') + params = WisunFan1v1ChannelParamsOcelot('MY', 0x18, 81, 400000, 919200000, 'Wi-SUN FAN, MY 919-923 MHz, Mode5 (2FSK 300kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy @@ -213,18 +188,18 @@ def PHY_WISUN_FAN_1v1_915MHz_Plan49_2FSK_5_PH_FEC(self, model, phy_name=None): phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_866MHz_Plan32_2FSK_1a_SG_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('SG', 0x11, 32, 100000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode1a (2FSK 50kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_866MHz_Plan41_2FSK_1a_SG_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('SG', 0x11, 41, 100000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode1a (2FSK 50kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_866MHz_Plan33_2FSK_2a_SG_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('SG', 0x13, 33, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode2a (2FSK 100kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_866MHz_Plan42_2FSK_2a_SG_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('SG', 0x13, 42, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode2a (2FSK 100kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy - def PHY_WISUN_FAN_1v1_866MHz_Plan33_2FSK_3_SG_FEC(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsOcelot('SG', 0x15, 33, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode3 (2FSK 150kbps mi=0.5), FEC') + def PHY_WISUN_FAN_1v1_866MHz_Plan42_2FSK_3_SG_FEC(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsOcelot('SG', 0x15, 42, 200000, 866100000, 'Wi-SUN FAN, SG 866-869 MHz, Mode3 (2FSK 150kbps mi=0.5), FEC') phy = self._make_wisun_fan_phy(model, params, phy_name=phy_name) return phy diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/Profile_Sigfox_TX.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/Profile_Sigfox_TX.py index b3944cb027..5ccb090798 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/Profile_Sigfox_TX.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/Profile_Sigfox_TX.py @@ -125,10 +125,10 @@ def set_header_defaults(self, model) -> None: def set_packet_inputs_defaults(self, model) -> None: # Packet Inputs - model.vars.frame_bitendian.value_forced = model.vars.frame_bitendian.var_enum.LSB_FIRST - model.vars.frame_length_type.value_forced = model.vars.frame_length_type.var_enum.VARIABLE_LENGTH + model.vars.frame_bitendian.value_forced = model.vars.frame_bitendian.var_enum.MSB_FIRST + model.vars.frame_length_type.value_forced = model.vars.frame_length_type.var_enum.FIXED_LENGTH model.vars.payload_white_en.value_forced = False - model.vars.payload_crc_en.value_forced = True + model.vars.payload_crc_en.value_forced = False def build_modem_inputs(self, profile: ModelProfile) -> None: pass @@ -173,6 +173,8 @@ def build_required_profile_inputs(self, model, profile: ModelProfile) -> None: IProfile.make_required_input(profile, model.vars.bitrate, "modem", readable_name="Bitrate", value_limit_min=100, value_limit_max=600, units_multiplier=UnitsMultiplier.KILO) + IProfile.make_required_input(profile, model.vars.fixed_length_size, category='frame_fixed_length', + readable_name="Fixed Payload Size", value_limit_min=0, value_limit_max=4095) def build_hidden_profile_inputs(self, model: ModelRoot, profile: ModelProfile) -> None: # Add Ocelot-specific variables @@ -195,8 +197,6 @@ def build_hidden_profile_inputs(self, model: ModelRoot, profile: ModelProfile) - # Hidden inputs to allow for fixed frame length testing self.make_hidden_input(profile, model.vars.frame_length_type, 'frame_general', readable_name="Frame Length Algorithm") - self.make_hidden_input(profile, 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a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/__pycache__/sw_profile_outputs_common.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/sw_profile_outputs_common.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/sw_profile_outputs_common.py index a6990ab718..39e74ddfd1 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/sw_profile_outputs_common.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/ocelot/profiles/sw_profile_outputs_common.py @@ -193,3 +193,5 @@ def build_rail_outputs(self, model, profile): if not hasattr(profile.outputs, "tx_eof_delay_ns"): profile.outputs.append(ModelOutput(model.vars.tx_eof_delay_ns, '', ModelOutputType.RAIL_CONFIG, readable_name='Time from TX EOF timestamp to end of frame on-air')) + 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b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_agc.py @@ -92,7 +92,7 @@ def calc_frzpkden_reg(self, model): def calc_gain_schedule_regs(self, model): lnaindexborder = 5 # Pre-silicon from Chris 10/23/23 - pgaindexborder = 4 # Pre-silicon from Chris 10/23/23 + pgaindexborder = 5 # From Chris 1/16/25 pnindexborder = 0 # New for Series3 # 0: RFPAD at end of RFPKD schedule # 1: RFPAD at end of IFPKD schedule diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_demodulator.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_demodulator.py index 644c08928c..0150beb296 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_demodulator.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_demodulator.py @@ -2,6 +2,11 @@ from pycalcmodel.core.variable import ModelVariableFormat, CreateModelVariableEnum from enum import Enum from math import * +import numpy as np +import numpy.matlib +from scipy import signal as sp +from pyradioconfig.parts.rainier.calculators.calc_shaping import CalcShapingRainier +from pyradioconfig.calculator_model_framework.Utils.LogMgr import LogMgr class CalcDemodulatorRainier(Calc_Demodulator_Bobcat): @@ -313,8 +318,115 @@ def calc_modeminfo_reg(self, model): self._reg_write(model.vars.SEQ_MODEMINFO_SOFTMODEM_EN, soft_modem_used) self._reg_write(model.vars.SEQ_MODEMINFO_SPARE2, 0) + def return_ksi2_ksi3_calc(self, model, ksi1): + # get parameters + lock_bwsel = model.vars.lock_bwsel.value # use the lock bw + bwsel = model.vars.bwsel.value # use the lock bw + osr = int(round(model.vars.oversampling_rate_actual.value)) + shaping_filter = model.vars.shaping_filter.value + # not using this model variable but keeping it here. Will remove it once, sure. + # shaping_coeff_override = model.vars.shaping_coeff_ksi_calc_override.value + + # calculate only if needed - ksi1 would be already calculated if that is the case + if (ksi1 == 0): + best_ksi2 = 0 + best_ksi3 = 0 + best_ksi3wb = 0 + else: + # get shaping filter and it oversampling rate with respect to baudrate + + # If no shaping_filter is a generic shape, use generic shape values for ksi calculation. + # If shaping_filter is custom, assumption is that shaping_filter will be set to NONE, and manual overrides + # will be used. In that case, check if there are any non-zero shaping coeffs, and use those coeffs for + # ksi calculation + sf = CalcShapingRainier().get_shaping_filter(model)/1.0 + if shaping_filter.value == model.vars.shaping_filter._var_enum.NONE.value: + if np.count_nonzero(sf) == 64: + LogMgr.Error("ERROR: No pulse shaping being used, please select a pulse shape in shaping_filter") + else: + # if shaping_filter is set to a generic shape (e.g. gaussian, rc, rrc), + # use generic filter to calculate ksi + sf, shaping = CalcShapingRainier().run_shaping_filter_calc(model) + sfosr = 8 # shaping filter coeffs are sampled at 8x + + # get channel filter and expend the symmetric part + cfh = np.asarray(self.return_coeffs(lock_bwsel)) + cf = np.block([cfh, cfh[-2::-1]])/1.0 + cfh = np.asarray(self.return_coeffs(bwsel)) + cfwb = np.block([cfh, cfh[-2::-1]])/1.0 + + # base sequences for +1 and -1 + a = np.array([ 1.0, 0, 0, 0, 0, 0, 0, 0]) + b = np.array([-1.0, 0, 0, 0, 0, 0, 0, 0]) + + # generate frequency signal for periodic 1 1 1 0 0 0 sequence for ksi1 + x1 = np.matlib.repmat(np.append(np.matlib.repmat(a, 1, 3),np.matlib.repmat(b, 1, 3)), 1, 4) + f1 = self.gen_frequency_signal( x1[0], sf, cf, sfosr, model) + + # generate frequency signal for periodic 1 1 0 0 1 1 sequence for ksi2 + x2 = np.matlib.repmat(np.append(np.matlib.repmat(a, 1, 2), np.matlib.repmat(b, 1, 2)), 1, 6) + f2 = self.gen_frequency_signal( x2[0], sf, cf, sfosr, model) + + # generate frequency signal for periodic 1 0 1 0 1 0 sequence for ksi3 + x3 = np.matlib.repmat(np.append(np.matlib.repmat(a, 1, 1), np.matlib.repmat(b, 1, 1)), 1, 12) + f3 = self.gen_frequency_signal( x3[0], sf, cf, sfosr, model) + + # generate frequency signal for periodic 1 0 1 0 1 0 sequence for ksi3 but with aqcusition channel filter + f3wb = self.gen_frequency_signal( x3[0], sf, cfwb, sfosr, model) + + # find scaling needed to get f1 to the desired ksi1 value and apply it to f2 and f3 + ind = osr - 1 + scaler = ksi1 / np.max(np.abs(f1[ind + 8 * osr - 1: - 2 * osr: osr])) + f2 = scaler * f2 + f3 = scaler * f3 + f3wb = scaler * f3wb + + # from matplotlib import pyplot as plt + # plt.plot(f1*scaler,'x-') + # plt.show() + # plt.plot(f2,'x-') + # plt.plot(f3,'x-') + # plt.plot(f3wb,'x-') + + # search for best phase to sample to get ksi3 value. + # best phase is the phase that gives largest eye opening + best_ksi3 = 0 + for ph in range(osr): + ksi3 = np.max(np.round(np.abs(f3[ - 6 * osr + ph: - 2 * osr: osr]))) + if ksi3 > best_ksi3: + best_ksi3 = ksi3 + + best_ksi3wb = 0 + for ph in range(osr): + ksi3wb = np.max(np.round(np.abs(f3wb[ - 6 * osr + ph: - 2 * osr: osr]))) + if ksi3wb > best_ksi3wb: + best_ksi3wb = ksi3wb + + # ksi2 is tricky depending if we sampled perfectly (symmetric around a + # pulse we should see the same value for 1 1 0 and 0 1 1 sequence but + # most of the time we cannot sample perfectly since can go as low as 4x + # oversampling for Viterbi PHYs. In this case we have 2 ksi values which we + # average to get the ksi2 value + best_cost = 1e9 + for ph in range(osr): + x = np.round(np.abs(f2[- 6 * osr + ph: - 2 * osr: osr])) + cost = np.sum(np.abs(x - np.mean(x))) + if cost < best_cost: + best_cost = cost + best_ksi2 = np.round(np.mean(x)) + + # ensure that ksi1 >= ksi2 >= ksi3 + # this code should only be needed in the extreme case when ksi1 = ksi2 = ksi3 and + # small variation can cause one to be larger than the other + best_ksi2 = ksi1 if best_ksi2 > ksi1 else best_ksi2 + best_ksi3 = best_ksi2 if best_ksi3 > best_ksi2 else best_ksi3 + best_ksi3wb = best_ksi2 if best_ksi3wb > best_ksi2 else best_ksi3wb + + return best_ksi2, best_ksi3, best_ksi3wb + + def calc_rssi_rf_adjust_db(self, model): - model.vars.rssi_rf_adjust_db.value = -14.0 + model.vars.rssi_rf_adjust_db.value = -15.8 def calc_dsss_concurrent_reg(self, model): trecs_used = model.vars.MODEM_VITERBIDEMOD_VTDEMODEN.value @@ -347,4 +459,51 @@ def calc_freq_gain_virtual_reg(self,model): self._reg_write(model.vars.SEQ_MODINDEX_CALC_FREQGAINM, freqgain_m) self._reg_write(model.vars.SEQ_MODINDEX_CALC_FREQGAINE, freqgain_e) self._reg_write(model.vars.SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINM, freqgain_m) - self._reg_write(model.vars.SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, freqgain_e) \ No newline at end of file + self._reg_write(model.vars.SEQ_MODINDEX_CALC_MODINDEXE_DOUBLED_FREQGAINE, freqgain_e) + + def calc_chmutetimer_reg(self, model): + hop_enable = True if model.vars.hop_enable.value == model.vars.hop_enable.var_enum.ENABLED else False + + if hop_enable: + chmutetimer = 195 # Default value for 2ZB hopping + else: + chmutetimer = 0 + + self._reg_write(model.vars.MODEM_SRCCHF_CHMUTETIMER, chmutetimer) + + def calc_fast_switching_regs(self, model): + hop_enable = True if model.vars.hop_enable.value == model.vars.hop_enable.var_enum.ENABLED else False + protocol_id = model.vars.protocol_id.value + + # Enable DTIMLOSS feature for fast switching PHYs + # See https://jira.silabs.com/browse/MCUW_RADIO_CFG-2525 + if hop_enable and protocol_id == model.vars.protocol_id.var_enum.Zigbee: + self._reg_write(model.vars.MODEM_TRECSCFG_DTIMLOSSEN, 1) + self._reg_write(model.vars.MODEM_TRECSCFG_DTIMLOSSTHD, 200) + elif hop_enable and protocol_id == model.vars.protocol_id.var_enum.BLE: + self._reg_write(model.vars.MODEM_TRECSCFG_DTIMLOSSEN, 1) + self._reg_write(model.vars.MODEM_TRECSCFG_DTIMLOSSTHD, 1000) + else: + self._reg_write(model.vars.MODEM_TRECSCFG_DTIMLOSSEN, 0) + self._reg_write(model.vars.MODEM_TRECSCFG_DTIMLOSSTHD, 0) + + def calc_spare_regs(self, model): + hop_enable = model.vars.hop_enable.value == model.vars.hop_enable.var_enum.ENABLED + + # revB0+ SPARE register is defined as follows: + # dsss_dsa_unqualified_sel= spare[0] + # lr_eof_sel_force0= spare[1] + # lrble_compound_muxctrl= spare[2] + + if hop_enable: + # : if fixed timeout is used to control hopping, the hopping controller requires unqualified DSA signal + # : Qualified DSA signal may take longer than 32 us timeout, causing an incorrect channel switch at the end + # : of the timeout. + dsss_dsa_unqualified_sel = 1 + else: + dsss_dsa_unqualified_sel = 0 + + # : if additional spare fields needs to be set, bitshift the values here + reg_val = dsss_dsa_unqualified_sel + + self._reg_write(model.vars.MODEM_SPARE_SPARE, reg_val) diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_enhanced.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_enhanced.py index 29093b573d..7122d9c0db 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_enhanced.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_enhanced.py @@ -48,4 +48,17 @@ def calc_enhanced_misc(self, model): self._reg_write(model.vars.MODEM_SICORR_CORRTHRESH2SYMB, default=True, do_not_care=do_not_care) self._reg_write(model.vars.MODEM_SICTRL1_FREQOFFTOLERANCE, default=True, do_not_care=do_not_care) self._reg_write(model.vars.MODEM_SICTRL2_SISTARTDELAY, default=True, do_not_care=do_not_care) - self._reg_write(model.vars.MODEM_SICTRL2_SISTARTDELAYMODE, default=True, do_not_care=do_not_care) \ No newline at end of file + self._reg_write(model.vars.MODEM_SICTRL2_SISTARTDELAYMODE, default=True, do_not_care=do_not_care) + + # : only available for B0 onward + if not model.part_revision in ['A0', 'A1', 'A2']: + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_FASTCWDETECTEN, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_FASTSUPERCHIPEN, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_FASTNARROWPULSEEN, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_EYEOPENINGMODE, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_CWDETECTSTARTWINDOW, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_CWDETECTTHRESHOLD, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_SUPERCHIPSTARTWINDOW, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_NPULSEFIXEDTHRESHOLD, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_NPULSETHRESHADJEN, default=True, do_not_care=do_not_care) + self._reg_write(model.vars.MODEM_SIFASTDETECTCTRL_NPULSETHRESHADJ, default=True, do_not_care=do_not_care) \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_global.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_global.py index df11b56768..3ed56b81fe 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_global.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_global.py @@ -8,6 +8,11 @@ def buildVariables(self, model): super().buildVariables(model) self._add_SYNTH_S3_regs(model) self._add_syctrl_regs_s3(model) + self._add_spare_regs(model) + self._add_fastdetect_regs(model) + + def _add_spare_regs(self, model): + self._addModelRegister(model, 'MODEM.SPARE.SPARE', int, ModelVariableFormat.HEX) def _add_common_regs(self, model): super()._add_common_regs(model) @@ -365,6 +370,26 @@ def _add_SYNTH_S3_regs(self, model): self._addModelRegister(model, 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINE', int, ModelVariableFormat.HEX) self._addModelRegister(model, 'SEQ.MODINDEX_CALC_MODINDEXE_DOUBLED.FREQGAINM', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.TRECSCFG.DTIMLOSSEN', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.TRECSCFG.DTIMLOSSTHD', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SRCCHF.CHMUTETIMER', int, ModelVariableFormat.HEX) + + self._addModelRegister(model, 'SEQ.MISC.SYNTH_MODE_TX00D_EN', int, ModelVariableFormat.HEX) + + def _add_fastdetect_regs(self, model): + if not (model.part_family.upper() == 'RAINIER' and model.part_revision in ['A0', 'A1', 'A2']): + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.FASTCWDETECTEN', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.FASTSUPERCHIPEN', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.FASTNARROWPULSEEN', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.EYEOPENINGMODE', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.CWDETECTSTARTWINDOW', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.CWDETECTTHRESHOLD', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.SUPERCHIPSTARTWINDOW', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.NPULSEFIXEDTHRESHOLD', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.NPULSETHRESHADJEN', int, ModelVariableFormat.HEX) + self._addModelRegister(model, 'MODEM.SIFASTDETECTCTRL.NPULSETHRESHADJ', int, ModelVariableFormat.HEX) + + def _add_RAC_CLKMULTEN0_en(self, model): """CLKMULTENADCDRV, CLKMULTENDACDRV become FW controlled as must shut them off during opposite operation""" pass diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_shaping.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_shaping.py index cdd7210d76..e398c48a81 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_shaping.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_shaping.py @@ -127,6 +127,12 @@ def calc_shaping_reg(self, model): model (ModelRoot) : Data model to read and write variables from """ + coeff, shaping = self.run_shaping_filter_calc(model) + + self.write_coeff_registers(model, coeff, shaping) + + def run_shaping_filter_calc(self, model): + shaping_filter_option = model.vars.shaping_filter.value max_filter_taps = model.vars.max_filter_taps.value coeff = np.zeros(max_filter_taps) @@ -175,4 +181,4 @@ def calc_shaping_reg(self, model): else: raise CalculationException("ERROR: Unrecognized shaping filter option") - self.write_coeff_registers(model, coeff, shaping) + return coeff, shaping diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_synth.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_synth.py index 8b464527dd..b117c558fa 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_synth.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/calculators/calc_synth.py @@ -68,6 +68,14 @@ def calc_ifadcenhalfmode_reg(self, model): self._reg_write(model.vars.RAC_ADCCTRL1_ADCENHALFMODE, reg) + def calc_synth_settling_mode(self, model): + hop_enable = model.vars.hop_enable.value # Disable by default + + if hop_enable == model.vars.hop_enable.var_enum.ENABLED: + model.vars.synth_settling_mode.value = model.vars.synth_settling_mode.var_enum.FAST + else: # FastSw Disabled + model.vars.synth_settling_mode.value = model.vars.synth_settling_mode.var_enum.NORMAL + def calc_adc_clockmode_reg(self, model): adc_clock_mode_actual = model.vars.adc_clock_mode.value @@ -340,8 +348,6 @@ def calc_tx_mode_reg(self, model): self._reg_write(model.vars.SYNTH_DSMCTRLTX_LSBFORCETX, tx_mode_settings['SYNTH.DSMCTRLTX.LSBFORCETX'][ind]) self._reg_write(model.vars.SYNTH_DSMCTRLTX_DEMMODETX, tx_mode_settings['SYNTH.DSMCTRLTX.DEMMODETX'][ind]) - #:self._reg_write(model.vars.RAC_SYCTRL1_SYLODIVSELFP4G82G4TX, tx_mode_settings['RAC_SYCTRL1_SYLODIVSELFP4G82G4TX'][ind]) - #self._reg_write(model.vars.RAC_SYMMDCTRL_SYMMDSEL56STGTX, tx_mode_settings['RAC_SYMMDCTRL_SYMMDSEL56STGTX'][ind]) def calc_dlf_ctrl(self, model): @@ -421,6 +427,9 @@ def calc_s3_synth_virtual_reg(self, model): self._reg_write(model.vars.SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT0, int(denominit0)) self._reg_write(model.vars.SEQ_MMDDENOMINIT_CALC_DOUBLED_DENOMINIT1, int(denominit1)) + # Force TX10D mode by default + self._reg_write(model.vars.SEQ_MISC_SYNTH_MODE_TX00D_EN, 0) + def calc_synth_misc(self, model): # self._reg_write(model.vars.RAC_SYCTRL1_SYLODIVSELFP4G82G4, 0) #RX always 2.4G, default REG value, remove from calculator # self._reg_write(model.vars.RAC_SYMMDCTRL_SYMMDSEL56STG, 0) #RX always 2.4G @@ -475,9 +484,8 @@ def calc_hop_enable(self, model): def calc_rx_mode(self, model): synth_settling_mode = model.vars.synth_settling_mode.value - hop_enable = True if model.vars.hop_enable.value == model.vars.hop_enable.var_enum.ENABLED else False - if hop_enable: + if synth_settling_mode == model.vars.synth_settling_mode.var_enum.FAST: model.vars.synth_rx_mode.value = model.vars.synth_rx_mode.var_enum.MODE_HOP elif synth_settling_mode == model.vars.synth_settling_mode.var_enum.BLE_LR: model.vars.synth_rx_mode.value = model.vars.synth_rx_mode.var_enum.MODE1 diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/filters/phy_filters.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/filters/phy_filters.py index 254ebd574b..d8e3108d06 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/filters/phy_filters.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/filters/phy_filters.py @@ -10,6 +10,8 @@ class PhyFiltersRainier(IPhyFilter): 'Phys_Internal_Base_ValOnly', 'Phys_Internal_Connect', 'Phys_Internal_Base_Customer_Signify', + 'Phys_Internal_Base_FastSw', + 'Phys_Internal_Base_DutyCycle' ] # Studio white list (these PHYs show in Studio as proprietary starting points) diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_BLE.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_BLE.py index cd9208fb45..6dbdfe1df6 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_BLE.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_BLE.py @@ -1,4 +1,5 @@ from pyradioconfig.parts.bobcat.phys.Phys_RAIL_Base_Standard_BLE import PHYS_Bluetooth_LE_Bobcat +from pyradioconfig.parts.rainier.phys.Phys_RAIL_Base_Standard_IEEE802154 import PhysRailBaseStandardIeee802154Rainier from pyradioconfig.parts.common.phys.phy_common import PHY_COMMON_FRAME_BLE, PHY_COMMON_FRAME_BLE_CODED, PHY_COMMON_FRAME_BLE_AOX from py_2_and_3_compatibility import * from pyradioconfig.calculator_model_framework.decorators.phy_decorators import do_not_inherit_prod_phys @@ -732,7 +733,7 @@ def PHY_Bluetooth_LongRange_NOdsa_125kbps(self, model, phy_name=None): phy_name=phy_name) self.Bluetooth_LongRange_base(phy, model) - phy.profile_outputs.AGC_GAINRANGE_PNGAINSTEP.override = 4 + phy.profile_outputs.AGC_GAINRANGE_PNGAINSTEP.override = 1 phy.profile_outputs.MODEM_LONGRANGE_LRBLEDSA.override = 0 phy.profile_outputs.rx_sync_delay_ns.override = 7000 @@ -764,7 +765,7 @@ def PHY_Bluetooth_LongRange_NOdsa_500kbps(self, model, phy_name=None): phy_name=phy_name) self.Bluetooth_LongRange_500kbps_base(phy, model) - phy.profile_outputs.AGC_GAINRANGE_PNGAINSTEP.override = 4 + phy.profile_outputs.AGC_GAINRANGE_PNGAINSTEP.override = 1 phy.profile_outputs.MODEM_LONGRANGE_LRBLEDSA.override = 0 phy.profile_outputs.rx_sync_delay_ns.override = 6750 @@ -901,14 +902,13 @@ def PHY_Bluetooth_1M_Concurrent(self, model, phy_name=None): phy.profile_outputs.MODEM_LONGRANGE6_LRSPIKETHD.override = 0 # MCUW_RADIO_CFG-1705, RAIL_LIB-6014 to be compatible with lynx workaround of MCUW_RADIO_CFG-1701 phy.profile_outputs.rx_sync_delay_ns.override = 50000 - phy.profile_outputs.rx_eof_delay_ns.override = 11750 + phy.profile_outputs.rx_eof_delay_ns.override = 10700 phy.profile_outputs.tx_sync_delay_ns.override = 2000 phy.profile_outputs.tx_eof_delay_ns.override = 2000 return phy - def PHY_Bluetooth_LongRange_nodsa_125kbps_dutycycle(self, model, phy_name=None): - phy = self.PHY_Bluetooth_LongRange_dsa_125kbps(model, phy_name) + def _ble_dutycycle_overrides(self, phy): phy.profile_outputs.AGC_CTRL7_SUBDEN.override = 2 phy.profile_outputs.AGC_CTRL7_SUBINT.override = 16 phy.profile_outputs.AGC_CTRL7_SUBNUM.override = 0 @@ -918,6 +918,16 @@ def PHY_Bluetooth_LongRange_nodsa_125kbps_dutycycle(self, model, phy_name=None): phy.profile_outputs.MODEM_LONGRANGE_LRBLEDSA.override = 0 return phy + def PHY_Bluetooth_LongRange_nodsa_125kbps_dutycycle(self, model, phy_name=None): + phy = self.PHY_Bluetooth_LongRange_dsa_125kbps(model, phy_name) + self._ble_dutycycle_overrides(phy) + return phy + + def PHY_Bluetooth_LongRange_nodsa_500kbps_dutycycle(self, model, phy_name=None): + phy = self.PHY_Bluetooth_LongRange_dsa_500kbps(model, phy_name) + self._ble_dutycycle_overrides(phy) + return phy + # ############## @@ -1285,4 +1295,91 @@ def BLE_2M_AOX_TX_Shaping_Coeffs_IQMOD(self, phy, model): phy.profile_outputs.MODEM_SHAPING3_COEFF14.override = 53 phy.profile_outputs.MODEM_SHAPING3_COEFF15.override = 37 - self.override_other_shaping_coeff_to_zero(phy, start_coeff=16) \ No newline at end of file + self.override_other_shaping_coeff_to_zero(phy, start_coeff=16) + + def PHY_BLE_ZB_Concurrent_Hop_BLERX(self, model, phy_name=None): + phy = PhysRailBaseStandardIeee802154Rainier().PHY_BLE_ZB_Concurrent_Hop(model) + + model.vars.targetmin_osr.value_forced = 2 # osr=2 is not actual BLE 1M OSR as PHY baudrate still references ZB + model.vars.src2_ratio.value_forced = 0.833333333333 # Consequence of forcing DEC1 + phy.profile_outputs.MODEM_CF_DEC1.override = 1 + phy.profile_outputs.MODEM_DIGMIXCTRL_BLEORZB.override = 0 + phy.profile_outputs.MODEM_DIGMIXCTRL_DIGMIXFREQ.override = 149640 + phy.profile_outputs.MODEM_DIGMIXCTRL_DSSSCFECOMBO.override = 0 + phy.profile_outputs.MODEM_DIGMIXCTRL_HOPPINGSRC.override = 0 + phy.profile_outputs.MODEM_DIGMIXCTRL_MULTIPHYHOP.override = 0 + phy.profile_outputs.MODEM_DIGMIXCTRL_RXBRINTSHIFT.override = 0 + phy.profile_outputs.MODEM_LOG2X4_LOG2X4.override = 4 + phy.profile_outputs.MODEM_LOG2X4_LOG2X4FWSEL.override = 1 + phy.profile_outputs.MODEM_SICTRL0_FREQNOMINAL.override = 55 + phy.profile_outputs.MODEM_SICTRL0_NOISETHRESH.override = 150 + phy.profile_outputs.MODEM_SICTRL0_NOISETHRESHADJ.override = 30 + phy.profile_outputs.MODEM_SICTRL0_PEAKNUMADJ.override = 1 + phy.profile_outputs.MODEM_SICTRL0_PEAKNUMTHRESHLW.override = 4 + phy.profile_outputs.MODEM_SICTRL0_SIMODE.override = 3 + phy.profile_outputs.MODEM_SICTRL2_PEAKNUMADJEN.override = 51 + phy.profile_outputs.MODEM_SICTRL2_SISTARTDELAY.override = 1 + phy.profile_outputs.MODEM_SICTRL2_SISTARTDELAYMODE.override = 1 + phy.profile_outputs.MODEM_SRCCHF_SRCRATIO2.override = 19661 + phy.profile_outputs.MODEM_SYNCWORDCTRL_DUALSYNC.override = 0 + phy.profile_outputs.MODEM_SYNCWORDCTRL_DUALSYNC2TH.override = 0 + phy.profile_outputs.MODEM_SYNCWORDCTRL_SYNCDET2TH.override = 0 + + phy.profile_outputs.MODEM_EHDSSSCFG3_LQIAVGWIN.override = 2 + phy.profile_outputs.MODEM_EHDSSSCFG3_OPMODE.override = 0 + phy.profile_outputs.MODEM_EHDSSSCTRL_EHDSSSEN.override = 0 # Somehow TRECS is not being enabled - disabling this seem to help + + phy.profile_outputs.FRC_CTRL_RXFCDMODE.override = 0 + phy.profile_outputs.FRC_DFLCTRL_DFLINCLUDECRC.override = 0 + phy.profile_outputs.FRC_DFLCTRL_DFLOFFSET.override = 1 + phy.profile_outputs.FRC_DFLCTRL_MINLENGTH.override = 1 + phy.profile_outputs.FRC_FCD0_CALCCRC.override = 1 + phy.profile_outputs.FRC_FCD0_INCLUDECRC.override = 1 + phy.profile_outputs.FRC_FCD0_WORDS.override = 255 + phy.profile_outputs.FRC_FCD2_CALCCRC.override = 1 + phy.profile_outputs.FRC_FCD2_INCLUDECRC.override = 1 + phy.profile_outputs.FRC_FCD2_WORDS.override = 255 + phy.profile_outputs.FRC_MAXLENGTH_MAXLENGTH.override = 256 + phy.profile_outputs.FRC_TRAILTXDATACTRL_POSTAMBLEEN.override = 1 + phy.profile_outputs.FRC_TRAILTXDATACTRL_TRAILTXDATACNT.override = 2 + phy.profile_outputs.FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE.override = 1 + phy.profile_outputs.FRC_WCNTCMP1_LENGTHFIELDLOC.override = 1 + phy.profile_outputs.RFCRC_CTRL_CRCWIDTH.override = 2 + phy.profile_outputs.RFCRC_INIT_INIT.override = 11184810 + phy.profile_outputs.RFCRC_POLY_POLY.override = 14311424 + + # These registers will be forced by calculator - need to force back + phy.profile_outputs.MODEM_CHFCOE00_SET0COEFF0.override = 995 + phy.profile_outputs.MODEM_CHFCOE00_SET0COEFF1.override = 952 + phy.profile_outputs.MODEM_CHFCOE00_SET0COEFF2.override = 955 + phy.profile_outputs.MODEM_CHFCOE01_SET0COEFF3.override = 73 + phy.profile_outputs.MODEM_CHFCOE01_SET0COEFF4.override = 372 + phy.profile_outputs.MODEM_CHFCOE02_SET0COEFF5.override = 658 + phy.profile_outputs.MODEM_CHFCOE02_SET0COEFF6.override = 611 + phy.profile_outputs.MODEM_CHFCOE03_SET0COEFF7.override = 3 + phy.profile_outputs.MODEM_CHFCOE03_SET0COEFF8.override = 3128 + phy.profile_outputs.MODEM_CHFCOE04_SET0COEFF10.override = 15430 + phy.profile_outputs.MODEM_CHFCOE04_SET0COEFF9.override = 14799 + phy.profile_outputs.MODEM_CHFCOE05_SET0COEFF11.override = 1337 + phy.profile_outputs.MODEM_CHFCOE05_SET0COEFF12.override = 4722 + phy.profile_outputs.MODEM_CHFCOE06_SET0COEFF13.override = 7779 + phy.profile_outputs.MODEM_CHFCOE06_SET0COEFF14.override = 9010 + phy.profile_outputs.MODEM_CHFCOE10_SET1COEFF0.override = 30 + phy.profile_outputs.MODEM_CHFCOE10_SET1COEFF1.override = 87 + phy.profile_outputs.MODEM_CHFCOE10_SET1COEFF2.override = 155 + phy.profile_outputs.MODEM_CHFCOE11_SET1COEFF3.override = 169 + phy.profile_outputs.MODEM_CHFCOE11_SET1COEFF4.override = 46 + phy.profile_outputs.MODEM_CHFCOE12_SET1COEFF5.override = 1780 + phy.profile_outputs.MODEM_CHFCOE12_SET1COEFF6.override = 3376 + phy.profile_outputs.MODEM_CHFCOE13_SET1COEFF7.override = 2984 + phy.profile_outputs.MODEM_CHFCOE13_SET1COEFF8.override = 2962 + phy.profile_outputs.MODEM_CHFCOE14_SET1COEFF10.override = 947 + phy.profile_outputs.MODEM_CHFCOE14_SET1COEFF9.override = 15896 + phy.profile_outputs.MODEM_CHFCOE15_SET1COEFF11.override = 2988 + phy.profile_outputs.MODEM_CHFCOE15_SET1COEFF12.override = 5154 + phy.profile_outputs.MODEM_CHFCOE16_SET1COEFF13.override = 6813 + phy.profile_outputs.MODEM_CHFCOE16_SET1COEFF14.override = 7436 + phy.profile_outputs.MODEM_RXBR_RXBRINT.override = 2 + + phy.profile_outputs.AGC_GAINSTEPLIM0_CFLOOPDEL.override = 45 + return phy \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_IEEE802154.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_IEEE802154.py index 0e96ea0281..f0c411dd25 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_IEEE802154.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/phys/Phys_RAIL_Base_Standard_IEEE802154.py @@ -103,7 +103,7 @@ def IEEE802154_2p4GHz_cohdsa_base(self, phy, model): phy.profile_outputs.MODEM_LONGRANGE1_HYSVAL.override = 3 phy.profile_outputs.MODEM_COH0_COHDYNAMICBBSSEN.override = 1 - LRCHPWR_sens = 29 # target sens is at -105.5 which is between CW CHPWR 27 and 28 + LRCHPWR_sens = 32 # target sens is at -105.5 which is between CW CHPWR 30 and 31 phy.profile_outputs.MODEM_LONGRANGE2_LRCHPWRTH1.override = LRCHPWR_sens - 6 - 6 phy.profile_outputs.MODEM_LONGRANGE2_LRCHPWRTH2.override = LRCHPWR_sens - 6 # this is neede dfo cases with strong blocker @@ -133,9 +133,9 @@ def IEEE802154_2p4GHz_cohdsa_base(self, phy, model): ################# # DSA settings ################# - LRSPIKETHD = 115 # allowing some false detections to perform better near sensitivity - FIXEDCDTHFORIIR = 125 # # choosing a value of LRSPIKETHD that causes no false detections at static BBSS in 10s - LRCHPWRSPIKETH = 32 # use fixed DSA threshold till -100dBm + LRSPIKETHD = 130 # allowing some false detections to perform better near sensitivity + FIXEDCDTHFORIIR = 145 # # choosing a value of LRSPIKETHD that causes no false detections at static BBSS in 10s + LRCHPWRSPIKETH = 34 # use fixed DSA threshold till -100dBm phy.profile_outputs.MODEM_COH3_COHDSAEN.override = 1 phy.profile_outputs.MODEM_COH3_CDSS.override = 4 @@ -208,7 +208,7 @@ def IEEE802154_2p4GHz_cohdsa_base(self, phy, model): phy.profile_outputs.MODEM_COH0_COHDYNAMICPRETHRESH.override = 1 phy.profile_outputs.MODEM_COH0_COHDYNAMICSYNCTHRESH.override = 1 - SYNCTHRESH0 = 25 + SYNCTHRESH0 = 45 phy.profile_outputs.MODEM_COH1_SYNCTHRESH0.override = SYNCTHRESH0 phy.profile_outputs.MODEM_COH1_SYNCTHRESH1.override = SYNCTHRESH0 + 5 phy.profile_outputs.MODEM_COH1_SYNCTHRESH2.override = SYNCTHRESH0 + 5 + 5 @@ -314,6 +314,21 @@ def IEEE802154_2p4GHz_signal_identifier_fast_hopping_overrides(self, phy, model) phy.profile_outputs.MODEM_SICORR_CORRTHRESHUP.override = 31 # 0X1F phy.profile_outputs.MODEM_SICORR_CORRTHRESH2SYMB.override = 219 # 0XDB + + # TODO: Add to lpwh72000 and lpwh74000 when available in register map + if not (model.part_family.upper() == 'RAINIER' and model.part_revision in ['A0', 'A1', 'A2']): + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_FASTCWDETECTEN.override = 1 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_FASTSUPERCHIPEN.override = 0 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_FASTNARROWPULSEEN.override = 1 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_EYEOPENINGMODE.override = 2 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_CWDETECTSTARTWINDOW.override = 5 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_CWDETECTTHRESHOLD.override = 25 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_SUPERCHIPSTARTWINDOW.override = 9 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_NPULSEFIXEDTHRESHOLD.override = 0 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_NPULSETHRESHADJEN.override = 5 + phy.profile_outputs.MODEM_SIFASTDETECTCTRL_NPULSETHRESHADJ.override = 3 + + def Enhanced_DSSS_comm_settings(self, model, phy_name=None): phy = self._makePhy(model, model.profiles.Base, readable_name='Legacy IEEE 802.15.4 2p4GHz PHY from Jumbo', phy_name=phy_name) @@ -658,6 +673,8 @@ def PHY_IEEE802154_2p4GHz_Enhanced_Scan(self, model, phy_name=None): def PHY_IEEE802154_2p4GHz_Enhanced_ANTDIV(self, model, phy_name=None): phy = self.PHY_IEEE802154_2p4GHz_Enhanced_Scan(model, phy_name=None) + phy.profile_inputs.hop_enable.value = model.vars.hop_enable.var_enum.DISABLED + phy.profile_inputs.synth_settling_mode.value = model.vars.synth_settling_mode.var_enum.FAST phy.profile_inputs.bandwidth_hz.value = 2200000 phy.profile_outputs.MODEM_SYNC2_SYNC2.override = 167 @@ -716,6 +733,7 @@ def PHY_IEEE802154_2p4GHz_Enhanced_ANTDIV(self, model, phy_name=None): def PHY_IEEE802154_2p4GHz_Enhanced_ANTDIV_Scan(self, model, phy_name=None): phy = self.PHY_IEEE802154_2p4GHz_Enhanced_ANTDIV(model, phy_name=None) + phy.profile_inputs.hop_enable.value = model.vars.hop_enable.var_enum.ENABLED phy.profile_outputs.MODEM_PHDMODCTRL_FASTHOPPINGEN.override = 1 phy.profile_outputs.MODEM_EHDSSSCTRL_DUALDSA.override = 1 @@ -780,11 +798,15 @@ def PHY_BLE_ZB_Concurrent_Hop(self, model, phy_name=None): phy.profile_outputs.MODEM_COH0_COHCHPWRTH0.override = 216 phy.profile_outputs.MODEM_COH0_COHCHPWRTH1.override = 0 + phy.profile_outputs.MODEM_SRCCHF_CHMUTETIMER.override = 245 # ZBRX value in sim fast sw SEQACC table + return phy def PHY_IEEE802154_2p4GHz_Enhanced_DutyCycling(self, model, phy_name=None): ### This PHY is used scan two 802154 channels with power duty cycling phy = self.PHY_IEEE802154_2p4GHz_Enhanced_Scan(model, phy_name=None) + phy.profile_inputs.hop_enable.value = model.vars.hop_enable.var_enum.DISABLED + phy.profile_inputs.synth_settling_mode.value = model.vars.synth_settling_mode.var_enum.FAST phy.profile_outputs.MODEM_COCURRMODE_DSSSDSACHK.override = 25 phy.profile_outputs.MODEM_EHDSSSCFG2_DSSSDSAQUALEN.override = 1 @@ -816,4 +838,4 @@ def PHY_IEEE802154_2p4GHz_cohdsa(self, model, phy_name=None): phy.profile_outputs.AGC_GAINRANGE_PNGAINSTEP.override = 3 phy.profile_outputs.MODEM_LONGRANGE1_AVGWIN.override = 2 - return phy + return phy \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/profiles/Profile_BLE.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/profiles/Profile_BLE.py index a171901d39..95436f5a73 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/profiles/Profile_BLE.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/rainier/profiles/Profile_BLE.py @@ -49,37 +49,37 @@ def _build_delay_settings(self, model): if ble_feature == model.vars.ble_feature.var_enum.LE_1M: model.vars.rx_sync_delay_ns.value_forced = 50000 - model.vars.rx_eof_delay_ns.value_forced = 11000 - model.vars.tx_sync_delay_ns.value_forced = 3500 - model.vars.tx_eof_delay_ns.value_forced = 750 + model.vars.rx_eof_delay_ns.value_forced = 9980 + model.vars.tx_sync_delay_ns.value_forced = 3210 + model.vars.tx_eof_delay_ns.value_forced = 1106 elif ble_feature == model.vars.ble_feature.var_enum.LE_2M: model.vars.rx_sync_delay_ns.value_forced = 12492 - model.vars.rx_eof_delay_ns.value_forced = 6000 - model.vars.tx_sync_delay_ns.value_forced = 3000 - model.vars.tx_eof_delay_ns.value_forced = 535 + model.vars.rx_eof_delay_ns.value_forced = 5460 + model.vars.tx_sync_delay_ns.value_forced = 1520 + model.vars.tx_eof_delay_ns.value_forced = 416 elif ble_feature == model.vars.ble_feature.var_enum.CODED_125K: model.vars.rx_sync_delay_ns.value_forced = 7000 - model.vars.rx_eof_delay_ns.value_forced = 6500 - model.vars.tx_sync_delay_ns.value_forced = 5375 - model.vars.tx_eof_delay_ns.value_forced = 500 + model.vars.rx_eof_delay_ns.value_forced = 7930 + model.vars.tx_sync_delay_ns.value_forced = 3182 + model.vars.tx_eof_delay_ns.value_forced = 1058 elif ble_feature == model.vars.ble_feature.var_enum.CODED_500K: model.vars.rx_sync_delay_ns.value_forced = 6750 - model.vars.rx_eof_delay_ns.value_forced = 6500 - model.vars.tx_sync_delay_ns.value_forced = 5375 - model.vars.tx_eof_delay_ns.value_forced = 500 + model.vars.rx_eof_delay_ns.value_forced = 7930 + model.vars.tx_sync_delay_ns.value_forced = 3182 + model.vars.tx_eof_delay_ns.value_forced = 1058 elif ble_feature == model.vars.ble_feature.var_enum.AOX_1M: model.vars.rx_sync_delay_ns.value_forced = 50000 - model.vars.rx_eof_delay_ns.value_forced = 11000 - model.vars.tx_sync_delay_ns.value_forced = 3500 - model.vars.tx_eof_delay_ns.value_forced = 750 + model.vars.rx_eof_delay_ns.value_forced = 9980 + model.vars.tx_sync_delay_ns.value_forced = 3210 + model.vars.tx_eof_delay_ns.value_forced = 1106 elif ble_feature == model.vars.ble_feature.var_enum.AOX_2M: model.vars.rx_sync_delay_ns.value_forced = 12492 - model.vars.rx_eof_delay_ns.value_forced = 6000 - model.vars.tx_sync_delay_ns.value_forced = 3000 - model.vars.tx_eof_delay_ns.value_forced = 535 + model.vars.rx_eof_delay_ns.value_forced = 5460 + model.vars.tx_sync_delay_ns.value_forced = 1520 + model.vars.tx_eof_delay_ns.value_forced = 416 elif ble_feature == model.vars.ble_feature.var_enum.CONCURRENT: model.vars.rx_sync_delay_ns.value_forced = 50000 - model.vars.rx_eof_delay_ns.value_forced = 11750 + model.vars.rx_eof_delay_ns.value_forced = 10700 model.vars.tx_sync_delay_ns.value_forced = 2000 model.vars.tx_eof_delay_ns.value_forced = 2000 elif ble_feature == model.vars.ble_feature.var_enum.HADM_1M: @@ -89,11 +89,11 @@ def _build_delay_settings(self, model): model.vars.tx_eof_delay_ns.value_forced = 0 elif ble_feature == model.vars.ble_feature.var_enum.HADM_2M: model.vars.rx_sync_delay_ns.value_forced = 12492 - model.vars.rx_eof_delay_ns.value_forced = 6000 - model.vars.tx_sync_delay_ns.value_forced = 3000 - model.vars.tx_eof_delay_ns.value_forced = 535 + model.vars.rx_eof_delay_ns.value_forced = 5460 + model.vars.tx_sync_delay_ns.value_forced = 1520 + model.vars.tx_eof_delay_ns.value_forced = 416 elif ble_feature == model.vars.ble_feature.var_enum.HADM_2M_2BT: model.vars.rx_sync_delay_ns.value_forced = 12492 - model.vars.rx_eof_delay_ns.value_forced = 6000 - model.vars.tx_sync_delay_ns.value_forced = 3000 - model.vars.tx_eof_delay_ns.value_forced = 535 \ No newline at end of file + model.vars.rx_eof_delay_ns.value_forced = 5460 + model.vars.tx_sync_delay_ns.value_forced = 1520 + model.vars.tx_eof_delay_ns.value_forced = 416 \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 3942823f04..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/calculators/__pycache__/__init__.cpython-310.pyc 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index 7aeda4ae91..e7e53b598c 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/calculators/calc_softmodem.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/calculators/calc_softmodem.py @@ -446,8 +446,10 @@ def calc_softmodem_sunofdm_afc_regs(self, model): fdec0_out_hz = adc_freq_actual/8.0/dec0_actual if afc_correction == 2: #For now we always choose this - afc_mixer_ratio_att = 16 - afc_mixer_ratio_gain = round(1302*lodiv_actual/xtal_frequency_hz*(2**(13+afc_mixer_ratio_att-ofdm_option_index))) + for afc_mixer_ratio_att in [16,15]: + afc_mixer_ratio_gain = round(1302*lodiv_actual/xtal_frequency_hz*(2**(13+afc_mixer_ratio_att-ofdm_option_index))) + if afc_mixer_ratio_gain <= 65535: # no saturation occurs + break else: afc_mixer_ratio_att = 15 afc_mixer_ratio_gain = round(1302/fdec0_out_hz*(2**(14+afc_mixer_ratio_att-ofdm_option_index))) diff --git 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a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/phys/phys_studio_wisun_fan_1_1.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/phys/phys_studio_wisun_fan_1_1.py index 1ba56774c3..b9224a726f 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/phys/phys_studio_wisun_fan_1_1.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/parts/sol/phys/phys_studio_wisun_fan_1_1.py @@ -139,8 +139,8 @@ def PHY_WISUN_FAN_1v1_866MHz_Plan40_OFDM_OPT4_IN(self, model, phy_name=None): ### SG Region PHYs From Wi-SUN FAN 1.1 Spec### # ChanPlanID 33 - def PHY_WISUN_FAN_1v1_867MHz_Plan33_OFDM_OPT4_SG(self, model, phy_name=None): - params = WisunFan1v1ChannelParamsSol('SG', 84, 33, 200000, 866100000, + def PHY_WISUN_FAN_1v1_867MHz_Plan42_OFDM_OPT4_SG(self, model, phy_name=None): + params = WisunFan1v1ChannelParamsSol('SG', 84, 42, 200000, 866100000, 'Wi-SUN FAN, SG 865-867 MHz, OFDM OPTION 4') phy = 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b/platform/radio/efr32_multiphy_configurator/pyradioconfig/protected_fields/__pycache__/rainier_protected_fields.cpython-310.pyc deleted file mode 100644 index 774a6aebe3..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/pyradioconfig/protected_fields/__pycache__/rainier_protected_fields.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/pyradioconfig/protected_fields/rainier_protected_fields.py b/platform/radio/efr32_multiphy_configurator/pyradioconfig/protected_fields/rainier_protected_fields.py index 95bef025bb..7037564653 100644 --- a/platform/radio/efr32_multiphy_configurator/pyradioconfig/protected_fields/rainier_protected_fields.py +++ b/platform/radio/efr32_multiphy_configurator/pyradioconfig/protected_fields/rainier_protected_fields.py @@ -131,6 +131,7 @@ class ProtectedFieldsRainier(ProtectedFieldsBase): 'RAC_CLKMULTEN0_CLKMULTENREFDIV': 'cal', 'RAC_CLKMULTEN0_CLKMULTENROTDET': 'cal', 'RAC_CLKMULTCTRL_CLKMULTRESETPHFRQDET': 'cal', + 'RAC_ADCCTRL0_ADCCTRLRESERVEDLV': 'cal', } # : List of fields found in PTE, but allow radio configurator to override the value diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/rail_scripts/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 25e8436d62..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/rail_scripts/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/__pycache__/_version.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/rail_scripts/__pycache__/_version.cpython-310.pyc deleted file mode 100644 index f0129645b6..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/rail_scripts/__pycache__/_version.cpython-310.pyc and /dev/null differ diff --git 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a/platform/radio/efr32_multiphy_configurator/rail_scripts/config.py b/platform/radio/efr32_multiphy_configurator/rail_scripts/config.py index 5b934c147c..016688d8f9 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/config.py +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/config.py @@ -273,6 +273,8 @@ def mergeDictionaries(dict1, dict2): 'caracal': mergeDictionaries(PROTECTED_FIELDS_BASE, PROTECTED_FIELDS_CARACAL), 'lion': mergeDictionaries(PROTECTED_FIELDS_BASE, PROTECTED_FIELDS_LION), 'rainier': ProtectedFieldsRainier().get_rail_protected_field_dict(), + 'lpwh72000': ProtectedFieldsRainier().get_rail_protected_field_dict(), + 'lpwh74000': ProtectedFieldsRainier().get_rail_protected_field_dict(), } # Radio config action "enum" diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/__init__.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/__init__.cpython-310.pyc deleted file mode 100644 index 56f4fa9be4..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/__init__.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/railConfig_sourceCodeGenerator.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/railConfig_sourceCodeGenerator.cpython-310.pyc deleted file mode 100644 index 8739a1a1eb..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/railConfig_sourceCodeGenerator.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/railTest_rmrCommandGenerator.cpython-310.pyc b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/railTest_rmrCommandGenerator.cpython-310.pyc deleted file mode 100644 index 047874beac..0000000000 Binary files a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/__pycache__/railTest_rmrCommandGenerator.cpython-310.pyc and /dev/null differ diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_compiler.py b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_compiler.py index cd9a17b913..08ae676a0a 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_compiler.py +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_compiler.py @@ -47,7 +47,6 @@ def __init__(self, chip, regBaseYml, dataYml, isInternal=False): self.isInternal = isInternal self.fileName = dataYml['Name'] + '_internal' if self.isInternal else dataYml['Name'] self.fileInclude = dataYml.get('FileIncludes') - self.alias = dataYml.get('Alias', {}) self.sequences = {} self.regBases = {} @@ -107,6 +106,7 @@ def __init__(self, chip, regBaseYml, dataYml, name, seqData, isInternal=False): self.baseAddrConfig = self.getConfig(regBaseYml, chip, self.baseAddrConfigName) if self.baseAddrConfig is None: + # Try with the part name self.baseAddrConfig = self.getConfig(regBaseYml, self.part, self.baseAddrConfigName) if self.baseAddrConfig is None: raise Exception("{} part is not defined in seqacc_regbases.yml." @@ -114,11 +114,17 @@ def __init__(self, chip, regBaseYml, dataYml, name, seqData, isInternal=False): self.basePos = self.getConfig(regBaseYml, chip, self.baseAddrConfigName, 'BasePos') if self.basePos is None: + # Try with the part name self.basePos = self.getConfig(regBaseYml, self.part, self.baseAddrConfigName, 'BasePos') if self.basePos is None: raise Exception("BasePos field not found in {}".format(self.baseAddrConfigName)) self.basePos &= 0x1F + self.alias = self.getConfig(regBaseYml, chip, self.baseAddrConfigName, 'Alias') + if self.alias is None: + # Try with the part name + self.alias = self.getConfig(regBaseYml, self.part, self.baseAddrConfigName, 'Alias', default={}) + self.sequenceCfg = self._encodeCfg() self.contWrPos = seqData.get('SequenceCfg', {}).get('CNTWRPOS', 16) self.value = [] diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_regbases.yml b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_regbases.yml index a0bc582720..f70c87da4d 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_regbases.yml +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/seqacc_regbases.yml @@ -17,9 +17,10 @@ RAINIER: 0xA0210000: 1 0xA0220000: 2 0xA0000000: 3 - 0xB0000000: 4 - 0x40860000: 5 + 0x40860000: 4 0xFFFFFFFF: 0xFFFFFFFF + Alias: + SEQRAM: 0xA0000000 LPWH72000: BaseAddrCfgDefault: @@ -33,8 +34,9 @@ LPWH72000: 0xB0280000: 5 0xB0000000: 6 0xB0010000: 7 - 0xA0000000: 8 0xFFFFFFFF: 0xFFFFFFFF + Alias: + SEQRAM: 0xB0010000 LPWH74000: BaseAddrCfgDefault: @@ -43,8 +45,11 @@ LPWH74000: 0xB0200000: 0 0xB0210000: 1 0xB0220000: 2 - 0xB0270000: 3 - 0xB0280000: 4 - 0xB0000000: 5 - 0xB0300000: 6 - 0xFFFFFFFF: 0xFFFFFFFF \ No newline at end of file + 0xB0260000: 3 + 0xB0270000: 4 + 0xB0280000: 5 + 0xB0000000: 6 + 0xB0010000: 7 + 0xFFFFFFFF: 0xFFFFFFFF + Alias: + SEQRAM: 0xB0010000 \ No newline at end of file diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/rail_config_multi_phy_2x.c.j2 b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/rail_config_multi_phy_2x.c.j2 index 34aa986475..e538e688ba 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/rail_config_multi_phy_2x.c.j2 +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/rail_config_multi_phy_2x.c.j2 @@ -260,6 +260,7 @@ static const uint32_t {{phyInfoEntryName}}[] = { {%- else %} (uint32_t) NULL, {%- endif %} + (uint32_t) {{phyInfoEntry.phyInfoData.trecsPreBitsToSync}}UL, }; {% endfor %} {%- for dynamicSlicerTableEntryName, dynamicSlicerTableEntry in multiPhyConfig.commonStructures.dynamicSlicerTableEntries.items() %} diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.c.j2 b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.c.j2 index 26e59c7d9c..92da784444 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.c.j2 +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.c.j2 @@ -6,7 +6,6 @@ // SEQACC base address configuration // Only MSB are kept, assuming the LSB are all zeros. -// Note: Need to keep 0xB000 for PHYINFO location by rail_scripts {% for baseAddrName, baseAddrCfg in RegBases.items() -%} uint16_t {{baseAddrName}}Array[{{"{}".format(baseAddrCfg['Define'])}}] = { {%- for addr in baseAddrCfg['BaseAddr'].keys() %} diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.h.j2 b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.h.j2 index 2d1a94d75a..f59760635c 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.h.j2 +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/generators/templates/seqacc_regbases.h.j2 @@ -10,6 +10,7 @@ {% for baseAddrName, baseAddrCfg in RegBases.items() -%} #define {{"{}".format(baseAddrCfg['Define'])}} ({{ baseAddrCfg['BaseAddr'] | length }}U) #define REG_BASES_MASK ({{ "0x{0:08X}UL".format(baseAddrCfg['RegBasesMask']) }}) +// We can bitset and bitclr in peripheral region only #define REG_BASE_BITOP_MASK ({{ "0x{0:02X}U".format(baseAddrCfg['BitOpMask']) }}) extern uint16_t {{baseAddrName}}Array[{{"{}".format(baseAddrCfg['Define'])}}]; diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter.py b/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter.py index a68bb77f15..256460d4d5 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter.py +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter.py @@ -93,16 +93,31 @@ def _encodeWriteAddress(self, reg_address, write_length=1, radio_action=0): return encodedAddress - def _getRegAddress(self, block, register): + def _getRegAddress(self, block, register, suffix=''): # Use the RM_Device object to get the absolute register address - baseAddrString = "self.rm.{0}.{1}.baseAddress".format(block, register) - regOffsetString = "self.rm.{0}.{1}.addressOffset".format(block, register) + baseAddrString = "self.rm.{}{}.{}.baseAddress".format(block, suffix, register) + regOffsetString = "self.rm.{}{}.{}.addressOffset".format(block, suffix, register) regAddr = eval(baseAddrString) + eval(regOffsetString) return regAddr + def _getRegAddressWithPolarity(self, block, register): + if self.series == 3: + try: + regAddr = self._getRegAddress(block, register, suffix='_NS') + regBase = self._regBases[int(regAddr) & 0xFFFF0000] + except (KeyError, AttributeError): + try: + regAddr = self._getRegAddress(block, register, suffix='_S') + except (KeyError, AttributeError): + regAddr = self._getRegAddress(block, register, suffix='') + else: + regAddr = self._getRegAddress(block, register) + return regAddr + def _regOutput(self, block, register, value, name=None): # Use the RM_Device object to get register address value pairs - regAddr = self._getRegAddress(block, register) + regAddr = self._getRegAddressWithPolarity(block, register) + if (name is None): return (regAddr, value) else: @@ -116,12 +131,11 @@ def _getRegBasesFromFamily(self, family): # Bit positions for base address and opcode basePos = 25 opCodePos = 28 - isSeries1or2 = True - if family in ["dumbo", "jumbo", "nerio", "nixi"]: + if self.series == 1: regBases = self._REG_BASES - elif family in ["panther", "lynx", "ocelot", "bobcat", "leopard", "margay", "caracal", "lion", "sol"]: + elif self.series == 2: regBases = self._REG_BASES_EFR32XG2x if family in ["sol"]: @@ -133,7 +147,6 @@ def _getRegBasesFromFamily(self, family): else: # Series 3 - isSeries1or2 = False basePos = 24 ymlSource = os.path.join(os.path.dirname(os.path.realpath(__file__)), 'generators/seqacc_regbases.yml') @@ -151,7 +164,7 @@ def _getRegBasesFromFamily(self, family): maxNumRegBases = 2 ** (opCodePos - basePos) - if isSeries1or2: + if self.series < 3: if len(regBases) > maxNumRegBases: raise Exception(("Number of register bases ({}) exceeds maximum allowed " "value ({}) for {}").format(len(regBases), maxNumRegBases, family)) @@ -163,6 +176,16 @@ def _getRegBasesFromFamily(self, family): self._regBases = regBases + @staticmethod + def _getSeriesFromFamily(family): + if family in ["dumbo", "jumbo", "nerio", "nixi"]: + series = 1 + elif family in ["panther", "lynx", "ocelot", "bobcat", "leopard", "margay", "caracal", "lion", "sol"]: + series = 2 + else: + series = 3 + return series + def getParserArgs(): """ Build argparse parser and return arguments from sys.argv. diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter_multi_phy.py b/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter_multi_phy.py index d243288f0c..6b859f5b34 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter_multi_phy.py +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_adapter_multi_phy.py @@ -11,7 +11,7 @@ import itertools # Update kRAILVersion to be used in phyInfoData. -kRAILVersion = 18 +kRAILVersion = 19 class ConcPhyEnum(IntEnum): CONC_PHY_NONE = 0 @@ -81,6 +81,7 @@ def __init__(self, **kwargs): self.railModel = RAILModel(self.yamlobject) self._railModelPopulated = False + self.series = self._getSeriesFromFamily(kwargs['mphyConfig'].get_part_family().lower()) # Store the register bases in self._regBases self._getRegBasesFromFamily(kwargs['mphyConfig'].get_part_family().lower()) @@ -88,14 +89,18 @@ def _encodeAction(self, modemConfig, address, length, values=[], names=[], debug # Get address for protected field regs on the current chip PROTECTED_FIELD_REG_VALUES = {} for register in config.PROTECTED_FIELDS[self.partFamily.lower()].keys(): - registerObject = getattr(self.rm, register.split('.')[0], None) + baseName = register.split('.')[0] + fieldName = register.split('.')[1] + try: + protectedAddress = self._getRegAddressWithPolarity(baseName, fieldName) + except AttributeError: + continue + registerObject = getattr(self.rm, baseName, None) if registerObject == None: continue - registerObject = getattr(registerObject, register.split('.')[1], None) + registerObject = getattr(registerObject, fieldName, None) if registerObject == None: continue - base = registerObject.baseAddress - offset = registerObject.addressOffset protectionMask = 0 for field in config.PROTECTED_FIELDS[self.partFamily.lower()][register]: fieldObject = getattr(registerObject, field, None) @@ -104,7 +109,7 @@ def _encodeAction(self, modemConfig, address, length, values=[], names=[], debug bitWidth = fieldObject.bitWidth bitOffset = fieldObject.bitOffset protectionMask |= ((2 ** bitWidth - 1) << bitOffset) - PROTECTED_FIELD_REG_VALUES[base + offset] = { 'protectionMask' : protectionMask, 'name': register } + PROTECTED_FIELD_REG_VALUES[protectedAddress] = { 'protectionMask' : protectionMask, 'name': register } while length > 0: currentLength = length @@ -254,7 +259,7 @@ def _optimizeWrite(base_streak, regs_channels, expensive, cheap): base_info["base"] = new_base # Move PHYINFO (and associated registers in a continuous write) to the start - address = self._getRegAddress("SEQ","PHYINFO") + address = self._getRegAddressWithPolarity("SEQ","PHYINFO") allWrites = [new_base] allWrites.extend(regs_channels) for add in allWrites: @@ -291,7 +296,7 @@ def _optimizeWrite(base_streak, regs_channels, expensive, cheap): if ((self.partFamily in ["ocelot", "margay"]) and (j != 0) and ((base_info["add"][j - 1][1][1].entryType.value == ConcPhyEnum.CONC_PHY_VT) or (base_info["add"][j - 1][1][1].entryType.value == ConcPhyEnum.CONC_PHY_9_6_NON_HOP))): # apply calculator workaround for ZWave concurrent PHY # need to make sure BCR demod is enable and viterbi demod is disabled for virtual concurrent PHY (i.e. Zwave 9.6K concurrent PHY) - if (register[0] == self._getRegAddress("MODEM", "BCRDEMODCTRL")): + if (register[0] == self._getRegAddressWithPolarity("MODEM", "BCRDEMODCTRL")): # Enable BCR demod # reg[1] = ((reg[1] | MODEM_BCRDEMODCTRL_BCRDEMODEN) & ~MODEM_BCRDEMODCTRL_BBPMDETEN) bcrdemoctrlReg.io = register[1] @@ -302,7 +307,7 @@ def _optimizeWrite(base_streak, regs_channels, expensive, cheap): chunkWrite[i] = (register[0], bcrdemoctrlReg.io, "MODEM.BCRDEMODCTRL") if (do_print): print("New BCRDEMODCTRL {}".format(chunkWrite[i])) - elif (register[0] == self._getRegAddress("MODEM", "VITERBIDEMOD")): + elif (register[0] == self._getRegAddressWithPolarity("MODEM", "VITERBIDEMOD")): # Disable Viterbi demod # reg[1] = (reg[1] & ~_MODEM_VITERBIDEMOD_VTDEMODEN_MASK) viterbidemodReg.io = register[1] @@ -329,7 +334,7 @@ def _optimizeWrite(base_streak, regs_channels, expensive, cheap): regNameLists = ["SRCCHF", "BCRDEMODCTRL", "VITERBIDEMOD", "CTRL0", "SYNC0", "FRMSCHTIME", "TRECPMPATT"] regLists = [] for regNameList in regNameLists: - regLists.append(self._getRegAddress("MODEM", regNameList)) + regLists.append(self._getRegAddressWithPolarity("MODEM", regNameList)) if (do_print): for regIdx, reg in enumerate(regLists): for add in allWrites: @@ -353,7 +358,7 @@ def _optimizeWrite(base_streak, regs_channels, expensive, cheap): lastWrites = [] # Find the registers that has to be executed first for list in firstWriteLists: - list_addr = self._getRegAddress("MODEM", list) + list_addr = self._getRegAddressWithPolarity("MODEM", list) regFound = False for i, reg in enumerate(reg_lists): if reg[0] == list_addr: @@ -369,7 +374,7 @@ def _optimizeWrite(base_streak, regs_channels, expensive, cheap): # Find the registers that has to be executed last for list in lastWriteLists: regFound = False - list_addr = self._getRegAddress("MODEM", list) + list_addr = self._getRegAddressWithPolarity("MODEM", list) for i, reg in enumerate(reg_lists): if reg[0] == list_addr: if (do_print): @@ -475,7 +480,7 @@ def formatModemConfigEntries(self, configName, phyConfigEntry, registerEntries, currentPhyConfigEntryModemConfigEntry.value = newModemConfig def _writeBRA(self, phyConfigEntry, model, regs): - address = self._getRegAddress("FRC", "BLOCKRAMADDR") + address = self._getRegAddressWithPolarity("FRC", "BLOCKRAMADDR") if phyConfigEntry.bchArray: # Write BLOCKRAMADDR self._loadBchLookupTable(model, regs, address, phyConfigEntry.bchArray) @@ -492,7 +497,7 @@ def _writeCRA(self, regs, fecEnabled): # On Panther, we decided to ALWAYS write the FRC_CONVRAMADDR to HIGH RAM offset 0 # On rest of series-2 after Panther, we decided to ALWAYS write the FRC_CONVRAMADDR to FRCRAM offset 0 # Since this varies per part it is now owned in the Radio Configurator in series 2+ - if self.partFamily.lower() in ["dumbo","jumbo","nerio","nixi"]: + if self.series == 1: # Series - 1 point to allocated buffer, or just leave at 0 if not needed. if fecEnabled: convDecodeBuffer = "convDecodeBuffer" @@ -501,7 +506,7 @@ def _writeCRA(self, regs, fecEnabled): # Write the address of the convDecodeBuffer to CONVRAMADDR when # fecEnabled, include even when absent for speed - address = self._getRegAddress("FRC", "CONVRAMADDR") + address = self._getRegAddressWithPolarity("FRC", "CONVRAMADDR") regs.append((address, convDecodeBuffer, "FRC.CONVRAMADDR")) regs.sort() return regs @@ -551,7 +556,7 @@ def _generateModemConfigEntries(self, phyConfigEntry, model, regs): if self.pte_script is False: # Write the address of the phyInfo structure to SEQ.PHYINFO.ADDRESS - address = self._getRegAddress("SEQ","PHYINFO") + address = self._getRegAddressWithPolarity("SEQ","PHYINFO") regs.append((address, phyConfigEntry.phyInfoEntry.value, "SEQ.PHYINFO")) # Write the address of the last Dynamic Slicer Configuration link @@ -559,7 +564,7 @@ def _generateModemConfigEntries(self, phyConfigEntry, model, regs): dynamicSlicerTableEntry = phyConfigEntry.dynamicSlicerTableEntry.value if dynamicSlicerTableEntry and len(dynamicSlicerTableEntry._elements) > 0 and \ self.partFamily in ["dumbo", "jumbo", "nerio", "nixi", "bobcat","caracal"]: - address = self._getRegAddress("SEQ","DYNAMIC_CHPWR_TABLE") + address = self._getRegAddressWithPolarity("SEQ","DYNAMIC_CHPWR_TABLE") regs.append((address, phyConfigEntry.dynamicSlicerTableEntry.value.lastElement, "SEQ.DYNAMIC_CHPWR_TABLE")) regs.sort() # Put the registers in the right order again @@ -664,6 +669,11 @@ def _generatePhyInfoStructure(self, phyConfigEntry, baseConfigOptions, channelCo data.src1Denominator.value = (outputs.get_output('src1_calcDenominator').var_value or 0) data.src2Denominator.value = (outputs.get_output('src2_calcDenominator').var_value or 0) + if hasattr(outputs, 'trecs_pre_bits_to_syncword'): + data.trecsPreBitsToSync.value = int(outputs.get_output('trecs_pre_bits_to_syncword').var_value or 0) + else: + data.trecsPreBitsToSync.value = 0 + modType = model.vars.modulation_type.value if hasattr(model.vars.modulation_type.var_enum, 'OFDM') and modType == model.vars.modulation_type.var_enum.OFDM: # In OFDM txBaudRate contains the symbol rate @@ -679,7 +689,7 @@ def _generatePhyInfoStructure(self, phyConfigEntry, baseConfigOptions, channelCo data.zWaveChannelHopTiming.value = (outputs.get_output('rx_ch_hopping_delay_usec').var_value or 0) data.rateInfo.value = (rssiAdjustDb & 0xFF) << 16 | data.baudPerSymbol.value << 8 | data.bitsPerSymbol.value - if self.partFamily.lower() not in ["dumbo","jumbo","nerio","nixi"]: + if self.series != 1: # Cap DEC0 at 3, since the decimation value for all values above 3 is 8. # Also don't use value 2, in case that's useful in the future DEC0_MAP = [0, 1, 1, 3, 3, 3, 3, 3] @@ -1566,7 +1576,7 @@ def _resolveConvDecoderBuffer(self, railModel): maxConvDecodeBufferSize = 0 # On Panther, we decided to ALWAYS write the FRC_CONVRAMADDR to HIGH RAM offset 0 # On Lynx+, we decided to ALWAYS write the FRC_CONVRAMADDR to FRCRAM offset 0 - if self.partFamily.lower() in ["dumbo","jumbo","nerio","nixi"]: + if self.series == 1: for multiPhyConfigEntry in railModel.multiPhyConfig.multiPhyConfigEntries._elements: for phyConfigEntry in multiPhyConfigEntry.phyConfigEntries._elements: if phyConfigEntry.convDecodeBufferSize.value > maxConvDecodeBufferSize: @@ -1663,7 +1673,10 @@ def populateModel(self): self.partFamily = self.mphyConfig.part_family # Create a proper rm object depending on partFamily - if self.mphyConfig.part_revision == 'ANY' or self.partFamily.upper() in RM_S1_PART_FAMILY_NAMES or self.partFamily.upper() in RM_S2_PART_FAMILY_NAMES: + if (self.mphyConfig.part_revision == 'ANY' + or self.partFamily.upper() in RM_S1_PART_FAMILY_NAMES + or self.partFamily.upper() in RM_S2_PART_FAMILY_NAMES + or self.partFamily.upper() in ["RAINIER"]): rm_factory = RM_Factory(self.partFamily.upper()) else: rm_factory = RM_Factory(self.partFamily.upper(), self.mphyConfig.part_revision) diff --git a/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_model_multi_phy_2x.yml b/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_model_multi_phy_2x.yml index 3a9baf556c..ce36b2049a 100644 --- a/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_model_multi_phy_2x.yml +++ b/platform/radio/efr32_multiphy_configurator/rail_scripts/rail_model_multi_phy_2x.yml @@ -370,6 +370,8 @@ RAILModel: - name: modemTxCompensation dataType: FieldDataType.INT16_T isPtr: True + - name: trecsPreBitsToSync + dataType: FieldDataType.UINT32_T - RAILModelObjectArray: name: modemConfigEntries diff --git a/platform/radio/mac/rail_mux/sl_rail_mux.c b/platform/radio/mac/rail_mux/sl_rail_mux.c index dac0208f6d..13a54dd9da 100644 --- a/platform/radio/mac/rail_mux/sl_rail_mux.c +++ b/platform/radio/mac/rail_mux/sl_rail_mux.c @@ -191,6 +191,12 @@ HIDDEN const RAIL_IEEE802154_Config_t ieee_802154_config = { false, // defaultFramePendingInOutgoingAcks }; +SL_WEAK void sl_rail_mux_invalid_rx_channel_detected_cb(int new_rx_channel, int old_rx_channel) +{ + //if(network up) + EFM_ASSERT(false); +} + //------------------------------------------------------------------------------ // Internal APIs @@ -599,6 +605,15 @@ RAIL_Status_t sl_rail_mux_StartRx(RAIL_Handle_t railHandle, // Check to ensure lock is not active before acting on startRx if ( check_lock_permissions(context_index) ) { + #ifndef SL_CATALOG_RAIL_UTIL_IEEE802154_FAST_CHANNEL_SWITCHING_PRESENT + if (!fn_get_context_flag_by_index(context_index, RAIL_MUX_PROTOCOL_FLAGS_LOCK_ACTIVE)) { + if (rx_channel != INVALID_CHANNEL && rx_channel != channel) { + // this protocol context rx channel is different from the other protocol context rx channel + sl_rail_mux_invalid_rx_channel_detected_cb(channel, rx_channel); + } + } + #endif + rx_channel = channel; fn_update_802154_address_filtering_table(); CONFIGURE_RX_CHANNEL_SWITCHING(mux_rail_handle, channel_switching_cfg); @@ -1533,12 +1548,13 @@ void sl_rail_mux_set_coex_counter_handler(RAIL_Handle_t railHandle, void sl_rail_util_coex_counter_on_event(sl_rail_util_coex_event_t event) { - uint8_t context_index = fn_get_active_tx_context_index(); - - EFM_ASSERT(context_index < SUPPORTED_PROTOCOL_COUNT); + uint8_t i; - if (protocol_context[context_index].coex_counter_handler != NULL) { - (*protocol_context[context_index].coex_counter_handler)(event); + for (i = 0; i < SUPPORTED_PROTOCOL_COUNT; i++) { + // we don't have a way to know which protocol is currently supposed to receive the coex event + if (protocol_context[i].coex_counter_handler != NULL) { + (*protocol_context[i].coex_counter_handler)(event); + } } } diff --git a/platform/radio/radio_configuration/radio_config_long_preamble_device_family_fgm23.slcc b/platform/radio/radio_configuration/radio_config_long_preamble_device_family_fgm23.slcc index 0ec411f588..ca27436822 100644 --- a/platform/radio/radio_configuration/radio_config_long_preamble_device_family_fgm23.slcc +++ b/platform/radio/radio_configuration/radio_config_long_preamble_device_family_fgm23.slcc @@ -19,6 +19,7 @@ template_contribution: value: radio_config_simple_rail_singlephy config_file: - path: platform/radio/radio_configuration/Base/simple_long_preamble/device_generic_family_efr32xg23/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_family_fgm23 diff --git a/platform/radio/radio_configuration/radio_config_range_test_sdid_210_868_915_phys.slcc b/platform/radio/radio_configuration/radio_config_range_test_sdid_210_868_915_phys.slcc index 75aaf7879d..a9bec907c2 100644 --- a/platform/radio/radio_configuration/radio_config_range_test_sdid_210_868_915_phys.slcc +++ b/platform/radio/radio_configuration/radio_config_range_test_sdid_210_868_915_phys.slcc @@ -36,6 +36,7 @@ config_file: - device_is_module - device_generic_family_efr32xg21 - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_has_radio_subghz @@ -58,12 +59,14 @@ config_file: - device_generic_family_efr32xg21 - device_supports_zwave - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_434/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_default_rf_band_434 - device_generic_family_efr32xg23 - device_supports_zwave - path: platform/radio/radio_configuration/Range_Test_sdid_210_868_915/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_supports_rf_band_868 @@ -73,6 +76,7 @@ config_file: - device_is_module - device_generic_family_efr32xg21 - path: platform/radio/radio_configuration/Range_Test_sdid_210_868_915/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_supports_rf_band_868 diff --git a/platform/radio/radio_configuration/radio_config_simple_rail_singlephy.slcc b/platform/radio/radio_configuration/radio_config_simple_rail_singlephy.slcc index 4a47812042..41c6193cfb 100644 --- a/platform/radio/radio_configuration/radio_config_simple_rail_singlephy.slcc +++ b/platform/radio/radio_configuration/radio_config_simple_rail_singlephy.slcc @@ -48,6 +48,7 @@ config_file: - device_is_module - device_generic_family_efr32xg21 - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_has_radio_subghz @@ -131,6 +132,7 @@ config_file: - device_is_module - device_generic_family_efr32xg21 - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg28/rf_band_2400/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_has_radio_2g4hz @@ -158,6 +160,7 @@ config_file: - device_is_module - device_generic_family_efr32xg21 - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg28/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_has_radio_subghz @@ -183,6 +186,7 @@ config_file: - device_is_module - device_generic_family_efr32xg21 - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg28/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_has_radio_dualband @@ -251,6 +255,7 @@ config_file: - device_generic_family_efr32xg21 - device_supports_zwave - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_315/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_default_rf_band_315 @@ -267,6 +272,7 @@ config_file: - device_generic_family_efr32xg21 - device_supports_zwave - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_434/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_default_rf_band_434 @@ -283,6 +289,7 @@ config_file: - device_generic_family_efr32xg21 - device_supports_zwave - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_470/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_default_rf_band_470 @@ -299,6 +306,7 @@ config_file: - device_generic_family_efr32xg21 - device_supports_zwave - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_default_rf_band_868 @@ -413,6 +421,7 @@ config_file: - device_generic_family_efr32xg21 - device_supports_zwave - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg28/rf_band_2400/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_default_rf_band_2400 @@ -429,6 +438,7 @@ config_file: - device_generic_family_efr32xg21 - device_supports_zwave - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg28/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - hardware_board_default_rf_band_868 diff --git a/platform/radio/radio_configuration/radio_config_singlephy_device_family_fgm23.slcc b/platform/radio/radio_configuration/radio_config_singlephy_device_family_fgm23.slcc index ade40bec3e..42905e9f8a 100644 --- a/platform/radio/radio_configuration/radio_config_singlephy_device_family_fgm23.slcc +++ b/platform/radio/radio_configuration/radio_config_singlephy_device_family_fgm23.slcc @@ -19,6 +19,7 @@ template_contribution: value: radio_config_simple_rail_singlephy config_file: - path: platform/radio/radio_configuration/Base/simple_rail_singlephy/device_generic_family_efr32xg23/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_family_fgm23 diff --git a/platform/radio/radio_configuration/radio_config_wmbus_collector_device_family_fgm23.slcc b/platform/radio/radio_configuration/radio_config_wmbus_collector_device_family_fgm23.slcc index 20b752b2e7..5d4619d086 100644 --- a/platform/radio/radio_configuration/radio_config_wmbus_collector_device_family_fgm23.slcc +++ b/platform/radio/radio_configuration/radio_config_wmbus_collector_device_family_fgm23.slcc @@ -19,6 +19,7 @@ template_contribution: value: radio_config_wmbus_collector config_file: - path: platform/radio/radio_configuration/Mbus/wmbus_collector_868/device_generic_family_efr32xg23/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_family_fgm23 diff --git a/platform/radio/radio_configuration/radio_config_wmbus_meter_device_family_fgm23.slcc b/platform/radio/radio_configuration/radio_config_wmbus_meter_device_family_fgm23.slcc index f2defa3682..12a177f848 100644 --- a/platform/radio/radio_configuration/radio_config_wmbus_meter_device_family_fgm23.slcc +++ b/platform/radio/radio_configuration/radio_config_wmbus_meter_device_family_fgm23.slcc @@ -19,6 +19,7 @@ template_contribution: value: radio_config_wmbus_meter config_file: - path: platform/radio/radio_configuration/Mbus/wmbus_meter_868/device_generic_family_efr32xg23/rf_band_868/radio_settings.radioconf + file_id: radio_configuration_settings directory: rail condition: - device_family_fgm23 diff --git a/platform/radio/rail_lib/apps/component/rail_test_core.slcc b/platform/radio/rail_lib/apps/component/rail_test_core.slcc index 5f2eb13338..fd855fc986 100644 --- a/platform/radio/rail_lib/apps/component/rail_test_core.slcc +++ b/platform/radio/rail_lib/apps/component/rail_test_core.slcc @@ -794,6 +794,12 @@ template_contribution: - type: uint32 help: "timingReSenseUs" + - name: cli_command + value: + name: triggerRxHop + handler: triggerRxHop + help: "Trigger a manual RX channel hopping hop." + - name: cli_command value: name: getRxHoppingRssi diff --git a/platform/radio/rail_lib/apps/railtest/app_ci/channel_hopping_ci.c b/platform/radio/rail_lib/apps/railtest/app_ci/channel_hopping_ci.c index ce2f2596ec..5732cac24c 100644 --- a/platform/radio/rail_lib/apps/railtest/app_ci/channel_hopping_ci.c +++ b/platform/radio/rail_lib/apps/railtest/app_ci/channel_hopping_ci.c @@ -663,3 +663,9 @@ void setNextBleTxRepeat(sl_cli_command_arg_t *args) txRepeatCount = repeats.iterations; responsePrint(command, "RepeatedTxCount:%u", repeats.iterations); } + +void triggerRxHop(sl_cli_command_arg_t *args) +{ + RAIL_Status_t ret = RAIL_TriggerRxChannelHop(railHandle); + responsePrint(sl_cli_get_command_string(args, 0), "HopTriggerStatus:%u", ret); +} diff --git a/platform/radio/rail_lib/apps/railtest/app_main.c b/platform/radio/rail_lib/apps/railtest/app_main.c index 733231a264..12dba13a60 100644 --- a/platform/radio/rail_lib/apps/railtest/app_main.c +++ b/platform/radio/rail_lib/apps/railtest/app_main.c @@ -1047,8 +1047,8 @@ void processPendingCalibrations(void) // Only calibrate the radio when not currently receiving a packet bool calsInMode = inAppMode(NONE, NULL); bool calsInTxMode = inAppMode(TX_N_PACKETS, NULL) - | inAppMode(TX_CONTINUOUS, NULL) - | inAppMode(TX_STREAM, NULL); + || inAppMode(TX_CONTINUOUS, NULL) + || inAppMode(TX_STREAM, NULL); bool receivingPacket = RAIL_GetRadioState(railHandle) == RAIL_RF_STATE_RX_ACTIVE; if (calibrateRadio && (calsInMode | calsInTxMode) && !skipCalibrations && !receivingPacket) { diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_gcc.a index 5058cdabf2..e6119a0dcc 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:87be51afb02191048a4fd1a555e4b8ce2cb27da9f35fb8f4bf57853082523b58 +oid sha256:a732e609928b42318593747632ad9bf09fb5cf9f7c00f3065dea9ee0b49e62ca size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_iar.a index 8bfe750e0d..5008e9b292 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aed804afd6983abfd6120e6c07fe7e58aba7403d935a29ee38b1ebc5394bbd8c +oid sha256:bc4fcf4cd3296dd3b72b794780650897e0035c2041347d4c015ce42a7fbb87cf size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_gcc.a index 3939b52f34..6b725de713 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2cb9dfdcd4aade3eaa7c1b4404f842a23987954edd323bbf54901c0d69b8b744 +oid sha256:d13f4eafbf22b8030c14ed2e37976d27a395613460a24ab42f29a45c719d0e83 size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_iar.a index 389f871c21..b1ae6e76da 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jnf_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9b32e476b060f4153aa59f0f44dcfe8311fd07a805b2ac35ee03193914b10bc4 +oid sha256:4faf62e23a3a4535bd532287ac9ff17643a9e4f547c5979b0b1025dc7cca5f0a size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_gcc.a index 8cb0dd312d..9e3f9f7564 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:663dca31b8efacbea5b67ea42a2f6dc7219d0f173af021483c490b6238425f57 +oid sha256:a05979c2309281ca8d298d168903919698f4882e3ad1e010a6040236dd33e061 size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_iar.a index 71e6e5e008..25ad224f50 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:23714a6f6b5aa25233d955e8e628de21fb293d7a03c36e77a883ec2a64e19568 +oid sha256:e5b6b4767a5d9f131dede7d7bd50015681c70dbc12d4dd3f19cecc62f6f18986 size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_gcc.a index 29dd18b65f..b764c89ea8 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0723e26a115ffebd291b529730db290a45bc08d57c6d65dbbd13193db49a050e +oid sha256:31747a79924019ea16163f359e0c3108e1129841f30c541b575f917b959f361b size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_iar.a index 1d01866ec7..86c7a4b928 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210la22jnf_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4bd74556daa646462c5ed2247b749fac8a72363b7a7d317ed6b8241480eb2558 +oid sha256:07fd416b0468dd98c11be167d88f55dc157c05a4c86680b199ca80a2c01ab66c size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_gcc.a index 3e009af289..b2f0e83dab 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8f14692b596403d19dbef6e2b19b2284b83b35ddf5087696998a756220091494 +oid sha256:b9168548a6a8513e2d37cc885b7a513d01571b58332299571ac9ec0914ec4373 size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_iar.a index 833d5dac11..380d80cfe0 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd4cc40289fa3d1c530de2e56b0b0e85ce43f471715f327022f250281345f8b6 +oid sha256:f95865bc5186386723419c8cbcfb8bdad27edb61cec0080de35196490af5cb7f size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_gcc.a index 9f3e98e813..a54b31808f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:54cce651f44b7ebf2e7982c8349a995805e313b2cf92e91dd7dfaed3f1d19572 +oid sha256:9777796b6c7b654205e7e17a961b7b78624efd05f01b8b0612a34b4849b3daa0 size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_iar.a index 0cccbff948..f91d68263d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p022jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3c0992145e650f7a106f3ce20cc99418cd13c4920235ba5ac43151f6a7a03b36 +oid sha256:6bdd2fd2d059aead48bba27c1bc3e7a2eba4bce33b1df836a7f48f882ee2d734 size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_gcc.a index bb4cf04ce8..d153acbda4 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6d0b6dea51385ad67c153507f570e784e07390acffdf415cf7c8a971b5bdbd35 +oid sha256:922113098aaecd967bd5fa9f78d8969b95eacb84c88feb9773c648c1fe348322 size 59290 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_iar.a index 7cf8a7f8c5..77bb5b1854 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:531a69571bb2f83e1f1e88323a20ea3c29e70944da4949132eb91ba9e12705c8 +oid sha256:58c0ae6743cb439b9719d2f6b0913fa7fd0335f5500fec5ef6121dabaabca024 size 41792 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_gcc.a index 5d685cd5fd..61cc126109 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:74d60c85920a041d41ab772d9622506d23f8b7b94a606ce5faae9062c54520ed +oid sha256:3c10d0eb8e48bbc0e9e968ef0c806e53affaeeea225ac43225947e5da772adc8 size 59290 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_iar.a index 59dd9aa5c4..359a2a0425 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210p032jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:74e48c5f0a482118be5a2c2efc2e2f6e2596642bbfd6b0c1717a9f6321dcfe45 +oid sha256:27f627fd64efbd23a283c18d8f57ce8e4a3812b635226573241ceb2383b67c45 size 41792 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_gcc.a index 7ebe4db003..b127a60276 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:07b36014392d405eb52c3fa5e8371af5b33e1afe148ac6da85f43e72c5e7213d +oid sha256:2e545a181582518e003354b3cb0c43aeb8ea1988cf30117de9bc1118cdf47bd7 size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_iar.a index e926d1adb2..90d972b040 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9327f128c0474a114605d48a2c76f6c11392e4e93e6b470ce723917ac1e2853c +oid sha256:bab67761555175e36ad0ef8803a93467329ab58e1e3db6f7a890c9651956fd90 size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_gcc.a index 54641f4330..c4e01b0a74 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4b95647d780be4fb7e224bfc56a2f56f857e45aac50d8bf1e329b4beba8ac811 +oid sha256:214021db35f2465c4c495c030ab561cf65845f4b734ad2e9acb9965d9de7e254 size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_iar.a index 1751c79fc2..cb31ff0c67 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa22jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:08c460ef876ffa3ba478f2bb028e07f221b845ead64252634e722ab19d2b0029 +oid sha256:9f337cd210c0745cbb4e1faea3aa7f16b5b19eb8a301b087a0d631b8fae08acf size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_gcc.a index ce3855993a..7c67762443 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:20e4a44fc8ab0538e48355b2e81ad762163d76e2934b2ff48e36ca76c20717bd +oid sha256:300acca56731037b1768c29dfb75243ca3836ef7b2aff333192ba77cf7a555a2 size 59290 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_iar.a index e0358942b5..96b1d17a8e 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8540033a397ba25ad7f9a8a89ce8c3df1297d2ee73cd604f35cbe0107d20f03c +oid sha256:50a9a5d33256698fc2e3d0ad349de72ba14bc315b75e0be348c4693ff226a772 size 41792 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_gcc.a index fbab2e8b4f..246a3ffb2d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:456229cd045133ac1cb6393c7046798b3d74a67cb81bd6d8a7d12d2c10ce2c22 +oid sha256:0c02a9111d79a0ecb48748de4e93ab894ad5973d74cc39a891346b0f7626cfff size 59290 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_iar.a index 9c0f5f8b60..c24d4c5874 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pa32jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7c0dc87e9e7bc5d28433f852f28cfc6d559b35ac8c7fbfab37a8712fe5eb0a2e +oid sha256:fabe29b3494420f92adb89082fd968905fcf781143ed964acb7f7a8009979b32 size 41792 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_gcc.a index d63760b4d1..bb3e7ee162 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e2ac61cc133fd19f1ac797ec077ba81e83619db040bbd225f441a6875333918a +oid sha256:7928fed2ba0b26adb1e04853a5d1c72fffc45b3c8a4e9f488aeda833457ace1f size 59150 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_iar.a index cfa18ef550..0601762a34 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb22jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4176ebfe48f7517110d4188e77f43f50621473ac9222c9e454c8429a38eea375 +oid sha256:22b84b8bb42c6a4599a7620ffc1c866e0bb0764df52c2f05e347885aeaa30b22 size 41512 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_gcc.a index 3497c74b8f..9eb610bd3a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:440ac17f94a9bcb4eb9cc97cb371dc18c72e72439720535bf6cd5fd08597a4eb +oid sha256:df2a52071fc9c5ed7027e2c15f770b6a2d251e36391e04fd9bfe1d92b2eeb2a8 size 59290 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_iar.a index bad817bce9..d6589ad01d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210pb32jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b118f11ded34107fcf55f56dd35c21e878e904c6b987676f08c3b605c033d8fa +oid sha256:8102a975484a612083d3ebaf300a374c58ca4644231737ac045ab5ffc5e26a33 size 41792 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_gcc.a index eaada0c9b3..41d7596212 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4925879a1bda1c0115c731dc2622d8ad5ea8384d04d65454c8149dbd330de3b0 +oid sha256:4c3d3a7e5ee17aee2bbcc017aabdf19505b742bf248dac96f0080d9ae7f351e3 size 64752 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_iar.a index 1e04e6eeb2..76a4ef4155 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22hna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ca2664a632df32f7e643a88658b7ee446f6c51af6aac5c0e452f6d4ea8d3bfe9 +oid sha256:4998809c9f1a3ce1e90b90a3204f7e41bab72e8428dc68dbaffff14a123474a4 size 45968 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_gcc.a index cfff76694d..0c1c5442fd 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e6f50920c5c292814fd2aa7fd52feda64bd1ec0606bcc8a78393d1d30662bda3 +oid sha256:aac6f370c326c1c0a2fae67060299891c784fc4b4730d835a5af85cc1a1e145e size 61142 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_iar.a index 2206ff57df..7a05790aa7 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220pc22wga_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:af99f515320b7f01f7a575f50bb25dd5a8db97c993fcb09fc728b4759acaf5e4 +oid sha256:d23b57ce91ebcf2fb025247a7b9d0f049f63a0fe172194b780597c2cf21a1fea size 42832 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_gcc.a index f2b62035c3..f73fa8c3e5 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:08c77c11d011833eb1726019ba21da809a79fcecd4eca6338012f47ab80f58f1 +oid sha256:6c86ed1e0460fcddd6f3d5425903a53f3a3059ce4b2208c46f54e3a0b23d14f4 size 61014 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_iar.a index 3e53e6d9b3..4df3372624 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc12wga_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:81477297dda4eefef76df2f2f8cff088a73bf0fef3a3427db7cb702a66d7866a +oid sha256:79eeb36a3f988b723fc79ac7cf9665a20c5794de84bf366fe8c69680c44a72d5 size 42192 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_gcc.a index 882dba74dc..4912a99dd9 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5d5bd97939b82a2a0fa679666802eb7b3051ad4fb3f46c2718d300e01686c55d +oid sha256:8330f554ace4eb4603e57044eb387b7b6ed7dfb2ad218ebaa14fa80e648a8247 size 64752 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_iar.a index bf4c6cdcda..f66ea0cbfa 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22hna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6088e4cad0f99861935b55c29e1fecffe489a9b62d63c560083eeabc33bb301f +oid sha256:e90afa6b903b175fb2da5d9d8e8d754704db89ca950c885bdb38929922ccf8df size 45968 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_gcc.a index c0a3959a22..4f58725d29 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:83409b7efac6fe57c0847d0a69d906dbccf3176971199cdd7a83d5f692c0d06f +oid sha256:6324eef827b4605be544d04e8dae19bb118b8151720a3b4310cf47baca85a092 size 61142 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_iar.a index 1575371723..9fb99ff512 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc22wga_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0d4a921030fb84aab75e5924f8e65729147a935e587fd7d5a71c907b4940a673 +oid sha256:4d5cac65459e824c1dec3501d9ee5360aea26c3dc61fd70992bc2384ff8b3082 size 42832 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_gcc.a index 78b06fa3bf..de73a3a17d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f9a13c2b80ddeac063f0f912bd26d9e2c6bf0604c278dfc3a01a53cfcaf304dc +oid sha256:d7daafa9cbbe5e96fe3278d4f25b063f40b692d5c5e641ba604f02a6b41c500a size 64752 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_iar.a index 6037a32a8c..f1eb258837 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm220sc23hna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:753224f19bb0c200f3abce232978b1fd0905eac995f9e3618e413092657f1146 +oid sha256:3eaa973047dbcda0751495304f42de7e542ae5ca57b32975079989449c238c5a size 45968 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_gcc.a index e74006b305..7d325bb4c7 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:16690fcd33e6b2faf6d684c5a3dbf3be6b569aee0018bb0fde4286f66417f062 +oid sha256:309bb33210c0c49f22a2c7418b3e65bbdd3e4dd52e9650abf08ec436b33a4dd1 size 64644 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_iar.a index b433d38c03..8b08f30d5f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:483212c23b2e1284274015a555e68a939febfd3df958babf697a9d9530706042 +oid sha256:743b57dc644dfda80d4b2b22aaaac827bd1f740db2ce1502fb8962d90af598ca size 45684 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_gcc.a index 071c855c63..02c0f4744f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7fc96b8d7d7df2449c764f2e4dc03a517847d71c76dcffcbe3054495f62b7d59 +oid sha256:64a87982753938f850015a7f64be08ca9445da4dc350413c9f1c76d0b495cee3 size 64908 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_iar.a index e4ea0c480d..af9bbf10af 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7e5b357b9c9574dd68d4b7783f5eb8fa0d40f673ef183a7990719c21957f9b6b +oid sha256:fbf956318e295acb32259a55fd0e626f9a9ea61714ced822712d3f894abb90df size 46134 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_gcc.a index b878123232..3780cb73d4 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:19948c2d55714654f3548540eaa4def6098c4674cb0661d4991d9c75d3e2fb2f +oid sha256:de9a6f7cc956735eb52f099abf1817497e03f7a52fe9fbb641142d7825ba116e size 64908 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_iar.a index 7dc54ac26c..77f2ba7ff0 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pa32vnn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:87d6a6f49c9ca08d118657d1eb7f75134a24da67eef434064a27c64d62c3ce29 +oid sha256:ce86f03c8d6a3fd78a725e8c3257cfbed978b5b94e0232fec5da4497143fe37a size 46134 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_gcc.a index 16183fe141..68de7382a6 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:21aa0e8ff16247d965c98adad9f943eef3706c169d933872b48a1135356a4e78 +oid sha256:65d3f1b201f9bb061352056cb9ce3e488e2363beff3350b876926d896fb918ff size 64644 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_iar.a index 12822dd61a..5d2510cf35 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9c7997b85e3410a8a3eed21bd470e39f05dc9d7d6041591fc7149361769158d2 +oid sha256:fe48d27f4b52fde995e7d4038af97591445950471390700706fba4ea9ced4c09 size 45684 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_gcc.a index 21bade6b4c..0397a0bbee 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dcbe3e14a92ca2b854c1b54059e2550e8913a0f7d1f3a1666a643dfd3b23089a +oid sha256:5e2489d94dace7d0a396b307b3f56c5f9a76de6f500723c8d588a5bef83436eb size 64908 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_iar.a index 3859f4fe80..0703ba6aef 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:103a3181d4c57d3c8a0e778e9ad47335cdc43d589e11a456221b3fbdffb320e6 +oid sha256:2b963e94f8f7a0560a7014bfbe90914108625b7c653385863e1d828eb3a7afb3 size 46134 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_gcc.a index fa10b7607a..8bb4559426 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e55f88759ec1cb2d03dc8b83dbfb4eaffcecebd5fec49e43312c24ffe44b32b3 +oid sha256:d9fa13c6d94fd60054e221e896fc0c865da0a0fa0ffa4d4ca0753a89a7a215cc size 64908 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_iar.a index 326d401e1d..ac59663031 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240pb32vnn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a821f7bd23ff8ab3c46757a6531cad40945415a625b0dba7f704665230412f5d +oid sha256:fc7984a946211d6c8c2aaf9e02fbada31403029941c764f887ecf5e5860eb997 size 46134 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_gcc.a index 0f2a06a283..9a70a58d8f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3cdeff226fe91493bdea9c35e1e7fd2afbff11e368e16791927687f1a7d02b35 +oid sha256:f4d081e1740d3523c2ccd714704ee3139f55631e0737ea5a3db70d7496763105 size 64644 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_iar.a index d18bf4e469..41f40dea58 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sa22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e9ac95b0d7b8650ba40dcfe5d61eedab07db741cdce492e5407a87da0e890cf8 +oid sha256:08b6cd27b9e8b7a8bb9db3d84c9a4e06d196478782df6d16085530381cf56ec8 size 45684 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_gcc.a index 1fa7d47da7..80ea9cb07b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4ac9163a1419b64e674931e26b4bcf53f248cc6d6246edd4c72b2b4fe046f475 +oid sha256:af770539fa3e0ea9a8e71f34c3815a51122c8e1ed16724ea1e08e7972f85921a size 64644 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_iar.a index b4574668cf..e402439ef4 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm240sb22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ef14a26b87a58baeeec628ee4e29809394250430d4d10fe22d06f7df80217979 +oid sha256:a62f540b07826553bc79eed17d5820ed42091ff509d59ed8d3efb48c3ab9a613 size 45684 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_gcc.a index 4b7882958e..4b17777873 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3ef3ddc306ad00e335f6b3da2571a7c4ea7a35a879ccaead201c736de6fb012f +oid sha256:40dd7353e1c95939eb6cb57692d2a46008a90c02a6f7729d981b1bfbbad36ade size 68070 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_iar.a index f28f5b2729..bee1238a5c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm241sd22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fdcf30bb5da86ca42a4ac42154fe113e6db1de7aef0dadd6cf15753ff90e3993 +oid sha256:760ff8d8c7d88fc6343003d9c6d303a76f44170a6f9d60df569685b81728dca4 size 48582 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_gcc.a new file mode 100644 index 0000000000..76b9f1287b --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_gcc.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cff0ecd5a17fd7ea83e6fab213dcc9f17be327d5066e3af33c37f99caa58eacf +size 64656 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_iar.a new file mode 100644 index 0000000000..135195eab4 --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_iar.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0c8eca0b1f0ef35b47ab71e13e82ef1463d43c3e4e1f1eb56ad9bca9dc6b50a2 +size 45696 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_gcc.a new file mode 100644 index 0000000000..a8c8e18864 --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_gcc.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:adc70fcb62ddec96815979ad93923a5de66ab10043db62ce0073efb52b4735b8 +size 65354 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_iar.a new file mode 100644 index 0000000000..eab89c01f7 --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_iar.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b19314060f99f7cb36a87745e1fb44af5ea200f65c126741d04e1c26de6df444 +size 47016 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_gcc.a index bf5d23e5e9..986035c42f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:14f354c415afed3db3323e2ecf17d50e7ae8709651240de84a2e90641e9a852f -size 64360 +oid sha256:28593183953cee1075e9f3339a784358405c3130e8339421e153062099e9388f +size 64368 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_iar.a index 8bdf8425b4..fcc6d14001 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sa27hgn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2e02ea54d32c60b8b0d84b75a3563252caf9fc049ba9dd60ee58a2010faeed5f -size 47528 +oid sha256:284a827ab8f799f52f761642198278b8beef198a3e90b38f6c58e19314ac7efd +size 47536 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_gcc.a index 74f73c6562..b72caa7c75 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eb6d104f073a7058862383f2cc07cc96f9704066c281f3df857c7564429aa640 -size 64360 +oid sha256:5cb6382f00f83dc83256e32a4ed1e10db4217085da78f9328204006aef9ab910 +size 64368 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_iar.a index 807f272707..1b48535b93 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_fgm230sb27hgn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d2d034d4afacde35a8400f1cbc740c50d348369b2b9dc4373915b451a2684c93 -size 47528 +oid sha256:7e30d3ef788a0bd19fef4cbe8240cd753350b367fd8e6a10298f8600389a265b +size 47536 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_gcc.a index b03897e800..d0e804c040 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fa4b28cd99543602ecf7547471f7a4e9ff8bd836407ff33db29d0ec5e41da49a +oid sha256:e993c3c0c3ad8e86ad1d48e8b6053028e4937a75867128c8798178fc3441657d size 63462 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_iar.a index 1004dde673..3d33d6679c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94320b535ac5f63a3b09bd0dad90a7eff5140ab035bedfe7be5b6cb93b136f74 +oid sha256:48f19228dd871f0bd939a11e7d730c2fba2fccc606a508120eb2442ea85db077 size 45310 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_gcc.a index 259f41915a..4e5d4d5a29 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6c1abbf8c9bab2e8429bec95be816e58a692895d44c366d27c56f4aaf9e0aeed +oid sha256:587ee886ca7d2f85a724ec732f585e56a33984f0656c970ae882b06b83d05ac6 size 63386 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_iar.a index 4287e28d95..fe912872b0 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210l022jnf_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0cfa9b21dfb1045a076f99d3a990691c3bd6a2ca114c03a2bb817347669b2f06 +oid sha256:de28bc88c73c95014860539af40b6c70eaa2f5fefbdbe58c111a7f605e176f0d size 45164 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_gcc.a index a51683df85..2783de14d0 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:881960bdb42272e4ad697a3d77934e388b0e19bad586d2f53118d7e2e6fce3a0 +oid sha256:93180c51216d760b8f66b5e6c1c98f8445f8cf214af82f899850fc16e1c25890 size 63386 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_iar.a index 550ab799f9..907adf7b19 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8aa4edfed2472540bec971198231e3d492cf24f547e42a1704e44946276930af +oid sha256:a7f5c93603b3c6a21f96c25af3eef54df86333df3a2672838fe09892b09a41fb size 45164 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_gcc.a index ca5344c859..01d7448b73 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:06bc0cff169a53a1acd44a98abb0989a0c1fa1ceb0679020609c2f3b5b18a70d +oid sha256:13c959bdd328c690be74982272e0cd0b1103db86985be7c0375141446b581cfd size 63386 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_iar.a index b329f4ba87..a9d94bc099 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210la22jnf_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:40c1de194d101985b7bf2f7cd374608e70b72e4fae928fb6cf1e940f92d6cd4a +oid sha256:1e25ccd269a1b68f1cca7d1ccb97017f45b243482978d9ac94bc0df751c0144c size 45164 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_gcc.a index e22e0c185c..4d5b6f7903 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:737810ebfb67ac0651f2cde30a7d31642c648b479b696ed598583cdd67cd6186 +oid sha256:6f73d5d56a1c08da033016d0515ac82bee53136537bf6b75c3c52d8153161f3d size 63216 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_iar.a index e073243635..60c7bef3a5 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3260825c4141d5066a4c7ea3d58840326bd384a9026f001e7044209605af0fba +oid sha256:a3a90b538f3bc7711173e2a499dd829fddb2748276f4e3295e55ab01771d5b02 size 44872 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_gcc.a index a3c6abc858..d5667d6b19 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cd92770bd4dbab5e8dc9da764574a2d6ecadf605dad9cb8f95e3078604c84241 +oid sha256:cb9181e2956e2047c1b07ac561f2973d43faf49bd8c9dbd90e3c2734c6534eb3 size 63216 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_iar.a index 68cdbb2de7..9664b30cd0 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p022jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8bc793e6b8c4fc0b93c43beb57eb8277a1a410663c08f0d17946ff0f997dd97e +oid sha256:47768e5d68f8a8432724fd0c78e72fae0ba39b970687e5bdec44fdbd8ce1d9a9 size 44872 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_gcc.a index 6a5843ce70..3d87b12913 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:323a771ce93b634c933d5ebf8e8331ffef3167c8461b8e60d5d92176443062cf +oid sha256:15d5e423592ed68a5fadd30d92f90e9e32485a8e0290046ef437ad536f537ebf size 63576 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_iar.a index 42b8782db7..0bc09048fc 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ab8b522fae4c4d403dd71b5f094c3c8cedef522c6585843ec57fa7239baba364 +oid sha256:9e6f4a6d8fb24a908882b065d4907fbb6f6d075e2a0e6dbf54b35f387d9c5fe5 size 45578 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_gcc.a index 4efffc9f75..c394082cbf 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ec5f874603af0f9b0f28ff19c09d90537c234123cd1d6887d7c18e5e32ba92c9 +oid sha256:e40ac0cc6f165bed5627357e033ead0f0f3f1c8275fb0bf0114b9e9bd8638513 size 63576 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_iar.a index 310211dc76..5403aab936 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210p032jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f26d84ac5d3c34d0e0d836fbce1646e54bde09c8d641e967962fa34cbadca5c6 +oid sha256:0283564e1ebfbea031625d0344819b837072db5f6902eb379fc213427a1cc0dd size 45578 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_gcc.a index eda91a89da..5013ddec85 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:df46dc0b4bae1786d025bd7d600fd402624d55d2023c7934e2fa89c98533a737 +oid sha256:42165c3cd1cbed6f68362b1fb6e69ca48fdfde4c30d5d8265af772f301ed13f3 size 63216 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_iar.a index e46ba33724..4f3ef15d6c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:90eeab4afbc5788002e3edc1d3a5c8d2cdc224a3490052000aa4d8e3a1d4d08c +oid sha256:f9e1121e63c54554426760246e37919bfb87aa8bdbea7f7fd1c130fcc343388b size 44872 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_gcc.a index 6ad8fbcb69..8ba38a7d9c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:248340121e1786f37417a1657178322cdd40bf2583c359344682c09ed569b819 +oid sha256:3b263a5b27a4264f730be82d277587f379501e25fc19cfe689c0287453de60b8 size 63216 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_iar.a index 9a48105667..818f286bf4 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa22jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7756be2a7156b941805c2f21efa61dddadcd46347e22a4e34f88ff03042c9efa +oid sha256:981515dbea32f25e8bac6da01764b116123f643aae4d6f298cd7cf5288bace8e size 44872 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_gcc.a index 45e7740b78..1aa363a4f8 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:84f6ad9bc6363a13ea2ab7b89b1a38e03ad462d0dbd36948d3c3f8faccb4b4b3 +oid sha256:0a140d355636199299ddd7e74d98547885b204d66f5238ff175a730d1eb7cf09 size 63576 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_iar.a index 90efd0735a..02b7684906 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ae1771285054636b1720b97ca2d54c7eb8044c4e0b6d58c3bcf9af1b22aeefd3 +oid sha256:46bee19aa4d020e2fac4db133f9af672d6551b1e364d2f2ea05a523fed932342 size 45578 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_gcc.a index 17291c7081..4ae092627b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:598edb298a955d1a7d406707b9e5a13794b0222de4c3195e83b5320e2a2ff0db +oid sha256:6bf18b5aa228cd3566b974f48e2846567d3dcce2cb6b648d51ab713008e33070 size 63576 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_iar.a index 6d3481140f..d8f9845138 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pa32jna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4ed59a68441b4d468ef8133504ea0008a8a01f3078a94dea7f2306214e16dc28 +oid sha256:8f12fed102e149afc8f265d3074ae02a76fb925db1919c4f9c1bd7782452a99d size 45578 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_gcc.a index a0a1fad325..518cda06e7 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:26ed292063229f5fd7d14b50584e8049e7c9fc8359d3cc261bf4934aef1ceeb4 +oid sha256:772f1c896a9e4c9797e9bdee5a057b3b38a26cc7f808094fccd29aabaaa46e08 size 63216 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_iar.a index 87c8e1847d..d81f0e5c62 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb22jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:622d3061286e475a9289376be78f53d3a6756bdae54003c2a8d2a4ed59cf48c3 +oid sha256:912f6648862dce9d714184c5825172db717f0849f2ff3190faca5687c328448c size 44872 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_gcc.a index 9ca4e29865..0f2ba52116 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9b3c75cf4b7713589080081a14fac6c1fdd5bf94c312329c0cddfa36c8774276 +oid sha256:75d91f87b2c4e9d9455d618987916540ee8183b7433e3f3137773547ed4cabc5 size 63576 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_iar.a index 5317e761c5..14ae7e2792 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm210pb32jia_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:315c9b40a2a05b87eb58a258910101fe17e4d7d276a0e06834e2da25f5a2954f +oid sha256:a98069ebe3e34c756872f2d257f7b2f151f5903a7ec7181e8d5241ecc0c9191a size 45578 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_gcc.a index 20da8935d4..4d0603c867 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1ea25d53d21392abd871fcf00db9759fedf96f5d288b2d3618b0df6e6c60edaf +oid sha256:e17c188fbddba24a65242ffc21e3f8705e896bc25f6c3b11bef06a8c7fc65f4d size 66748 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_iar.a index 88c005b148..edb399abc1 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220pc22hna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4928065201c62fac1ae25202d5d81ad8bc88dda9a878a39699567aeebe34d6c6 +oid sha256:cb62abc77a8c99a691335832a2ee6a54e6b5fdc006698e0780407d6cbd7520c7 size 47718 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_gcc.a index 78d6e4b28a..1d49226f22 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1661def0108451dddf9242567ca4706383d94c4142888055bca648bcfcf5fa7c +oid sha256:69c05111fc2408ca15483d0b326e825208b81b35c9edd25b382f6c8afda678b9 size 66620 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_iar.a index 1df771bafd..6a70f75ee9 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm220sc22hna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1cbc09235dd29870f905db794c83bbab5a48637a5dc94a28c1826070e8010877 +oid sha256:490f91459a9edca05ec573cf720acdc3d2bb91838556ecec81e51ccac11f064a size 47078 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_gcc.a index 9ae632eed0..d8f7936dc3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f0b2802670f6ecda756ba1e5061db138352cd839fb579bfc6383cad1fb2b158 +oid sha256:6e4e8dd84e0a5b0aaf09c79b0f413f7f643550a4e39ccdb1bde9155c86c35d7b size 73964 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_iar.a index ba6f97bca2..3df75db5df 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022rnf_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4bd40d5f471a78edfbe646ada5666850d862ae6f5cae5ae68d6c6b7e25868426 +oid sha256:1b2ee55ae471b7252dba7272015798a7dc021b1512cd8da3c4ba0b3e664329cb size 54122 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_gcc.a index 6df3478b0b..b3982debb5 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:28332a81082785dbc313af8b2d2ee94d0fa48966d36998ab86e3847e72755e23 +oid sha256:daa660fb1d13794f5977cda89877a4669db85b93e05870bc50654480ee4b76a8 size 73964 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_iar.a index ddf15d5983..c4fa016e4d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ee37242a3a6eac5aa7753ce717fc625d5b58814d1a7bdaa38f0ad32c1a79e145 +oid sha256:90441e372556add1a10dbe236b979757514d3a8015ab6db9b3495966fe2fb88f size 54122 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_gcc.a index 09991a28ce..5b08e11aaa 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c4b120318dbe55dfb8ac14d5f5ef22dae277cc531c58554a38d313bcc056f205 +oid sha256:df9ed934fa88470d333d7f1b7f5789f5ba49265c6665fc5bc5122e2854f27efa size 73964 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_iar.a index 2a41ab6002..29699c031b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240l022vnf_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5bb65668ad2c2fa9523527c6be9b50a53ba20eee5c21796cf65e40520fa4600b +oid sha256:c29a879e98f2bea14e3b196c836e069fc5018bb49077a4bf9200bf3835498fef size 54122 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_gcc.a index c20a895858..29303ed4e9 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f6897a6b1e5c3d04ba5e0e78ab8cf3aa0c1ba4316f0b4cfac7c8a2263bd90093 +oid sha256:74fb07b3ebb0fb1acd1c6179565d1aedae4cf87b926e30df9a002431e67f4c3f size 73964 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_iar.a index 5ce09e5751..663e7a1f0a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22uif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:54687daa8f0b88b05963fdffe04a82693e33d4aa0c5de2e69944296795b23314 +oid sha256:66688489061418cf4e55ed9a9ccd62699ada09b3f9236fd9e4af3fafb359d5cb size 54122 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_gcc.a index cd4985f02c..c73cd47c72 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f294afeb01fa99abc95f3748a55d5d606c93dad4b51adbe95823f0d057f88071 +oid sha256:b9fdadbdc3843e17c4302ee4414e79cf430b3168b42f80ec507b23eb4cac808d size 73964 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_iar.a index 8ed20a8aa8..aeff1d5a7f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240la22vif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:abc50a0d4fe9844865512d98caf2a36d02f7cdecb6356e05f4052170e7799af9 +oid sha256:809820a2dbb61b6676165dbe85e1882a37defe2ac796124f72260c23475d2391 size 54122 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_gcc.a index 54c7b454f2..e1478f658a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0eb5066405a50715863c453adae2665c3712c0b44c3e98e9c386b0f3f09f8cba +oid sha256:ee0fb9c76911f25013c9d4cf3a40096c7c39a575fd31582794a4f404dd6f2119 size 73964 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_iar.a index d8d35d6f75..4735685682 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240ld22vif_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:009eab1bf34c69d2f8ac6c6e67ff9fc2862f9d347701e3423db614d4697b82ff +oid sha256:0646b57e0f4ffba8e4157be8fad9278b42c10649a7ef53e7913c58f2f41bb205 size 54122 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_gcc.a index 808e82f0ff..1985eb385c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:500445cee7cf6ebd70b2632a278aa20cdc9f528e220349902ddfca31b190d7c9 +oid sha256:a4dcc9a627a4cb8d8d3990a69665ec05a7f3600f63ee32417b7e66734de8e413 size 73944 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_iar.a index b3454e8c43..44ad7cab39 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ec9bafde0a0eda33de548b450951c7e3c83aba2cb0d88007444a270edf5bae14 +oid sha256:39a86ab9ea431aa3d1a6ec8cadfbb139ce1c3caac964f3fb2f442135747f7b40 size 54102 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_gcc.a index 2b479ad62a..5b2d17dde5 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:32de342176c44e68c324c071ab7b73f5d26bb2958ec60db8e7bfe380e1b0dc82 +oid sha256:7036c4a9e35242408771a9a72807ab29bca659cab920ce144c1fc8939611bc4c size 74466 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_iar.a index 2aef2c9bb4..84274bba10 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c07643616c6634bae3a6de4e755315072af6e02183269297e7e3124a6d90c6ab +oid sha256:5113e511f577e784c46ad74d7f67daabdcb644794216e7b4c73a89bc3f312bbb size 55210 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_gcc.a index c91c8cd189..5f9003c05a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:74e12e5158a2d175eac2c73b4edc4a3f99578516fdb2915dfff0807d74c27b41 +oid sha256:4ce10fd496dbc35a1f418262a7b7da59ae5e0b487709cce4383a841ff189aecc size 74466 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_iar.a index 76b6f449a2..e268e96909 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pa32vnn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9d5e935085fcdc399177bc24f9bb8dedb599cd4f92f6da07734ffc4cbf17c316 +oid sha256:87770a07c3228856cc77905c49ef65b578b2cde36fc723194568603ddc68ef0b size 55210 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_gcc.a index 6ec9d930b6..40d51d4d08 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:960d95736af4c0925a5f6d60a050b0076a6e5519ef163c3cd4b05e9e5ee674ec +oid sha256:0d23894eff2bd588eff12106ed84159a9b98cf93dae096819e82d10c9c8c9524 size 73944 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_iar.a index 9a384331de..c4ed07ac9b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7400e9abe63ac3a6ef0dabae4e99edabfa97a9dc041363ecb1bb10c82f1c739c +oid sha256:ebde7f9cd27c2ae3bcb7cf5f8b010c39d31d719520441faaf1046b1fade60a5d size 54102 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_gcc.a index 086c91ce9d..11f52db862 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aebe2f67edc968142bde0fa93d1f9200fee454b2ae5cc9590a4825226a4823f9 +oid sha256:4ecd37a278c7819e70711695eaf5bad3c4bc5caf4ed05ede4245b18acd83c2f0 size 74466 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_iar.a index 289348580d..f2579326a3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7aeaf495358b140e3145ba953158f4d5f7d16cc82a0107e15ed099c97fa975bf +oid sha256:75ab196fc34ff951ea07660f644e505eaa4e3eee5cdce97d07b9a8100b8f8bab size 55210 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_gcc.a index 8633dff6b7..0ec4b2b383 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:367934eeefb2b25b69de48b299f0a2759e4caf2ac503b97ac2b5de3e6ffc67e8 +oid sha256:0b6e23f14fa899524af5bd00412d73aa461446ece175ea3a26044326f907fb63 size 74466 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_iar.a index 25747a3f7b..9c3d75a53d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240pb32vnn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:415d9f4c5844d3def068f98e4e180169482782032d1836e31c0c3647c97b5522 +oid sha256:fedf02e70ea07be54ae238cc6fde83b1ca2708398216d6641b24f55d00b97af5 size 55210 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_gcc.a index 6ff6b412e3..c3fa9c6b85 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8ad586be442482f6507c936f3b80f9af412f4ac49a89ed3219f27ac44b14ddcf +oid sha256:4310772bc185838f5e9567008c06267c0a5526f8234f39e837df6a4ad61cdb4c size 73944 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_iar.a index 3e5d1d988c..be439a2347 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sa22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:38358c2f8c883649a6f9e54829ff4b7b6a78bd3274eab50cbc1c33d338fa64c1 +oid sha256:88ed430c903efeed06e2bd8f64677c5693e8968cf383f60157f5cc591ee7410b size 54102 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_gcc.a index 6bfd84c1f4..cd3e79d4e2 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:619c122c103970646cfd6384e3fd4c081146583d91e1f2ab2a5ffe511618ee64 +oid sha256:2a072d2ce96c3828cc7bad5299fe2bb71a00c2426d9aa7229a49f57f5a3a5eeb size 73944 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_iar.a index 77f92a567d..5a0bb33e0e 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sb22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8715ccd98bb2f7048a142d2140d6dc60ec926ea4cad09a4fbced009cda5836a9 +oid sha256:9abb785eb2a3b0651e57b69ec0a29713a984b00e6e528fe1d21baf875d4cf59d size 54102 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_gcc.a index 855ddd6c73..63f0c52ad6 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:101fa195dcb5f5707cd81050cbe0760bfa07d653540eca446f25e230309cff10 +oid sha256:314e20f38f9e32a3dc0ba5a55ee4cf8ba1f00ef534318e0b9d7ac0daff704ebd size 73944 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_iar.a index 2dfd1077d4..4eb4f964b3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm240sd22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eacf15d9457a728f29c3af1350b47834e6a31d7e233f8702b7532e92675ed342 +oid sha256:47ef703a418c78a29f8a86787dd43f3179efd12164216b1e4ab2f929d41c9910 size 54102 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_gcc.a index b220e37ad6..d97bf17b62 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c0271488caf76ffebcf26f8c2474ff928f6e3682a55c6e4cb43d114a24b5fc91 -size 73956 +oid sha256:871a578e1bafb9bc77fe3c327e410382db15735b789191e45306bb311e71599a +size 74236 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_iar.a index 10f7cf6159..56328c1cb2 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb22vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:24767a9738fe6c034c625895739e1c33a99c2fd30ce1ab6ae60ce3d38fd32078 -size 54114 +oid sha256:cf67d80644ae6bd5a8b4bf52e4768fd6d400bcdc2a495852bbc23495fe4987ca +size 54774 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_gcc.a index 360462920d..5919b22afa 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:67486a91674a4b46d076953cc16c4e7951a00982b409cc849ae5004cd5eb3e84 -size 74838 +oid sha256:b2f5c49cfce80954cdd3c1c7047e2b59980753bde7ffa6a49536b50f81a890f8 +size 74918 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_iar.a index 878af51f2c..85b334f126 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vna_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1fd03156e0ff8420492fc82af8de42659e5715e963f78e1d1f4ee560dfb7b247 -size 55954 +oid sha256:6ea216a120e21b45aecdc3ff1f93ad4702eec58ed79f0a07ef6b2ceff7ab3105 +size 56094 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_gcc.a index 0f0dfbcc6e..77f7408467 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0281ca0d0959c386dab7e20b026918e4af55e8fce9410c8af8fc9297287bf01f -size 74838 +oid sha256:3ed798ea3f659126f0c3d189896fa56c7a6b808c5d2469a6b908438090b44271 +size 74918 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_iar.a index f62910ef27..803cc0a448 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pb32vnn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dc258b54ddf5374069df2bd7c410ef1c5894d494191a0784baed6ad19b130a1d -size 55954 +oid sha256:dfb4ce471c8c29c52ad94c2b1804e012d36bf911c5f8f2d2fee70e27f9151b89 +size 56094 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_gcc.a new file mode 100644 index 0000000000..6ebeb8acfa --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_gcc.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a6eeb168208bdfa72d61cd2bc21e47bd3ea3afb16e55c2fc1b628b953f1d87e6 +size 74236 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_iar.a new file mode 100644 index 0000000000..59c8172915 --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_iar.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:70bf55ca5595e3ddf39c2335216df4b9672ae7794f45303f94b7e12dfe82201b +size 54774 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_gcc.a new file mode 100644 index 0000000000..824cfd8620 --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_gcc.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e66a1cc61dcd1e2e004ec04acc4f081854d61612a925f8a32be13c9fa229de02 +size 74918 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_iar.a new file mode 100644 index 0000000000..6e8a448102 --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_iar.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dc41f82e1676df8188878cfc72dfa998b2802f5950efc0b53e551b6e0ef3f0b8 +size 56094 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_gcc.a new file mode 100644 index 0000000000..9892a157b9 --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_gcc.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dd625b9971d9fa24645aab2e3581ad38d2046fc7cb9164cf72a3532c5e8fd04a +size 74918 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_iar.a new file mode 100644 index 0000000000..5c3836dbec --- /dev/null +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_iar.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:20265e6cb8a4a5afefc063de5bb1760e56958a77565f6b8e977a8d6a828398e4 +size 56094 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_gcc.a index 9504730384..e99004db12 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3896be24e359c51bdf9e3925d31a0f002c6c9ed8cae42ac5aa2cd0b71563cce5 -size 72176 +oid sha256:081ac1c0c26d2978cdc2bf419933216030650f0d2aa8abd8e6e1cda55d2592a5 +size 72196 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_iar.a index db9ed3e472..74143bfb34 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hgn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:78cf0feb23dc7ccacbb18dcea68cf5a7f27ea327583e98d15599651531817a2a -size 56412 +oid sha256:e34481f3df3ceecae3a2baa4d539cf828dd40e6a35abae2124569e2cc8bf6b7b +size 56432 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_gcc.a index fc6913b27d..280ba8ab2b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e8821f2ab0d21b64e51fd13b181fafa464237f04f270a4e8ba37f8ffdb0382f9 -size 72176 +oid sha256:afc3c3f18d52ac82725d817c0d8ac7dec74abe6f3b6c47ff73e040cf8b89c503 +size 72196 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_iar.a index dbb4573d7d..83308b4f38 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sa27hnn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1f43e0dd8adbe255bbd9487fa203a36872ecee327297c3ea4c935c6241054ffe -size 56412 +oid sha256:e22ad5df88ac12679635811804c1fda23786b211a68c9d6d391351507e88bf21 +size 56432 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_gcc.a index d0cdf5a1b0..173285d3d4 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fb370e83ce849d5ed634f3f191a1be2d54e900e453ada11b3cc806727bbf7f85 -size 72176 +oid sha256:7fdf5ced6350b1ae3abf67d13c08e1bae33e3ec5cf662fe99047f6a8933df727 +size 72196 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_iar.a index 8daa4b0f7c..408dcb760f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_zgm230sb27hgn_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:198aac2ebed8b31cb8893582777e0da7c0198619bed76761e582d8d0ac9be07b -size 56412 +oid sha256:9467b469963f810261f3e1cd19948d63e17543013bbe33bcf3aa2ab503f60e39 +size 56432 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_gcc_release.a index 399e16ba17..f39992cea4 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:27450969a71f072465a926f94920957872084c717638d7b47706b17f9c4e08ce -size 1482910 +oid sha256:daa6e8050301a5ff89bc89b0de8f8a752cf4c32bf78a7fbeebbaad76f880b9f2 +size 1484048 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_iar_release.a index e8eafe7ae3..48909a7df5 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:80300569a875185ee0f6dfa5d7ee41953cc1543bccc9a6c798a1977249d0d3ab -size 1987126 +oid sha256:4495adddf701a36d1d235c238317a5c0c091e5b913fe713b6bd7399e861f95a4 +size 1990136 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_gcc_release.a index c2e48b0f04..43757c5ceb 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2fd82a535badff2b6e8d768e61284354f4cdff638a60f20472631eddffcc0a2d -size 1504640 +oid sha256:07aa378ae83e5dc0ea548329f08e7bcf5b6cc4003cea6d689be983263a0910da +size 1506456 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_iar_release.a index fd3ad892a5..7cb499485a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c28d3c42c0e2ad8e5f77655e16097d7425c931d0b825e5b55d140acf0a2b681e -size 2026280 +oid sha256:da6a4c2e8adee759302b56e035194feb4d63da762318276f098a58f8913891ef +size 2030160 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_gcc_release.a index 1c44b8a1a6..db569e442f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:26eb8ed1be21ee0217f2f793ce096d22ccdb97f56a4b4a482fc183ebb83fbd09 -size 1533644 +oid sha256:70fd05fc2e149605a7e3a6c2965495b78989510def2762c944f006a459c5dd81 +size 1535358 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_iar_release.a index febb56bf02..1bb5a09dcb 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6960162bb654033b2c58711a8255666ba982d64730851f5454d9c9702eacd920 -size 2092044 +oid sha256:d69514d63e8c99d0e1cacab996b5899628b3bb81b5537272209dfa304bfdf08d +size 2096354 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_gcc_release.a index 088c6ee5cb..e6fbc515c8 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f8d026207d60d69fdb078de4174ff4678b10a5c3b7d7090d1e547eeaf09f92be -size 1579882 +oid sha256:df5a4cf39aa3f5fe85c95ffaefbc0d5db3e4ae5f32185d5db918e8f79d732257 +size 1583306 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_iar_release.a index 324e8d04aa..b68c6f89f3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:349d1945f59ebaca3a9a0864057ca6ff65656cca79fc1971c62f9f3ec965f8de -size 2157590 +oid sha256:70a460d8c10f1bd59a4b79cee67cbb863d7a273c2f0307341cba132dc5d8c577 +size 2165310 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_gcc_release.a index 5bf1c30c34..a6a060ad3e 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:341a995c4f49cc7aa23be3ea5804192d0567535b619fd901f26c9a6cca19d27c -size 1718726 +oid sha256:d92945c12c6894a9f89a9c3506f3cd0c56753f6e8d8ffafffff0520c273a8cda +size 1722266 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_iar_release.a index 95d634a8f5..99e9016d12 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2ac3d73166f78207fb0b8d4962e6362dfd518e26a63129999bdfad4cbe4742f7 -size 2288858 +oid sha256:f765651797666d09ccd47d46055d5fa49baaa10e66603ad2527984bff39851e0 +size 2295398 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_gcc_release.a index b0d24af10c..de7537424a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6626468a3ef0aadef29d8a294c6317b12c2b94a1f4e71593814b9451581846d5 -size 1550850 +oid sha256:33bba8e0aef4ad5c771832fe6d478e98dd2af3a3a47933247a4b69f5eff7d9ab +size 1553328 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_iar_release.a index 8cf8571960..9debd6a8a8 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg26_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:75113df90f93f3bab19055cf173d851e6fd2c468b733b317d31533d75153c593 -size 2083702 +oid sha256:b564fcfd63fe59630f6d69e22418d54420f87f743f14fc56c31a327c79e78d61 +size 2088028 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_gcc_release.a index 1c9f9dcaae..fcd3d73bfb 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:48b191217805f6e9f07a99d78eef8c6d73390104d6473ef64d316409dba89276 -size 1502228 +oid sha256:4ee64f0deea72f364a4b04bdacaea5558e17fb53e49706e5e055fc15a7d02460 +size 1504068 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_iar_release.a index 9f019d6c4a..9f815b4e11 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7355f3c5e664822425259bd5727a2f40fe28b0b8c6aa6715861d9575c47f64e2 -size 2021544 +oid sha256:b2dc293309fbce43c5732f6dd5d0a1c96b91128923e479b6947f83ee1562372d +size 2025456 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_gcc_release.a index 58e5c05a5c..4302aa978b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:387656d8ad8a8f17c31484a3ffb59861646ac854f585224b4cc2d4a3decdc5c7 -size 1567654 +oid sha256:200361fbf5c99a465b479b4aa07fb7278158822063026663bac6e7cfc8d80816 +size 1569152 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_iar_release.a index f224713c30..f4de000e98 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:40d1f508903d9e57055c27e65bd6643e6d79d6bf4267cb63d620a8efa0450ae2 -size 2152018 +oid sha256:f6bc00234d1f36431e9ba1cec8de9af400f40f30f44ffae989bc3fa7b3695c70 +size 2156436 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_gcc_release.a index 917c416606..28f72c9676 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:53fb836230bd945197166e944e78a4d83addade66846216a08b0dfd2ae9f40f3 -size 1502184 +oid sha256:b94b6d4920835c0d63f0a3b337095b2b5596d34b623375ff1ac9eeb639673223 +size 1504024 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_iar_release.a index d6d20b3822..44f050de9c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dbf8c3e6062d75a51fcf331eec22949a4c86d31b4a474b66cda8080da8310676 -size 2021432 +oid sha256:9688573b4cb44be3beb21a58dae16652d7815e87880d728375f5d585524e81ea +size 2025344 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_gcc_release.a index 22639e1759..0ec37347bf 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:de0cba34a69ad19a688004f46f2b3ea77c392ff0ea17e42fb72dd5223c002fc5 -size 1460498 +oid sha256:1fb77281ba9367a138171fb80ee38bc6694421ff2b804df401c9fd625651cba7 +size 1461636 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_iar_release.a index cbf013a96f..097e28d428 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e843f17f290b2f4f9fb3df43930267e5a90c4cb2f9aa321c613705f3f01e48ba -size 1962090 +oid sha256:aaa225bbbfa7236965b89ba8058c33e20af29a8619f2516c0f4729aaf208e390 +size 1965100 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_gcc_release.a index d30b975531..8703e1c43b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f95be1e92399f10481afb34ce12b4a3750d8ff33a2a32bb9b98b8931b1ff0ffe -size 1479902 +oid sha256:f99e34ea00f3001ec97cfafa32d531d2b770eb5507dceea7487a8228d5db629d +size 1481722 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_iar_release.a index 4f69b5e2f2..d18562c84d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:089d485510caeb16e87aa542ae898ea16bd45dfa0eb83ef562b2832f47a10ccb -size 1998026 +oid sha256:0130ce7fc00417021497304cfea5bbb6df7d1b2e9cb1cad570e1696a511e3720 +size 2001906 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_gcc_release.a index 6f3f7e1a18..4be9bed005 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:215480ba02ee75290c938c14802f9057ce41612aa043d00dceab357cbe79a428 -size 1500806 +oid sha256:7ec13f945583c06214abcc3f58b3bd4044d95289dfb8b6a53c455da994fb8a5f +size 1502494 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_iar_release.a index e279457649..bf3496a0fd 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg23_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ce5377320663764fc93a5127ec3960166f4da719773cdea8f9aa6b0829e0af55 -size 2056670 +oid sha256:3a0f0a893e376b770f3f58d283373561e8f0d093c968097d5847905a7c1b5c58 +size 2060954 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_gcc_release.a index 7410e09949..2c8e4448be 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e3c9bc12459a1ee081925ad046818bebb8099b3109cdbbaadfa6bd1c1d19dfee -size 1547686 +oid sha256:974c67e06275221d4738cc4d8e3deb19b0b311b370a528a0d4e93e4947879ff8 +size 1551108 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_iar_release.a index 0d6ee8c991..cc78c5c050 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9b19126f07d75dc53ca18d4f4e2dbf98b9907ab97060a1241597a562be5eb9e6 -size 2124266 +oid sha256:a3c3347fb1ee8b3e51f5e05c4b5f62f2b19a4f670c5538d71e6dc528e4afd81b +size 2131976 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_gcc_release.a index dfd1bd0bca..4b66c13fee 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:82310c4cd077a78d5ec2c95017ba2ad7b03d4cc1afa304c4aa7b4195cbb43534 -size 1711126 +oid sha256:fad5409ea8b8b8f63b5be70c5f90e2b6bad7cb6f6eaf201663bce032e2dcb356 +size 1714666 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_iar_release.a index dbe4e52056..4870fc5f87 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg25_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a375a15a6e8e7e55443025b95bafff763f4e821cc31fb01a4a26fd9ab1a4dd30 -size 2283470 +oid sha256:ec68f0ece6a35297187771ffe3c2bf82c389f8fc5d06c1a6761018f59442d099 +size 2290014 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_gcc_release.a index 2ebc2b9a27..f8f2a9409d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9ea00ec39cad27314ddb785427f715c58e7b5b83f666c34f3e5abccf457b9b57 -size 1512608 +oid sha256:0e3e2e95f9a27d22deb98da8b5002c96a5cb09bff0aa07568f6d711bdb511325 +size 1515084 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_iar_release.a index 773011426f..7511113161 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg26_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4bc6cef4cbb0e3908c1101122d3665e41c864736ebcca3b14b257c4fff56b43e -size 2044068 +oid sha256:6bf27220f40bd9b3822fe3ea3e5c400f51bcc196c7e6557a82cce27c15a65df5 +size 2048388 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_gcc_release.a index d3b9353863..07dd3b5be0 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3029db699d607b1bd7364f7318c2ba4ff5f2618d4bb58abe9d0b8e2f80445fdc -size 1477522 +oid sha256:9a71b6971ae06dc89f851e323255bb78451d9ef4ecfb1967592c6be1f7db5b66 +size 1479366 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_iar_release.a index 4a02c86dc3..e1edb1be8f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5ca2a73c88318557e360cbd34dc5797db2366c697e5356d2b34c7e1f013aa762 -size 1992782 +oid sha256:0ad0cc075df380bc865c10262b788073805cb98c5173ea296c3d046451809b40 +size 1996698 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_gcc_release.a index 262888e67a..a890a98330 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:662eb574d6c9853b55f3715506a789d2afcec59224237419089a78d9f6e88eb0 -size 1524942 +oid sha256:7a6a873765868a4c940b5a9f473b74fab648192738e84337044c7e41199efaf0 +size 1526416 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_iar_release.a index 6f6bef0eb7..1188183a6d 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ba4ad5614b4f39dcc3990c1c0ae5f580aee1339065fe91bc3cb537ca9e304aa7 -size 2105350 +oid sha256:7181c3359d77834c5b001a97df727f0061bc3b2623fc738f82d6f4ee574a4762 +size 2109472 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_gcc_release.a index d4f4075304..7d9ae30e90 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:733a15dbad5428faad0e16ec5d245fd85fc04083602d2a979d6e06153bb51fd7 -size 1477474 +oid sha256:0a00494a2938536745ee1322dc7b51acf1afead0439eb8500bf46fc200489acb +size 1479318 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_iar_release.a index 8978ac3973..357a3104b9 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_efr32xg29_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:13ed0714521b8233943d6a876fbe386af6f8e2dab31e63349579b384f589f7cf -size 1992670 +oid sha256:c10cf173e926bde3ad6370864ca3a80ba6a510fcfd3b486b82375b9c1159970b +size 1996586 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_gcc_release.a index 884e0af53e..4024fa05a7 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:db6bb2cd52438f96652d2a9634f36a57950d157f1b70693541ab5020163ab8d8 -size 1538230 +oid sha256:2dc78744ebf353fe224909d5a6dd11285e4436444d0b7d38f34c4cbda218ef79 +size 1542396 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_iar_release.a index e14914dca3..70a32bc991 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_module_sixg301_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ef87598f975379e9defec67ede5840c765f46c0b0d65fef6c24687cc40900f66 -size 2087742 +oid sha256:acacb29d259af5eb5ffc80d1ec388f355e707448a50951697f3712e9ff0aa200 +size 2095644 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_gcc_release.a index ac6678ea64..b356d5637e 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e9d6231a2b5327ab85f4e8f949df82b94982327c6e839af6a3045a95b8a1cb09 -size 1517280 +oid sha256:3bcf3a7e59216fe85b859dd2e746aebc5ebcf1c1a40c5d0efe84ced347355e95 +size 1518444 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_iar_release.a index cb2d7ba0c8..ba1b2d6add 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f7b3e1470ea0bb24d01072818e0b10e6da407b4df52c2af42c34528282c639cb -size 2146412 +oid sha256:8bac578b23c5d259c775ef4b3b04b38565d18ceff6f287d7e48e8bac1a23b716 +size 2149120 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_gcc_release.a index 3d93a294f6..315f31e7fd 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e02bf3a4732d9086009fe731caba94d88d2ca97c40e6d914cef9645788a7ba2 -size 1539028 +oid sha256:abb14b72a71195e8f9df4123e55168f9441e2b603ad50471aea4384b96cc7463 +size 1540864 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_iar_release.a index a44bdd5884..62074ef2ce 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0a1086a8cb5d8a3aa0fa3bc6c192e355f1208b2a4e0213fd4b0bbe58b8a23677 -size 2185396 +oid sha256:ba16fe66379b78876f3cccbd88ae0acee606e41c09ee12eadac6a62191e9dee5 +size 2188112 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_gcc_release.a index b701f1d963..e519b829a6 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e600e62f27262cca6515f29318b5b305da93125a8fc8cb22a925e7f9bf26eb0a -size 1569156 +oid sha256:ba2bd6b7b380312a521e3bc74329951a0fde67e30bd24f0f57c79ac825b96c32 +size 1570898 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_iar_release.a index cc7a884907..61723567fa 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg23_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c9bda51fbae73bc5da520c5821a50742e2e28fc5fa7f11ee429ced775e77c526 -size 2250860 +oid sha256:d535d8f4b6024adb7fdfd4d3f6953b7e7d4450cec748b8f056b3c6bf90515839 +size 2255322 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_gcc_release.a index e9eca2d7d9..5998137132 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b6e0e1eff284280a4a00ef57c5158abc067d297724b3d8ddc1851902304fa013 -size 1615340 +oid sha256:deb01f903f0a0d67a4ac38e6fb8a5ce6d2855ca9a96865eebb454980097dff76 +size 1618798 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_iar_release.a index cff6e5a685..ecc52131c2 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b3c4da8f6663a79c113a239e72a0dea1b684f2a7294b885e170723da11576dcf -size 2319628 +oid sha256:b7ea62afcd56339b08b715550e15727a1bffc2411e5860205c2695cfaf452662 +size 2327514 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_gcc_release.a index 50bf1c2e07..4db6338055 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e5b9fd0fe3ac9f10b55a45b949eda6f3078a82fe11e68d2688f8d8f8fbea4398 -size 1752954 +oid sha256:b9b2bf5267b662431278b57d41e4c838bd1cf5d0f63c10f38651d96cf95a3dd6 +size 1756530 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_iar_release.a index b57a213ff2..f192c2a0b3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg25_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8810f847eec9dda2211c5ada59ed2a00b1f8baf9f346670e407f41a0f4ec2210 -size 2445430 +oid sha256:785742cdbf5ae2def980ff9e9ce04b9c924664163e74913f528f461e57b35cae +size 2452126 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_gcc_release.a index 762bc00c79..c9a5e439ec 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9943b6a83eabd057f0a8d97ed4dff7c15b060c95ac5706d9bfc27a4fe21d6752 -size 1586274 +oid sha256:dc8192f4b7367d2f50ca142dab73d9fa31362a6b5a89133bebbaa4f4c21ca49b +size 1588774 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_iar_release.a index e44d257774..e83370f296 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg26_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a2a0751bb32fe05d6a01616d1fd9cde551c3063f8e519c6ecbd5f53c329e71ac -size 2246202 +oid sha256:495b1d8f2e54540ebb7e3533f5bec7425f6314535a4dff5db358b15a54ecc613 +size 2250706 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_gcc_release.a index 30c0a6fcf2..fe45db5214 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f36cc68fad0bb00913332ffea816d766bf4c2672e0fc72d8690b0dcedeefde09 -size 1536620 +oid sha256:9f0aeb78689a31f054258b0e217f0dbf5fe9ef6ca254029c84962dd50497b61e +size 1538480 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_iar_release.a index 844632485c..f7b1510a8b 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:95778ebfb6308d72561fa9b37411feab2183758b1ffb421be02d1d475c0e40d1 -size 2180796 +oid sha256:9cd57f89644565f5c10d0b8fd1f7176ccaf55d2396e89d7c0debef466a1bcac6 +size 2183548 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_gcc_release.a index 9b1a9f9e8e..ab1a0f4c62 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:af94142ed49bf49f407fe229e4162f8b95e05c5cf5d0a6f3f28e1d0878e7fb7e -size 1604502 +oid sha256:ead9ae752eb87d72c3b8aefa75662caef5a50baec44f9911a51a7ac427e46ab6 +size 1606008 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_iar_release.a index 51b002ecc9..742e4baf40 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:66dcee571b2bfdda15a35004ffbdc83d6d6bc81f2f90abfd58d7dc215d97beef -size 2319478 +oid sha256:bdb5ad5721fdd4b33d051919c476f2f82f49a7b4d0cf695c6a243e6af7f5fec2 +size 2323764 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_gcc_release.a index 1e36168b09..02236ac89c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5a8a4cfc56456bc186f38fc530ba40572dbf067ba587de19c34029508cfcc3de -size 1536576 +oid sha256:888f017507cc677cd4a6114feefce148a3dc7f11389a40d041ee3c0df922a29f +size 1538436 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_iar_release.a index 520339026d..07b6477462 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_efr32xg29_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:67966abad1b3797387a35abd209888d52778e39cb4c44c9fc7c4faf25809631b -size 2180684 +oid sha256:1a3da5aacb4374f67267f3b559024fa25ab05aa90319cb719999534868933469 +size 2183436 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a index 72048bd09b..1230a86656 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ae7fd53c7401ed27bd890ea39a7e6d0648fc16680bcfbe739cd770f8d604d47b -size 1494876 +oid sha256:f7c096113b244e25a24607fff84fc30700292d95fafd0ffee3891901f621b4a2 +size 1496036 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a index ccf5e76201..cccdf8c39a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:09f01643ef47f9ff42f4e7f9f5751c08e74f3cfcc14874c9663912100c68c01a -size 2120688 +oid sha256:bff2baf9e3f8a6dd0c146b0b70e2835b013192fadf4ae9c528914549cdd7f0e6 +size 2124716 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a index 768867ac9e..d2746d37d6 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9dab1d5e06dbc4faa8d099abe1b5731091d7235013af5fd56a654b2e5d3c769a -size 1514302 +oid sha256:2c69505fb4895bf15d865e87b2fecab629320637230dadad57aa9dc5768180b2 +size 1516130 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a index af8ba1a6c1..444006dca5 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:68b43594bacf55644b2714681cd06713844967043632b71eccc9edefd4c252dd -size 2156414 +oid sha256:dac5a136fd5debfed57c9a2dccfacde5770c3c4f4211a2a8ca8f1a2c41c4b24a +size 2160530 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a index 90262e292f..dc898d25da 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b393a43634503d8b47dd1ea77fc18430a492a696f58192411232f000e2d94709 -size 1536318 +oid sha256:ca9f42d404ff9a54fd5dcf84725d9e80ba2fefb69d9aaf2ac78b5b30fc4edf2e +size 1538042 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a index 3cd375b342..c650191f03 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:09dcfef219d41b1e768ec0f46f4ca88cf4d6eab5a14c68d9a573a5c022d2ea99 -size 2214602 +oid sha256:17e268fee5d612d7a3b6954ccd012d3aa91b15b1db4473a3583007a03c49b22b +size 2220462 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a index 2287c6abeb..dfa20b41b3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd56948391431c2e99872b6229fac251729a74d55acb5adfcc906ab5d8062e89 -size 1583142 +oid sha256:7512b0052cdce240e0791c5edfdb82900f47dd3329a111aab73525cbcc9b3767 +size 1586594 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a index d4e9695aad..bb4971bd41 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ccc8555e7f1942ca3b4f5b3398927feb12addc330f46d728b3a7cb7fd405cb4a -size 2285670 +oid sha256:680cb7b29237f9dcd8374156a7b3b8da15634bdce90ddf2517b479cf55ab82e4 +size 2294882 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a index 7915bf900e..df6cfdcf30 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7c5c6ad2061706e27ab7946e117f9280f7a27cf737e4c568bfa1f340ff3c65e0 -size 1745350 +oid sha256:4b80e87f192ebffb372ef4830fba9db1093946a00485d70c81497663a82d7737 +size 1748922 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a index 86be410e24..936d4be604 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:48ff121ac831aa4a233faf0ff6e588ba5467e8505f3433f1239efbfd2b24ca75 -size 2439986 +oid sha256:15b1cda9d87691dc26eb46a057941b4be598630e2163798936b8a558340e94b2 +size 2446670 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_gcc_release.a index f69c426ab9..d714350bdc 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:75b6509a643baad0843ce58aa9dea98a0e7d938afb936465f64f6ee3e378f00c -size 1548030 +oid sha256:fd3770729658225ebd306678daa61dd1dc3b833c5debb4e60066a448e4621500 +size 1550528 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_iar_release.a index 53a4f25f74..164342ceae 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg26_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6f075e2870eaefb4a8c6bfc33d5a6e739d883652a6816864a233691681683ea8 -size 2205942 +oid sha256:4e694dd1b7da5195f6e0be627960880a7cf1ce2a2c7bc44ba79a88663a0bdc80 +size 2211764 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a index 5fc405cc3a..6139fafc3f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9831b8f7c06623e1f5fb8bde15f299f10b03ff360f4673b07a1ae6fcb33ee1e6 -size 1511926 +oid sha256:797185deab6180b48ff35db32727d1e5ab45dc63c567930ff7adbddebaf1960e +size 1513778 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a index 51067c4c72..748cab7fd9 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:126caf2ba0ec9b132167472fb4fc9848eae5f2068cb3a02df7bdb49fdc93cd3c -size 2151026 +oid sha256:f8caad8324ff64e830c1b750ce55eba1bb34e69621d6bb3bb2e2ad1d266964ae +size 2155186 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_gcc_release.a index 8fc4d8a18f..8aaadc2ccd 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:16df7f68465f677f6aa97af30c13b1626b2678e7c60cf45e5cbca041e2af7277 -size 1561794 +oid sha256:20f196262b974ba2661090b29359fa3452226ae966b6c37a9c285558ea2b8ccd +size 1563284 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_iar_release.a index ad81bf7909..f22d536c09 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6f81dfc50f4eadd923b57e506857ac107cc565f97111fc16ae0a2e76726c24b3 -size 2271710 +oid sha256:9ba38be4e00748f915b9c4e9fdc120aaad516dd3263850d04c95e7e54782118b +size 2277304 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_gcc_release.a index ef5729327c..e1cedc1e54 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eccf3e0525fcab0f3f3d30e9321bad6f9f900904f74510e2f1c4c59ceeb85174 -size 1511878 +oid sha256:32cf9682da4a97e47b9077d4402daec06c291eeeacfeb9ee6c510751a9ce2ea4 +size 1513730 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_iar_release.a index 9b0652607a..e6dbffc5fc 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg29_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cd77af077374ab214617558d756930d47e5b214d835b067c6305df3f19f27f60 -size 2150914 +oid sha256:e9ef2f7f91513e13827e4d1f1916df9f16e082a1d84e9260a9f38eb45b14d6f8 +size 2155074 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_gcc_release.a index 04cfbda563..0aa11cf4b9 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:42e1d8ba62a202a3a32df169c1d37c123a632e3717234095f6efedecb09f8227 -size 1573010 +oid sha256:9237466d5947d5ee53a575eccced35fa42ec330e6281285f22758e1606a2947d +size 1577212 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_iar_release.a index e9bd5c0a1b..e834437945 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_sixg301_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1bc717e31e60fa81cfe0fccc1458df46a3f9ad0a02ff0cdd33a2705007698ba0 -size 2251394 +oid sha256:586c16593d2e319082af676b819cbe09fdb1be1bfa87ac53cf38b04ae5c3821c +size 2257388 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_gcc_release.a index e876c1131b..6fec271fd2 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:45c540af11ce66082860add632018b65555582756374bec42cde1c4204662650 -size 1600056 +oid sha256:991679c1ed148cbdc3b738bf93f856106ea121e9125ac50b668bf85aaa024de8 +size 1604388 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_iar_release.a index af42258add..e8cd44691c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_sixg301_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:de31780be75ab522bff72c4bc09debad934181885e22446a41479a71dfac502d -size 2278532 +oid sha256:9a01f3a7be7dc3474dd2a9138a927f26b54050d34e26f088cf955b1062842097 +size 2283588 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_gcc_release.a index ca984ff29c..4a5d67eca2 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:af8c89dc6c925a1f4f96b525d7ade2727dfdc266e32be4b61ba99bc8cc0d847e -size 1565280 +oid sha256:548368b63acdc3cba21ab9e66414a4eb206d40ec8e0cb5d97ded8ced6cbe8b5a +size 1569572 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_iar_release.a index 0a9393a06e..6aa43add49 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_sixg301_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:787ee2adc43262676e92d1c74ebcae402781723fa2cb8305dcec517ce60994d4 -size 2113740 +oid sha256:0305c4375db2a4ac7fef0e435e3a601abf72f95eb2efe3d779e424b9ba92196c +size 2121764 diff --git a/platform/radio/rail_lib/autogen/ver_def.h b/platform/radio/rail_lib/autogen/ver_def.h index 8009671ce4..72666ebbcc 100644 --- a/platform/radio/rail_lib/autogen/ver_def.h +++ b/platform/radio/rail_lib/autogen/ver_def.h @@ -42,10 +42,10 @@ typedef struct // LOCAL_COMMITS_FLAG << 1 | DIRTY_FLAG) } FW_GIT_INFO_t; -#define GIT_INFO_SHORT_HASH (0x79ba4a1cUL) +#define GIT_INFO_SHORT_HASH (0x4d9cee3eUL) #define GIT_INFO_TAG_MAJOR (2) #define GIT_INFO_TAG_MINOR (18) -#define GIT_INFO_TAG_REV (0) +#define GIT_INFO_TAG_REV (1) #define GIT_INFO_TAG_BUILD (0) #define GIT_INFO_DETAILS (0x11) diff --git a/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h b/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h index b8c3d0d3b4..d1d83f4ccf 100644 --- a/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h +++ b/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h @@ -97,7 +97,7 @@ extern "C" { * @brief The EFR32xG25 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 624 +#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 632 /** * @def RAIL_EFR32XG26_STATE_BUFFER_BYTES diff --git a/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h b/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h index 7ad70b028e..8f99e3e2ce 100644 --- a/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h +++ b/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h @@ -271,11 +271,6 @@ struct RAIL_ChannelConfigEntryAttr { */ #if (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4GIG_HP or \ref RAIL_TX_POWER_MODE_2P4GIG_LP modes. - */ -#define RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MAX (95U) /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4GIG_HP or \ref RAIL_TX_POWER_MODE_2P4GIG_LP modes. @@ -284,11 +279,11 @@ struct RAIL_ChannelConfigEntryAttr { /** Legacy define for High Power (HP) and Low Power (LP) modes. */ #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MIN) /** Legacy define for High Power (HP) and Low Power (LP) modes. */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MAX) +#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (31U) /** Legacy define for High Power (HP) and Low Power (LP) modes. */ #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MIN) /** Legacy define for High Power (HP) and Low Power (LP) modes. */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MAX) +#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (95U) #else #error "RAIL_TX_POWER_LEVEL not defined for this device" #endif @@ -382,7 +377,7 @@ struct RAIL_ChannelConfigEntryAttr { * @note Transitions may need to be slower than this when using longer * \ref RAIL_TxPowerConfig_t::rampTime values */ -#define RAIL_MINIMUM_TRANSITION_US (100U) +#define RAIL_MINIMUM_TRANSITION_US (75U) /** * @def RAIL_MAXIMUM_TRANSITION_US diff --git a/platform/radio/rail_lib/common/rail.h b/platform/radio/rail_lib/common/rail.h index 4cb415c439..4c1bf9d513 100644 --- a/platform/radio/rail_lib/common/rail.h +++ b/platform/radio/rail_lib/common/rail.h @@ -849,6 +849,11 @@ RAIL_Status_t RAIL_GetSyncWords(RAIL_Handle_t railHandle, * This function will return \ref RAIL_STATUS_INVALID_STATE if called when BLE * has been enabled for this railHandle. When changing sync words in BLE mode, * use \ref RAIL_BLE_ConfigChannelRadioParams() instead. + * + * @note If multiple protocols share the same radio configuration, the user + * should not set custom sync words in any of those protocols as these + * sync words could leak into the other protocol sharing the same radio + * configuration. **/ RAIL_Status_t RAIL_ConfigSyncWords(RAIL_Handle_t railHandle, const RAIL_SyncWordConfig_t *syncWordConfig); @@ -2879,7 +2884,7 @@ RAIL_TxPowerLevel_t RAIL_GetTxPower(RAIL_Handle_t railHandle); * function was called, so it is okay to use either a real protocol handle, or one * of the radio-generic ones, such as \ref RAIL_EFR32_HANDLE. * - * Although the definitions of this function may change, the signature + * Although the implementation of this function may change, the signature * must be as declared here. */ RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, @@ -2907,13 +2912,43 @@ RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, * function was called, so it is okay to use either a real protocol handle, or one * of the radio-generic ones, such as \ref RAIL_EFR32_HANDLE. * - * Although the definitions of this function may change, the signature + * Although the implementation of this function may change, the signature * must be as declared here. */ RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, RAIL_TxPower_t power); +/** + * Converts the desired decibel value (in units of deci-dBm) + * to a \ref RAIL_TxPowerSettingEntry_t. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mode PA mode for which the conversion is to be done. + * @param[in] power Desired dBm value in units of deci-dBm. + * @param[out] pPowerSettingInfo A non-NULL pointer to the + * \ref RAIL_TxPowerSettingEntry_t structure to be filled in with the + * converted value. + * @return Status code indicating success of function call. + * + * A weak version of this function is provided that is tuned + * to provide accurate values for our boards. For a + * custom board, the relationship between what is written to the TX amplifier + * and the actual output power should be characterized and implemented in an + * overriding version of \ref RAIL_ConvertDbmToPowerSettingEntry(). + * In the weak version provided with the RAIL + * library, railHandle is only used to indicate to the user from where the + * function was called, so it is okay to use either a real protocol handle, or one + * of the radio-generic ones, such as \ref RAIL_EFR32_HANDLE. + * + * Although the implementation of this function may change, the signature + * must be as declared here. + */ +RAIL_Status_t RAIL_ConvertDbmToPowerSettingEntry(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPower_t power, + RAIL_TxPowerSettingEntry_t *pPowerSettingInfo); + struct RAIL_TxPowerCurvesConfigAlt; /// Verify the TX Power Curves on modules. /// @@ -5277,6 +5312,10 @@ RAIL_Status_t RAIL_CalibrateIrAlt(RAIL_Handle_t railHandle, * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is * not active. In that case, the calibration will be automatically performed * next time the radio enters receive. + * + * @note If RX channel hopping is enabled this function may trigger a + * channel hop, which can result in \ref + * RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE occuring before it returns. */ RAIL_Status_t RAIL_CalibrateTemp(RAIL_Handle_t railHandle); @@ -5601,6 +5640,21 @@ RAIL_Status_t RAIL_EnableRxChannelHopping(RAIL_Handle_t railHandle, bool enable, bool reset); +/** + * Manually trigger an Rx channel hop. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. + * + * This function facilitates a manual hop when using \ref + * RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL. (It will also trigger a hop + * in other automatic hop modes as well, so use with caution.) + * + * @note This function may cause \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE + * to occur before it returns. + */ +RAIL_Status_t RAIL_TriggerRxChannelHop(RAIL_Handle_t railHandle); + /** * Get RSSI in deci-dBm of one channel in the channel hopping sequence, during * channel hopping. diff --git a/platform/radio/rail_lib/common/rail_assert_error_codes.h b/platform/radio/rail_lib/common/rail_assert_error_codes.h index 6ed1948849..7bc0ad8651 100644 --- a/platform/radio/rail_lib/common/rail_assert_error_codes.h +++ b/platform/radio/rail_lib/common/rail_assert_error_codes.h @@ -350,7 +350,7 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) /* 7*/ "Reached unexpected state while handling RXLEN FIFO events", \ /* 8*/ "Reached unexpected state while handling TX FIFO events", \ /* 9*/ "Reached unexpected state while handling TX ACK FIFO events", \ - /*10*/ "Invalid assert, no longer used", \ + /*10*/ "Invalid memory region accessed", \ /*11*/ "Invalid assert, no longer used", \ /*12*/ "Invalid assert, no longer used", \ /*13*/ "Error synchronizing the RAIL timebase after sleep", \ diff --git a/platform/radio/rail_lib/common/rail_types.h b/platform/radio/rail_lib/common/rail_types.h index d11fba6cf7..1a0fbe2c24 100644 --- a/platform/radio/rail_lib/common/rail_types.h +++ b/platform/radio/rail_lib/common/rail_types.h @@ -1191,11 +1191,6 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * through the channels again. If this event is left on indefinitely and not * handled it will likely be a fairly noisy event, as it continues to fire * each time the hopping algorithm cycles through the channel sequence. - * - * @warning This event currently does not occur when using \ref - * RAIL_RxChannelHoppingMode_t::RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL. - * As a workaround, an application can monitor the current hop channel - * with \ref RAIL_GetChannelAlt(). */ #define RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE (1ULL << RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT) @@ -1768,6 +1763,22 @@ typedef uint32_t RAIL_PaPowerSetting_t; */ #define RAIL_TX_PA_POWER_SETTING_UNSUPPORTED (0U) +/** + * @struct RAIL_TxPowerSettingEntry_t + * + * @brief A structure containing power-setting information for a deci-dBm power. + */ +typedef struct RAIL_TxPowerSettingEntry { + /** PowerSetting information corresponds to currentPaPowerDdbm*/ + RAIL_PaPowerSetting_t paPowerSetting; + /** Minimum power (in deci-dBm) supported by powersetting table in use */ + RAIL_TxPower_t minPaPowerDdbm; + /** Maximum power (in deci-dBm) supported by powersetting table in use */ + RAIL_TxPower_t maxPaPowerDdbm; + /** Current power (in deci-dBm) */ + RAIL_TxPower_t currentPaPowerDdbm; +} RAIL_TxPowerSettingEntry_t; + /** * @enum RAIL_TxPowerMode_t * @brief An enumeration of the EFR32 power modes. @@ -4911,13 +4922,7 @@ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) { * Switch to the next channel each time the radio re-enters RX after * packet reception or a transmit based on the corresponding \ref * State_Transitions. A hop can also be manually triggered by calling - * \ref RAIL_CalibrateTemp() while the radio is listening. - * - * @warning This mode currently does not issue \ref - * RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE when hopping out of - * the last channel in the hop sequence. - * As a workaround, an application can monitor the current hop channel - * with \ref RAIL_GetChannelAlt(). + * \ref RAIL_TriggerRxChannelHop() while the radio is listening. */ RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL = 0, /** @@ -5121,7 +5126,7 @@ RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) { RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL_SHIFT = 1, /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD bit. */ RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT = 2, - /** Stop hopping on this hop. */ + /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_STOP bit. */ RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT = 3, /** A count of the choices in this enumeration. Must be last. */ RAIL_RX_CHANNEL_HOPPING_OPTIONS_COUNT @@ -5159,7 +5164,8 @@ RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) { #define RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT) /** * An option to stop the hopping sequence at this entry in the hop - * table. + * table, which also idles the radio. Intended only for testing + * purposes and not supported on EFR32xG21. */ #define RAIL_RX_CHANNEL_HOPPING_OPTION_STOP (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT) diff --git a/platform/radio/rail_lib/component/rail_lib_config_module.slcc b/platform/radio/rail_lib/component/rail_lib_config_module.slcc index a93f8890cf..1a5713d0e8 100644 --- a/platform/radio/rail_lib/component/rail_lib_config_module.slcc +++ b/platform/radio/rail_lib/component/rail_lib_config_module.slcc @@ -288,6 +288,26 @@ library: condition: - toolchain_iar - mgm260pb32vnn + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_iar.a + condition: + - toolchain_iar + - mgm260pd22vna + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_iar.a + condition: + - toolchain_iar + - mgm260pd32vna + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_iar.a + condition: + - toolchain_iar + - mgm260pd32vnn + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_iar.a + condition: + - toolchain_iar + - bgm260pb22vna + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_iar.a + condition: + - toolchain_iar + - bgm260pb32vna - path: platform/radio/rail_lib/autogen/librail_release/librail_config_bgm210l022jif_gcc.a condition: @@ -561,3 +581,23 @@ library: condition: - toolchain_gcc - mgm260pb32vnn + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd22vna_gcc.a + condition: + - toolchain_gcc + - mgm260pd22vna + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vna_gcc.a + condition: + - toolchain_gcc + - mgm260pd32vna + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_mgm260pd32vnn_gcc.a + condition: + - toolchain_gcc + - mgm260pd32vnn + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb22vna_gcc.a + condition: + - toolchain_gcc + - bgm260pb22vna + - path: platform/radio/rail_lib/autogen/librail_release/librail_config_bgm260pb32vna_gcc.a + condition: + - toolchain_gcc + - bgm260pb32vna diff --git a/platform/radio/rail_lib/plugin/component/rail_util_load_devinfo.slcc b/platform/radio/rail_lib/plugin/component/rail_util_load_devinfo.slcc index b92a92cf08..7b58d1ac38 100644 --- a/platform/radio/rail_lib/plugin/component/rail_util_load_devinfo.slcc +++ b/platform/radio/rail_lib/plugin/component/rail_util_load_devinfo.slcc @@ -14,11 +14,11 @@ requires: provides: - name: rail_util_load_devinfo include: - - path: platform/radio/rail_lib/plugin/rail_utiL_load_devinfo + - path: platform/radio/rail_lib/plugin/rail_util_load_devinfo file_list: - path: sl_rail_util_load_devinfo.h source: - - path: platform/radio/rail_lib/plugin/rail_utiL_load_devinfo/sl_rail_util_load_devinfo.c + - path: platform/radio/rail_lib/plugin/rail_util_load_devinfo/sl_rail_util_load_devinfo.c template_contribution: - name: event_handler value: diff --git a/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c b/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c index 0491fb0aab..a942b41c8c 100644 --- a/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c +++ b/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c @@ -302,25 +302,16 @@ const RAIL_PaPowerSetting_t *RAIL_GetPowerSettingTable(RAIL_Handle_t railHandle, #ifdef RAIL_PA_CONVERSIONS_WEAK __WEAK #endif -RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t mode, - RAIL_TxPower_t power) +RAIL_Status_t RAIL_ConvertDbmToPowerSettingEntry(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPower_t power, + RAIL_TxPowerSettingEntry_t *powerSettingInfo) { (void)railHandle; - // When a channel dBm limitation greater than or equal to \ref RAIL_TX_POWER_MAX - // is converted to raw units, the max RAIL_TxPowerLevel_t will be - // returned. When compared to the current power level of the PA, - // it will always be greater, indicating that no power coercion - // is necessary to comply with channel limitations. - if (power >= RAIL_TX_POWER_MAX) { - return 255U; - } - +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE if ((mode < sizeof(supportedPaIndices)) && (supportedPaIndices[mode] < RAIL_NUM_PA)) { RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; - uint32_t minPowerLevel = MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { RAIL_TxPower_t minPower = modeInfo->minPowerDbm; RAIL_TxPower_t maxPower = modeInfo->maxPowerDbm; @@ -335,19 +326,67 @@ RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, // Power level is within bounds (MISRA required else) } - uint32_t powerIndex = (power - minPower) / step; - RAIL_SetPaPowerSetting(railHandle, modeInfo->conversion.mappingTable[powerIndex], minPower, maxPower, power); -#ifdef _SILICON_LABS_32B_SERIES_3 - // Hack until librail is switched over to enforcing power limits in dBm - // This should work on rainier as rainier power table is only based on RAC_TX_PAPOWERSCALOR register, - // so the table value is guaranteed to be monotonic. - // As sol using a combination of more than a register field, the resulting power table is not guaranteed to be monotonic - return (RAIL_TxPowerLevel_t)(modeInfo->conversion.mappingTable[powerIndex]); -#else - return 0U; -#endif + // Calculate indices + uint32_t maxIndex = (uint32_t)((maxPower - minPower) / step); + uint32_t powerIndex = (uint32_t)((power - minPower) / step); + + // Ensure powerIndex is within bounds + if (powerIndex > maxIndex) { + powerIndex = maxIndex; + } + + RAIL_PaPowerSetting_t powerSetting = modeInfo->conversion.mappingTable[powerIndex]; + + while ((powerIndex > 0U) + && (powerSetting == (RAIL_PaPowerSetting_t)modeInfo->conversion.mappingTable[powerIndex - 1U])) { + powerIndex--; + } + power = minPower + ((RAIL_TxPower_t)powerIndex * step); + + powerSettingInfo->paPowerSetting = powerSetting; + powerSettingInfo->minPaPowerDdbm = minPower; + powerSettingInfo->maxPaPowerDdbm = maxPower; + powerSettingInfo->currentPaPowerDdbm = power; + return RAIL_STATUS_NO_ERROR; } + } + return RAIL_STATUS_INVALID_CALL; +#else + (void) mode; + (void) power; + (void) powerSettingInfo; + return RAIL_STATUS_INVALID_CALL; +#endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE +} + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK #endif +RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPower_t power) +{ + (void)railHandle; +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE + // Powersetting tables do not have raw powerlevels. + // Could use RAIL_ConvertDbmToPowerSettingEntry + (void)mode; + (void) power; +#else + + // When a channel dBm limitation greater than or equal to \ref RAIL_TX_POWER_MAX + // is converted to raw units, the max RAIL_TxPowerLevel_t will be + // returned. When compared to the current power level of the PA, + // it will always be greater, indicating that no power coercion + // is necessary to comply with channel limitations. + if (power >= RAIL_TX_POWER_MAX) { + return 255U; + } + + if ((mode < sizeof(supportedPaIndices)) + && (supportedPaIndices[mode] < RAIL_NUM_PA)) { + RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; + uint32_t minPowerLevel = MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); // If we're in low power mode, just use the simple lookup table if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) { @@ -450,6 +489,7 @@ RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, return (RAIL_TxPowerLevel_t)powerLevel; } +#endif // RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE return 0U; } diff --git a/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h b/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h index f87333ca78..b663012bcc 100644 --- a/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h +++ b/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h @@ -38,61 +38,93 @@ extern "C" { #endif -#define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_NUM_VALUES (21U) +#define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_NUM_VALUES (45U) #define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_STEP_DDBM (10U) -#define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_MAX_POWER_DDBM (100U) -#define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_MIN_POWER_DDBM (-100) +#define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_MAX_POWER_DDBM (120U) +#define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_MIN_POWER_DDBM (-320) #define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_CURVES \ { \ - 0x4001 /* -10.0 dBm */, \ - 0x4004 /* -9.0 dBm */, \ - 0x400a /* -8.0 dBm */, \ - 0x400e /* -7.0 dBm */, \ - 0x4013 /* -6.0 dBm */, \ - 0x4017 /* -5.0 dBm */, \ - 0x401c /* -4.0 dBm */, \ - 0x4021 /* -3.0 dBm */, \ - 0x4027 /* -2.0 dBm */, \ - 0x402a /* -1.0 dBm */, \ - 0x402f /* 0.0 dBm */, \ - 0x4035 /* 1.0 dBm */, \ - 0x4039 /* 2.0 dBm */, \ - 0x403d /* 3.0 dBm */, \ - 0x4042 /* 4.0 dBm */, \ - 0x4047 /* 5.0 dBm */, \ - 0x404c /* 6.0 dBm */, \ - 0x4050 /* 7.0 dBm */, \ - 0x4055 /* 8.0 dBm */, \ - 0x405a /* 9.0 dBm */, \ - 0x405f /* 10.0 dBm */ \ + 0x0 /* -32.0 dBm */, \ + 0x0 /* -31.0 dBm */, \ + 0x0 /* -30.0 dBm */, \ + 0x0 /* -29.0 dBm */, \ + 0x0 /* -28.0 dBm */, \ + 0x0 /* -27.0 dBm */, \ + 0x0 /* -26.0 dBm */, \ + 0x0 /* -25.0 dBm */, \ + 0x0 /* -24.0 dBm */, \ + 0x0 /* -23.0 dBm */, \ + 0x0 /* -22.0 dBm */, \ + 0x0 /* -21.0 dBm */, \ + 0x0 /* -20.0 dBm */, \ + 0x0 /* -19.0 dBm */, \ + 0x0 /* -18.0 dBm */, \ + 0x0 /* -17.0 dBm */, \ + 0x0 /* -16.0 dBm */, \ + 0x0 /* -15.0 dBm */, \ + 0x1 /* -14.0 dBm */, \ + 0x1 /* -13.0 dBm */, \ + 0x1 /* -12.0 dBm */, \ + 0x1 /* -11.0 dBm */, \ + 0x1 /* -10.0 dBm */, \ + 0x1 /* -9.0 dBm */, \ + 0x2 /* -8.0 dBm */, \ + 0x2 /* -7.0 dBm */, \ + 0x2 /* -6.0 dBm */, \ + 0x3 /* -5.0 dBm */, \ + 0x3 /* -4.0 dBm */, \ + 0x3 /* -3.0 dBm */, \ + 0x4 /* -2.0 dBm */, \ + 0x5 /* -1.0 dBm */, \ + 0x5 /* 0.0 dBm */, \ + 0x6 /* 1.0 dBm */, \ + 0x7 /* 2.0 dBm */, \ + 0x8 /* 3.0 dBm */, \ + 0x9 /* 4.0 dBm */, \ + 0xb /* 5.0 dBm */, \ + 0xd /* 6.0 dBm */, \ + 0x10 /* 7.0 dBm */, \ + 0x13 /* 8.0 dBm */, \ + 0x19 /* 9.0 dBm */, \ + 0x22 /* 10.0 dBm */, \ + 0x37 /* 11.0 dBm */, \ + 0x5f /* 12.0 dBm */ \ } -#define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_NUM_VALUES (20U) +#define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_NUM_VALUES (28U) #define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_STEP_DDBM (10U) -#define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_MAX_POWER_DDBM (0U) -#define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_MIN_POWER_DDBM (-190) +#define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_MAX_POWER_DDBM (20U) +#define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_MIN_POWER_DDBM (-250) #define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_CURVES \ { \ - 0x9 /* -19.0 dBm */, \ - 0xa /* -18.0 dBm */, \ - 0xd /* -17.0 dBm */, \ - 0x10 /* -16.0 dBm */, \ - 0x13 /* -15.0 dBm */, \ - 0x19 /* -14.0 dBm */, \ - 0x1f /* -13.0 dBm */, \ - 0x25 /* -12.0 dBm */, \ - 0x2b /* -11.0 dBm */, \ - 0x34 /* -10.0 dBm */, \ - 0x3c /* -9.0 dBm */, \ - 0x43 /* -8.0 dBm */, \ - 0x4a /* -7.0 dBm */, \ - 0x50 /* -6.0 dBm */, \ - 0x54 /* -5.0 dBm */, \ - 0x57 /* -4.0 dBm */, \ - 0x5a /* -3.0 dBm */, \ - 0x5d /* -2.0 dBm */, \ - 0x5e /* -1.0 dBm */, \ - 0x5f /* 0.0 dBm */ \ + 0x4000 /* -25.0 dBm */, \ + 0x4000 /* -24.0 dBm */, \ + 0x4000 /* -23.0 dBm */, \ + 0x4000 /* -22.0 dBm */, \ + 0x4000 /* -21.0 dBm */, \ + 0x4001 /* -20.0 dBm */, \ + 0x4001 /* -19.0 dBm */, \ + 0x4001 /* -18.0 dBm */, \ + 0x4001 /* -17.0 dBm */, \ + 0x4001 /* -16.0 dBm */, \ + 0x4002 /* -15.0 dBm */, \ + 0x4002 /* -14.0 dBm */, \ + 0x4002 /* -13.0 dBm */, \ + 0x4003 /* -12.0 dBm */, \ + 0x4003 /* -11.0 dBm */, \ + 0x4003 /* -10.0 dBm */, \ + 0x4004 /* -9.0 dBm */, \ + 0x4005 /* -8.0 dBm */, \ + 0x4005 /* -7.0 dBm */, \ + 0x4006 /* -6.0 dBm */, \ + 0x4007 /* -5.0 dBm */, \ + 0x4009 /* -4.0 dBm */, \ + 0x400b /* -3.0 dBm */, \ + 0x400d /* -2.0 dBm */, \ + 0x4010 /* -1.0 dBm */, \ + 0x4014 /* 0.0 dBm */, \ + 0x401b /* 1.0 dBm */, \ + 0x401f /* 2.0 dBm */ \ } #endif diff --git a/platform/radio/rail_lib/plugin/rail_utiL_load_devinfo/sl_rail_util_load_devinfo.c b/platform/radio/rail_lib/plugin/rail_util_load_devinfo/sl_rail_util_load_devinfo.c similarity index 98% rename from platform/radio/rail_lib/plugin/rail_utiL_load_devinfo/sl_rail_util_load_devinfo.c rename to platform/radio/rail_lib/plugin/rail_util_load_devinfo/sl_rail_util_load_devinfo.c index 3d4ebefa66..e63d574de8 100644 --- a/platform/radio/rail_lib/plugin/rail_utiL_load_devinfo/sl_rail_util_load_devinfo.c +++ b/platform/radio/rail_lib/plugin/rail_util_load_devinfo/sl_rail_util_load_devinfo.c @@ -29,6 +29,7 @@ ******************************************************************************/ #include "sl_rail_util_load_devinfo.h" +#include "rail.h" void sl_rail_util_load_devinfo(void) { diff --git a/platform/radio/rail_lib/plugin/rail_utiL_load_devinfo/sl_rail_util_load_devinfo.h b/platform/radio/rail_lib/plugin/rail_util_load_devinfo/sl_rail_util_load_devinfo.h similarity index 98% rename from platform/radio/rail_lib/plugin/rail_utiL_load_devinfo/sl_rail_util_load_devinfo.h rename to platform/radio/rail_lib/plugin/rail_util_load_devinfo/sl_rail_util_load_devinfo.h index d36dd81dbb..40d9c6bb76 100644 --- a/platform/radio/rail_lib/plugin/rail_utiL_load_devinfo/sl_rail_util_load_devinfo.h +++ b/platform/radio/rail_lib/plugin/rail_util_load_devinfo/sl_rail_util_load_devinfo.h @@ -31,8 +31,6 @@ #ifndef SL_RAIL_UTIL_LOAD_DEVINFO_H #define SL_RAIL_UTIL_LOAD_DEVINFO_H -#include "rail.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/platform/radio/rail_lib/tools/pa_dbm_mapping_table_generator.py b/platform/radio/rail_lib/tools/pa_dbm_mapping_table_generator.py index 25ff66dd64..5d6f099217 100644 --- a/platform/radio/rail_lib/tools/pa_dbm_mapping_table_generator.py +++ b/platform/radio/rail_lib/tools/pa_dbm_mapping_table_generator.py @@ -243,7 +243,7 @@ def GenerateDbmToPowerSettingTableCommonInterface( """ ramplev = GetCommonInterfaceData(File) submode = 0 - if variant == "10dbm": + if variant != "10dbm": submode = 1 assert ramplev.__len__() == (abs(maxpwr - minpwr) / increment) + 1, \ "Expected number of power levels {} does not match actual number of power levels {}".format( diff --git a/platform/security/component/psa_crypto.slcc b/platform/security/component/psa_crypto.slcc index 49355e64d7..0a9700393a 100644 --- a/platform/security/component/psa_crypto.slcc +++ b/platform/security/component/psa_crypto.slcc @@ -105,7 +105,7 @@ template_contribution: handler: psa_crypto_init priority: 1 condition: [trustzone_unaware, psa_crypto_trng] - unless: [zigbee_classic_key_storage, native, device_si91x] + unless: [native, device_si91x] - name: event_handler value: event: service_init @@ -113,7 +113,7 @@ template_contribution: handler: psa_crypto_init priority: 1 condition: [trustzone_unaware, mbedtls_entropy_nvseed] - unless: [rail_lib, zigbee_classic_key_storage, native] + unless: [rail_lib, native] - name: mbedtls_config value: MBEDTLS_PSA_CRYPTO_C @@ -124,9 +124,6 @@ template_contribution: - name: mbedtls_config value: MBEDTLS_CIPHER_C - - name: mbedtls_config - value: MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS - - name: psa_key_slots value: name: psa_key_slots_minimum diff --git a/platform/security/component/sli_crypto.slcc b/platform/security/component/sli_crypto.slcc index 0d30d62a90..ae3d0a8a96 100644 --- a/platform/security/component/sli_crypto.slcc +++ b/platform/security/component/sli_crypto.slcc @@ -11,10 +11,20 @@ provides: - name: sli_crypto requires: - name: device + - name: code_classification - name: sli_crypto_s2 condition: [device_series_2] - name: sli_crypto_s3 condition: [device_series_3] + +define: + - name: SL_CODE_COMPONENT_SLI_CRYPTO + value: sli_crypto + +template_contribution: + - name: code_classification_components + value: sli_crypto + metadata: sbom: license: Zlib diff --git a/platform/security/component/sli_protocol_crypto.slcc b/platform/security/component/sli_protocol_crypto.slcc index a026b22965..747f0e9512 100644 --- a/platform/security/component/sli_protocol_crypto.slcc +++ b/platform/security/component/sli_protocol_crypto.slcc @@ -24,6 +24,7 @@ provides: requires: - name: device - name: status + - name: code_classification - name: emlib_core - name: sli_psec_osal condition: [device_has_radioaes] @@ -34,8 +35,13 @@ conflicts: define: - name: SLI_RADIOAES_REQUIRES_MASKING condition: [device_has_radioaes] -# Add a component catalog entry to allow build-time detection of protocol crypto presence + - name: SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO + value: sli_protocol_crypto + template_contribution: + - name: code_classification_components + value: sli_protocol_crypto +# Add a component catalog entry to allow build-time detection of protocol crypto presence - name: component_catalog value: sli_protocol_crypto - name: event_handler @@ -54,6 +60,7 @@ template_contribution: # PSA crypto core. priority: 2 condition: [device_has_radioaes] + metadata: sbom: license: Zlib diff --git a/platform/security/component/sli_psec_osal.slcc b/platform/security/component/sli_psec_osal.slcc index eba429451c..9949d9d45e 100644 --- a/platform/security/component/sli_psec_osal.slcc +++ b/platform/security/component/sli_psec_osal.slcc @@ -34,7 +34,7 @@ provides: define: - name: SL_CODE_COMPONENT_PSEC_OSAL - value: psec_osal + value: psec_osal template_contribution: - name: code_classification_components diff --git a/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h b/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h index 27e75008fd..eb380eda39 100644 --- a/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h +++ b/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h @@ -1213,7 +1213,7 @@ sl_status_t sl_se_hmac_multipart_update(sl_se_command_context_t *cmd_ctx, * @param[in] state_in * Pointer to memory buffer containing the HMAC state. * - * @param[in] state_in_out_len + * @param[in] state_in_len * The length of the HMAC state buffer, must be at least the size * of the corresponding hash type + 8 bytes. * diff --git a/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h b/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h index 8489bdb947..3e3ef2d475 100644 --- a/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h +++ b/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h @@ -219,6 +219,11 @@ extern "C" { /// in the SE. See documentation for a list of available keys. #define SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE 0x03 +#if defined(_SILICON_LABS_32B_SERIES_3) +/// Key is stored in the KSURAM, an internal Key Slot RAM. + #define SL_SE_KEY_STORAGE_INTERNAL_KSU 0x04 +#endif + /// List of available internal SE key slots #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) #define SL_SE_KEY_SLOT_VOLATILE_0 0x00 ///< Internal volatile slot 0 @@ -459,18 +464,28 @@ extern "C" { #define SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP (1UL << 2) /// Tamper is kept alive during sleep (down to EM3) /// @} (end addtogroup sl_se_manager_util_tamper) - /// @} (end addtogroup sl_se_manager_util) -/// @addtogroup sl_se_manager_cipher -/// @{ +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/// Initial values for CMAC streaming context struct @ref sl_se_cmac_streaming_context_t +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2025_6 +/// Initial values for CMAC streaming context struct @ref sl_se_cmac_multipart_context_t #define SL_SE_CMAC_STREAMING_INIT_DEFAULT { NULL, { 0 }, { 0 }, 0 } -/// Initial values for AES-GCM streaming context struct @ref sl_se_gcm_streaming_context_t +/// Initial values for AES-GCM streaming context struct @ref sl_se_gcm_multipart_context_t #define SL_SE_GCM_STREAMING_INIT_DEFAULT { NULL, 0, 0, { 0 }, { 0 }, \ { 0 }, 0, 0 } +#else +#define SL_SE_GCM_STREAMING_INIT_DEFAULT _Pragma("GCC warning \"'SL_SE_GCM_STREAMING_INIT_DEFAULT' macro is deprecated as of Simplicity SDK release 2024.12\""){ NULL, 0, 0, { 0 }, { 0 }, \ + { 0 }, 0, 0 } + +#define SL_SE_CMAC_STREAMING_INIT_DEFAULT _Pragma("GCC warning \"'SL_SE_CMAC_STREAMING_INIT_DEFAULT' macro is deprecated as of Simplicity SDK release 2024.12\"") { NULL, { 0 }, { 0 }, 0 } + +#endif +/// @endcond + +/// @addtogroup sl_se_manager_cipher +/// @{ /// Block size for the AES #define SL_SE_AES_BLOCK_SIZE (16u) diff --git a/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h b/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h index ad7ad318ce..0b0f0efbb5 100644 --- a/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h +++ b/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h @@ -212,8 +212,9 @@ typedef uint32_t sl_se_key_type_t; /// Key storage method. Can have one of @ref SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, /// @ref SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, -/// @ref SL_SE_KEY_STORAGE_INTERNAL_VOLATILE or -/// @ref SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE. +/// @ref SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, +/// @ref SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE or +/// @ref SL_SE_KEY_STORAGE_INTERNAL_KSU. typedef uint32_t sl_se_storage_method_t; /// Internal SE key slot @@ -225,6 +226,16 @@ typedef struct { uint32_t size; ///< Size of buffer. } sl_se_buffer_t; +/// KSU Metadata +#if defined(_SILICON_LABS_32B_SERIES_3) +typedef struct { + uint8_t keyslot; ///< Keyslot to store key at in KSU + uint8_t id; ///< KSU instance to store key + uint8_t crypto_engine_id; ///< Which Crypto Engine to use this key + uint8_t allowed_key_users; ///< Allowed key users +} sl_se_ksu_metadata_t; +#endif + /// Describes the storage location of keys typedef struct { /// Key storage method. Sets meaning of data in location. @@ -234,9 +245,13 @@ typedef struct { /// @ref SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, while @ref sl_se_key_slot_t is /// used for @ref SL_SE_KEY_STORAGE_INTERNAL_VOLATILE or /// @ref SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE. + /// @ref ksu is used for @ref SL_SE_KEY_STORAGE_INTERNAL_KSU union { sl_se_buffer_t buffer; sl_se_key_slot_t slot; +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_se_ksu_metadata_t ksu; +#endif } location; } sl_se_key_storage_t; @@ -318,7 +333,9 @@ typedef struct { uint32_t tamper_status_raw; #if defined(_SILICON_LABS_32B_SERIES_3) uint8_t rom_revision; + /// ROM revision uint8_t otp_patch_sequence; + /// OTP patch sequence #endif } sl_se_status_t; @@ -484,71 +501,6 @@ typedef sl_se_hash_type_t sl_se_pbkdf2_prf_type_t; /// @} (end addtogroup sl_se_manager_key_derivation) -#if defined(_SILICON_LABS_32B_SERIES_3) - -/// @addtogroup sl_se_manager_extmem -/// @{ - -/// SE Crypto algorithms (ciphers, AEADs, MACs, hashes, etc) used for -/// the code region write function. -typedef enum { - SL_SE_ALG_AES_CTR, ///< Counter mode AES cipher - SL_SE_ALG_SHA_256, ///< SHA2-256 -} sl_se_crypto_alg_t; - -typedef struct { - sl_se_cipher_operation_t mode; ///< encryption or decryption - sl_se_key_descriptor_t *key; ///< Key to be used for encryption or decryption - unsigned char *iv; ///< Initial Vector/Nonce - size_t iv_len; ///< Initial Vector/Nonce length - unsigned char *add; ///< Additional data - size_t add_len; ///< Additional data length - unsigned char *tag; ///< Tag - size_t tag_len; ///< Tag length -} sl_se_aead_info_t; - -typedef struct { - sl_se_cipher_operation_t mode; ///< encryption or decryption - sl_se_key_descriptor_t *key; ///< Key to be used for encryption or decryption -} sl_se_cipher_info_t; - -typedef struct { - unsigned char *digest; ///< Pointer to message digest buffer - size_t digest_size; ///< Size of message digest -} sl_se_hash_info_t; - -typedef union { - sl_se_aead_info_t aead; - sl_se_cipher_info_t cipher; - sl_se_hash_info_t hash; -} sl_se_crypto_alg_specific_info_t; - -/// Information associated with cryupto related operations -typedef struct { - sl_se_crypto_alg_t *alg; ///< SE Crypto algorithm - sl_se_crypto_alg_specific_info_t alg_specific_info; -} sl_se_crypto_operation_t; - -/// Security level of code region -typedef enum { - SL_SE_CODE_REGION_SECURITY_LEVEL_PLAINTEXT = 0, - SL_SE_CODE_REGION_SECURITY_LEVEL_ENC_ONLY, - SL_SE_CODE_REGION_SECURITY_LEVEL_ENC_AUTH, -} sl_se_code_region_security_level_t; - -/// Code region configuration -typedef struct { - unsigned int region_idx; ///< Index of code region - unsigned int region_size; ///< Size of code region - sl_se_code_region_security_level_t security_level; ///< Security level of region - bool bank_swapping_enabled; ///< Bank swapping enabled (if true) - bool locked; ///< Region is locked (if true) -} sl_code_region_config_t; - -/// @} (end addtogroup sl_se_manager_extmem) - -#endif // defined(_SILICON_LABS_32B_SERIES_3) - #endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) #ifdef __cplusplus diff --git a/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h b/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h index 0a47846bf7..36d3faa6fc 100644 --- a/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h +++ b/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h @@ -64,6 +64,23 @@ extern "C" { #endif +#if defined(_SILICON_LABS_32B_SERIES_3) +/// Lifecycle event flags keep track of certain events and state changes by setting a one-time +/// irreversible flag in the OTP. This enum contains information on what the separate event flags +/// indicate. The lifecycle state flags can be fetched using @ref sl_se_get_lifecycle_event_flags. The utility +/// @ref sl_se_lifecycle_event_flag_is_set can be used to check if any specific flag has been set. +typedef enum { + SL_SE_LIFECYCLE_EVENT_HOST_UNSECURE_UNLOCKED = 0, ///< Host has been unsecure-unlocked + SL_SE_LIFECYCLE_EVENT_HOST_SECURE_UNLOCKED = 1, ///< Host has been secure-unlocked + SL_SE_LIFECYCLE_EVENT_SE_SECURE_UNLOCKED = 2, ///< SE has been secure-unlocked + SL_SE_LIFECYCLE_EVENT_INITIAL_DEBUG_LOCK_SET = 3, ///< Initial debug lock token has been set in MTP + SL_SE_LIFECYCLE_EVENT_HOST_SECURE_DEBUG_ENABLED = 4, ///< Host secure debug has been enabled + SL_SE_LIFECYCLE_EVENT_HOST_SECURE_DEBUG_DISABLED = 5, ///< Host secure debug has been disabled + SL_SE_LIFECYCLE_EVENT_HOST_DEBUG_LOCKED = 6, ///< Host has been debug locked + SL_SE_LIFECYCLE_EVENT_AXIP_NONCE_ROLL_DISABLED = 7, ///< AXiP nonce rolling has been disabled +} sl_se_lifecycle_event_flag_t; +#endif // #if defined(_SILICON_LABS_32B_SERIES_3) + // ----------------------------------------------------------------------------- // Prototypes @@ -82,7 +99,7 @@ extern "C" { * Pointer to SE image to validate. * * @return - * One of the following sl_status_t codes: + * One of the following @ref status codes: * - @c SL_STATUS_OK when the command was executed successfully * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ @@ -531,6 +548,46 @@ sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, uint32_t *reset_cause); #endif // SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE +#if defined(_SILICON_LABS_32B_SERIES_3) +/***************************************************************************//** + * @brief + * Reads out traceable lifecycle event flags from the OTP. See + * \ref sl_se_lifecycle_event_flag_t for details on what the individual flag bits + * indicate. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] event_flags + * Pointer to an array of at least 8 bytes, to contain the trace flags + * + * @return + * SL_STATUS_OK upon successfull execution, error code elsewise + ******************************************************************************/ +sl_status_t sl_se_get_lifecycle_event_flags(sl_se_command_context_t *cmd_ctx, uint64_t *event_flags); + +/***************************************************************************//** + * @brief + * Utility for checking if a certain lifecycle event flag is set + * + * @param[in] flags + * Pointer to an 8 byte array of lifecycle event flags (event_flags from + * \ref sl_se_get_lifecycle_event_flags) + * + * @param[in] flag_index + * Which bit (event flag) to check if is set + * + * @return + * true if event flag bit was set + * false if event flag bit was not set + ******************************************************************************/ +__STATIC_INLINE bool sl_se_lifecycle_event_flag_is_set(uint64_t *flags, sl_se_lifecycle_event_flag_t flag_index) +{ + return (*flags & (1 << flag_index) ? true : false); +} + +#endif // #if defined(_SILICON_LABS_32B_SERIES_3) + /***************************************************************************//** * @brief * Enables the secure debug functionality. @@ -768,7 +825,7 @@ sl_status_t sl_se_read_cert_size(sl_se_command_context_t *cmd_ctx, * Length of certificate in number of bytes. * * @return - * Status code, @ref sl_status.h. + * Status code, @ref status ******************************************************************************/ sl_status_t sl_se_read_cert(sl_se_command_context_t *cmd_ctx, sl_se_cert_type_t cert_type, @@ -828,9 +885,9 @@ sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx); * Pointer to location where the rollback counter value will be returned. * * @return - * SL_STATUS_OK when the functions was successfully, or else, a status code + * SL_STATUS_OK when the function executed successfully, else, a status code * of type sl_status_t that indicates why the function was not successful, - * ref sl_status.h. + * @ref status ******************************************************************************/ sl_status_t sl_se_get_rollback_counter(sl_se_command_context_t *cmd_ctx, uint32_t *rollback_counter); @@ -842,12 +899,16 @@ sl_status_t sl_se_get_rollback_counter(sl_se_command_context_t *cmd_ctx, * @param[in] cmd_ctx * Pointer to an SE command context object. * + * @param[out] rollback_counter + * Optional: Retrieve the rollback counter count after increment + * Set to NULL to ignore * @return - * SL_STATUS_OK when the functions was successfully, or else, a status code + * SL_STATUS_OK when the function executed successfully, else, a status code * of type sl_status_t that indicates why the function was not successful, - * ref sl_status.h. + * @ref status ******************************************************************************/ -sl_status_t sl_se_increment_rollback_counter(sl_se_command_context_t *cmd_ctx); +sl_status_t sl_se_increment_rollback_counter(sl_se_command_context_t *cmd_ctx, + uint32_t *rollback_counter); /***************************************************************************//** * @brief @@ -859,9 +920,9 @@ sl_status_t sl_se_increment_rollback_counter(sl_se_command_context_t *cmd_ctx); * The stored upgrade file version. * * @return - * SL_STATUS_OK when the functions was successfully, or else, a status code + * SL_STATUS_OK when the function executed successfully, else, a status code * of type sl_status_t that indicates why the function was not successful, - * ref sl_status.h. + * @ref status ******************************************************************************/ sl_status_t sl_se_get_upgrade_file_version(sl_se_command_context_t *cmd_ctx, uint32_t *version); @@ -876,9 +937,9 @@ sl_status_t sl_se_get_upgrade_file_version(sl_se_command_context_t *cmd_ctx, * New upgrade file version * * @return - * SL_STATUS_OK when the functions was successfully, or else, a status code + * \ref SL_STATUS_OK when the function executed successfully, else, a status code * of type sl_status_t that indicates why the function was not successful, - * ref sl_status.h. + * @ref status ******************************************************************************/ sl_status_t sl_se_set_upgrade_file_version(sl_se_command_context_t *cmd_ctx, uint32_t version); diff --git a/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h b/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h index 3d1f8b2bee..c639407954 100644 --- a/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h +++ b/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h @@ -46,7 +46,6 @@ #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE #define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE - #else // DOXYGEN #if defined(__linux__) @@ -92,9 +91,10 @@ #define SLI_MAILBOX_COMMAND_SUPPORTED -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) \ - && (defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && _SILICON_LABS_32B_SERIES_2_CONFIG >= 3)) +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) \ + && ((defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && _SILICON_LABS_32B_SERIES_2_CONFIG >= 3) \ + || defined(_SILICON_LABS_32B_SERIES_3))) // Reading the latest cached tamper reset cause requires SE version 2.2.1 or above. #define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE // The option to keep the tamper alive during sleep is only configurable for SE with major version 2 diff --git a/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h b/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h index 3155e3f515..95de5572fb 100644 --- a/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h +++ b/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h @@ -166,6 +166,7 @@ extern "C" { #define SLI_SE_COMMAND_PROTECTED_REGISTER 0x43210000UL #if defined(_SILICON_LABS_32B_SERIES_3) #define SLI_SE_COMMAND_READ_DEVICE_DATA 0x43300000UL + #define SLI_SE_COMMAND_GET_ROLLBACK_COUNTER 0x43400000UL #endif #if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) // SLI_SE_COMMAND_STATUS_READ_RSTCAUSE is only available on xG21 devices (series-2-config-1) @@ -197,7 +198,9 @@ extern "C" { #define SLI_SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL #define SLI_SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL #define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE 0xFE050000UL - +#if defined(_SILICON_LABS_32B_SERIES_3) + #define SLI_SE_COMMAND_READ_TRACE_FLAGS 0xFE060000UL +#endif #define SLI_SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL #define SLI_SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL #define SLI_SE_COMMAND_INIT_AES_128_KEY 0xFF0B0001UL @@ -505,8 +508,55 @@ __STATIC_INLINE sli_se_mailbox_response_t sli_se_mailbox_read_response(void) // Return command response return (sli_se_mailbox_response_t)(SEMAILBOX_HOST->RX_HEADER & SLI_SE_RESPONSE_MASK); } + +/** + * \brief Handle the response of the previously executed command. + * + * \details This function handles the response of the previously + * executed HSE command by calling sli_se_mailbox_read_response + * to read the response value and returns it. For Series-3 this + * function also clears the SEMAILBOX FIFO by reading out the + * unused command handle word. + * This function is called by the ISR of the SEMAILBOX (called + * SEMBRX_IRQHandler ) to clear the SEMBRX_IRQn interrupt signal + * on the SEMAILBOX peripheral side. NOTE: The ISR will also + * need to clear the SEMBRX_IRQn condition in the internal/local + * interrupt controller (NVIC) by calling + * NVIC_ClearPendingIRQ(SEMBRX_IRQn). + * + * \return Value returned by sli_se_mailbox_read_response. + ******************************************************************************/ +__STATIC_INLINE sli_se_mailbox_response_t sli_se_mailbox_handle_response(void) +{ + // Read command response + sli_se_mailbox_response_t se_mailbox_response = sli_se_mailbox_read_response(); + + #if defined(_SILICON_LABS_32B_SERIES_3) + // Read the command handle word ( not used ) from the SEMAILBOX FIFO + SEMAILBOX_HOST->FIFO; + #endif + + // Return command response + return se_mailbox_response; +} + #elif defined(CRYPTOACC_PRESENT) sli_se_mailbox_response_t sli_se_mailbox_read_response(void); + +/** + * \brief Handle the response of the previously executed command. + * + * \details This function handles the response of the previously + * executed VSE command by calling sli_se_mailbox_read_response + * to read the response value and returns it. + * + * \return Value returned by sli_se_mailbox_read_response. + ******************************************************************************/ +__STATIC_INLINE sli_se_mailbox_response_t sli_se_mailbox_handle_response(void) +{ + // Read and return VSE mailbox command response + return sli_se_mailbox_read_response(); +} #endif // #if defined(SEMAILBOX_PRESENT) /***************************************************************************//** diff --git a/platform/security/sl_component/se_manager/src/sl_se_manager.c b/platform/security/sl_component/se_manager/src/sl_se_manager.c index 01756c6852..b4679aa028 100644 --- a/platform/security/sl_component/se_manager/src/sl_se_manager.c +++ b/platform/security/sl_component/se_manager/src/sl_se_manager.c @@ -328,8 +328,8 @@ void SEMBRX_IRQHandler(void) status = sli_psec_osal_complete(&se_command_completion); EFM_ASSERT(status == SL_STATUS_OK); } - // Get command response (clears interrupt condition in SEMAILBOX) - se_manager_command_response = sli_se_mailbox_read_response(); + // Get command response and clear interrupt condition in SEMAILBOX peripheral + se_manager_command_response = sli_se_mailbox_handle_response(); // Clear interrupt condition in NVIC NVIC_ClearPendingIRQ(SEMBRX_IRQn); } @@ -388,8 +388,7 @@ sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) // Execute SE mailbox command sli_se_mailbox_execute_command(&cmd_ctx->command); - #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \ - && !defined(_SILICON_LABS_32B_SERIES_3) + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) if (cmd_ctx->yield) { // Enable SEMAILBOX RXINT interrupt sli_se_mailbox_enable_interrupt(SEMAILBOX_CONFIGURATION_RXINTEN); @@ -416,30 +415,16 @@ sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) se_manager_command_response = SLI_SE_RESPONSE_INTERNAL_ERROR; } else { // Wait for command completion and get command response - command_response = sli_se_mailbox_read_response(); + command_response = sli_se_mailbox_handle_response(); } #else // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - #if defined(_SILICON_LABS_32B_SERIES_3) - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - #endif - // Wait for command completion and get command response - command_response = sli_se_mailbox_read_response(); - - #if defined(_SILICON_LABS_32B_SERIES_3) - CORE_EXIT_ATOMIC(); - #endif + command_response = sli_se_mailbox_handle_response(); #endif // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - #if (_SILICON_LABS_32B_SERIES == 3) - // Read the command handle word ( not used ) from the SEMAILBOX FIFO - SEMAILBOX_HOST->FIFO; - #endif // #if (_SILICON_LABS_32B_SERIES == 3) - // Release SE lock status = sli_se_lock_release(); diff --git a/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c b/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c index 2fc3ecca28..beab735d25 100644 --- a/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c +++ b/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c @@ -1584,7 +1584,11 @@ sl_status_t sl_se_hmac(sl_se_command_context_t *cmd_ctx, uint8_t *output, size_t output_len) { - if (cmd_ctx == NULL || key == NULL || message == NULL || output == NULL) { + if (cmd_ctx == NULL || key == NULL || output == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ( message == NULL && message_len != 0 ) { return SL_STATUS_INVALID_PARAMETER; } @@ -3055,26 +3059,31 @@ sl_status_t sl_se_hmac_multipart_finish(sl_se_command_context_t *cmd_ctx, case SL_SE_HASH_SHA1: command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA1; hmac_state_len = 20; + hmac_len = 20; break; case SL_SE_HASH_SHA224: command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA224; hmac_state_len = 32; + hmac_len = 28; break; case SL_SE_HASH_SHA256: command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA256; hmac_state_len = 32; + hmac_len = 32; break; case SL_SE_HASH_SHA384: command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA384; hmac_state_len = 64; + hmac_len = 48; break; case SL_SE_HASH_SHA512: command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA512; hmac_state_len = 64; + hmac_len = 64; break; default: @@ -3082,35 +3091,11 @@ sl_status_t sl_se_hmac_multipart_finish(sl_se_command_context_t *cmd_ctx, break; } hmac_state_len += 8u; // adding 8 bytes for storing the HMAC multipart internal states + if (state_in_len != hmac_state_len) { return SL_STATUS_INVALID_PARAMETER; } - switch (hash_type) { - case SL_SE_HASH_SHA1: - hmac_len = 20; - break; - - case SL_SE_HASH_SHA224: - hmac_len = 28; - break; - - case SL_SE_HASH_SHA256: - hmac_len = 32; - break; - - case SL_SE_HASH_SHA384: - hmac_len = 48; - break; - - case SL_SE_HASH_SHA512: - hmac_len = 64; - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - break; - } if (output_len < hmac_len) { return SL_STATUS_INVALID_PARAMETER; } diff --git a/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c b/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c index d9e7a556f5..8e35c93751 100644 --- a/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c +++ b/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c @@ -33,6 +33,7 @@ #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +#include "sl_se_manager_defines.h" #include "sli_se_manager_internal.h" #include "sl_se_manager_key_handling.h" @@ -54,7 +55,14 @@ #define KEYSPEC_MODE_OFFSET 26 #define KEYSPEC_MODE_UNPROTECTED (0UL << KEYSPEC_MODE_OFFSET) #define KEYSPEC_MODE_VOLATILE (1UL << KEYSPEC_MODE_OFFSET) +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define KEYSPEC_MODE_WRAPPED (2UL << KEYSPEC_MODE_OFFSET) +#endif +#if defined(_SILICON_LABS_32B_SERIES_3) + #define KEYSPEC_MODE_KSU (3UL << KEYSPEC_MODE_OFFSET) +#endif +// Key Mode Specific KEYSPEC fields #define KEYSPEC_RESTRICTION_MASK 0x03000000U #define KEYSPEC_RESTRICTION_OFFSET 24U @@ -63,16 +71,19 @@ #define KEYSPEC_INDEX_MASK 0x00ff0000U #define KEYSPEC_INDEX_OFFSET 16U -#define KEYSPEC_TRANSFER_MODE_MASK 0x00000300U -#define KEYSPEC_TRANSFER_MODE_OFFSET 8U -#define KEYSPEC_TRANSFER_INDEX_MASK 0x000000ffU -#define KEYSPEC_TRANSFER_INDEX_OFFSET 0U -#define KEYSPEC_TRANSFER_PROT_BIT_MASK 0xffe00000U -#define KEYSPEC_TRANSFER_PROT_BIT_OFFSET 21U - #define KEYSPEC_NOPROT_MASK 0x00008000U #define KEYSPEC_NOPROT_OFFSET 15U +// KSU KEYSPEC Fields +#define KEYSPEC_KSU_ID_MASK 0x03000000U +#define KEYSPEC_KSU_ID_OFFSET 24U + +#define KEYSPEC_KSU_KEYSLOT_MASK 0x00FC0000U +#define KEYSPEC_KSU_KEYSLOT_OFFSET 18U + +#define KEYSPEC_KSU_KEY_USAGE_MASK 0x00038000U +#define KEYSPEC_KSU_KEY_USAGE_OFFSET 15U + #define KEYSPEC_ATTRIBUTES_MASK 0x00007fffU #define KEYSPEC_ATTRIBUTES_OFFSET 0U @@ -82,15 +93,28 @@ #define KEYSPEC_ATTRIBUTES_ECC_SIGN (1U << 10) #define KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK 0x0000007fU +// Transfer KEYSPECS +#define KEYSPEC_TRANSFER_MODE_MASK 0x00000300U +#define KEYSPEC_TRANSFER_MODE_OFFSET 8U +#define KEYSPEC_TRANSFER_INDEX_MASK 0x000000ffU +#define KEYSPEC_TRANSFER_INDEX_OFFSET 0U +#define KEYSPEC_TRANSFER_PROT_BIT_MASK 0xffe00000U +#define KEYSPEC_TRANSFER_PROT_BIT_OFFSET 21U + +#if defined(_SILICON_LABS_32B_SERIES_3) +// Transfer KeySpecs for KSU Keys +#define KEYSPEC_TRANSFER_KSU_ID_MASK 0x00000C00U +#define KEYSPEC_TRANSFER_KSU_ID_OFFSET 10U +#define KEYSPEC_TRANSFER_KSU_KEY_USAGE_MASK 0x00007000U +#define KEYSPEC_TRANSFER_KSU_KEY_USAGE_OFFSET 12U +#endif + #define KEYSPEC_TYPE_ECC_EDWARDS ((uint32_t)(0xaUL << KEYSPEC_TYPE_OFFSET)) #define KEYSPEC_TYPE_ECC_MONTGOMERY ((uint32_t)(0xbUL << KEYSPEC_TYPE_OFFSET)) #define KEYSPEC_TYPE_ECC_EDDSA ((uint32_t)(0xcUL << KEYSPEC_TYPE_OFFSET)) #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - #define KEYSPEC_MODE_WRAPPED \ - (2UL << KEYSPEC_MODE_OFFSET) - #define KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_ZERO \ (1U << 9) #define KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_MINUS_THREE \ @@ -333,6 +357,8 @@ sl_status_t sli_se_key_to_keyspec(const sl_se_key_descriptor_t *key, return SL_STATUS_INVALID_PARAMETER; } + uint32_t keyspec_restriction = 0; + // Clear output *keyspec = 0; @@ -362,63 +388,102 @@ sl_status_t sli_se_key_to_keyspec(const sl_se_key_descriptor_t *key, case SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE: *keyspec |= KEYSPEC_MODE_VOLATILE; break; - +#if defined(_SILICON_LABS_32B_SERIES_3) + case SL_SE_KEY_STORAGE_INTERNAL_KSU: + *keyspec |= KEYSPEC_MODE_KSU; + break; +#endif default: return SL_STATUS_INVALID_PARAMETER; } - // --------------------- - // Key restriction [25-24] - - uint32_t keyspec_restriction = 0; - if (key->flags & SL_SE_KEY_FLAG_NON_EXPORTABLE) { - keyspec_restriction = KEYSPEC_RESTRICTION_LOCKED; - } - if (key->flags & SL_SE_KEY_FLAG_IS_DEVICE_GENERATED) { - keyspec_restriction = KEYSPEC_RESTRICTION_INTERNAL; - } - if ((key->flags & SL_SE_KEY_FLAG_IS_RESTRICTED) == SL_SE_KEY_FLAG_IS_RESTRICTED) { - keyspec_restriction = KEYSPEC_RESTRICTION_RESTRICTED; - } - // Key restrictions are only applicable to volatile and wrapped keys - if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { - if (keyspec_restriction != 0) { - return SL_STATUS_INVALID_PARAMETER; - } - } + // Handle key mode specific attributes: + switch (key->storage.method) { + #if defined(_SILICON_LABS_32B_SERIES_3) + case SL_SE_KEY_STORAGE_INTERNAL_KSU: + // --------------------- + // KSU ID [25-24] + // Not currently handled + // --------------------- + // KSU KeySlot [23-18] + #if defined(_SILICON_LABS_32B_SERIES_3) + if (key->storage.location.ksu.keyslot > 63) { + return SL_STATUS_INVALID_PARAMETER; + } + *keyspec = (*keyspec & ~KEYSPEC_KSU_KEYSLOT_MASK) + | ((key->storage.location.ksu.keyslot << KEYSPEC_KSU_KEYSLOT_OFFSET) + & KEYSPEC_KSU_KEYSLOT_MASK); + #endif + // --------------------- + // KSU KeyUsage [17-15] + if (key->storage.location.ksu.crypto_engine_id > 7) { + return SL_STATUS_INVALID_PARAMETER; + } + *keyspec = (*keyspec & ~KEYSPEC_KSU_KEY_USAGE_MASK) + | ((key->storage.location.ksu.crypto_engine_id << KEYSPEC_KSU_KEY_USAGE_OFFSET) + & KEYSPEC_KSU_KEY_USAGE_MASK); + // --------------------- + // KSU AllowedKeyUsers [14-12] + // Not currently handled + + // KSU does not support flags + if (key->flags != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + break; + #endif - *keyspec = (*keyspec & ~KEYSPEC_RESTRICTION_MASK) - | (keyspec_restriction & KEYSPEC_RESTRICTION_MASK); + default: + // --------------------- + // Key restriction [25-24] + if (key->flags & SL_SE_KEY_FLAG_NON_EXPORTABLE) { + keyspec_restriction = KEYSPEC_RESTRICTION_LOCKED; + } + if (key->flags & SL_SE_KEY_FLAG_IS_DEVICE_GENERATED) { + keyspec_restriction = KEYSPEC_RESTRICTION_INTERNAL; + } + if ((key->flags & SL_SE_KEY_FLAG_IS_RESTRICTED) == SL_SE_KEY_FLAG_IS_RESTRICTED) { + keyspec_restriction = KEYSPEC_RESTRICTION_RESTRICTED; + } + // Key restrictions are only applicable to volatile and wrapped keys + if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { + if (keyspec_restriction != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + } - // --------------------- - // Key index [23-16] + *keyspec = (*keyspec & ~KEYSPEC_RESTRICTION_MASK) + | (keyspec_restriction & KEYSPEC_RESTRICTION_MASK); -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) { - if (key->storage.location.slot > SL_SE_KEY_SLOT_VOLATILE_3) { - return SL_STATUS_INVALID_PARAMETER; - } - *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) - | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) - & KEYSPEC_INDEX_MASK); - } -#endif + // --------------------- + // Key index [23-16] - if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) { - if (key->storage.location.slot - < SL_SE_KEY_SLOT_INTERNAL_MIN) { - return SL_STATUS_INVALID_PARAMETER; - } - *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) - | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) - & KEYSPEC_INDEX_MASK); - } + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) { + if (key->storage.location.slot > SL_SE_KEY_SLOT_VOLATILE_3) { + return SL_STATUS_INVALID_PARAMETER; + } + *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) + | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) + & KEYSPEC_INDEX_MASK); + } + #endif - // --------------------- - // Key NoProt [15] + if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) { + if (key->storage.location.slot + < SL_SE_KEY_SLOT_INTERNAL_MIN) { + return SL_STATUS_INVALID_PARAMETER; + } + *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) + | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) + & KEYSPEC_INDEX_MASK); + } - if (key->flags & SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS) { - *keyspec = (*keyspec & ~KEYSPEC_NOPROT_MASK) | (1 << KEYSPEC_NOPROT_OFFSET); + // --------------------- + // Key NoProt [15] + if (key->flags & SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS) { + *keyspec = (*keyspec & ~KEYSPEC_NOPROT_MASK) | (1 << KEYSPEC_NOPROT_OFFSET); + } } // --------------------- @@ -568,26 +633,39 @@ sl_status_t sli_se_keyspec_to_key(const uint32_t keyspec, return SL_STATUS_INVALID_PARAMETER; } key->storage.location.slot = key_index; - } else { + } + #if defined(_SILICON_LABS_32B_SERIES_3) + else if ((keyspec & KEYSPEC_MODE_MASK) == KEYSPEC_MODE_KSU) { + key->storage.method = SL_SE_KEY_STORAGE_INTERNAL_KSU; + } + #endif + else { return SL_STATUS_INVALID_PARAMETER; } +#if defined(_SILICON_LABS_32B_SERIES_3) + if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_KSU) { + key->storage.location.ksu.keyslot = (keyspec & KEYSPEC_KSU_KEYSLOT_MASK) >> KEYSPEC_KSU_KEYSLOT_OFFSET; + key->storage.location.ksu.crypto_engine_id = (keyspec & KEYSPEC_KSU_KEY_USAGE_MASK) >> KEYSPEC_KSU_KEY_USAGE_OFFSET; + // KSU_ID + // KSU_ALLOWED_USERS + } else { +#endif // --------------------- // Key restriction [25-24] - uint32_t keyspec_restriction = (keyspec & KEYSPEC_RESTRICTION_MASK); if (keyspec_restriction == KEYSPEC_RESTRICTION_LOCKED) { key->flags |= SL_SE_KEY_FLAG_NON_EXPORTABLE; } else if (keyspec_restriction == KEYSPEC_RESTRICTION_UNLOCKED) { // no-op } -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) else if (keyspec_restriction == KEYSPEC_RESTRICTION_INTERNAL) { key->flags |= SL_SE_KEY_FLAG_IS_DEVICE_GENERATED; } else if (keyspec_restriction == KEYSPEC_RESTRICTION_RESTRICTED) { key->flags |= SL_SE_KEY_FLAG_IS_RESTRICTED; } -#endif + #endif else { return SL_STATUS_INVALID_PARAMETER; } @@ -605,6 +683,9 @@ sl_status_t sli_se_keyspec_to_key(const uint32_t keyspec, if ((keyspec & KEYSPEC_NOPROT_MASK) == (1 << KEYSPEC_NOPROT_OFFSET)) { key->flags |= SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS; } +#if defined(_SILICON_LABS_32B_SERIES_3) +} // if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_KSU); +#endif // --------------------- // Key attributes [14-0] @@ -738,11 +819,18 @@ sl_status_t sli_se_get_key_input_output(const sl_se_key_descriptor_t *key, return SL_STATUS_WOULD_OVERFLOW; } + if (key->storage.location.buffer.pointer == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + buffer->data = key->storage.location.buffer.pointer; buffer->length = total_storage_size | SLI_SE_DATATRANSFER_REALIGN; } else if ((key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) || (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) +#endif +#if defined(_SILICON_LABS_32B_SERIES_3) + || (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_KSU) #endif ) { buffer->length = 0; @@ -1003,8 +1091,14 @@ sl_status_t sl_se_import_key(sl_se_command_context_t *cmd_ctx, return status; } + // We only support importing keys with + // key_type in = plaintext + // key out volatile, wrapped or KSU storage if ((key_in->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) || ((key_out->storage.method != SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) + #if defined(_SILICON_LABS_32B_SERIES_3) + && (key_out->storage.method != SL_SE_KEY_STORAGE_INTERNAL_KSU) + #endif && (key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED))) { return SL_STATUS_INVALID_PARAMETER; } @@ -1106,6 +1200,9 @@ sl_status_t sl_se_transfer_key(sl_se_command_context_t *cmd_ctx, if ((key_in->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) || (key_in->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) + #if defined(_SILICON_LABS_32B_SERIES_3) + || (key_in->storage.method == SL_SE_KEY_STORAGE_INTERNAL_KSU) + #endif || (key_out->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) || (key_out->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE)) { return SL_STATUS_INVALID_PARAMETER; @@ -1125,6 +1222,21 @@ sl_status_t sl_se_transfer_key(sl_se_command_context_t *cmd_ctx, } key_update_index = ((keyspec_out & KEYSPEC_INDEX_MASK) >> KEYSPEC_INDEX_OFFSET); key_update_mode = ((keyspec_out & KEYSPEC_MODE_MASK) >> KEYSPEC_MODE_OFFSET); + + #if defined(_SILICON_LABS_32B_SERIES_3) + if (key_out->storage.method == SL_SE_KEY_STORAGE_INTERNAL_KSU) { + // Set KSU specific keyspecs + key_update_index = ((keyspec_out & KEYSPEC_KSU_KEYSLOT_MASK) >> KEYSPEC_KSU_KEYSLOT_OFFSET); + uint32_t key_update_ksu_id = ((keyspec_out & KEYSPEC_KSU_ID_MASK) >> KEYSPEC_KSU_ID_OFFSET); + uint32_t key_update_ksu_usage = ((keyspec_out & KEYSPEC_KSU_KEY_USAGE_MASK) >> KEYSPEC_KSU_KEY_USAGE_OFFSET); + keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_KSU_ID_MASK) + | ((key_update_ksu_id << KEYSPEC_TRANSFER_KSU_ID_OFFSET) + & KEYSPEC_TRANSFER_KSU_ID_MASK); + keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_KSU_ID_MASK) + | ((key_update_ksu_usage << KEYSPEC_TRANSFER_KSU_KEY_USAGE_OFFSET) + & KEYSPEC_TRANSFER_KSU_KEY_USAGE_MASK); + } + #endif keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_INDEX_MASK) | ((key_update_index << KEYSPEC_TRANSFER_INDEX_OFFSET) & KEYSPEC_TRANSFER_INDEX_MASK); diff --git a/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c b/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c index 0e8c591ea5..40f0127a09 100644 --- a/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c +++ b/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c @@ -55,7 +55,10 @@ sl_status_t sl_se_ecc_sign(sl_se_command_context_t *cmd_ctx, unsigned char *signature, size_t signature_len) { - if (cmd_ctx == NULL || key == NULL || message == NULL || signature == NULL) { + if (cmd_ctx == NULL || key == NULL || signature == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if ( message == NULL && message_len != 0 ) { return SL_STATUS_INVALID_PARAMETER; } diff --git a/platform/security/sl_component/se_manager/src/sl_se_manager_util.c b/platform/security/sl_component/se_manager/src/sl_se_manager_util.c index 9ac2764efb..24a534241b 100644 --- a/platform/security/sl_component/se_manager/src/sl_se_manager_util.c +++ b/platform/security/sl_component/se_manager/src/sl_se_manager_util.c @@ -29,6 +29,8 @@ ******************************************************************************/ #include "sl_se_manager_util.h" +#include "sl_se_manager_types.h" +#include #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) @@ -1019,27 +1021,25 @@ sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, } #if defined(_SILICON_LABS_32B_SERIES_3) - /* TODO: Enable once register available: PSEC-5574 - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); - // Read state of CMU_CLKEN0_SYSCFG - bool syscfg_clock_was_enabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + // Read state of CMU_CLKEN0_SYSCFG + bool syscfg_clock_was_enabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - // Read SE FW version from SYSCFG - * version = (uint32_t)(((SYSCFG->ROOTSESWVERSION) & 0xFF000000) >> 24); - * version -= (uint32_t)((SYSCFG->ROMREVHW) & 0x000000FF); + // Read SE FW version from SYSCFG + *version = (uint32_t)(((SYSCFG->ROOTSESWVERSION) & 0xFF000000) >> 24); + *version -= (uint32_t)((SYSCFG->ROMREVHW) & 0x000000FF); + + if (!syscfg_clock_was_enabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + CORE_EXIT_CRITICAL(); - if (!syscfg_clock_was_enabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - CORE_EXIT_CRITICAL(); + return SL_STATUS_OK; - return SL_STATUS_OK; - */ - return SL_STATUS_NOT_SUPPORTED; #else // SE command structures sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; @@ -1119,6 +1119,36 @@ sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, } #endif // SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE +#if defined(_SILICON_LABS_32B_SERIES_3) +/***************************************************************************//** + * Reads out traceable event flags from the OTP + ******************************************************************************/ +sl_status_t sl_se_get_lifecycle_event_flags(sl_se_command_context_t *cmd_ctx, uint64_t *event_flags) +{ + sl_status_t status; + if (cmd_ctx == NULL || event_flags == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t se_version = 0; + status = sl_se_get_se_version(cmd_ctx, &se_version); + if (status != SL_STATUS_OK) { + return status; + } + if (se_version < 0x030002UL) { + // SE FW version lower than 3.0.2 does not support reading trace flags + return SL_STATUS_NOT_SUPPORTED; + } + + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_TRACE_FLAGS); + + sli_se_datatransfer_t out_data = SLI_SE_DATATRANSFER_DEFAULT(event_flags, 8); + sli_se_mailbox_command_add_output(se_cmd, &out_data); + return sli_se_execute_and_wait(cmd_ctx); +} +#endif /***************************************************************************//** * Enables the secure debug functionality. ******************************************************************************/ @@ -1397,6 +1427,56 @@ sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx) #endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) #if defined(_SILICON_LABS_32B_SERIES_3) +/***************************************************************************//** + * @brief + * Read the OTP rollback counter. + ******************************************************************************/ +sl_status_t sl_se_get_rollback_counter(sl_se_command_context_t *cmd_ctx, + uint32_t *rollback_counter) +{ + if ((cmd_ctx == NULL) || (rollback_counter == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_GET_ROLLBACK_COUNTER); + + sli_se_datatransfer_t out_data + = SLI_SE_DATATRANSFER_DEFAULT(rollback_counter, sizeof(uint32_t)); + sli_se_mailbox_command_add_output(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * @brief + * Increment the OTP rollback counter. + ******************************************************************************/ +sl_status_t sl_se_increment_rollback_counter(sl_se_command_context_t *cmd_ctx, + uint32_t *rollback_counter) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + + sli_se_command_init(cmd_ctx, (SLI_SE_COMMAND_GET_ROLLBACK_COUNTER | 0x00000100)); + + uint32_t output = 0; + + sli_se_datatransfer_t out_data + = SLI_SE_DATATRANSFER_DEFAULT(&output, sizeof(uint32_t)); + sli_se_mailbox_command_add_output(se_cmd, &out_data); + + sl_status_t status = sli_se_execute_and_wait(cmd_ctx); + + if (rollback_counter != NULL) { + *rollback_counter = output; + } + return status; +} /***************************************************************************//** * Reads back the stored upgrade file version. diff --git a/platform/security/sl_component/sl_mbedtls_support/config/template/sl_mbedtls_config.h b/platform/security/sl_component/sl_mbedtls_support/config/template/sl_mbedtls_config.h index 39b51496fd..25e3a57c06 100644 --- a/platform/security/sl_component/sl_mbedtls_support/config/template/sl_mbedtls_config.h +++ b/platform/security/sl_component/sl_mbedtls_support/config/template/sl_mbedtls_config.h @@ -67,6 +67,15 @@ // Enable parsing of the compressed curves. #define SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING 0 +// Assume all buffers passed to PSA functions are owned exclusively by the PSA function. +// Default: 0 +// This option may be enabled if all buffers passed to any PSA function reside +// in memory that is accessible only to the PSA function during its execution. +// This option MUST be disabled whenever buffer arguments are in memory shared +// with an untrusted party, for example where arguments to PSA calls are passed +// across a trust boundary. +#define SL_MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS 0 + // // RSA configuration diff --git a/platform/security/sl_component/sl_mbedtls_support/config/template/sli_mbedtls_config_transform_autogen.h.jinja b/platform/security/sl_component/sl_mbedtls_support/config/template/sli_mbedtls_config_transform_autogen.h.jinja index 8ff43fb503..e9859ab06f 100644 --- a/platform/security/sl_component/sl_mbedtls_support/config/template/sli_mbedtls_config_transform_autogen.h.jinja +++ b/platform/security/sl_component/sl_mbedtls_support/config/template/sli_mbedtls_config_transform_autogen.h.jinja @@ -38,6 +38,9 @@ #if SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING #define MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING #endif +#if SL_MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + #define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS +#endif #if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) #define MBEDTLS_SSL_IN_CONTENT_LEN SL_MBEDTLS_SSL_IN_CONTENT_LEN diff --git a/platform/security/sl_component/sl_mbedtls_support/inc/se_management.h b/platform/security/sl_component/sl_mbedtls_support/inc/se_management.h index 1c7484bb61..a56740d0b8 100644 --- a/platform/security/sl_component/sl_mbedtls_support/inc/se_management.h +++ b/platform/security/sl_component/sl_mbedtls_support/inc/se_management.h @@ -78,41 +78,6 @@ __STATIC_INLINE int se_management_release(void) return sli_se_lock_release() == SL_STATUS_OK ? 0 : -1; } -/** - * \brief Handle the response of the previously executed command. - * - * \details This function handles the response of the previously - * executed HSE command by calling sli_se_mailbox_read_response - * to read the response value and returns it. For Series-3 this - * function executes sli_se_mailbox_read_response inside an - * atomic section and clears the SEMAILBOX FIFO at the end. - * - * \note This function implements a workaround that is planned to be - * replaced in https://jira.silabs.com/browse/PSEC-5643. - * - * \return Value returned by sli_se_mailbox_read_response. - ******************************************************************************/ -__STATIC_INLINE sli_se_mailbox_response_t sli_se_handle_mailbox_response(void) -{ - #if defined(_SILICON_LABS_32B_SERIES_3) - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - #endif - - // Read command response - sli_se_mailbox_response_t se_mailbox_response = sli_se_mailbox_read_response(); - - #if defined(_SILICON_LABS_32B_SERIES_3) - CORE_EXIT_ATOMIC(); - - // Read the command handle word ( not used ) from the SEMAILBOX FIFO - SEMAILBOX_HOST->FIFO; - #endif - - // Return command response - return se_mailbox_response; -} - #ifdef __cplusplus } #endif diff --git a/platform/security/sl_component/sl_mbedtls_support/src/se_aes.c b/platform/security/sl_component/sl_mbedtls_support/src/se_aes.c index 4614184a31..6e9ee8c297 100644 --- a/platform/security/sl_component/sl_mbedtls_support/src/se_aes.c +++ b/platform/security/sl_component/sl_mbedtls_support/src/se_aes.c @@ -406,7 +406,7 @@ int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, } sli_se_mailbox_execute_command(&command); - command_status = sli_se_handle_mailbox_response(); + command_status = sli_se_mailbox_handle_response(); se_management_release(); @@ -466,7 +466,7 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, } sli_se_mailbox_execute_command(&command); - command_status = sli_se_handle_mailbox_response(); + command_status = sli_se_mailbox_handle_response(); se_management_release(); @@ -544,7 +544,7 @@ int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, } sli_se_mailbox_execute_command(&command); - command_status = sli_se_handle_mailbox_response(); + command_status = sli_se_mailbox_handle_response(); se_management_release(); processed += iterations * 16; @@ -685,7 +685,7 @@ int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, } sli_se_mailbox_execute_command(&command); - command_status = sli_se_handle_mailbox_response(); + command_status = sli_se_mailbox_handle_response(); se_management_release(); processed += iterations * 16; diff --git a/platform/security/sl_component/sl_mbedtls_support/src/se_gcm.c b/platform/security/sl_component/sl_mbedtls_support/src/se_gcm.c index 462ec432c3..41ffba2a61 100644 --- a/platform/security/sl_component/sl_mbedtls_support/src/se_gcm.c +++ b/platform/security/sl_component/sl_mbedtls_support/src/se_gcm.c @@ -46,6 +46,7 @@ #include "mbedtls/platform_util.h" #include "mbedtls/error.h" #include "se_management.h" +#include "sli_se_manager_mailbox.h" #include /* Implementation that should never be optimized out by the compiler */ @@ -225,9 +226,9 @@ int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, } /* Execute GCM operation */ sli_se_mailbox_execute_command(&gcm_cmd_enc_full); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); sli_se_mailbox_execute_command(&gcm_cmd_enc); - se_response |= sli_se_handle_mailbox_response(); + se_response |= sli_se_mailbox_handle_response(); se_management_release(); @@ -257,7 +258,7 @@ int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, } /* Execute GCM operation */ sli_se_mailbox_execute_command(&gcm_cmd_dec); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); se_management_release(); } @@ -375,7 +376,7 @@ int mbedtls_gcm_update(mbedtls_gcm_context *ctx, sli_se_mailbox_command_add_parameter(&gcm_cmd_dec, input_length); sli_se_mailbox_execute_command(&gcm_cmd_dec); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); // Getting an 'invalid signature' error here is acceptable, since we're not trying to verify the tag if (se_response == SLI_SE_RESPONSE_INVALID_SIGNATURE) { se_response = SLI_SE_RESPONSE_OK; @@ -413,7 +414,7 @@ int mbedtls_gcm_update(mbedtls_gcm_context *ctx, sli_se_mailbox_command_add_parameter(&gcm_cmd_enc_final, input_length); sli_se_mailbox_execute_command(&gcm_cmd_enc_final); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); if (se_response != SLI_SE_RESPONSE_OK) { goto exit; } @@ -459,7 +460,7 @@ int mbedtls_gcm_update(mbedtls_gcm_context *ctx, sli_se_mailbox_command_add_parameter(&gcm_cmd_enc, input_length); sli_se_mailbox_execute_command(&gcm_cmd_enc); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); } exit: @@ -570,7 +571,7 @@ int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, return status; } sli_se_mailbox_execute_command(&gcm_cmd); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); se_management_release(); // Getting an 'invalid signature' error here is acceptable, since we're not trying to verify the tag if (se_response == SLI_SE_RESPONSE_INVALID_SIGNATURE) { @@ -616,7 +617,7 @@ int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, } /* Execute GCM operation */ sli_se_mailbox_execute_command(&gcm_cmd); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); se_management_release(); } @@ -696,7 +697,7 @@ int mbedtls_gcm_auth_decrypt(mbedtls_gcm_context *ctx, return status; } sli_se_mailbox_execute_command(&gcm_cmd); - se_response = sli_se_handle_mailbox_response(); + se_response = sli_se_mailbox_handle_response(); se_management_release(); if (se_response == SLI_SE_RESPONSE_OK) { diff --git a/platform/security/sl_component/sl_mbedtls_support/src/se_jpake.c b/platform/security/sl_component/sl_mbedtls_support/src/se_jpake.c index fe57b5d8a7..09e30693bd 100644 --- a/platform/security/sl_component/sl_mbedtls_support/src/se_jpake.c +++ b/platform/security/sl_component/sl_mbedtls_support/src/se_jpake.c @@ -360,7 +360,7 @@ int mbedtls_ecjpake_write_round_one(mbedtls_ecjpake_context *ctx, } sli_se_mailbox_execute_command(&command); - sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + sli_se_mailbox_response_t res = sli_se_mailbox_handle_response(); se_management_release(); @@ -483,7 +483,7 @@ int mbedtls_ecjpake_read_round_one(mbedtls_ecjpake_context *ctx, } sli_se_mailbox_execute_command(&command); - sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + sli_se_mailbox_response_t res = sli_se_mailbox_handle_response(); se_management_release(); @@ -544,7 +544,7 @@ int mbedtls_ecjpake_write_round_two(mbedtls_ecjpake_context *ctx, } sli_se_mailbox_execute_command(&command); - sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + sli_se_mailbox_response_t res = sli_se_mailbox_handle_response(); se_management_release(); @@ -685,7 +685,7 @@ int mbedtls_ecjpake_read_round_two(mbedtls_ecjpake_context *ctx, } sli_se_mailbox_execute_command(&command); - sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + sli_se_mailbox_response_t res = sli_se_mailbox_handle_response(); se_management_release(); @@ -741,7 +741,7 @@ int mbedtls_ecjpake_derive_secret(mbedtls_ecjpake_context *ctx, } sli_se_mailbox_execute_command(&command); - sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + sli_se_mailbox_response_t res = sli_se_mailbox_handle_response(); se_management_release(); diff --git a/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h b/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h index a14c58e6ee..52f6fdfdcb 100644 --- a/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h +++ b/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h @@ -41,6 +41,7 @@ ******************************************************************************/ #include "sl_status.h" +#include "sl_code_classification.h" #include "em_device.h" #include #include @@ -69,6 +70,7 @@ sl_status_t sli_protocol_crypto_init(void); * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_aes_crypt_ctr_radio(const unsigned char *key, unsigned int keybits, const unsigned char input[16], @@ -87,6 +89,7 @@ sl_status_t sli_aes_crypt_ctr_radio(const unsigned char *key, * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_aes_crypt_ecb_radio(bool encrypt, const unsigned char *key, unsigned int keybits, @@ -105,6 +108,7 @@ sl_status_t sli_aes_crypt_ecb_radio(bool encrypt, * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_aes_cmac_radio(const unsigned char *key, unsigned int keybits, const unsigned char *input, @@ -116,6 +120,7 @@ sl_status_t sli_aes_cmac_radio(const unsigned char *key, during initialization in order to avoid taking the potential hit of requesting RNG output in an IRQ context. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) void sli_aes_seed_mask(void); #endif @@ -133,6 +138,7 @@ void sli_aes_seed_mask(void); * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, * relevant status code on other error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_ccm_auth_decrypt_ble(unsigned char *data, size_t length, const unsigned char *key, @@ -152,6 +158,7 @@ sl_status_t sli_ccm_auth_decrypt_ble(unsigned char *data, * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_ccm_encrypt_and_tag_ble(unsigned char *data, size_t length, const unsigned char *key, @@ -175,6 +182,7 @@ sl_status_t sli_ccm_encrypt_and_tag_ble(unsigned char *data, * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, * relevant status code on other error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_ccm_zigbee(bool encrypt, const unsigned char *data_in, unsigned char *data_out, @@ -198,6 +206,7 @@ sl_status_t sli_ccm_zigbee(bool encrypt, * * @return 0-based index of matching key if a match is found, -1 for no match. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) int sli_process_ble_rpa(const unsigned char keytable[], uint32_t keymask, uint32_t prand, diff --git a/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c b/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c index 6e74ca7fb7..006cd4f6c2 100644 --- a/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c +++ b/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c @@ -34,6 +34,7 @@ #include "sli_radioaes_management.h" #include "sli_protocol_crypto.h" +#include "sl_code_classification.h" #include "em_core.h" #define AES_BLOCK_BYTES 16U @@ -187,6 +188,7 @@ static const uint32_t aes_ccm_config_decrypt = AES_MODEID_CCM | AES_MODEID_DECRYPT; static const uint32_t zeros = 0; +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) static sl_status_t sli_radioaes_run_operation(sli_radioaes_dma_descr_t *first_fetch_descriptor, sli_radioaes_dma_descr_t *first_push_descriptor) { @@ -224,6 +226,7 @@ static sl_status_t sli_radioaes_run_operation(sli_radioaes_dma_descr_t *first_fe } // CCM (and CCM-star) implementation +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) static sl_status_t aes_ccm_radio(bool encrypt, const unsigned char *add_data, size_t add_length, @@ -407,6 +410,7 @@ static sl_status_t aes_ccm_radio(bool encrypt, // * in-place encrypt/decrypt with variable length plain/ciphertext // (up to 64 kB, uint16 overflow) // * 4 byte tag +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) static sl_status_t aes_ccm_ble(bool encrypt, unsigned char *data, size_t length, diff --git a/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c b/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c index 7fab1a2bfe..ad9335402a 100644 --- a/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c +++ b/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c @@ -35,6 +35,7 @@ #include "sli_radioaes_management.h" #include "sli_psec_osal.h" #include "em_core.h" +#include "sl_code_classification.h" #if defined(SLI_PSEC_THREADING) static sli_psec_osal_lock_t radioaes_lock = { 0 }; @@ -61,6 +62,7 @@ static volatile bool radioaes_lock_initialized = false; uint32_t sli_radioaes_mask = 0; +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) static void sli_radioaes_update_mask(void) { if (sli_radioaes_mask == 0) { diff --git a/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h b/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h index b07b98bc03..3064821a1d 100644 --- a/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h +++ b/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h @@ -34,6 +34,7 @@ #include #include "sl_status.h" +#include "sl_code_classification.h" #if defined(RADIOAES_PRESENT) @@ -64,6 +65,7 @@ extern uint32_t sli_radioaes_mask; * which case the caller is responsible for saving state, * relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_radioaes_acquire(void); /***************************************************************************//** @@ -71,6 +73,7 @@ sl_status_t sli_radioaes_acquire(void); * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_radioaes_release(void); /***************************************************************************//** @@ -80,6 +83,7 @@ sl_status_t sli_radioaes_release(void); * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_radioaes_save_state(sli_radioaes_state_t *ctx); /***************************************************************************//** @@ -89,6 +93,7 @@ sl_status_t sli_radioaes_save_state(sli_radioaes_state_t *ctx); * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_PROTOCOL_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_radioaes_restore_state(sli_radioaes_state_t *ctx); #ifdef __cplusplus diff --git a/platform/security/sl_component/sl_trustzone/src/sli_tz_service_attestation.c b/platform/security/sl_component/sl_trustzone/src/sli_tz_service_attestation.c index fe4a56c10d..1aec203f30 100644 --- a/platform/security/sl_component/sl_trustzone/src/sli_tz_service_attestation.c +++ b/platform/security/sl_component/sl_trustzone/src/sli_tz_service_attestation.c @@ -211,11 +211,11 @@ static psa_status_t generate_firmware_hash(uint8_t *firmware_addr, uint8_t *hash_buffer, size_t *hash_size) { - #if (FLASH_BASE == 0UL) - // Process the first 4 bytes by moving them into the stack buffer. - // this is needed since the address 0 can't be used as the input. - - #define HASH_BUFFER_SIZE (4u) + // Calculate the hash by moving into a temporary small buffer on stack + // because the SKL and device is usually not configured with a sufficiently + // sized heap to allocate a full exclusive buffer internally in the PSA Crypto + // library. + #define HASH_BUFFER_SIZE (256u) psa_hash_operation_t hash_operation; hash_operation = psa_hash_operation_init(); @@ -224,31 +224,23 @@ static psa_status_t generate_firmware_hash(uint8_t *firmware_addr, return status; } uint8_t hash_in_buffer[HASH_BUFFER_SIZE]; - memcpy(hash_in_buffer, (uint8_t *)((uint32_t)firmware_addr), HASH_BUFFER_SIZE); - status = psa_hash_update(&hash_operation, - (const uint8_t *)hash_in_buffer, - HASH_BUFFER_SIZE); - if (status != PSA_SUCCESS) { - return status; - } - status = psa_hash_update(&hash_operation, - (uint8_t *)((uint32_t)firmware_addr + HASH_BUFFER_SIZE), - firmware_size - HASH_BUFFER_SIZE); - if (status != PSA_SUCCESS) { - return status; + size_t bytes_to_copy; + while (firmware_size > 0) { + bytes_to_copy = firmware_size > HASH_BUFFER_SIZE ? HASH_BUFFER_SIZE : firmware_size; + memcpy(hash_in_buffer, (uint8_t *)((uint32_t)firmware_addr), bytes_to_copy); + status = psa_hash_update(&hash_operation, + (const uint8_t *)hash_in_buffer, + bytes_to_copy); + if (status != PSA_SUCCESS) { + return status; + } + firmware_addr += bytes_to_copy; + firmware_size -= bytes_to_copy; } status = psa_hash_finish(&hash_operation, hash_buffer, TZ_ATTESTATION_SHA256_DIGESTSIZE, hash_size); - #else - psa_status_t status = psa_hash_compute(PSA_ALG_SHA_256, - (const uint8_t *)firmware_addr, - firmware_size, - hash_buffer, - TZ_ATTESTATION_SHA256_DIGESTSIZE, - hash_size); - #endif return status; } diff --git a/platform/security/sl_component/sli_crypto/inc/sli_crypto.h b/platform/security/sl_component/sli_crypto/inc/sli_crypto.h index f948449fc7..e696487ffe 100644 --- a/platform/security/sl_component/sli_crypto/inc/sli_crypto.h +++ b/platform/security/sl_component/sli_crypto/inc/sli_crypto.h @@ -39,6 +39,7 @@ #error Unsupported device. #endif #include "sl_status.h" +#include "sl_code_classification.h" #include #include #include @@ -62,6 +63,7 @@ extern "C" { * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, * relevant status code on other error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_crypto_ccm_auth_decrypt_ble(sli_crypto_descriptor_t *key_descriptor, unsigned char *data, size_t length, @@ -82,6 +84,7 @@ sl_status_t sli_crypto_ccm_auth_decrypt_ble(sli_crypto_descriptor_t *key_des * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_crypto_ccm_encrypt_and_tag_ble(sli_crypto_descriptor_t *key_descriptor, unsigned char *data, size_t length, @@ -108,6 +111,7 @@ sl_status_t sli_crypto_ccm_encrypt_and_tag_ble(sli_crypto_descriptor_t *key_ * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, * relevant status code on other error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_crypto_ccm_zigbee(sli_crypto_descriptor_t *key_descriptor, bool encrypt, const unsigned char *data_in, @@ -138,6 +142,7 @@ sl_status_t sli_crypto_ccm_zigbee(sli_crypto_descriptor_t *key_descriptor, * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_crypto_process_rpa(sli_crypto_descriptor_t *key_descriptor, size_t irk_len, uint64_t keymask, @@ -157,6 +162,7 @@ sl_status_t sli_crypto_process_rpa(sli_crypto_descriptor_t *key_descriptor, * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_crypto_aes_ctr_radio(sli_crypto_descriptor_t *key_descriptor, unsigned int keybits, const unsigned char input[SLI_CRYPTO_AES_BLOCK_SIZE], @@ -175,6 +181,7 @@ sl_status_t sli_crypto_aes_ctr_radio(sli_crypto_descriptor_t *key_descriptor, * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_crypto_aes_ecb_radio(bool encrypt, sli_crypto_descriptor_t *key_descriptor, unsigned int keybits, @@ -192,6 +199,7 @@ sl_status_t sli_crypto_aes_ecb_radio(bool encrypt, * * @return SL_STATUS_OK if successful, relevant status code on error ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLI_CRYPTO, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_crypto_aes_cmac_radio(sli_crypto_descriptor_t *key_descriptor, unsigned int keybits, const unsigned char *input, diff --git a/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_cmsis_rtos2.h b/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_cmsis_rtos2.h index 6c388aab23..f2a0c3aff6 100644 --- a/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_cmsis_rtos2.h +++ b/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_cmsis_rtos2.h @@ -172,6 +172,16 @@ __STATIC_INLINE sl_status_t sli_psec_osal_free_lock(sli_psec_osal_lock_t *lock) return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); } +/***************************************************************************//** + * @brief Check if lock is open for calling thread + * + * @param lock Pointer to the lock to be checked + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PSEC_OSAL, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_psec_osal_lock_is_accessible(sli_psec_osal_lock_t *lock); + /***************************************************************************//** * @brief Pend on a lock with timeout * diff --git a/platform/security/sl_component/sli_psec_osal/src/sli_psec_osal_cmsis_rtos2.c b/platform/security/sl_component/sli_psec_osal/src/sli_psec_osal_cmsis_rtos2.c index f0e8d63d8a..163b80be4b 100644 --- a/platform/security/sl_component/sli_psec_osal/src/sli_psec_osal_cmsis_rtos2.c +++ b/platform/security/sl_component/sli_psec_osal/src/sli_psec_osal_cmsis_rtos2.c @@ -37,7 +37,6 @@ // Functions /// Check if lock is open for calling thread -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PSEC_OSAL, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_psec_osal_lock_is_accessible(sli_psec_osal_lock_t *lock) { sl_status_t sl_status; diff --git a/platform/service/cli/src/sl_cli_threaded_host.c b/platform/service/cli/src/sl_cli_threaded_host.c index a833912fc9..77f5e21ec6 100644 --- a/platform/service/cli/src/sl_cli_threaded_host.c +++ b/platform/service/cli/src/sl_cli_threaded_host.c @@ -105,6 +105,7 @@ void *threaded_tick(void *ptr) if (threaded_tick_cli_handle->req_prompt) { threaded_tick_cli_handle->req_prompt = false; sli_cli_io_printf("%s", threaded_tick_cli_handle->prompt_string); + fflush(stdout); } #if defined(SL_CLI_ACTIVE_FLAG_EN) threaded_tick_cli_handle->active = false; diff --git a/platform/service/clock_manager/clock_manager_validation.lua b/platform/service/clock_manager/clock_manager_validation.lua index 9ed7cc12a9..a65e678edd 100644 --- a/platform/service/clock_manager/clock_manager_validation.lua +++ b/platform/service/clock_manager/clock_manager_validation.lua @@ -27,6 +27,7 @@ local socpll_refclk = slc.config("SL_CLOCK_MANAGER_SOCPLL_REFCLK") local clkin0_freq = slc.config("SL_CLOCK_MANAGER_CLKIN0_FREQ") local qspi_advanced_config_enable = slc.config("SL_CLOCK_MANAGER_QSPICLK_CUSTOM_FREQ") local qspi_custom_freq = slc.config("SL_CLOCK_MANAGER_QSPICLK_CUSTOM_FREQ") +local socpll_advanced_settings = slc.config("SOCPLL_ADVANCED_SETTINGS") -- OSCILLATORS VALIDATION -- -- HFXO related @@ -88,7 +89,7 @@ if (sysclk_source.value == "CMU_SYSCLKCTRL_CLKSEL_CLKIN0") or (em01grpbclk_sourc nil, nil) end - if clkin0_freq < 1000000 or clkin0_freq > 38000000 then + if tonumber(clkin0_freq.value) < 1000000 or tonumber(clkin0_freq.value) > 38000000 then validation.warning( "Unsupported CLKIN0 frequency. It should be between 1MHz and 38MHz", validation.target_for_defines({"SL_CLOCK_MANAGER_CLKIN0_FREQ"}), @@ -148,7 +149,7 @@ end socpll_refclk_freq = tonumber(slc.config("SL_CLOCK_MANAGER_HFRCO_BAND").value) end end - if socpll_refclk_freq ~= nil then + if socpll_refclk_freq ~= nil and socpll_advanced_settings ~= nil and socpll_advanced_settings == 1 then -- check formula validation: socpll_freq = Fref * (DIVN+2 + DIVF/1024) / 6 local socpll_freq local socpll_freq_expected = tonumber(slc.config("SL_CLOCK_MANAGER_SOCPLL_FREQ").value) diff --git a/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_oscillator_config.h index e156b6ee8e..03b36c2c16 100644 --- a/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_tree_config.h index ab95b171d4..356d9a07c5 100644 --- a/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_oscillator_config.h index 517d85a1ca..fd29e48d65 100644 --- a/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_tree_config.h index 36636df039..6048358fea 100644 --- a/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_oscillator_config.h index 0c9f5747eb..f9d310a2ab 100644 --- a/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_tree_config.h index c123248949..7880af02e8 100644 --- a/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_oscillator_config.h index 20cc0d452c..902dfceeca 100644 --- a/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_tree_config.h index 472741a24e..0ebeef29ac 100644 --- a/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_oscillator_config.h index d18036a867..3c103e5300 100644 --- a/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_tree_config.h index 992643d9c5..928f96a4b5 100644 --- a/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_oscillator_config.h index 20cc0d452c..902dfceeca 100644 --- a/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_tree_config.h index 6ec4ee9818..8d03d88de0 100644 --- a/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_oscillator_config.h index 517d85a1ca..fd29e48d65 100644 --- a/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_tree_config.h index 3f788869d5..170fe15d65 100644 --- a/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_oscillator_config.h index 0c9f5747eb..f9d310a2ab 100644 --- a/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -91,6 +91,13 @@ #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + // HFXO crystal sharing feature // Enable to configure HFXO crystal sharing leader or follower #ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN @@ -206,6 +213,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_tree_config.h index 7f8119fb7a..280db32dbf 100644 --- a/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_oscillator_config.h index 517d85a1ca..fd29e48d65 100644 --- a/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_tree_config.h index 850679a7df..899b83ec3b 100644 --- a/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_oscillator_config.h b/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_oscillator_config.h index e156b6ee8e..03b36c2c16 100644 --- a/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_oscillator_config.h +++ b/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_oscillator_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Oscillators configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -89,6 +89,13 @@ #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif // // LFXO Settings (if Low Frequency crystal is used) @@ -133,6 +140,13 @@ #ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT #define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K #endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif // // HFRCO and DPLL Settings diff --git a/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_tree_config.h b/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_tree_config.h index 47a508dee7..7bf0d3bf3a 100644 --- a/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_tree_config.h +++ b/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_tree_config.h @@ -3,7 +3,7 @@ * @brief Clock Manager - Clock Tree configuration file. ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/service/clock_manager/inc/sl_clock_manager.h b/platform/service/clock_manager/inc/sl_clock_manager.h index f81db0a1e0..e2eb0531bc 100644 --- a/platform/service/clock_manager/inc/sl_clock_manager.h +++ b/platform/service/clock_manager/inc/sl_clock_manager.h @@ -627,6 +627,31 @@ sl_status_t sl_clock_manager_wait_usbpll(void); ******************************************************************************/ void sl_clock_manager_hfxo_notify_consecutive_failed_startups(void); +/***************************************************************************//** + * Sets the external FLASH reference clock. + * + * @param[in] oscillator Oscillator used to clock the external FLASH. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note This API is not thread-safe and should therefore not be called + * across multiple tasks. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_clock_manager_set_ext_flash_clk(sl_oscillator_t oscillator); + +/***************************************************************************//** + * Gets the external FLASH clock source. + * + * @param[out] oscillator Oscillator used to clock the external FLASH. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_clock_manager_get_ext_flash_clk(sl_oscillator_t *oscillator); + /** @} (end addtogroup clock_manager) */ #ifdef __cplusplus diff --git a/platform/service/clock_manager/inc/sl_clock_manager_oscillator_calibration_override.h b/platform/service/clock_manager/inc/sl_clock_manager_oscillator_calibration_override.h new file mode 100644 index 0000000000..2c0d01afdd --- /dev/null +++ b/platform/service/clock_manager/inc/sl_clock_manager_oscillator_calibration_override.h @@ -0,0 +1,91 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager Oscillator Calibration Override APIs. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CALIBRATION_OVERRIDE_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CALIBRATION_OVERRIDE_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup clock_manager Clock Manager + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Configure Oscillator CTune settings using override key values stored in + * NVM3. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_init_oscillator_calibration_override(void); + +/***************************************************************************//** + * Write HFXO override calibration value to NVM3. + * + * @param[in] ctune The HFXO override CTune value to write to NVM3. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_write_hfxo_calibration_override(uint32_t ctune); + +/***************************************************************************//** + * Read HFXO override calibration value from NVM3. + * + * @param[out] ctune HFXO override CTune value read from NVM3. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_read_hfxo_calibration_override(uint32_t *ctune); + +/***************************************************************************//** + * Delete HFXO override calibration value from NVM3. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_delete_hfxo_calibration_override(void); + +/** @} (end addtogroup clock_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_CLOCK_MANAGER_OSCILLATOR_CALIBRATION_OVERRIDE_H diff --git a/platform/service/clock_manager/inc/sli_clock_manager.h b/platform/service/clock_manager/inc/sli_clock_manager.h index c6645da764..205c46eb51 100644 --- a/platform/service/clock_manager/inc/sli_clock_manager.h +++ b/platform/service/clock_manager/inc/sli_clock_manager.h @@ -33,7 +33,8 @@ #include "sl_clock_manager.h" #include "sl_status.h" -#include "em_device.h" +#include "sl_compiler.h" +#include "sl_code_classification.h" #ifdef __cplusplus extern "C" { @@ -42,11 +43,13 @@ extern "C" { /***************************************************************************//** * Set SYSCLK clock source. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_clock_manager_set_sysclk_source(sl_oscillator_t source); /***************************************************************************//** * Get SYSCLK clock source. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_clock_manager_get_sysclk_source(sl_oscillator_t *source); /***************************************************************************//** diff --git a/platform/service/clock_manager/src/sl_clock_manager.c b/platform/service/clock_manager/src/sl_clock_manager.c index 5f30b26cde..67faff9c76 100644 --- a/platform/service/clock_manager/src/sl_clock_manager.c +++ b/platform/service/clock_manager/src/sl_clock_manager.c @@ -28,7 +28,9 @@ * ******************************************************************************/ +#include "sli_clock_manager.h" #include "sl_clock_manager.h" +#include "sli_clock_manager.h" #include "sli_clock_manager_hal.h" #include "sl_assert.h" #include "cmsis_compiler.h" @@ -293,3 +295,19 @@ __WEAK void sl_clock_manager_hfxo_notify_consecutive_failed_startups(void) { EFM_ASSERT(false); } + +/***************************************************************************//** + * Sets the external FLASH reference clock. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_ext_flash_clk(sl_oscillator_t oscillator) +{ + return sli_clock_manager_hal_set_ext_flash_clk(oscillator); +} + +/***************************************************************************//** + * Gets the external FLASH clock source. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_ext_flash_clk(sl_oscillator_t *oscillator) +{ + return sli_clock_manager_hal_get_ext_flash_clk(oscillator); +} diff --git a/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c b/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c index 3d7aa35bbe..8d3900b98c 100644 --- a/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c +++ b/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c @@ -1018,18 +1018,18 @@ sl_status_t sli_clock_manager_hal_wait_usbpll(void) } /***************************************************************************//** - * Updates QSPI clock and reference clock. + * Sets the external FLASH reference clock. ******************************************************************************/ -sl_status_t sli_clock_manager_hal_update_qspi_clk(sl_oscillator_t oscillator) +sl_status_t sli_clock_manager_hal_set_ext_flash_clk(sl_oscillator_t oscillator) { (void)oscillator; return SL_STATUS_NOT_AVAILABLE; } /***************************************************************************//** - * Gets QSPI clock source. + * Gets the external FLASH clock source. ******************************************************************************/ -sl_status_t sli_clock_manager_get_current_qspi_clk(sl_oscillator_t *oscillator) +sl_status_t sli_clock_manager_hal_get_ext_flash_clk(sl_oscillator_t *oscillator) { if (oscillator == NULL) { return SL_STATUS_NULL_POINTER; diff --git a/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c b/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c index 7173f92b79..e7dcd402ed 100644 --- a/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c +++ b/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c @@ -154,17 +154,18 @@ FUNCTION_SCOPE sl_status_t init_hfxo(void) int ctune = -1; -#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 #if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) // Use HFXO tuning value from DEVINFO if available (PCB modules) if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; } -#endif #endif // Use HFXO tuning value from MFG token in UD page if not already set if ((ctune == -1) +#if defined(SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN) + && (SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN == 1) +#endif && (MFG_CTUNE_HFXO_VAL <= (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT))) { ctune = MFG_CTUNE_HFXO_VAL; } @@ -307,6 +308,9 @@ FUNCTION_SCOPE sl_status_t init_lfxo(void) #endif if ((clock_manager_lfxo_init.capTune == 0xFF) +#if defined(SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN) + && (SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN == 1) +#endif && (MFG_CTUNE_LFXO_VAL <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT))) { clock_manager_lfxo_init.capTune = MFG_CTUNE_LFXO_VAL; } diff --git a/platform/service/clock_manager/src/sl_clock_manager_oscillator_calibration_override.c b/platform/service/clock_manager/src/sl_clock_manager_oscillator_calibration_override.c new file mode 100644 index 0000000000..b6ac01de73 --- /dev/null +++ b/platform/service/clock_manager/src/sl_clock_manager_oscillator_calibration_override.c @@ -0,0 +1,118 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager Oscillator Calibration Override API implementations. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_clock_manager.h" +#include "sl_clock_manager_oscillator_calibration_override.h" +#include "nvm3.h" + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +// Allocated range of NVM3 IDs for oscillator calibration usage */ +#define HFXO_CTUNE_NVM3_RESERVED_ID (0x89800UL) + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Configure Oscillator CTune settings using key values stored in NVM3. + ******************************************************************************/ +sl_status_t sl_clock_manager_init_oscillator_calibration_override(void) +{ + sl_status_t status = SL_STATUS_OK; + uint32_t hfxo_calibration; + + status = sl_clock_manager_read_hfxo_calibration_override(&hfxo_calibration); + + if (status != SL_STATUS_OK ) { + return status; + } + + status = slx_clock_manager_hfxo_calibrate_ctune(hfxo_calibration); + + return status; +} + +/***************************************************************************//** + * Write HFXO calibration value to NVM3. + ******************************************************************************/ +sl_status_t sl_clock_manager_write_hfxo_calibration_override(uint32_t ctune) +{ + // Ensure CTUNE value is within the allowable range. + if (ctune > (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_status_t status; + nvm3_ObjectKey_t object_id = HFXO_CTUNE_NVM3_RESERVED_ID; + + // Write NVM3 HFXO calibration value. + status = nvm3_writeData(nvm3_defaultHandle, object_id, &ctune, sizeof(ctune)); + + return status; +} + +/***************************************************************************//** + * Read HFXO calibration value from NVM3. + ******************************************************************************/ +sl_status_t sl_clock_manager_read_hfxo_calibration_override(uint32_t *ctune) +{ + // Ensure CTUNE is not NULL. + if (ctune == NULL ) { + return SL_STATUS_NULL_POINTER; + } + + sl_status_t status; + nvm3_ObjectKey_t object_id = HFXO_CTUNE_NVM3_RESERVED_ID; + + // Read NVM3 HFXO calibration value. + status = nvm3_readData(nvm3_defaultHandle, object_id, ctune, sizeof(ctune)); + + if (status == SL_STATUS_NOT_FOUND) { + *ctune = 0xFFFF; + } + + return status; +} + +/***************************************************************************//** + * Delete HFXO calibration value from NVM3. + ******************************************************************************/ +sl_status_t sl_clock_manager_delete_hfxo_calibration_override(void) +{ + sl_status_t status; + nvm3_ObjectKey_t object_id = HFXO_CTUNE_NVM3_RESERVED_ID; + + status = nvm3_deleteObject(nvm3_defaultHandle, object_id); + + return status; +} diff --git a/platform/service/clock_manager/src/sli_clock_manager_hal.h b/platform/service/clock_manager/src/sli_clock_manager_hal.h index 695ab87727..bb7e3f758a 100644 --- a/platform/service/clock_manager/src/sli_clock_manager_hal.h +++ b/platform/service/clock_manager/src/sli_clock_manager_hal.h @@ -162,11 +162,13 @@ sl_status_t sli_clock_manager_hal_get_rco_calibration_count(uint32_t *count); /***************************************************************************//** * Sets SYSCLK clock source. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_clock_manager_hal_set_sysclk_source(sl_oscillator_t source); /***************************************************************************//** * Gets SYSCLK clock source. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_clock_manager_hal_get_sysclk_source(sl_oscillator_t *source); /***************************************************************************//** @@ -175,19 +177,19 @@ sl_status_t sli_clock_manager_hal_get_sysclk_source(sl_oscillator_t *source); sl_status_t sli_clock_manager_hal_wait_usbpll(void); /***************************************************************************//** - * Updates QSPI clock and reference clock. + * Sets the external FLASH reference clock. * * @note This API is not thread-safe and should therefore not be called - across multiple tasks. + * across multiple tasks. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -sl_status_t sli_clock_manager_hal_update_qspi_clk(sl_oscillator_t oscillator); +sl_status_t sli_clock_manager_hal_set_ext_flash_clk(sl_oscillator_t oscillator); /***************************************************************************//** - * Gets QSPI clock source. + * Gets the external FLASH clock source. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -sl_status_t sli_clock_manager_get_current_qspi_clk(sl_oscillator_t *oscillator); +sl_status_t sli_clock_manager_hal_get_ext_flash_clk(sl_oscillator_t *oscillator); #ifdef __cplusplus } diff --git a/platform/service/component/clock_manager_oscillator_calibration_override.slcc b/platform/service/component/clock_manager_oscillator_calibration_override.slcc new file mode 100644 index 0000000000..284421ec3c --- /dev/null +++ b/platform/service/component/clock_manager_oscillator_calibration_override.slcc @@ -0,0 +1,32 @@ +id: clock_manager_oscillator_calibration_override +label: Clock Manager Calibration Override +package: platform +description: > + The Clock Manager Oscillator Calibration Override module provides an API to initialize oscillator calibration settings + using override key values stored in NVM. The module also provides API's to read and modify specific oscillator calibration + override values stored in NVM. +category: Services|Clock Manager +quality: production +metadata: + sbom: + license: Zlib +provides: + - name: clock_manager_oscillator_calibration_override +requires: + - name: nvm3 + - name: clock_manager_runtime +root_path: platform/service/clock_manager +source: + - path: src/sl_clock_manager_oscillator_calibration_override.c +include: + - path: inc + file_list: + - path: sl_clock_manager_oscillator_calibration_override.h +template_contribution: + - name: event_handler + value: + event: platform_init + include: sl_clock_manager_oscillator_calibration_override.h + handler: sl_clock_manager_init_oscillator_calibration_override + priority: 9999 + condition: [sl_system] \ No newline at end of file diff --git a/platform/service/component/interrupt_manager.slcc b/platform/service/component/interrupt_manager.slcc index 1571166ec9..c4f8ad80fb 100644 --- a/platform/service/component/interrupt_manager.slcc +++ b/platform/service/component/interrupt_manager.slcc @@ -31,6 +31,8 @@ requires: - name: status - name: cmsis_core - name: component_catalog + - name: interrupt_manager_vector_table_in_ram + condition: [device_series_3] template_contribution: - name: component_catalog value: interrupt_manager diff --git a/platform/service/component/interrupt_manager_hooks.slcc b/platform/service/component/interrupt_manager_hooks.slcc new file mode 100644 index 0000000000..985a96ef17 --- /dev/null +++ b/platform/service/component/interrupt_manager_hooks.slcc @@ -0,0 +1,19 @@ +id: interrupt_manager_hooks +label: "interrupt Manager: Enable Hooks support." +package: platform +description: | + Specify that Interrupt Manager enables support for Hooks. +category: Services|Interrupt Manager +quality: production +metadata: + sbom: + license: Zlib +provides: + - name: interrupt_manager_hooks +requires: + - name: interrupt_manager + - name: interrupt_manager_vector_table_in_ram + - name: component_catalog +template_contribution: + - name: component_catalog + value: interrupt_manager_hooks diff --git a/platform/service/component/token_manager.slcc b/platform/service/component/token_manager.slcc index 2df5ed05c5..4578e550b7 100644 --- a/platform/service/component/token_manager.slcc +++ b/platform/service/component/token_manager.slcc @@ -53,9 +53,6 @@ template_contribution: - name: static_tokens_enable value: 1 condition: [device_series_3] - - name: userdata_size - value: 4096 - condition: [device_series_3] - name: lockbits_size value: 8192 condition: [device_series_3] diff --git a/platform/service/component/token_manager_test.slcc b/platform/service/component/token_manager_test.slcc deleted file mode 100644 index ff8a955dfd..0000000000 --- a/platform/service/component/token_manager_test.slcc +++ /dev/null @@ -1,21 +0,0 @@ -id: token_manager_test -label: Token Manager Test -package: platform -description: Tester component to satisfy the required compatible stack. -category: Services|Token Manager -quality: production -metadata: - sbom: - license: MSLA - -provides: - - name: wireless_stack - allow_multiple: true - -requires: - - name: test_framework_unity - -define: - - name: TOKEN_MANAGER_TEST - - name: "STACK_TYPES_HEADER" - value: "\"../test/stack/include/sl_zigbee_types.h\"" diff --git a/platform/service/cpc/inc/sl_cpc.h b/platform/service/cpc/inc/sl_cpc.h index 6430ff2635..644323167d 100644 --- a/platform/service/cpc/inc/sl_cpc.h +++ b/platform/service/cpc/inc/sl_cpc.h @@ -133,7 +133,7 @@ SL_ENUM(sl_cpc_endpoint_option_t){ #define SL_CPC_OPEN_ENDPOINT_FLAG_DISABLE_ENCRYPTION SL_CPC_ENDPOINT_FLAG_DISABLE_ENCRYPTION #define SL_CPC_MAJOR_VERSION 4 -#define SL_CPC_MINOR_VERSION 5 +#define SL_CPC_MINOR_VERSION 6 #define SL_CPC_PATCH_VERSION 0 /***************************************************************************//** diff --git a/platform/service/device_init/src/sl_device_init_hfxo_s2.c b/platform/service/device_init/src/sl_device_init_hfxo_s2.c index 1f9c32ace5..a65242be76 100644 --- a/platform/service/device_init/src/sl_device_init_hfxo_s2.c +++ b/platform/service/device_init/src/sl_device_init_hfxo_s2.c @@ -47,13 +47,11 @@ sl_status_t sl_device_init_hfxo(void) int ctune = -1; -#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 #if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) // Use HFXO tuning value from DEVINFO if available (PCB modules) if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; } -#endif #endif // Use HFXO tuning value from MFG token in UD page if not already set diff --git a/platform/service/device_init/src/sl_device_init_lfxo_s2.c b/platform/service/device_init/src/sl_device_init_lfxo_s2.c index ed3264516b..8096521e0e 100644 --- a/platform/service/device_init/src/sl_device_init_lfxo_s2.c +++ b/platform/service/device_init/src/sl_device_init_lfxo_s2.c @@ -45,13 +45,11 @@ sl_status_t sl_device_init_lfxo(void) int ctune = -1; -#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 #if defined(_DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) // Use LFXO tuning value from DEVINFO if available (PCB modules) if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_LFXOCALVAL_MASK) == _DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK; } -#endif #endif // Use LFXO tuning value from MFG token in UD page if not already set diff --git a/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c b/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c index 42552c66cd..cfeb5c4dd4 100644 --- a/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c +++ b/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c @@ -58,16 +58,14 @@ #define VECTOR_TABLE_ALIGNMENT (512) // Interrupt vector placement is in RAM -#if defined(_SILICON_LABS_32B_SERIES_3) \ - || (defined(SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM) \ - && (SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM == 1)) \ +#if (defined(SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM) \ + && (SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM == 1)) \ || defined(SL_CATALOG_INTERRUPT_MANAGER_VECTOR_TABLE_IN_RAM_PRESENT) #define VECTOR_TABLE_IN_RAM (1) #endif -// Interrupt manager ISR hooks are enabled. The interrupt vector must be in RAM. -#if defined(VECTOR_TABLE_IN_RAM) && defined(_SILICON_LABS_32B_SERIES_3) -#define SL_INTERRUPT_MANAGER_HOOKS_ENABLED (1) +#if defined(SL_CATALOG_INTERRUPT_MANAGER_HOOKS_PRESENT) +#define SL_INTERRUPT_MANAGER_ENABLE_HOOKS (1) #endif // Interrupt vector table need to be in a different section of RAM for Cortex-M55. @@ -95,7 +93,7 @@ static sl_interrupt_manager_irq_handler_t vector_table_ram[TOTAL_INTERRUPTS] __a static sl_interrupt_manager_irq_handler_t vector_table_ram[TOTAL_INTERRUPTS] VECTOR_TABLE_SECTION; #endif /* defined(__GNUC__) */ -#if defined(SL_INTERRUPT_MANAGER_HOOKS_ENABLED) +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) // When interrupt manager hooks are enabled, the actual vector table (either in // ram or in flash) will call an ISR wrapper. The actual ISRs will be registered // and called from the wrapped_vector_table. @@ -105,7 +103,7 @@ static sl_interrupt_manager_irq_handler_t wrapped_vector_table[TOTAL_INTERRUPTS] #pragma data_alignment = VECTOR_TABLE_ALIGNMENT static sl_interrupt_manager_irq_handler_t wrapped_vector_table[TOTAL_INTERRUPTS] VECTOR_TABLE_SECTION; #endif /* defined(__GNUC__) */ -#endif /* SL_INTERRUPT_MANAGER_HOOKS_ENABLED */ +#endif /* SL_INTERRUPT_MANAGER_ENABLE_HOOKS */ #endif /* VECTOR_TABLE_IN_RAM */ @@ -117,7 +115,7 @@ static void disable_interrupt(int32_t irqn); static void set_priority(int32_t irqn, uint32_t priority); static uint32_t get_priority(int32_t irqn); -#if defined(SL_INTERRUPT_MANAGER_HOOKS_ENABLED) +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) #if defined(SL_CATALOG_CODE_CLASSIFICATION_VALIDATOR_PRESENT) CCV_SECTION #endif @@ -136,7 +134,7 @@ static bool is_interrupt_manager_initialized = false; ******************************************************************************/ #if defined(VECTOR_TABLE_IN_RAM) -#if defined(SL_INTERRUPT_MANAGER_HOOKS_ENABLED) +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) __WEAK void sl_interrupt_manager_irq_enter_hook(void) { @@ -227,7 +225,7 @@ void sl_interrupt_manager_init(void) // copy ROM vector table to RAM table for (uint32_t i = 0; i < TOTAL_INTERRUPTS; i++) { - #if defined(SL_INTERRUPT_MANAGER_HOOKS_ENABLED) + #if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) wrapped_vector_table[i] = current[i]; if ( i >= CORTEX_INTERRUPTS ) { vector_table_ram[i] = sli_interrupt_manager_isr_wrapper; @@ -417,11 +415,11 @@ sl_status_t sl_interrupt_manager_set_irq_handler(int32_t irqn, // Disable irqn interrupt while updating the handler's address sl_interrupt_manager_disable_irq(irqn); - #if defined(SL_INTERRUPT_MANAGER_HOOKS_ENABLED) + #if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) table = wrapped_vector_table; #else table = (sl_interrupt_manager_irq_handler_t*)SCB->VTOR; - #endif /* SL_INTERRUPT_MANAGER_HOOKS_ENABLED */ + #endif /* SL_INTERRUPT_MANAGER_ENABLE_HOOKS */ // Make sure the VTOR points to a table in RAM. if (((uint32_t)table < RAM_BASE) || (uint32_t)table > (RAM_BASE + RAM_SIZE)) { @@ -595,9 +593,9 @@ uint32_t get_priority(int32_t irqn) ******************************************************************************/ sl_interrupt_manager_irq_handler_t* sl_interrupt_manager_get_isr_table(void) { -#if defined(SL_INTERRUPT_MANAGER_HOOKS_ENABLED) +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) return wrapped_vector_table; #else return (sl_interrupt_manager_irq_handler_t*)SCB->VTOR; -#endif /* SL_INTERRUPT_MANAGER_HOOKS_ENABLED */ +#endif /* SL_INTERRUPT_MANAGER_ENABLE_HOOKS */ } diff --git a/platform/service/interrupt_manager/src/sli_interrupt_manager.h b/platform/service/interrupt_manager/src/sli_interrupt_manager.h index cc0780566f..4da329da4c 100644 --- a/platform/service/interrupt_manager/src/sli_interrupt_manager.h +++ b/platform/service/interrupt_manager/src/sli_interrupt_manager.h @@ -77,7 +77,7 @@ sl_interrupt_manager_irq_handler_t *sli_interrupt_manager_set_irq_table(sl_inter * * @details * This function is called before each interrupt service routine - * when SL_INTERRUPT_MANAGER_HOOKS is enabled. + * when the interrupt manager hooks feature is enabled. * * @note * The function is weakly defined, and may be user-defined. By default, the @@ -91,7 +91,7 @@ void sl_interrupt_manager_irq_enter_hook(void); * * @details * This function is called after each interrupt service routine - * when SL_INTERRUPT_MANAGER_HOOKS is enabled. + * when the interrupt manager hooks feature is enabled. * * @note * The function is weakly defined, and may be user-defined. By default, the diff --git a/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h b/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h index 085b27aaa3..b7f0be00f2 100644 --- a/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h +++ b/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h @@ -75,8 +75,15 @@ // Enable QSPI clock switch for sleep // Enable/Disable the QSPI clock switching when entering sleep. // By default the QSPI clock uses a PLL. To further reduce the power consumption in sleep, the QSPI can be switched to a RCO oscillator during the sleep period. +// Default: 0 +#define SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN 0 +// + +// Enable SYSCLK on SOCPLL to switch to HFXO for sleep +// Enable/Disable the SYSCLK switching to HFXO when entering sleep. +// By default SYSCLK uses a SOCPLL. To further reduce the power consumption in sleep, the SYSCLK can be switched to HFXO during the sleep period. // Default: 1 -#define SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN 1 +#define SL_POWER_MANAGER_SYSCLK_SWITCH_TO_HFXO_IN_SLEEP_EN 1 // // diff --git a/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_sixg301.c b/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_sixg301.c index dea193639d..16d3631561 100644 --- a/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_sixg301.c +++ b/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_sixg301.c @@ -38,7 +38,7 @@ #include "sl_component_catalog.h" #endif #include "sl_clock_manager.h" -#include "sli_clock_manager_hal.h" +#include "sli_clock_manager.h" #include #if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) @@ -49,8 +49,15 @@ *************************** LOCAL VARIABLES ******************************** ******************************************************************************/ +#if defined(SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN) && (SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN == 1) +static sl_oscillator_t qspi_reference_clock; +#endif + +#if defined(SL_POWER_MANAGER_SYSCLK_SWITCH_TO_HFXO_IN_SLEEP_EN) && (SL_POWER_MANAGER_SYSCLK_SWITCH_TO_HFXO_IN_SLEEP_EN == 1) +static bool em1hclkdiv_sysclk_switch_en; +#endif + static uint32_t sysclk_prescalers_value; -sl_oscillator_t qspi_reference_clock; /***************************************************************************//** * Do some hardware initialization if necessary. @@ -152,13 +159,27 @@ uint32_t sli_power_manager_get_wakeup_process_time_overhead(void) ******************************************************************************/ void sli_power_manager_em1hclkdiv_presleep_operations(void) { -#if defined(SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN) && (SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN == 1) sl_status_t status; + sl_oscillator_t osc; + + // Retrieve SYSCLK oscillator + status = sli_clock_manager_get_sysclk_source(&osc); + EFM_ASSERT(status == SL_STATUS_OK); + +#if defined(SL_POWER_MANAGER_SYSCLK_SWITCH_TO_HFXO_IN_SLEEP_EN) && (SL_POWER_MANAGER_SYSCLK_SWITCH_TO_HFXO_IN_SLEEP_EN == 1) + // Change SYSCLK to HFXO if on SOCPLL to reduce power consumption + if (osc == SL_OSCILLATOR_SOCPLL) { + em1hclkdiv_sysclk_switch_en = true; + sli_clock_manager_set_sysclk_source(SL_OSCILLATOR_HFXO); + } +#endif + +#if defined(SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN) && (SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN == 1) // Save current QSPI reference clock. - status = sli_clock_manager_get_current_qspi_clk(&qspi_reference_clock); + status = sl_clock_manager_get_ext_flash_clk(&qspi_reference_clock); EFM_ASSERT(status == SL_STATUS_OK); // Update QSPI clock source. - status = sli_clock_manager_hal_update_qspi_clk(SL_OSCILLATOR_FSRCO); + status = sl_clock_manager_set_ext_flash_clk(SL_OSCILLATOR_FSRCO); EFM_ASSERT(status == SL_STATUS_OK); #endif } @@ -168,10 +189,18 @@ void sli_power_manager_em1hclkdiv_presleep_operations(void) ******************************************************************************/ void sli_power_manager_em1hclkdiv_postsleep_operations(void) { +#if defined(SL_POWER_MANAGER_SYSCLK_SWITCH_TO_HFXO_IN_SLEEP_EN) && (SL_POWER_MANAGER_SYSCLK_SWITCH_TO_HFXO_IN_SLEEP_EN == 1) + // Switch back SYSCLK to SOCPLL if necessary + if (em1hclkdiv_sysclk_switch_en) { + sli_clock_manager_set_sysclk_source(SL_OSCILLATOR_SOCPLL); + em1hclkdiv_sysclk_switch_en = false; + } +#endif + #if defined(SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN) && (SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN == 1) sl_status_t status; // Restore original QSPI clock source. - status = sli_clock_manager_hal_update_qspi_clk(qspi_reference_clock); + status = sl_clock_manager_set_ext_flash_clk(qspi_reference_clock); EFM_ASSERT(status == SL_STATUS_OK); #endif } diff --git a/platform/service/token_manager/inc/sl_token_api.h b/platform/service/token_manager/inc/sl_token_api.h index 2a6ff05b1a..f9aa273f35 100644 --- a/platform/service/token_manager/inc/sl_token_api.h +++ b/platform/service/token_manager/inc/sl_token_api.h @@ -105,4 +105,6 @@ void halInternalSetTokenData(uint16_t token, uint8_t index, void *data, uint8_t void halInternalIncrementCounterToken(uint8_t token); +void sl_token_mfg_init(void); + #endif // _TOKEN_API_H_ diff --git a/platform/service/token_manager/inc/sl_token_manufacturing_api.h b/platform/service/token_manager/inc/sl_token_manufacturing_api.h index dd2bdc7b3d..f0022ca6f0 100644 --- a/platform/service/token_manager/inc/sl_token_manufacturing_api.h +++ b/platform/service/token_manager/inc/sl_token_manufacturing_api.h @@ -43,16 +43,11 @@ // In non-Series2 devices the top page of flash is free for all existing prior uses. #define LOCKBITS_BASE ((FLASH_BASE + FLASH_SIZE) - FLASH_PAGE_SIZE) #elif defined(_SILICON_LABS_32B_SERIES_3) -// In Series3, USER DATA and LOCK BITS region are defined in the Host data region -// 3 flash pages have been reserved. -// Outof which 1 flash page (at the end of flash) is reserved for USER DATA and -// 2 flash pages reserved for LOCKBITS DATA. +// In Series3, LOCK BITS region is defined in the Host data region, +// 2 flash pages have been reserved for LOCKBITS DATA(at the end of flash). #define NUM_OF_FLASH_PAGES 2U -#define USER_DATA_SIZE FLASH_PAGE_SIZE #define LOCKBITS_DATA_SIZE (NUM_OF_FLASH_PAGES * FLASH_PAGE_SIZE) -#define USERDATA_BASE (FLASH_BASE + FLASH_SIZE - USER_DATA_SIZE) -#define USERDATA_END (USERDATA_BASE + USER_DATA_SIZE) -#define LOCKBITS_BASE (USERDATA_BASE - LOCKBITS_DATA_SIZE) +#define LOCKBITS_BASE (FLASH_BASE + FLASH_SIZE - LOCKBITS_DATA_SIZE) #define LOCKBITS_END (LOCKBITS_BASE + LOCKBITS_DATA_SIZE) #else #error The flash map of manufacturing tokens is not configured for this device diff --git a/platform/service/token_manager/src/sl_token_manager.c b/platform/service/token_manager/src/sl_token_manager.c index 4c5a7c3d9e..24cc54911d 100644 --- a/platform/service/token_manager/src/sl_token_manager.c +++ b/platform/service/token_manager/src/sl_token_manager.c @@ -80,6 +80,13 @@ sl_status_t sl_token_init(void) sl_status_t slStatus, status; nvm3_HalInfo_t halInfo; +#if !defined(NVM3_OVERRIDE_ENABLE) + //TODO: For now all the tokens are stored in NVM3. + //Below INIT should be enabled, once we enable the flash access via SE. + //Manufacturing init + sl_token_mfg_init(); +#endif + slStatus = nvm3_open(nvm3_defaultHandle, nvm3_defaultInit); TOKENDBG(printf("halStackInitTokens nvm3_open status: 0x%0lx\r\n", slStatus); ) if (slStatus != SL_STATUS_OK) { diff --git a/platform/service/token_manager/src/sl_token_manufacturing.c b/platform/service/token_manager/src/sl_token_manufacturing.c index 093b227d47..c19398cedb 100644 --- a/platform/service/token_manager/src/sl_token_manufacturing.c +++ b/platform/service/token_manager/src/sl_token_manufacturing.c @@ -32,6 +32,11 @@ #include "sl_se_manager_util.h" #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#if defined(_SILICON_LABS_32B_SERIES_3) +#include "sl_se_manager.h" +#include "sl_se_manager_extmem.h" +#endif //_SILICON_LABS_32B_SERIES_3 + #define DEFINETOKENS #define TOKEN_MFG(name, creator, iscnt, isidx, type, arraysize, ...) \ const uint16_t TOKEN_##name = TOKEN_##name##_ADDRESS; @@ -95,10 +100,14 @@ static void getMfgTokenData(void *data, i++; } } else if ((token & 0xF000) == (USERDATA_TOKENS & 0xF000)) { +#if (_SILICON_LABS_32B_SERIES == 2) uint32_t realAddress = ((USERDATA_BASE + (token & 0x0FFF)) + (len * index)); uint8_t *flash = (uint8_t *)realAddress; memcpy(ram, flash, len); +#elif (_SILICON_LABS_32B_SERIES == 3) + //TODO: Handle UD data write into SE MTP region once the API's are available. +#endif } else if (((token & 0xF000) == (LOCKBITS_TOKENS & 0xF000)) || ((token & 0xF000) == (LOCKBITSDATA_TOKENS & 0xF000))) { uint32_t realAddress = ((LOCKBITS_BASE + (token & 0x0FFF)) + (len * index)); @@ -280,8 +289,11 @@ sl_status_t halInternalFlashWrite(uint32_t address, uint16_t *data, uint32_t len return SL_STATUS_OK; } -// Odd len is not supported by this function -static void halFlashWrite(uint32_t realAddress, void *data, uint32_t len) +/***************************************************************************//** + * This function is used to write data to the User or Lockbits page. + * Odd len is not supported by this function + ******************************************************************************/ +static void hal_flash_write(uint32_t realAddress, void *data, uint32_t len) { sl_status_t flashStatus = SL_STATUS_FAIL; flashStatus = halInternalFlashWrite(realAddress, (uint16_t*)data, (len / 2)); @@ -290,6 +302,84 @@ static void halFlashWrite(uint32_t realAddress, void *data, uint32_t len) #endif +#if defined(_SILICON_LABS_32B_SERIES_3) +#define CHECK_DATA 1 ///< Macro defining if data should be checked +/***************************************************************************//** + * Open the MFG hal for usage. SE will take care of clocking the externalflash. + * This function initializes the SE lock mutex and checks if LOCKBITS + * start and end addresses are within the data region or not. + ******************************************************************************/ +static sl_status_t hal_external_flash_open(void) +{ + sl_status_t slStatus; + void *startAdr; + size_t regSize; + sl_se_command_context_t cmd_ctx; + + slStatus = sl_se_init(); + + if (slStatus != SL_STATUS_OK) { + return SL_STATUS_NOT_INITIALIZED; + } + + sl_se_init_command_context(&cmd_ctx); + slStatus = sl_se_data_region_get_location(&cmd_ctx, &startAdr, ®Size); + + if (slStatus == SL_STATUS_OK) { + // Check if LOCKBITS page's start and end addresses are within the data region or not + if (((size_t)LOCKBITS_BASE < (size_t)startAdr) || (((size_t)LOCKBITS_END) > ((size_t)startAdr + regSize))) { + return SL_STATUS_INVALID_PARAMETER; + } + } else { + return SL_STATUS_INVALID_STATE; + } + + return slStatus; +} + +/***************************************************************************//** + * This function is used to write data to the LOCKBITS page, using SE API. + ******************************************************************************/ +static void hal_external_flash_write(uint32_t dstAdr, void const *src, size_t length) +{ + sl_status_t slStatus; + sl_se_command_context_t cmd_ctx; + size_t byte_count = length; + size_t word_count = byte_count / sizeof(uint32_t); + + //make it word aligned + if ((byte_count % sizeof(uint32_t)) != 0) { + word_count = word_count + 1; + } + + sl_se_init_command_context(&cmd_ctx); + slStatus = sl_se_data_region_write(&cmd_ctx, (void *)dstAdr, src, (word_count * sizeof(uint32_t))); + +#if CHECK_DATA + if (slStatus == SL_STATUS_OK) { + if (memcmp((void *)dstAdr, src, byte_count) != 0) { + slStatus = SL_STATUS_FAIL; + } + } +#endif + + assert(slStatus == SL_STATUS_OK); +} +#endif + +/***************************************************************************//** + * This function is used to initialize SE + ******************************************************************************/ +void sl_token_mfg_init(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_status_t slStatus; + //Init SE manager + slStatus = hal_external_flash_open(); + assert(slStatus == SL_STATUS_OK); +#endif +} + #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) static void halFlashWriteSE(uint32_t realAddress, void *data, uint32_t len) { @@ -299,7 +389,7 @@ static void halFlashWriteSE(uint32_t realAddress, void *data, uint32_t len) status = sl_se_write_user_data(&cmd_ctx, (realAddress & 0x0FFF), data, len); assert(status == SL_STATUS_OK); } else { - halFlashWrite(realAddress, data, len); + hal_flash_write(realAddress, data, len); } } #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) @@ -316,12 +406,13 @@ static void halFlashWriteSE(uint32_t realAddress, void *data, uint32_t len) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) #define FLASHWRITE(realAddress, data, len) \ - (halFlashWrite((realAddress), (data), (len))) + (hal_flash_write((realAddress), (data), (len))) #else #error Unknown device configuration #endif #elif (_SILICON_LABS_32B_SERIES == 3) -//TODO:Handle S3 flash write by using SE APIs +#define FLASHWRITE(realAddress, data, len) \ + (hal_external_flash_write((realAddress), (data), (len))) #else #error Unknown device series #endif @@ -394,11 +485,14 @@ sl_status_t sl_token_set_manufacturing_data(uint32_t token, return status; } -#if (_SILICON_LABS_32B_SERIES == 2) if ((token & 0xF000) == (USERDATA_TOKENS & 0xF000)) { +#if (_SILICON_LABS_32B_SERIES == 2) realAddress = ((USERDATA_BASE + (token & 0x0FFF))); flash = (uint8_t *)realAddress; assert((realAddress >= USERDATA_BASE) && ((realAddress + length - 1) <= USERDATA_END)); +#elif (_SILICON_LABS_32B_SERIES == 3) + //TODO: Handle UD data write into SE MTP region once the API's are available. +#endif } else if (((token & 0xF000) == (LOCKBITS_TOKENS & 0xF000)) || ((token & 0xF000) == (LOCKBITSDATA_TOKENS & 0xF000))) { realAddress = ((LOCKBITS_BASE + (token & 0x0FFF))); @@ -408,6 +502,7 @@ sl_status_t sl_token_set_manufacturing_data(uint32_t token, assert(0); } +#if (_SILICON_LABS_32B_SERIES == 2) //UserData and LockBits manufacturing tokens can only be written by on-chip //code if the token is currently unprogrammed. Verify the entire token is //unwritten. The flash library performs a similar check, but verifying here @@ -441,17 +536,13 @@ sl_status_t sl_token_set_manufacturing_data(uint32_t token, length -= 2; writeEndWord(realAddress, data, length); } - - if (length > 0) { - FLASHWRITE(realAddress, data, length); - } - #elif (_SILICON_LABS_32B_SERIES == 3) - //TODO: Handle flash write specific to S3 - (void) realAddress; (void) flash; (void) i; #endif + if (length > 0) { + FLASHWRITE(realAddress, data, length); + } return SL_STATUS_OK; } diff --git a/protocol/bluetooth/api/sl_bt.xapi b/protocol/bluetooth/api/sl_bt.xapi index 38d0cb7a11..1bb17b17b7 100644 --- a/protocol/bluetooth/api/sl_bt.xapi +++ b/protocol/bluetooth/api/sl_bt.xapi @@ -1,5 +1,5 @@ - + diff --git a/protocol/bluetooth/api/sl_btmesh.xapi b/protocol/bluetooth/api/sl_btmesh.xapi index 1051f0ad1d..a34eef4eaa 100644 --- a/protocol/bluetooth/api/sl_btmesh.xapi +++ b/protocol/bluetooth/api/sl_btmesh.xapi @@ -1,5 +1,5 @@ - + diff --git a/protocol/bluetooth/api/sli_bgapi_debug.xapi b/protocol/bluetooth/api/sli_bgapi_debug.xapi index a6c8d05edc..09d8199809 100644 --- a/protocol/bluetooth/api/sli_bgapi_debug.xapi +++ b/protocol/bluetooth/api/sli_bgapi_debug.xapi @@ -1,5 +1,5 @@ - + diff --git a/protocol/bluetooth/apploader/build/gcc/cortex-m33/release/libapploader.a b/protocol/bluetooth/apploader/build/gcc/cortex-m33/release/libapploader.a index ad9b295724..1134ab2a77 100644 --- a/protocol/bluetooth/apploader/build/gcc/cortex-m33/release/libapploader.a +++ b/protocol/bluetooth/apploader/build/gcc/cortex-m33/release/libapploader.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0dc451f6a6818efa58fb34fba5e657dfd39a1970abf95f85b96a80002a963922 +oid sha256:1ed26d5982e3289b85391f8d71cc1488de7a38e11c0d971b987ad5bb8e9f8b8f size 73080 diff --git a/protocol/bluetooth/apploader/build/iar/cortex-m33/release/libapploader.a b/protocol/bluetooth/apploader/build/iar/cortex-m33/release/libapploader.a index 834f434c0d..e9eefb3391 100644 --- a/protocol/bluetooth/apploader/build/iar/cortex-m33/release/libapploader.a +++ b/protocol/bluetooth/apploader/build/iar/cortex-m33/release/libapploader.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bc136e1fed028abff2ee8088d8e5783a7c051323ac7fdccdeafbfb9be2c41277 +oid sha256:7cb27378fb540bdd5c579f77f5f66ee0700d11a88b5f21d7d0c4a93b4c21d28e size 167358 diff --git a/protocol/bluetooth/bgcommon/lib/build/gcc/cortex-m33/bgcommon/release/libbgcommon.a b/protocol/bluetooth/bgcommon/lib/build/gcc/cortex-m33/bgcommon/release/libbgcommon.a index 4d95f4905f..7a5758bd4b 100644 --- a/protocol/bluetooth/bgcommon/lib/build/gcc/cortex-m33/bgcommon/release/libbgcommon.a +++ b/protocol/bluetooth/bgcommon/lib/build/gcc/cortex-m33/bgcommon/release/libbgcommon.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f562d2d1f340181ec43ddfa2d6c5c1cb278f6689a0eedc92bc95e001ff2b0a7b +oid sha256:571bd2d7c6eb21b6103818c5359039b873495cdf627c8992cb90397b25147eab size 50616 diff --git a/protocol/bluetooth/bgcommon/lib/build/iar/cortex-m33/bgcommon/release/libbgcommon.a b/protocol/bluetooth/bgcommon/lib/build/iar/cortex-m33/bgcommon/release/libbgcommon.a index 6736c97538..1fe72e5d1e 100644 --- a/protocol/bluetooth/bgcommon/lib/build/iar/cortex-m33/bgcommon/release/libbgcommon.a +++ b/protocol/bluetooth/bgcommon/lib/build/iar/cortex-m33/bgcommon/release/libbgcommon.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:43e446e4d4ca3f4725a878b265fb44638d400d589b6cf37ac403ddf89d9c32df +oid sha256:51067d67a7e1cfb2e11466a32ed7c90bcefed889459855f2d0d7d4799d9bca4f size 113938 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/x301/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/x301/release/liblinklayer.a index 9d58efd865..a9494c3fbf 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/x301/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/x301/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c846c9913ed80ff3189e67f1a41c5e14239abdf53aa64c804c68f52b27128b83 -size 2494388 +oid sha256:8f195db7c0486c4eb622d8bc9980bd1dfb7228f7ef74866d18baf6b73eb5f8bf +size 2499084 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/xg21/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/xg21/release/liblinklayer.a index d0a68efc2e..98bc033fd6 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/xg21/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/xg21/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6e1b2f043ac214e3bb01e060e502342c2d86a0f1264cb8adf6b90ec09cf63774 -size 2495368 +oid sha256:002ffc153cd463c0608804b9392f4bbf4f0f3c693b24f733eadfca4b7910449c +size 2497398 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/xg22/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/xg22/release/liblinklayer.a index d2804bc792..53edc9d3e4 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/xg22/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/xg22/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:77b50c2d3c22c4f23a848d719737f4c0fd6efe764458739559cb36b9554b996b -size 2496192 +oid sha256:1c8bb19c241a6cf7c9b7d8ea28cc87a35f45b696355c6fb814dc011cdb066fcd +size 2498222 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/xg24/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/xg24/release/liblinklayer.a index e8a09c0cc9..410adf171d 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/xg24/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/xg24/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8f8c77f3eeb612efc2523ae9dacf520ecc61a61319838a5868c5c8383a56870d -size 2496192 +oid sha256:2442c2e6cfa6924d8c4929c1a2589634f459f965c5a55b9a72ed75cf8e033ffe +size 2498222 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/xg26/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/xg26/release/liblinklayer.a index a1fd2cd5ec..6cea94781f 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/xg26/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/xg26/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5dc262db47d63f9471c27d1ace4e23e2c3e5dc0c4d734e0f8c15736dae5450fa -size 2496192 +oid sha256:266a01aaf44cbbf073ee5c49086dcdf90bf8ecb59c930ae359c5a93d142a09cc +size 2498222 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/xg27/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/xg27/release/liblinklayer.a index 81af751e27..0340ad6a67 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/xg27/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/xg27/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f7c7e60a3dde8b38fd7ef0d8e374f0fb1d1e9828b434a2ea717bf1125c53a40b -size 2496192 +oid sha256:cde5a7a78183db552c6b59a0937b247e4eeb7fc91f752a3524e7f457d943629d +size 2498222 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/xg28/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/xg28/release/liblinklayer.a index 604e96d471..b2e5a009c5 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/xg28/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/xg28/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:578d240d187a16917dde73a8d354534481719d64c9b3b79ae3f2a52df4757a21 -size 2496192 +oid sha256:335597f071aa9e8e41c56158762822415c5d445cd2805423dbdc61eca600df8e +size 2498222 diff --git a/protocol/bluetooth/bgstack/ll/build/gcc/xg29/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/gcc/xg29/release/liblinklayer.a index c9a0c17197..2ffdf0ca78 100644 --- a/protocol/bluetooth/bgstack/ll/build/gcc/xg29/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/gcc/xg29/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:93579e2431c68423e06096065b8b6ac493e14400f7eb1f22ac1b248ac16332e1 -size 2496192 +oid sha256:135956848a756df779c2b0eb15ab720123f25110f96b695e5ddd318baac68202 +size 2498222 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/x301/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/x301/release/liblinklayer.a index 08b6a4c908..f35b5e0272 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/x301/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/x301/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b4030e0f45f7d91e8063265b7c219b316045282541625b35adfd912da920f5a2 -size 5319578 +oid sha256:1bb12578e601520eae0de1226cce53df7a1838255acf149faef54c45f321e96c +size 5322586 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/xg21/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/xg21/release/liblinklayer.a index e5ba026c75..e0ccb86a10 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/xg21/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/xg21/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9c51475b5469a2810daf79385bb1a26fa96cc6f30d1da03bc1c4f7b4bee4dd2f -size 5330756 +oid sha256:ee9cf8f03246244f3daddb12b66e9733036dd39170f14c0db8ba6187c54d5e48 +size 5337774 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/xg22/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/xg22/release/liblinklayer.a index 0cbb8f4b3c..6ff3755d39 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/xg22/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/xg22/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9831d3cd8e65aa47e41df78e5bef52dc92b23effbb8f85b2bc0bc8e2f8698746 -size 5332380 +oid sha256:0add75f1021c22d430072d6c289f66db8a20cc42a02c75fc5879cf1112c2df84 +size 5339400 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/xg24/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/xg24/release/liblinklayer.a index 9a69553c2a..b4fcd1e426 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/xg24/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/xg24/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:08ce5dbdb6ba91dc486c111182987638cb4878725f7e6cfda09aadceb27bb4b2 -size 5332380 +oid sha256:61cf021a6cbc6065fff14d1c76ea20fe7317ac1db59e87c7aece7e60042ea9c0 +size 5339400 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/xg26/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/xg26/release/liblinklayer.a index c29dc67212..5be168debe 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/xg26/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/xg26/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2469c6841e4a2c57ef24bbe6fdb6c92a5c2155ca9d0f11c639fefa5cc52d3eb5 -size 5332380 +oid sha256:e3cf705d69064a2c2cb1539d347a52b0bcb21e20ab81ee96cebd1c787ad94930 +size 5339400 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/xg27/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/xg27/release/liblinklayer.a index e50be87407..7729757106 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/xg27/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/xg27/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7548e954da25e12d1dbb4f68d43a4741421f961d8321832884fc50c33c2ef523 -size 5328184 +oid sha256:f1c893d1fa13f7935f5db4f707349562a054b256bd7e40f72dac9934a6391341 +size 5335204 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/xg28/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/xg28/release/liblinklayer.a index c77bbdf25c..d7cb23de91 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/xg28/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/xg28/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ffc82c9aac8f0ce32edd1517adf48025c374ba85ee153e466a6dbbe7f0acf6c1 -size 5332380 +oid sha256:171d86b2748b7166e0abb00709c3203f6074664714854cb4815781d125e6b9aa +size 5339400 diff --git a/protocol/bluetooth/bgstack/ll/build/iar/xg29/release/liblinklayer.a b/protocol/bluetooth/bgstack/ll/build/iar/xg29/release/liblinklayer.a index ed7cbb0cbf..e2fc1109f9 100644 --- a/protocol/bluetooth/bgstack/ll/build/iar/xg29/release/liblinklayer.a +++ b/protocol/bluetooth/bgstack/ll/build/iar/xg29/release/liblinklayer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b749e0425feec25cc2db2c4d87e08f020b6b2e9a788185f69969f9409266cfe2 -size 5332380 +oid sha256:6aea0096540d605574ce84507271437586b1a533ac9ccf2d28f20e415fd08a3d +size 5339400 diff --git a/protocol/bluetooth/bgstack/ll/inc/sl_bt_ll_config.h b/protocol/bluetooth/bgstack/ll/inc/sl_bt_ll_config.h index 7cd2d9cdd4..3949caab9e 100644 --- a/protocol/bluetooth/bgstack/ll/inc/sl_bt_ll_config.h +++ b/protocol/bluetooth/bgstack/ll/inc/sl_bt_ll_config.h @@ -54,6 +54,8 @@ typedef struct { #define SL_BT_BLUETOOTH_PRIORITIES_DEFAULT { 191, 143, 175, 127, 135, 0, 55, 15, 16, 16, 0, 4, 4, 15, 5, 20, 10 } #define SL_BT_BLUETOOTH_PA_AUTOMODE 0xff +#define SL_BT_BLUETOOTH_HIGHEST_PA 0xfe +#define SL_BT_BLUETOOTH_RAIL_UTIL_PA 0xfd #include "sl_common.h" SL_PACK_START(1) diff --git a/protocol/bluetooth/build/gcc/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a b/protocol/bluetooth/build/gcc/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a index 37b36a87c6..6176e13bf0 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3488ec9e11f2a1fda95c161ce60accdb1a7b1416cf1211156c2cba18ca313287 -size 16398 +oid sha256:71fcf8e065f6e39a08df5eff34395c1d98d202c2b1e2dd9848789daf791c6367 +size 16410 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a index 0c01d88cb8..d8456a2768 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3a83c0aca9503cf66236f72e82915893baec3d4d693eba6f89baa1f3d918162d -size 75974 +oid sha256:489ac99302e1b66d9bcfe117861b8c052e566ee8f7644fd751ca3ce162231f46 +size 76074 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a index 1f648144b7..dc59d4b7f6 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ad0e4ef93f0c03e13bf3ce65dc6f38e5356bc28ea44e8a22ff2ea9bdb84b38ff +oid sha256:51c9f658fb6492a3f46b1c0d67f280209592d8f1f65c1dfea18b89d144b86d08 size 5644 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libble_host.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libble_host.a index 7109bd3c48..2ef6599b31 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libble_host.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libble_host.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3207bf9458f295856d5ee9e9b71fc936026bcf13612e98d55ce86f61f0ce9fb3 -size 3203024 +oid sha256:76fffbb4acd0ec44138435bab975fc21f1a13e79915de02888a299341f4e82db +size 3203184 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb.a index 773e602315..1ba32c605c 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d7a47eb125384cafb8658c3af27c43e51be8ac2f9d4ddd653c36c0f1723f0212 +oid sha256:d2df60103d2918776a6419002758543de6542b5624ae0823f69e2fcbe60093ac size 70406 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a index 8df03cca7b..0b5206277c 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6e55a6af3d63414835026c366321e3be2c17847d07563e555d660da5fb28a7ed +oid sha256:ae18acfa51879b217f6ee375650d7e4ebc6c263c2708a79e2fddf42dae7386e9 size 25970 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a index 704b851510..6176d4acc0 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7ba7dfdaa01ba80cb31accb46a08bf7feec0cc2a5bece7959e4c650e796b3593 -size 8696608 +oid sha256:ba4c6827e8bb6abd9f2f5c854103b45835d7bde085b4b3b52cf638b7b9ad85a6 +size 8700236 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a index fa6ec007a6..357948ac11 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:00c868a7eba9c0b3f5c9b365a2eab9412191ebf462cd71108ebd55d846b915af -size 256388 +oid sha256:9b0c083b219886c79f64a47b532e52962c38331e2050e7fb353e3a7f7eb67004 +size 256472 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a index ea858663ae..37240a66eb 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a9f5e0bcbdd1aaf913df70791fba3d0a1569f54a64a7cf852a15c5ffda7fad3f -size 253440 +oid sha256:be0e0857381773bed7151c25e57dc94bf3e0f2640f568e08d486e98c6fd10bdc +size 253520 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a index 72a3266749..66e8b04572 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f05da3967cc34a73fe89d8c70f0489ba3e931280951e2541ede8045faf3367bc +oid sha256:5e5b4fbc88536f3d92bff09a856789a5f3abca6d6c0774720eb66fe530936b2e size 10468 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a index b1b2b528f5..5a2fd00277 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0a88c889f59ae05ada75cac388d9a9101400d7e0ba9edf5628c0b01cbd482086 +oid sha256:aff11c3831f208ace260b3b0723462b05977cb9a3fa92b33a7d11891d574b3a3 size 10468 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a index c343d00b44..1167c6cf20 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:06ffb7fe8c60e66bdea9ec8919fc2c54abde9d5f5685eb01da02d3390dc11e03 +oid sha256:a71ed11f78b178b9387f0f4d9f1587e71276030f36c5417191321c01d1b93ff8 size 1166 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a index f8a7c69c6f..5a614dc0ca 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:727ea6e70b9fa25629ba45d6430fae66e31d2f7090c31f4b0fee1e20c8c00483 +oid sha256:092c8c8e27a9defc58b2acc4b39af12b4c2e4067a88bed732476a74d70397666 size 1114 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hci/release/libble_host_hci.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hci/release/libble_host_hci.a index 1e5eee9e48..45b928f273 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hci/release/libble_host_hci.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/hci/release/libble_host_hci.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:743d8c77c8b4f1aa2ddc6893f562e6b4f2d272fc38d5f44812a9e975ae57d5c7 -size 313524 +oid sha256:ff9421c092db5b8d2e23819cdbeff3002f1d5563e564aff54acdce0618d731f7 +size 313528 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/system/release/libble_system.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/system/release/libble_system.a index 44c8d4e20b..3e7356c328 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_host/system/release/libble_system.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_host/system/release/libble_system.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8e22a5d23cd54cff947b65296f4613163c6251de928f254759bb903f06d92fa2 -size 102182 +oid sha256:9733ff1b282aadd828b986d196241ee4504818ddf0c0d66c6c424531e0bb43e5 +size 102230 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a index 00af7f5773..33345ca400 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:58793cab9a6111fc28bdd1e677768c442b78ddf9a31555e881633e4fe79574d6 +oid sha256:468fd62d9ab07c7aa316c84d8a069a91aa318cfddce54689617ac4738633e35a size 6870 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a index bceaec676e..54d778f60c 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6e4c9a593fa90db6a541efae1acf2b17717192a1ccb8ce2cf278f25b401da5be +oid sha256:56b488a550c4c10ff48a57d81e6571915c60ade64ad94350c701227121fa722b size 84854 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a index 0a09ba4f3f..e6326517c1 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:246c3b60b16154f2c39965aad3fde7d71b7072f4e0c1072dd21cbbb85cbf477d +oid sha256:99961dc4cd463e4f547c5d9bf307fa58b1de0695b2d9c5943079f1853cccc92a size 41522 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_core.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_core.a index 292dcfc3dc..a267b7637a 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_core.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:89266e91badcc27bda0b79a2356e0778acc4db556e909981aeefe2be099fa109 -size 1009056 +oid sha256:5dd1723369abb452dd8e078e3f4c1adc9ae7a1c2a4d2d87509e236ccecd0acd6 +size 1009376 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a index 1fd4647eb3..fcd518ba55 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:83b2429187c10a67dd33a971e0ad274fdb2341a3493e4d1319293960281cd8fa +oid sha256:a0fd8ef32090aa2ef8363bae03f0f0aac55c56ab9af2248609adba8b85d88da5 size 29126 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a index bd543a68e6..ee37b638bf 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bbbeb585f392c9143ba0e4ae3702747cb2350068c263aa33593bcf48c37de59e +oid sha256:285a7185e0f102afebfa96fc267d9de01b4450cce58e029a55e641df64dfb71e size 28602 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a index 05f17e4cab..5bdce96f03 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:32c62c04a4544b5697f092ac219c4a087178975d684c3363b772a6c5d7250e56 +oid sha256:ea2e000345e762627c367518538e740aee69ce8642d18dcd6bb39aeb302e9021 size 3314 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a index 6d1d5c9299..c132e91c03 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a5846408c0d59da63e06df51312de7fdf3195a3b03eaada3d20ee5c69df2d6ec +oid sha256:2031d4f76d12d52d75e5b5dc5b4eb783534319b33240b0dabb47b767f822ebd0 size 1972 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a index 0536bdfac1..b5333f8e16 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1cc8c80aeee29fc08fea8b07d4a1c6473c85045c66f2270d09401b14e10d196d +oid sha256:85df14ffda1f6302373ac4e9c882d46a643942ba777cb915bd966d4901d0f28f size 12594 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a index b976ebc7b1..818af341dd 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2e81a5c3c6cbf9215a6fceacc2a4fec5ea59a3ca47e4724fd8a42e5a40c2762a +oid sha256:dff2d7ae51e64b11a3fb8291396bee3b2d05af402d4b5d91fbfe3443ac280925 size 51830 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal.a b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal.a index 9489400bb5..9e9dca4460 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:224a04d3aaf28750a2acdded0f4761b76aeedc7fd3ba7d62a8df2846dfaf5ad1 +oid sha256:1a64158201bd71d4c55d2171ba7696230a3db0246171f0c75e69926c980235ad size 1068188 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a index 2967abd7d7..287c544fbb 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:14003fcc56920e5527c37433ab05074454c9bfdb20d102ba2531f5de850aa6a8 +oid sha256:d69f4690c3b8259cc73ee7b2a25dc44dd0405864f8030e3f87fe89bd73b4ffa8 size 4396 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a index d400634721..d402687d31 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a03d54603fc08c97fc79000cea33350d7bcfdb1ef781bffd5fd44a90c065c2d5 +oid sha256:5b0e9c8e4d918fa12ed4c83a4a4224fdeed8d144f8cb25ccab521263e1fdc81f size 6072 diff --git a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a index 9a28f1bf73..81a16e1d4b 100644 --- a/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a +++ b/protocol/bluetooth/build/gcc/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:18c241fd736e502343da3dc66733e45439fa9bb3762fa2eb812af834ee7315b5 +oid sha256:d3584bc3718db46e006d1a26b97d58c2cdc73b042ef21522c20e23cbc44b4bfd size 13996 diff --git a/protocol/bluetooth/build/iar/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a b/protocol/bluetooth/build/iar/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a index c08edc4f86..f2e8cd2bdd 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a +++ b/protocol/bluetooth/build/iar/cortex-m33/bgapi_protocol/api3/release/libbgapi_core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7246292f0f08a56aeb9e3e90e8453a5adaf0f0d943de22a9f6acb0acfd50b37d -size 28960 +oid sha256:d2a7667a5c989d58c337f7c0c85901159a9ae362a7d9a8ad71161395a2c6e898 +size 28976 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a index 69176c1226..0d87bad10b 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ddf1862bc052f32171d25449127ffeb012c50973b92cbee77e81d1d67d6b6fbc +oid sha256:1e752f3b61f55e97b40b914d9469e6dda27bb159d51972c292c79789b6c8b931 size 13324 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a index c832f7690a..ade02b977c 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/accept_list/release/libble_host_accept_list_stub.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a4b14fd804c2aa826ba3ce856991c90ef5e888890c5346f857eb4181aa9efa3a +oid sha256:a0c944c9dcd1e30a98710507efe0931c260d94d6d37870e821ee2243ad35e5be size 3538 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libble_host.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libble_host.a index 1e9141e1ae..62b748765d 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libble_host.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libble_host.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8e3d6d68d63be9cb94088f8b994b227f117cb83f6f3f677f5d0c32baf64742de +oid sha256:bd5c78fa96dbec7abe6b68207b5d704cd1ee34b6b780f49dffd8b49012869810 size 1452206 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb.a index 7d1844ee61..3fc3107d01 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a7f528627427201d0a790c7ed932c690466a7c89e90a5c91caa6e3ae5622704e +oid sha256:da9484e85b8ed08e226d8810f17562bfc909e794a60646f5296935b89c58ae99 size 32536 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a index 5e0c66b1c8..fb539ef3c9 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/bgstack/release/libbondingdb_stub.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e335b7bc56fd10077deb10388c3aeb74fbd08d465a88567b4b7fb335b62da6df +oid sha256:0fb9383ef2d9a114e6d7091194f0ad27b7c0f5183869a7f9d70acf1ed3fd40bf size 14068 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a index a3ede527ca..1ed727098a 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b10c363ca33e1e2d8f9cae52d6f1125ec15a3573ec47e0b260a15f7201c38e31 -size 2069216 +oid sha256:d3b2cbbf27c9a5b23fa0fc017afed122947f7c6d4dac7bee4a1b2c203685aa3e +size 2069636 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a index e07c4298fd..c4aeaa0c8f 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_client.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6aaee45b39a5eda7c07fdd9efebb2172624fc8572edc05d08ae0f6262f8c660a +oid sha256:51d2e6642526c23a77b5d6321fd957a9b0c69776d1853248c14f40f1d0d3431b size 65240 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a index 1d300b918c..c14d2a097f 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_gatt_server.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ac818f6af96860fd12fb0326f6471fbe023168a05ab7bf8256d70483a421cec0 +oid sha256:1c6a4fb13724cd4ddd33d5b45655433df4425999f9ed05b842b87f6bb46dd297 size 60316 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a index 2bbadf3f73..cc2e4a0fc7 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_client.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:def99d447172f7dd2ba11d840e5c60f0a04a4afebd4a431d120a8f9327098587 +oid sha256:0953f77242939c7f2c3e118e92b7805a45400b5126fc28a171089a0b48c74f99 size 6910 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a index 99e6494d0b..6eef0906b1 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/ble_bgapi/release/libble_bgapi_stub_gatt_server.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b9544555dad55b6bf337f68e8d9b3d61e5709fa0d03bd4ec4ad5d3bcc96260e3 +oid sha256:cc7828f7e253293bc17d02ce2cccb2c91884842a0a0ef8e66eb5f6ba33a76fcd size 6910 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a index 74dac4d865..01b3783a7f 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series2.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0f4b95eb70501c8ec8688e0d5a8e093c1edd717de6ba1cafd3229af6b17ee063 +oid sha256:4d30ec88593a754ff2eaec71b1edd308ad606d7555ed50e6454607a17f7958cc size 2824 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a index cd4c712403..82370aa5cb 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/hal/release/libble_host_hal_series3.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6a1ff3093f71ff73b4938987a8e0bac465b86fa22a0d32ac79cc33aafa0a6c11 +oid sha256:a5da019e141bc982cec8e5bb27ebe607cea6f2032807566e67cce27140916043 size 2706 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/hci/release/libble_host_hci.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/hci/release/libble_host_hci.a index 4ffb36e43f..16b7d6bcdc 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/hci/release/libble_host_hci.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/hci/release/libble_host_hci.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4bbc1f824996e7941e7b600f8db144c032147f56de042f5f07393290caaa84a2 +oid sha256:e96383cbfb4540ac35f228674baef92397f58d024e90ef14297ba4b0d0608d74 size 142818 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_host/system/release/libble_system.a b/protocol/bluetooth/build/iar/cortex-m33/ble_host/system/release/libble_system.a index d68281ca4c..ec224a4b2c 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_host/system/release/libble_system.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_host/system/release/libble_system.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b2be9db868b5ee40e9a3184e02c6ba60da41b2debe26ce4dbe2393d9ad218589 +oid sha256:f1bade66bb9f732014b3c068537a84410e846c3049e08c3ac6865b62740cb931 size 58316 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a index aa6b8d43e3..1c65856682 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_dfu_ncp_fw_list.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fb14811083a5a66711f0b5a64e440adefc4b6a67a84888865e669f8b66c0e4cf +oid sha256:0d049756ef5a13c43f1e70908d82893bf3e0dbd81bfb380578bc846dcaa3508d size 15220 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a index bb245121c4..fc3f190254 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_dfu/release/libbtmesh_model_dfu.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f3133b63c7e85c2a0318a838c45f9b5a04ed35e08a321ee00afc50cd896937d7 +oid sha256:b90604c3b608e061e61f211f4f70afabb124ac08621a63008f3689b63eacfb58 size 222104 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a index cff191e39d..a223793bfe 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/model_mbt/release/libbtmesh_model_mbt.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b32d5e2315a16c9c00af7a10608f64a5022ebca22e74e743d37a5840ff772ee6 +oid sha256:c1e587f0fda0a2c48e13008dc7c8ac490874a23281f1b5afef121dc96a5e05f6 size 127074 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_core.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_core.a index 9fc2be44b2..7d7709c462 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_core.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fb880e5187028498b96a05cafcb8c95df6591ff36240f4d94e91f50e76658a98 -size 2529266 +oid sha256:78bcd07769dd0849629efed9809a6e7c32a7f9d749492b6f785d0c1b35d3637f +size 2530278 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a index f47ec5e74e..0cd1cb1e7b 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_cache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:70be564cbe5ce58a3893bca12d0b3d7c37814cf08f19d021cbbb14e5133a620e +oid sha256:aa6374cc8d3387bff3890f5d97dbfb0d53ea9e51f4931d6ae59c7073d80b57ce size 68794 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a index 371f6c59ed..3287ddbd82 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_common_nocache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ddf597ceb1c97cbce06a6dc220fb9b8943479150d6b8e55ffaddbb3ff3965f5a +oid sha256:0dd279849a8b029092afe6bcbda756e8c67dd60510c2c7623808104cac185388 size 71688 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a index 85c2be0cbf..62be2481ce 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a74e1ec7e62f5a7acead3613694344d63fdc235f92f458bc563d832d1f6c3bd4 +oid sha256:9359d41105048c4015e0321ac9261747287048dfd18d7a06036d727106d2a6bf size 9762 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a index be156759bb..cbaa370fe4 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_key_cache_dummy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8fc6b398fbc9376903a4cd61950505de7441862a60978883f0a3ded1f87f2364 +oid sha256:5da2d0af7480a3e1f2c066716806c109597d1797ebd34224123c248eca546231 size 5140 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a index 0c801ab2a3..1ca5f7e03b 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_crypto_psa.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6f3149b5f97c624cad268d6f91ab477e46dd662ae75b667de5955ce4cc495665 +oid sha256:473bcc250d3ef864b8094f193dd508039b68f85bb21e267a54d71b3eb585f301 size 26920 diff --git a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a index 68480465f9..579e3bde86 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a +++ b/protocol/bluetooth/build/iar/cortex-m33/ble_mesh/release/libbtmesh_its_keystorage.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a287afcdf513e49ae2fb2206b487e47896b3c2755eaed323b7dc825b269958b0 +oid sha256:33380cc7c72e7388bb340055732df5fddb7fa1b687b2c45561b28b70e09feae8 size 124244 diff --git a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal.a b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal.a index 7f4fa3d75f..79fb6f5832 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal.a +++ b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:79b8952e42b44b8fb1b04a20451892fecc464e9b2e5eed947a8b5fdb682afe4a +oid sha256:e6baf7eb51280a5c749e40c7ea71338edc62136dd5d90adfa975b09bbdf2ad84 size 2329708 diff --git a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a index 5c07536bd3..a226d4c800 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a +++ b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_nonobfuscated_nvm.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a0326bf0793bdfbaaf44542839f07da01e9bc39bd27b62cdfca554ff3310e936 +oid sha256:b64c622090c2e8677d4319575afe361e5da5cf4a9d1e42fd70a8b125fc1df886 size 10710 diff --git a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a index 285a065c4a..d85f065dc7 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a +++ b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_obfuscated_nvm.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:207cdce98f0e1c65d477da45b48583b3bd43d5df291b750e75c8086fee275889 +oid sha256:f6c88da515417d53a03bf88119ed03ef4267da8693544dc91296c7fff6af5b2c size 13768 diff --git a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a index dab8320b87..31a8eb9487 100644 --- a/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a +++ b/protocol/bluetooth/build/iar/cortex-m33/mesh_app/release/libbtmesh_hal_psa.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f8769c8bd6ef22fc1cbf8ba150333dfefa4f7b152243cf295ee793ae071bd50d +oid sha256:81c757b1f0047b06309f37bd7c92f27a6d73b718d8e86bae90c3bb219bfc9368 size 39160 diff --git a/protocol/bluetooth/inc/sl_bt_ll_config.h b/protocol/bluetooth/inc/sl_bt_ll_config.h index 7cd2d9cdd4..3949caab9e 100644 --- a/protocol/bluetooth/inc/sl_bt_ll_config.h +++ b/protocol/bluetooth/inc/sl_bt_ll_config.h @@ -54,6 +54,8 @@ typedef struct { #define SL_BT_BLUETOOTH_PRIORITIES_DEFAULT { 191, 143, 175, 127, 135, 0, 55, 15, 16, 16, 0, 4, 4, 15, 5, 20, 10 } #define SL_BT_BLUETOOTH_PA_AUTOMODE 0xff +#define SL_BT_BLUETOOTH_HIGHEST_PA 0xfe +#define SL_BT_BLUETOOTH_RAIL_UTIL_PA 0xfd #include "sl_common.h" SL_PACK_START(1) diff --git a/protocol/bluetooth/inc/sl_bt_version.h b/protocol/bluetooth/inc/sl_bt_version.h index d95a1da5b7..3e270b9a3a 100644 --- a/protocol/bluetooth/inc/sl_bt_version.h +++ b/protocol/bluetooth/inc/sl_bt_version.h @@ -42,17 +42,17 @@ * * An increment indicates backwards compatible bug fixes. */ -#define SL_BT_VERSION_PATCH 0 +#define SL_BT_VERSION_PATCH 1 /** * @brief The build number which the Bluetooth SDK was created from */ -#define SL_BT_VERSION_BUILD 190 +#define SL_BT_VERSION_BUILD 341 /** * @brief The hash value of the build the Bluetooth SDK was created from */ -#define SL_BT_VERSION_HASH {0x79,0xba,0x4a,0x1c,0xb3,0x8e,0x8e,0x03,0x0b,0x82,0x0b,0xc8,0xaa,0x54,0xda,0xa6,0xe5,0x7d,0xda,0x77} +#define SL_BT_VERSION_HASH {0x4d,0x9c,0xee,0x3e,0x47,0x47,0x76,0xad,0x6d,0x0c,0xc3,0x0c,0xe5,0x8c,0x68,0x88,0xd9,0xd6,0x50,0xd4} /** * Deprecated and replaced by SL_BT_VERSION_MAJOR diff --git a/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-gcc.a index 3633197a8f..de6b31b97f 100644 --- a/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bd6fbca08b9db9748587eb4e127a0c7eb5835ac12387bf821f2fffef81818069 +oid sha256:ec2d9661f4214ad77fc2ba8bd711d55acf9eafa29b9ac954ea0fbf38451866ef size 75662 diff --git a/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-iar.a index 64851c7b37..1d5748cc38 100644 --- a/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-aes-security-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:90c04ab107be69e40f3613e85a0472338534d9b297c31d8b77e8e898f4baef37 +oid sha256:e4a030fd8b9f3234e0d001f062ea08a1f56aa2baca5a6a8dee6eaac26c09b20a size 50636 diff --git a/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-gcc.a index 30871622c0..0d531906f3 100644 --- a/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2a8a17f0c680903aefae976a3cf54650df495966eb11c71bcf5eeb6977ddbde5 +oid sha256:803af77a22c79932a548299c2c6443aa1f6f077d9b40aa83802c54e84a746b73 size 42150 diff --git a/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-iar.a index a6ddbac97d..e864536798 100644 --- a/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-frequency-hopping-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1879433440ea2ce2d6ed2075dc1953a50e4a6c2cca9692937136686de4c4dd62 +oid sha256:37f7fa54ddb9620690ac9c46494cf78b648c5c27b6951258c543e06eb6f6807d size 34704 diff --git a/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-gcc.a index 9b139ac901..0e1d353dac 100644 --- a/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fbaaf7fdf5c0639f47d3e27a77b4b34db0f662e3f89e8cc9cfe204d7ce8093a3 +oid sha256:5fea72e6e5914f376dc246249d409aa7bf8146f32b1ab202931eecfdb3fc65ec size 12752 diff --git a/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-iar.a index 87336cd36e..2dc4c2aae0 100644 --- a/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-packet-queue-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a446b11e0d9f36e4e4437a9bc546bfce93ab85aae4159a9c72ff846dc32e28e9 +oid sha256:82194fac57497b80bd2c750c4b5a4e48782d2abe4d48aea8659e58505298aff0 size 6900 diff --git a/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-gcc.a index 49d7f37218..2a03f6fc23 100644 --- a/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:21ce010d9afe9547871510d9834b190d1453c5517beafdd4aae7f28450d97904 +oid sha256:527b16c953515e8687af6d09f00ac8e9681db051535f7717f3066e2b187a8315 size 91750 diff --git a/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-iar.a index f211d0f553..9cfe292c4f 100644 --- a/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-parent-support-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8cb0800b1593620c788637b3526de328d39935387cb959971b595a3af72f848c +oid sha256:6d1e08ae8c2fc5fd075583e93c762bd4c66ccfad088a6cc1897938ba5d24cef5 size 63190 diff --git a/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-gcc.a index ccab4cd5b2..691ac6f674 100644 --- a/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8f0ee62028f15a5de17717295302185017312627f02b440af1358c257c240172 +oid sha256:4327cbf8635fcedf194106c61f44ce998bed5dffc436216492ce0a358d5b8882 size 72016 diff --git a/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-iar.a index 0b076aeac0..f7923d6c4a 100644 --- a/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-psa-security-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:49e1b6fe0683940f6756265038b8a4df7ba2d153207422c1070923039250df2c +oid sha256:9405a8ab44f99251871042885ba25d7c704baa501e80a5f3f9ce40c19ed064ae size 49338 diff --git a/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-gcc.a index 975f06dea4..ddccf13837 100644 --- a/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e27ec7bb8ffad242f28dde1a04359d94145a9af0cc47f9fe0e6e6070e583b952 +oid sha256:80117e0e436301368076c4838a16a440b3db2493906fd171a2474016b7329545 size 8092 diff --git a/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-iar.a index 26f644ac3b..e365b03ba0 100644 --- a/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-radio-stream-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:450d5588d7c513f9094d243b648cba01b92ba051a5a27675a855377a36f9e445 +oid sha256:267e644954744af9962ee1b39db1729d2a16be7660fcbf3400a1531d54161fff size 4884 diff --git a/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-gcc.a index 34dd63dedf..3daefa0094 100644 --- a/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1b3a89af7dc6b72e03bb58aec39acbacc18365718dffc5717d080b3e3066a80a +oid sha256:36ce2027f7dba8b872ea0abd5556545c8ef6cdd9f52bfce89d7f65252178f1b9 size 420754 diff --git a/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-iar.a index 80ee45e584..b86416c714 100644 --- a/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-stack-common-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:476a80d565c42d7daa8b16886954562d7caf473dd1dbd8ff4fd9e12b654be998 +oid sha256:965d29ab0d345186fa112661cfd2c141001092d435a990a8b1e6be3c54fe8b88 size 335876 diff --git a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a index ceed4e6b91..990df2d994 100644 --- a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1c9f468eb9ae6594baffa0c2bda9f10b5944f9072044eacc5b6e66c9be8c1964 +oid sha256:2c4790b1c5351e3253bf185a5e3eba646dea54c583834681e03697cdec62d30f size 9764 diff --git a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a index 627883b01f..1a7922c7b0 100644 --- a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9aedec2bcba45718dd8a0a0eaf6c17acd96fd4dea8a519d5b3be9cd524bbbe6e +oid sha256:7c986c73b5bca887c179bca2e97a8cf02998aa0234b38f79c67191bf89e6521b size 4732 diff --git a/protocol/flex/stack/config/config.h b/protocol/flex/stack/config/config.h index 0054c3012a..7ef147c8b3 100644 --- a/protocol/flex/stack/config/config.h +++ b/protocol/flex/stack/config/config.h @@ -63,7 +63,7 @@ /** * @brief Build number of the release. Should be stored on 2 bytes. */ -#define EMBER_BUILD_NUMBER 190 +#define EMBER_BUILD_NUMBER 341 /** * @brief Full version number stored on 2 bytes, with each of the four digits diff --git a/protocol/openthread/component/ot_platform_abstraction.slcc b/protocol/openthread/component/ot_platform_abstraction.slcc index c17bbb4b9d..243dbc9f3a 100644 --- a/protocol/openthread/component/ot_platform_abstraction.slcc +++ b/protocol/openthread/component/ot_platform_abstraction.slcc @@ -46,10 +46,6 @@ toolchain_settings: value: "-Werror=unused-label" - option: gcc_compiler_option value: "-Werror=unused-variable" - - option: preinclude - value: sl_openthread_rtos_config.h - condition: - - kernel - option: preinclude value: sl_openthread_subghz_config.h condition: diff --git a/protocol/openthread/component/script/upgrade_uart_intf_instances.lua b/protocol/openthread/component/script/upgrade_uart_intf_instances.lua deleted file mode 100644 index f91d369f06..0000000000 --- a/protocol/openthread/component/script/upgrade_uart_intf_instances.lua +++ /dev/null @@ -1,25 +0,0 @@ -function update_instances(changeset, orig_component, new_component) - local instances = slc.component(orig_component).instances - for instance,_ in pairs(instances) do - table.insert(changeset, { - ['component'] = orig_component, - ['instance'] = {instance}, - ['action'] = 'remove' - }) - table.insert(changeset, { - ['component'] = new_component, - ['instance'] = {instance}, - ['action'] = 'add' - }) - end -end - -local changeset = {} - --- Only update instances if application uses OT platform abstraction -if slc.is_selected('ot_platform_abstraction_core') then - update_instances(changeset, 'uartdrv_usart', 'iostream_usart') - update_instances(changeset, 'uartdrv_eusart', 'iostream_eusart') -end - -return changeset diff --git a/protocol/openthread/component/upgrade.slcu b/protocol/openthread/component/upgrade.slcu index 7f8c56cd95..8d86c2f396 100644 --- a/protocol/openthread/component/upgrade.slcu +++ b/protocol/openthread/component/upgrade.slcu @@ -36,10 +36,6 @@ upgrade: id: simplicity_sdk version: "2024.12.0" component: - - script: protocol/openthread/component/script/upgrade_uart_intf_instances.lua - description: > - Support for uartdrv instances in thread projects has been deprecated. - Replacing uartdrv instances with iostream instances. - script: protocol/openthread/component/script/upgrade_diag_config.lua description: > Diagnostic configuration support has been moved to ot_diags component. diff --git a/protocol/openthread/config/sl_openthread_features_ftd_cert_config.h b/protocol/openthread/config/sl_openthread_features_ftd_cert_config.h index 3639f8847f..419a96c885 100644 --- a/protocol/openthread/config/sl_openthread_features_ftd_cert_config.h +++ b/protocol/openthread/config/sl_openthread_features_ftd_cert_config.h @@ -295,6 +295,11 @@ #define OPENTHREAD_CONFIG_NET_DIAG_VENDOR_INFO_SET_API_ENABLE 1 #endif // +// Uptime of OpenThread instance +#ifndef OPENTHREAD_CONFIG_UPTIME_ENABLE +#define OPENTHREAD_CONFIG_UPTIME_ENABLE 1 +#endif +// // Time Synchronization Service #define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0 // diff --git a/protocol/openthread/config/sl_openthread_features_mtd_cert_config.h b/protocol/openthread/config/sl_openthread_features_mtd_cert_config.h index 7e83e435ff..165cd74d8c 100644 --- a/protocol/openthread/config/sl_openthread_features_mtd_cert_config.h +++ b/protocol/openthread/config/sl_openthread_features_mtd_cert_config.h @@ -295,6 +295,11 @@ #define OPENTHREAD_CONFIG_NET_DIAG_VENDOR_INFO_SET_API_ENABLE 1 #endif // +// Uptime of OpenThread instance +#ifndef OPENTHREAD_CONFIG_UPTIME_ENABLE +#define OPENTHREAD_CONFIG_UPTIME_ENABLE 1 +#endif +// // Time Synchronization Service #define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0 // diff --git a/protocol/openthread/config/sl_openthread_generic_config.h b/protocol/openthread/config/sl_openthread_generic_config.h index 56cda2d6dc..04b04ea8da 100644 --- a/protocol/openthread/config/sl_openthread_generic_config.h +++ b/protocol/openthread/config/sl_openthread_generic_config.h @@ -95,7 +95,7 @@ #define PACKAGE_NAME "SL-OPENTHREAD" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "SL-OPENTHREAD/2.6.0.0_GitHub-7f6723ffb" +#define PACKAGE_STRING "SL-OPENTHREAD/2.6.1.0_GitHub-7f6723ffb" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "openthread" @@ -107,13 +107,13 @@ * Note: When adding the label below with OpenThread version, please make * sure it is a valid GitHub version. Avoid merge or local commit hashes. */ -#define PACKAGE_VERSION "2.6.0.0_GitHub-7f6723ffb" +#define PACKAGE_VERSION "2.6.1.0_GitHub-7f6723ffb" /* Define to 1 if you have the ANSI C header files. */ #define STDC_HEADERS 1 /* Version number of package */ -#define VERSION "2.6.0.0_GitHub-7f6723ffb" +#define VERSION "2.6.1.0_GitHub-7f6723ffb" /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most significant byte first (like Motorola and SPARC, unlike Intel). */ diff --git a/protocol/openthread/config/sl_openthread_reference_device_config.h b/protocol/openthread/config/sl_openthread_reference_device_config.h index d883dd2cc5..7a4954c898 100644 --- a/protocol/openthread/config/sl_openthread_reference_device_config.h +++ b/protocol/openthread/config/sl_openthread_reference_device_config.h @@ -269,6 +269,11 @@ #define OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE 1 #endif // +// Uptime of OpenThread instance +#ifndef OPENTHREAD_CONFIG_UPTIME_ENABLE +#define OPENTHREAD_CONFIG_UPTIME_ENABLE 1 +#endif +// // RAM (volatile-only storage) #ifndef OPENTHREAD_SETTINGS_RAM #define OPENTHREAD_SETTINGS_RAM 0 diff --git a/protocol/openthread/config/sl_openthread_rtos_config.h b/protocol/openthread/config/sl_openthread_rtos_config.h index d4798d6a89..2f8932d479 100644 --- a/protocol/openthread/config/sl_openthread_rtos_config.h +++ b/protocol/openthread/config/sl_openthread_rtos_config.h @@ -57,7 +57,13 @@ // Default: 4608 // Defines the stack size of the OpenThread RTOS stack task. The value is in bytes and // and will be word aligned when it is applied at the task creation. +#ifndef SL_OPENTHREAD_STACK_TASK_MEM_SIZE +#if defined(_SILICON_LABS_32B_SERIES_3) +#define SL_OPENTHREAD_STACK_TASK_MEM_SIZE (6144) +#else #define SL_OPENTHREAD_STACK_TASK_MEM_SIZE (4608) +#endif +#endif // OpenThread app task stack size in bytes <1000-20000> // Default: 4608 @@ -70,6 +76,7 @@ // Defines the stack size of the OpenThread RTOS serial task. The value is in bytes and // and will be word aligned when it is applied at the task creation. #define SL_OPENTHREAD_SERIAL_TASK_MEM_SIZE (3072) + // // Priority Configuration for OpenThread RTOS Stack Task // OpenThread serial task prority @@ -78,12 +85,6 @@ // from CMSIS-RTOS2 osPriority_t definition. #define SL_OPENTHREAD_RTOS_SERIAL_TASK_PRIORITY (16) -// OpenThread serial task stack size in bytes <1000-20000> -// Default: 2048 -// Defines the stack size of the OpenThread RTOS serial task. The value is in bytes and -// and will be word aligned when it is applied at the task creation. -#define SL_OPENTHREAD_OS_SERIAL_TASK_SIZE 2048 - // // App Task // Enable default App task diff --git a/protocol/openthread/documentation/release-highlights.txt b/protocol/openthread/documentation/release-highlights.txt index a2e2b3c87a..69c0f9afba 100644 --- a/protocol/openthread/documentation/release-highlights.txt +++ b/protocol/openthread/documentation/release-highlights.txt @@ -1,14 +1,5 @@ -Silicon Labs OpenThread SDK 2.6.0.0 +Silicon Labs OpenThread SDK 2.6.1.0 - Thread - - Thread 1.4 certification compliance for Thread devices (SoC) - - Thread 1.3 certification compliance, and 1.4 Alpha support for OTBR - - OTBR NCP mode support - Alpha - - OTBR RCP mode with MCU host (x917) - Alpha - - KNX IOT API support (delivered in Silabs GitHub) - - xG26 Module support - - TrustZone secure key storage support for Thread / MP SoC projects + - Targeted quality improvements and bug fixes. - Multiprotocol - - ZigbeeD and OTBR support on OpenWRT – GA - - DMP BLE + CMP ZB & Matter/OT with Concurrent Listening on MG26 for SoC – GA - - 802.15.4 Unified radio scheduler priority component - - Debian packaging support for MP host applications - Alpha + - Targeted quality improvements and bug fixes. diff --git a/protocol/openthread/esf.properties b/protocol/openthread/esf.properties index 650a03fbbd..9d332c296d 100644 --- a/protocol/openthread/esf.properties +++ b/protocol/openthread/esf.properties @@ -11,10 +11,10 @@ # sure it is a valid GitHub version. Avoid merge or local commit hashes. id=com.silabs.sdk.stack.openthread -version=2.6.0.0 +version=2.6.1.0 label=OpenThread SDK description=OpenThread stack support for EFR32 devices -prop.subLabel=OpenThread\\ 2.6.0.0\\ (GitHub-7f6723ffb) +prop.subLabel=OpenThread\\ 2.6.1.0\\ (GitHub-7f6723ffb) prop.file.docsFile=documentation/slOpenThread_docContent.xml prop.file.templatesFile=openthread_experimental_templates.xml openthread_evaluation_templates.xml openthread_internal_templates.xml openthread_production_templates.xml diff --git a/protocol/openthread/libs/libsl_openthread_cm33_gcc.a b/protocol/openthread/libs/libsl_openthread_cm33_gcc.a index b66ec61217..3e2b4b8ece 100644 --- a/protocol/openthread/libs/libsl_openthread_cm33_gcc.a +++ b/protocol/openthread/libs/libsl_openthread_cm33_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bb27e9a95b14d73279aa6974064382158f45d69ddbcef6d7e348c530bde3d34e +oid sha256:ce45f4cac6bd2dcf34287457e003fc2dfa6f451373ab610790ae61b6c75ed273 size 1068 diff --git a/protocol/openthread/libs/libsl_openthread_wrapper_gcc.a b/protocol/openthread/libs/libsl_openthread_wrapper_gcc.a index b1918e0760..3f3e78ce8d 100644 --- a/protocol/openthread/libs/libsl_openthread_wrapper_gcc.a +++ b/protocol/openthread/libs/libsl_openthread_wrapper_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1e88d4b67c4ea87e56cbcd520a8a7949f3fb4423a3b7ab5b2c9fd6a755d0ad8c +oid sha256:2c964d578baaf1b955e87cbf8ab6eef9fddcd3a5aa9ea6ab84cf24dfc9328643 size 369272 diff --git a/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg21_gcc.a b/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg21_gcc.a index 469c4298f7..42b01d6dd6 100644 --- a/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg21_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg21_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a8845c58f3b9bbb68c67cd79e7816b078a4b7ec8f98936d6a937e5539066cb50 +oid sha256:cac8e5693c013a87059b7e0e498cafb70f442dfcdab469a38a5a150f5b6d9fc5 size 1588740 diff --git a/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg24_gcc.a b/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg24_gcc.a index 8f1496c263..1e08ebcaa1 100644 --- a/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg24_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg24_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:48fbbb99773cac4f1531b828a3a8d8f7a0a9fec39dc314ef6271ee0782019331 +oid sha256:4c2b4abfec2fe07db1f50a65cede5b74eacc046480d5f24ed57f81d5f2564c5b size 1588740 diff --git a/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg26_gcc.a b/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg26_gcc.a index 8555805916..1106abf997 100644 --- a/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg26_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_ftd_coap_efr32mg26_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7ae8f7ca0ae7a178d92466d51009ecff68fb975599093859096fd0eba54b9fbd +oid sha256:21cea10a693615c782d9ebd4e3f0b8843a46eb427474a22777a1acd337ad4234 size 1588740 diff --git a/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg21_gcc.a b/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg21_gcc.a index 343913d862..2faa702eb6 100644 --- a/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg21_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg21_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ab893f1cff0bec024c5783dec817b8cc33892d0caee1d5486cc763b4a5d9095d +oid sha256:efe0b4d7f9776cf2a95adf6ca3f7fcc8ca56fab0afb82905b92d84febf1294d3 size 1532338 diff --git a/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg24_gcc.a b/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg24_gcc.a index 2f1f051ece..b1143612a2 100644 --- a/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg24_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg24_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d1fd98c76c2a5d41ee8f4fba2707708db8025e19c4ca750a2fb5850dc1acc9b3 +oid sha256:9a1d0ab2647896211612a81f87b6ea291fbe7dec5f6e6ce932e48d08899c360b size 1532338 diff --git a/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg26_gcc.a b/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg26_gcc.a index 8dda43d5e3..f75d8adc48 100644 --- a/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg26_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg26_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:67d23bc4c6f4d5109f8bfbae1cd331da252fd6b1fc6985eb5a809aac254c42fb +oid sha256:1f472370984be87b4994fdfb73c1e31d92d07cb886569299695f121f438ee3c2 size 1532338 diff --git a/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg21_gcc.a b/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg21_gcc.a index 315415113f..f31f9fcbfa 100644 --- a/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg21_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg21_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e3f8b07ca73d27bfeda8bf5978c1a63a759ce8faac7d00830b77d14813c62da2 -size 1300912 +oid sha256:647fa7c6b8f691089a1c0ec9a653047a8a2ee70665a8a2a4887f0c9a2612be59 +size 1306090 diff --git a/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg24_gcc.a b/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg24_gcc.a index 8678de2719..33279cbd34 100644 --- a/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg24_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg24_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b84f90cab3bc2df044fb251c2afb3c8378397b4c3810207dd714cba7fcadb081 -size 1300912 +oid sha256:6a6245813077b331391c813e9a8a7f9d9328433f8a86ca4ce1f6f731397749f7 +size 1306090 diff --git a/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg26_gcc.a b/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg26_gcc.a index 5cc6f5ad71..2215485958 100644 --- a/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg26_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_mtd_coap_efr32mg26_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cdceb81f4252db1485f2aad397fe94cff3657bf1328713c4b762b2055f2c0f9b -size 1300912 +oid sha256:9434adfc9bff4ec2adb6787c2ca8dcc7c0bc7c6f7b000610ca08a079d506f229 +size 1306090 diff --git a/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg21_gcc.a b/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg21_gcc.a index 35d08f7f27..d35fa0c79b 100644 --- a/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg21_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg21_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d590205bfadec79a17eb1b24721c8cbeec086d5748fb106fd9f22dc843fb2db5 -size 1244498 +oid sha256:4f5e5ae6cee708a91881cc3f95fe8e732a746e7ee3178f8b956cccb11e60bd06 +size 1249676 diff --git a/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg24_gcc.a b/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg24_gcc.a index fd8ace8702..00a31fdb08 100644 --- a/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg24_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg24_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:01a6e2e13e403eb5f27072b4276734fc1f8f868a6454f2d64545aca35b1da33d -size 1244498 +oid sha256:5e4ead76bb58530caa701837c64d6ad53f30ac3a73f30b7c69eff1083b84ecc6 +size 1249676 diff --git a/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg26_gcc.a b/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg26_gcc.a index ce4a03f7cf..7e27b62b91 100644 --- a/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg26_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg26_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7c79b3cf45bbaaa592641ad326064a13bf6e6caabce02c37bfb2bd3c8b9c9d89 -size 1244498 +oid sha256:4aa6811bfa5f58e77372e2b4dab3c177a3b7d5fb12f3c3d97483206fadb457c7 +size 1249676 diff --git a/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg21_gcc.a b/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg21_gcc.a index 0dac7b610a..560828940f 100644 --- a/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg21_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg21_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:69ec32fcdf7d2cb8cbd700f3e7c0369e2b1429a35782742439c315c8ab56ab34 +oid sha256:8d20986a9e3f03e81da8813fe07804f0b0a3c6ef3054e9271c6e7605cc662552 size 301110 diff --git a/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg24_gcc.a b/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg24_gcc.a index 846709366d..6eba0400b5 100644 --- a/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg24_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg24_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:08d4493edfd4f134f9aaa7b4f63662329a9dda876e5cb6fecb5013738874b130 +oid sha256:6ea7fb0686cbcd27b25f441cd31f7b283e34d07d0bb1b76a5f599a36f55a0b98 size 301110 diff --git a/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg26_gcc.a b/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg26_gcc.a index 563be9337d..55478ed5e5 100644 --- a/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg26_gcc.a +++ b/protocol/openthread/libs/libsl_ot_stack_tcp_efr32mg26_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:566af80f47703d09c142b21d213cd986a5bda3cb5582c235302b167d5719009e +oid sha256:4d35ea74c64bc81b53f949ea726da8ab344f3e30bba82e822805503b73bae52b size 301110 diff --git a/protocol/openthread/openthread_experimental_templates.xml b/protocol/openthread/openthread_experimental_templates.xml index c42ddfe146..e7b69c980e 100644 --- a/protocol/openthread/openthread_experimental_templates.xml +++ b/protocol/openthread/openthread_experimental_templates.xml @@ -36,7 +36,7 @@ - + @@ -51,7 +51,7 @@ - + diff --git a/protocol/openthread/openthread_production_demos.xml b/protocol/openthread/openthread_production_demos.xml index 2df2f42e19..5e73323905 100644 --- a/protocol/openthread/openthread_production_demos.xml +++ b/protocol/openthread/openthread_production_demos.xml @@ -6,7 +6,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -28,7 +28,7 @@ - + @@ -39,7 +39,7 @@ - + @@ -50,7 +50,7 @@ - + @@ -61,7 +61,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -116,7 +116,7 @@ - + @@ -127,7 +127,7 @@ - + @@ -138,7 +138,7 @@ - + @@ -149,7 +149,7 @@ - + @@ -160,7 +160,7 @@ - + @@ -171,7 +171,7 @@ - + @@ -182,7 +182,7 @@ - + @@ -193,7 +193,7 @@ - + @@ -204,7 +204,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -226,7 +226,7 @@ - + @@ -237,7 +237,7 @@ - + @@ -248,7 +248,7 @@ - + @@ -259,7 +259,7 @@ - + @@ -270,7 +270,7 @@ - + @@ -281,7 +281,7 @@ - + @@ -292,7 +292,7 @@ - + @@ -303,7 +303,7 @@ - + @@ -314,7 +314,7 @@ - + @@ -325,7 +325,7 @@ - + @@ -336,7 +336,7 @@ - + @@ -347,7 +347,7 @@ - + @@ -358,7 +358,7 @@ - + @@ -369,7 +369,7 @@ - + @@ -380,7 +380,7 @@ - + @@ -391,7 +391,7 @@ - + @@ -402,7 +402,7 @@ - + @@ -413,7 +413,7 @@ - + @@ -424,7 +424,7 @@ - + @@ -435,7 +435,7 @@ - + @@ -446,7 +446,7 @@ - + @@ -457,7 +457,7 @@ - + @@ -468,7 +468,7 @@ - + @@ -480,7 +480,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -492,7 +492,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -504,7 +504,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -516,7 +516,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -527,7 +527,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -538,7 +538,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -549,7 +549,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -560,7 +560,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + diff --git a/protocol/openthread/openthread_production_templates.xml b/protocol/openthread/openthread_production_templates.xml index 26034bcdc1..6d2c930383 100644 --- a/protocol/openthread/openthread_production_templates.xml +++ b/protocol/openthread/openthread_production_templates.xml @@ -6,7 +6,7 @@ - + @@ -22,7 +22,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -54,7 +54,7 @@ - + @@ -69,7 +69,7 @@ - + @@ -84,7 +84,7 @@ - + @@ -99,7 +99,7 @@ - + @@ -114,7 +114,7 @@ - + @@ -129,7 +129,7 @@ - + @@ -144,7 +144,7 @@ - + @@ -159,7 +159,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -189,7 +189,7 @@ - + @@ -204,7 +204,7 @@ - + @@ -219,7 +219,7 @@ - + diff --git a/protocol/openthread/platform-abstraction/efr32/crypto.c b/protocol/openthread/platform-abstraction/efr32/crypto.c index ada89193c9..fc529a78e0 100644 --- a/protocol/openthread/platform-abstraction/efr32/crypto.c +++ b/protocol/openthread/platform-abstraction/efr32/crypto.c @@ -143,6 +143,11 @@ static psa_key_usage_t getPsaKeyUsage(int aKeyUsage) aPsaKeyUsage |= PSA_KEY_USAGE_SIGN_HASH; } + if (aKeyUsage & OT_CRYPTO_KEY_USAGE_VERIFY_HASH) + { + aPsaKeyUsage |= PSA_KEY_USAGE_VERIFY_HASH; + } + return aPsaKeyUsage; } @@ -202,8 +207,6 @@ static void checkAndWrapKeys(void) void otPlatCryptoInit(void) { - (void)sl_sec_man_init(); - #if defined(SEMAILBOX_PRESENT) && !defined(SL_TRUSTZONE_NONSECURE) if (GET_SECURITY_CAPABILITY() == VAULT_ENABLED) { @@ -743,4 +746,51 @@ otError otPlatCryptoPbkdf2GenerateKey(const uint8_t *aPassword, return error; } +otError otPlatCryptoEcdsaVerify(const otPlatCryptoEcdsaPublicKey *aPublicKey, + const otPlatCryptoSha256Hash *aHash, + const otPlatCryptoEcdsaSignature *aSignature) +{ + otError error = OT_ERROR_NONE; + psa_status_t status; + bool aIsHash = true; + uint8_t aByteArray[OT_CRYPTO_ECDSA_PUBLIC_KEY_SIZE + 1]; + otCryptoKeyRef aKeyId; + + otEXPECT_ACTION(((aPublicKey != NULL) && (aHash != NULL) && (aSignature != NULL)), error = OT_ERROR_INVALID_ARGS); + + // Public key needs a extra byt of encoding header, which has a value of 0x04, to be included for PSA to validate + // and process the publc key. Copy the key into a new temp array and append the encoding header to it. + aByteArray[0] = 0x04; + memcpy(&aByteArray[1], aPublicKey, OT_CRYPTO_ECDSA_PUBLIC_KEY_SIZE); + + // Import the public key into a temp slot. + status = sl_sec_man_import_key(&aKeyId, + PSA_KEY_TYPE_ECC_PUBLIC_KEY(PSA_ECC_FAMILY_SECP_R1), + PSA_ALG_ECDSA(PSA_ALG_ANY_HASH), + PSA_KEY_USAGE_VERIFY_HASH, + PSA_KEY_PERSISTENCE_VOLATILE, + aByteArray, + OT_CRYPTO_ECDSA_PUBLIC_KEY_SIZE + 1); // To account for the padded byte. + + // If key import fails, assert, as we cannot proceed + OT_ASSERT(status == PSA_SUCCESS); + + // Verify the signature. + status = sl_sec_man_verify(aKeyId, + PSA_ALG_ECDSA(PSA_ALG_SHA_256), + aHash->m8, + sizeof(aHash->m8), + aSignature->m8, + sizeof(aSignature->m8), + aIsHash); + + // Destroy the temp key. + sl_sec_man_destroy_key(aKeyId); + + otEXPECT_ACTION((status == PSA_SUCCESS), error = OT_ERROR_FAILED); + +exit: + return error; +} + #endif // OPENTHREAD_CONFIG_CRYPTO_LIB == OPENTHREAD_CONFIG_CRYPTO_LIB_PSA diff --git a/protocol/openthread/platform-abstraction/efr32/entropy.c b/protocol/openthread/platform-abstraction/efr32/entropy.c index e04836d68e..602a9c3aa5 100644 --- a/protocol/openthread/platform-abstraction/efr32/entropy.c +++ b/protocol/openthread/platform-abstraction/efr32/entropy.c @@ -43,12 +43,6 @@ void otPlatCryptoRandomInit(void) { - // Security manager is initialised by OT stack, in key_manager. - // But Random manager is initialised much before this, so we - // initialise security manager here. Later initialisation by - // stack is ignored by security manager. - - (void)sl_sec_man_init(); } void otPlatCryptoRandomDeinit(void) diff --git a/protocol/openthread/platform-abstraction/efr32/flash.c b/protocol/openthread/platform-abstraction/efr32/flash.c index da504dee76..ddb80093d8 100644 --- a/protocol/openthread/platform-abstraction/efr32/flash.c +++ b/protocol/openthread/platform-abstraction/efr32/flash.c @@ -216,7 +216,7 @@ otError otPlatSettingsGet(otInstance *aInstance, uint16_t aKey, int aIndex, uint // number of bytes to the read destination buffer. uint8_t *buf = NULL; - status = sl_memory_alloc(valueLength, BLOCK_TYPE_SHORT_TERM, (void **)&buf); + status = sl_memory_alloc(valueLength, BLOCK_TYPE_LONG_TERM, (void **)&buf); VerifyOrExit(status == SL_STATUS_OK, err = OT_ERROR_FAILED); err = mapNvm3Error(nvm3_readData(nvm3_defaultHandle, nvm3Key, buf, valueLength)); @@ -345,14 +345,24 @@ otError otPlatSettingsDelete(otInstance *aInstance, uint16_t aKey, int aIndex) void otPlatSettingsWipe(otInstance *aInstance) { + nvm3_ObjectKey_t firstNvm3Key = makeNvm3ObjKey(1, 0); + nvm3_ObjectKey_t LastNvm3Key = makeNvm3ObjKey(0xFF, 0xFF); + nvm3_ObjectKey_t keys[ENUM_NVM3_KEY_LIST_SIZE]; + size_t objCnt; + OT_UNUSED_VARIABLE(aInstance); otEXPECT(sl_ot_rtos_task_can_access_pal()); - // Delete nvm3 objects for all OT Settings keys (and any of their associated 'indexes'). - // Note- any OT User nvm3 objects in the OT nvm3 area are NOT be erased. - for (uint16_t aKey = 0; aKey < 8; ++aKey) + objCnt = nvm3_enumObjects(nvm3_defaultHandle, keys, ENUM_NVM3_KEY_LIST_SIZE, firstNvm3Key, LastNvm3Key); + + while (objCnt > 0) { - otPlatSettingsDelete(NULL, aKey, -1); + for (size_t i = 0; i < objCnt; ++i) + { + nvm3_deleteObject(nvm3_defaultHandle, keys[i]); + } + + objCnt = nvm3_enumObjects(nvm3_defaultHandle, keys, ENUM_NVM3_KEY_LIST_SIZE, firstNvm3Key, LastNvm3Key); } exit: diff --git a/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h b/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h index 95eb4f5f7a..2453175878 100644 --- a/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h +++ b/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h @@ -227,8 +227,12 @@ * */ #ifndef OPENTHREAD_CONFIG_MAC_CSL_REQUEST_AHEAD_US +#if defined(_SILICON_LABS_32B_SERIES_3) +#define OPENTHREAD_CONFIG_MAC_CSL_REQUEST_AHEAD_US 15000 +#else #define OPENTHREAD_CONFIG_MAC_CSL_REQUEST_AHEAD_US 2000 #endif +#endif /** * @def OPENTHREAD_CONFIG_CSL_RECEIVE_TIME_AHEAD diff --git a/protocol/openthread/platform-abstraction/rtos/sl_ot_rtos_adaptation.c b/protocol/openthread/platform-abstraction/rtos/sl_ot_rtos_adaptation.c index 88eebca846..66993c2c74 100644 --- a/protocol/openthread/platform-abstraction/rtos/sl_ot_rtos_adaptation.c +++ b/protocol/openthread/platform-abstraction/rtos/sl_ot_rtos_adaptation.c @@ -43,6 +43,7 @@ #include "platform-efr32.h" #include "sl_cmsis_os2_common.h" #include "sl_component_catalog.h" +#include "sl_openthread_rtos_config.h" #include "sl_ot_init.h" #include "sl_ot_rtos_adaptation.h" diff --git a/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp-no-buttons.slcp b/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp-no-buttons.slcp index f04e5ef04f..6be2158116 100644 --- a/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp-no-buttons.slcp +++ b/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp-no-buttons.slcp @@ -69,8 +69,12 @@ configuration: condition: [iostream_eusart] - name: SL_HEAP_SIZE value: 16384 + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: OPENTHREAD_CONFIG_TMF_NETDIAG_CLIENT_ENABLE value: 0 - name: OPENTHREAD_CONFIG_LOG_OUTPUT diff --git a/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp b/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp index afbd849bd1..d57b655195 100644 --- a/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp +++ b/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp @@ -52,8 +52,12 @@ configuration: - name: SL_HEAP_SIZE value: 16384 condition: [freertos] + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED condition: [ot_rtt_log] diff --git a/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp b/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp index ac18a3a2f0..a09671eea5 100644 --- a/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp +++ b/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp @@ -52,8 +52,12 @@ configuration: - name: SL_HEAP_SIZE value: 16384 condition: [freertos] + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED condition: [ot_rtt_log] diff --git a/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-ftd-tz-ns.slcp b/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-ftd-tz-ns.slcp index 626484e600..afd1fd0415 100644 --- a/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-ftd-tz-ns.slcp +++ b/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-ftd-tz-ns.slcp @@ -52,8 +52,12 @@ configuration: - name: SL_HEAP_SIZE value: 16384 condition: [freertos] + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: CIRCULAR_QUEUE_LEN_MAX value: 16 - name: SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE diff --git a/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-mtd-tz-ns.slcp b/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-mtd-tz-ns.slcp index a51fe15516..52fec3ae55 100644 --- a/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-mtd-tz-ns.slcp +++ b/protocol/openthread/sample-apps/ot-cli/trustzone/ot-cli-mtd-tz-ns.slcp @@ -52,8 +52,12 @@ configuration: - name: SL_HEAP_SIZE value: 16384 condition: [freertos] + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: CIRCULAR_QUEUE_LEN_MAX value: 16 - name: SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE diff --git a/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp b/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp index 023b475c73..71495caf87 100644 --- a/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp @@ -52,8 +52,12 @@ configuration: - name: BUFFER_SIZE_UP value: 768 condition: [ot_rtt_log] + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: BUFFER_SIZE_DOWN value: 0 condition: [ot_rtt_log] diff --git a/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp b/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp index 9e0fd31c40..4941890d44 100644 --- a/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp @@ -59,7 +59,9 @@ configuration: - name: SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE value: SL_IOSTREAM_EUSART_UART_FLOW_CTRL_CTS_RTS condition: [iostream_eusart] - + - name: SL_OPENTHREAD_STACK_TASK_MEM_SIZE + value: 4608 + tag: - prebuilt_demo diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp index b238e460fa..249dd0c4a6 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp @@ -93,7 +93,9 @@ configuration: value: 15 - name: CIRCULAR_QUEUE_LEN_MAX value: 16 - + - name: SL_OPENTHREAD_STACK_TASK_MEM_SIZE + value: 4608 + template_contribution: - name: component_catalog value: bluetooth_ncp diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp index 05f2cffb43..9b63821bfe 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp @@ -68,7 +68,9 @@ configuration: value: 15 - name: CIRCULAR_QUEUE_LEN_MAX value: 16 - + - name: SL_OPENTHREAD_STACK_TASK_MEM_SIZE + value: 4608 + tag: - prebuilt_demo diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp index 448b6e49b1..9b8d4387f3 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp @@ -99,7 +99,9 @@ configuration: value: 15 - name: CIRCULAR_QUEUE_LEN_MAX value: 16 - + - name: SL_OPENTHREAD_STACK_TASK_MEM_SIZE + value: 4608 + template_contribution: - name: component_catalog value: bluetooth_ncp diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp index 3b6d26f947..ba6031f43a 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp @@ -74,6 +74,8 @@ configuration: value: 15 - name: CIRCULAR_QUEUE_LEN_MAX value: 16 + - name: SL_OPENTHREAD_STACK_TASK_MEM_SIZE + value: 4608 tag: - prebuilt_demo diff --git a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp index 72f6c38494..2d9f966066 100644 --- a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp +++ b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp @@ -44,8 +44,12 @@ configuration: - name: SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE value: 128 # Increase from default 32 condition: [iostream_eusart] + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED condition: [ot_rtt_log] diff --git a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp index 817294657a..a3bf09ab7b 100644 --- a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp +++ b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp @@ -53,8 +53,12 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED condition: [ot_rtt_log] diff --git a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ssed.slcp b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ssed.slcp index ea895e5210..107e32ef55 100644 --- a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ssed.slcp +++ b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ssed.slcp @@ -53,8 +53,12 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 + - name: SL_STACK_SIZE + value: 5120 + unless: [freertos] - name: SL_STACK_SIZE value: 4608 + condition: [freertos] - name: OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE value: 1 - name: OPENTHREAD_CONFIG_LOG_OUTPUT diff --git a/protocol/usb/usb.properties b/protocol/usb/usb.properties index 1f919b3701..7b4a9bbf66 100644 --- a/protocol/usb/usb.properties +++ b/protocol/usb/usb.properties @@ -11,7 +11,7 @@ # sure it is a valid GitHub version. Avoid merge or local commit hashes. id=com.silabs.sdk.stack.usb -version=1.4.0.0 +version=1.4.1.0 label=USB SDK description=USB stack support for EFM32 and EFR32 devices -prop.subLabel=USB\\ 1.4.0.0 +prop.subLabel=USB\\ 1.4.1.0 diff --git a/protocol/wisun/app/wisun_soc_brcli/app.c b/protocol/wisun/app/wisun_soc_brcli/app.c index 2aed790253..75524f80b1 100644 --- a/protocol/wisun/app/wisun_soc_brcli/app.c +++ b/protocol/wisun/app/wisun_soc_brcli/app.c @@ -60,7 +60,7 @@ #include "sl_wisun_br_dhcpv6_server.h" #endif -#define APP_TASK_PRIORITY osPriorityLow3 // Lowest priority in the system for all CLI related task +#define APP_TASK_PRIORITY osPriorityLow1 // (CLI related task) must be the lowest priority in the system #define APP_TASK_STACK_SIZE 500 // in units of CPU_INT32U #define APP_ICMPV6_TYPE_ECHO_REQUEST 128 @@ -76,7 +76,7 @@ #define APP_CERTIFICATE_INDEX_ALL 255 #define APP_SERVICE_TASK_NAME "app_service_task" -#define APP_SERVICE_TASK_PRIORITY osPriorityLow3 +#define APP_SERVICE_TASK_PRIORITY osPriorityBelowNormal1 #define APP_SERVICE_TASK_STACK_SIZE 500 // in units of CPU_INT32U SL_PACK_START(1) @@ -271,7 +271,7 @@ static sl_slist_node_t *app_socket_entry_list; static app_socket_entry_t app_socket_entries[APP_MAX_SOCKET_ENTRIES]; static bool app_started; -static int app_dhcpv6_socket; +static int app_dhcpv6_socket = SOCKET_INVALID_ID; static void app_handle_join_state_ind(sl_wisun_evt_t *evt) { @@ -429,6 +429,12 @@ static void app_handle_socket_data_ind(sl_wisun_evt_t *evt) static void app_handle_socket_data_available_ind(sl_wisun_evt_t *evt) { + app_socket_entry_t *entry; + + entry = app_socket_entry(evt->evt.socket_data_sent.socket_id); + if (!entry) { + return; + } printf("[Data available: %lu,%u]\r\n", evt->evt.socket_data_available.socket_id, evt->evt.socket_data_available.data_length); @@ -544,9 +550,9 @@ static void app_handle_dhcp_vendor_data_ind(sl_wisun_evt_t *evt) static void app_handle_br_stopped_ind(sl_wisun_evt_t *evt) { if (evt->evt.br_stopped.status == SL_STATUS_OK) { - printf("[Border Router stopped]"); + printf("[Border Router stopped]\r\n"); } else { - printf("[Failed to stop Border Router]"); + printf("[Failed to stop Border Router]\r\n"); } } @@ -1324,6 +1330,23 @@ void app_set_trace_level(sl_cli_command_arg_t *arguments) app_wisun_cli_mutex_unlock(); } +void app_clear_credential_cache(sl_cli_command_arg_t *arguments) +{ + sl_status_t ret; + (void)arguments; + + app_wisun_cli_mutex_lock(); + + ret = sl_wisun_clear_credential_cache(); + if (ret == SL_STATUS_OK) { + printf("[Credential cache cleared]\r\n"); + } else { + printf("[Credential cache clear failed: %lu]\r\n", ret); + } + + app_wisun_cli_mutex_unlock(); +} + void app_reset_statistics(sl_cli_command_arg_t *arguments) { sl_status_t ret; diff --git a/protocol/wisun/app/wisun_soc_brcli/app_settings.c b/protocol/wisun/app/wisun_soc_brcli/app_settings.c index b10e41e942..1c9421031b 100644 --- a/protocol/wisun/app/wisun_soc_brcli/app_settings.c +++ b/protocol/wisun/app/wisun_soc_brcli/app_settings.c @@ -35,7 +35,7 @@ #include "sl_wisun_br_wifi.h" #endif -#ifdef WISUN_FAN_CERTIFICATION +#ifdef SL_CATALOG_WISUN_FAN_CERTIFICATION_PRESENT // Defaults for Wi-SUN FAN Certification. @@ -47,7 +47,7 @@ #define APP_SETTINGS_WISUN_DEFAULT_CHAN_PLAN_ID 1 #define APP_SETTINGS_WISUN_DEFAULT_PHY_MODE_ID 2 #define APP_SETTINGS_WISUN_DEFAULT_NETWORK_SIZE SL_WISUN_NETWORK_SIZE_CERTIFICATION - #define APP_SETTINGS_WISUN_DEFAULT_ALLOWED_CHANNELS "0" + #define APP_SETTINGS_WISUN_DEFAULT_ALLOWED_CHANNELS "10" #elif defined SL_CATALOG_WISUN_CONFIG_PRESENT @@ -420,6 +420,7 @@ static const app_enum_t app_settings_wisun_regulation_enum[] = { "none", SL_WISUN_REGULATION_NONE }, { "arib", SL_WISUN_REGULATION_ARIB }, { "wpc", SL_WISUN_REGULATION_WPC }, + { "etsi", SL_WISUN_REGULATION_ETSI }, { NULL, 0 } }; diff --git a/protocol/wisun/app/wisun_soc_brcli/doc/readme.md b/protocol/wisun/app/wisun_soc_brcli/doc/readme.md index 7a7cf4b42f..121c60af9f 100644 --- a/protocol/wisun/app/wisun_soc_brcli/doc/readme.md +++ b/protocol/wisun/app/wisun_soc_brcli/doc/readme.md @@ -72,10 +72,11 @@ The list of available commands is output on the console with the associated help | wisun udp_client \ \ | Open a UDP connection to a remote host | > wisun udp_client fd00:6172:6d00:0:3038:5115:26:27 7 | | wisun udp_server \ | Open a UDP server port | > wisun udp_server 5001 | | wisun socket_get_option \ \ This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -22,13 +22,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -37,13 +37,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -52,13 +52,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -67,13 +67,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -82,13 +82,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -97,13 +97,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -112,13 +112,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -127,13 +127,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -142,13 +142,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -157,13 +157,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -172,13 +172,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -187,13 +187,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -202,13 +202,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -217,13 +217,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -232,13 +232,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -247,13 +247,13 @@ - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -262,13 +262,13 @@ - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -278,13 +278,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -294,13 +294,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -310,13 +310,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -326,13 +326,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -342,13 +342,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -358,13 +358,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -374,13 +374,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -390,13 +390,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTW update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -406,13 +406,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -422,13 +422,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -438,13 +438,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -454,13 +454,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -470,13 +470,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -486,13 +486,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -502,13 +502,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -518,13 +518,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -534,13 +534,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By SerialAPI Application, the region is selected by the Host application. @@ -550,130 +550,130 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: By the NCP Zniffer Application, the region is selected by the Host application. The Z-Wave Zniffer Application - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -682,13 +682,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -697,13 +697,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -712,13 +712,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -727,13 +727,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -742,13 +742,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -757,13 +757,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -772,13 +772,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -787,13 +787,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -802,13 +802,13 @@ The Serial API End Device allows the user to create a product with a host applic - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -818,13 +818,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -834,13 +834,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -850,13 +850,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -866,13 +866,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -882,13 +882,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -898,13 +898,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -914,13 +914,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -930,13 +930,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -946,13 +946,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -962,13 +962,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -978,13 +978,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -994,13 +994,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1010,13 +1010,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1026,13 +1026,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1042,13 +1042,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1058,13 +1058,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1074,13 +1074,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1090,13 +1090,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1105,13 +1105,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1120,13 +1120,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1135,13 +1135,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1150,13 +1150,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1165,13 +1165,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1180,13 +1180,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1195,13 +1195,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1210,13 +1210,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1225,13 +1225,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1240,13 +1240,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1255,13 +1255,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1270,13 +1270,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1285,13 +1285,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1300,13 +1300,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1315,13 +1315,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1330,13 +1330,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1345,13 +1345,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1360,13 +1360,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1375,13 +1375,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1390,13 +1390,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1405,13 +1405,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1420,13 +1420,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1435,13 +1435,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1450,13 +1450,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1465,13 +1465,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1480,13 +1480,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1495,13 +1495,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1510,13 +1510,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1525,13 +1525,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1540,13 +1540,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1555,13 +1555,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1570,13 +1570,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1585,13 +1585,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1600,13 +1600,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1615,13 +1615,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1630,13 +1630,13 @@ For certain devices, the application supports and uses the User Credential Comma - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1647,13 +1647,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1664,13 +1664,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1681,13 +1681,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1698,13 +1698,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1715,13 +1715,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1732,13 +1732,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1749,13 +1749,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1766,13 +1766,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1783,13 +1783,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1800,13 +1800,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1817,13 +1817,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1834,13 +1834,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1851,13 +1851,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1868,13 +1868,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1885,13 +1885,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1902,13 +1902,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1919,13 +1919,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1936,13 +1936,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1951,13 +1951,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1966,13 +1966,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1981,13 +1981,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -1996,13 +1996,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2011,13 +2011,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2026,13 +2026,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2041,13 +2041,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2056,13 +2056,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2071,13 +2071,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2086,13 +2086,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2101,13 +2101,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2116,13 +2116,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2131,13 +2131,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2146,13 +2146,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2161,13 +2161,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2176,13 +2176,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2191,13 +2191,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2206,13 +2206,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2221,13 +2221,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2236,13 +2236,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2251,13 +2251,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2266,13 +2266,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2281,13 +2281,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2296,13 +2296,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2311,13 +2311,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2326,13 +2326,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2341,13 +2341,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2356,13 +2356,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2371,13 +2371,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2386,13 +2386,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2401,13 +2401,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2416,13 +2416,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2431,13 +2431,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2446,13 +2446,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2461,13 +2461,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2476,13 +2476,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2491,13 +2491,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2506,13 +2506,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2521,13 +2521,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2536,13 +2536,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2551,13 +2551,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2566,13 +2566,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2581,13 +2581,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2596,13 +2596,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + This variant of demo is created for testing OTA update. The firmware is the same as the default variant, except the application version is set to '255.0.0'. IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2611,13 +2611,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2626,13 +2626,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2641,13 +2641,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2656,13 +2656,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2671,13 +2671,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2686,13 +2686,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2701,13 +2701,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2716,13 +2716,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2731,13 +2731,13 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + IMPORTANT: The default region for this firmware is EU. This region is only applied by SoC applications if the dedicated MFG_ZWAVE_COUNTRY_FREQ token is empty (0xFF) when the application first starts up. If another region is needed, then the MFG_ZWAVE_COUNTRY_FREQ token must be set with Simplicity Commander using the following command: `commander flash --tokengroup znet --token MFG_ZWAVE_COUNTRY_FREQ:{region_hex}`, where the {region_hex} is the desired region. The available regions can be found in the `zpal_radio.h` file, such as REGION_EU. @@ -2746,12 +2746,12 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + - + diff --git a/protocol/z-wave/zwave.properties b/protocol/z-wave/zwave.properties index 67110a66b7..0877ff7891 100644 --- a/protocol/z-wave/zwave.properties +++ b/protocol/z-wave/zwave.properties @@ -3,7 +3,7 @@ id=com.silabs.sdk.stack.zwave label=Z-Wave SDK description=Silicon Labs Z-Wave SDK for the EFR32 family -version=7.23.0.0 +version=7.23.1.0 #Build Information @@ -12,7 +12,7 @@ buildNumber=0 # Note: this particular string must be escaped -prop.subLabel=Z-Wave\\ SDK\\ 7.23.0.0 +prop.subLabel=Z-Wave\\ SDK\\ 7.23.1.0 # Path to side-package properties file # extendedProperties= diff --git a/protocol/zigbee/app/em260/serial-interface.h b/protocol/zigbee/app/em260/serial-interface.h index c76a29622a..e4dd439da4 100644 --- a/protocol/zigbee/app/em260/serial-interface.h +++ b/protocol/zigbee/app/em260/serial-interface.h @@ -46,6 +46,10 @@ bool serialCallbackResponse(void); void serialMfglibFillPacket(uint8_t *packet); void serialDelayTest(uint16_t delay); +#ifdef EZSP_CPC +void sli_zigbee_cpc_serial_buffer_init(void); +#endif // EZSP_CPC + #ifdef SLEEPY_EZSP_ASH #include "hal/micro/generic/ash-ncp.h" #else diff --git a/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.c.jinja b/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.c.jinja index dda8ffd49e..854f0db702 100644 --- a/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.c.jinja +++ b/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.c.jinja @@ -714,6 +714,17 @@ void sli_zigbee_af_counter_rollover( {% endfor -%} } +{# MUX_INVALID_RX #} +// mux_invalid_rx +void sli_zigbee_af_mux_invalid_rx(uint8_t new_rx_channel, uint8_t old_rx_channel) +{ +{% for cb in zigbee_stack_callback -%} +{% if cb['callback_type'] == "mux_invalid_rx" -%} +{{ cb['function_name'] }}(new_rx_channel, old_rx_channel); +{% endif -%} +{% endfor -%} +} + {# RAW_TRANSMIT_COMPLETE #} // Raw Transmit Complete diff --git a/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.h.jinja b/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.h.jinja index b8c6429cfd..3aa44e04d7 100644 --- a/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.h.jinja +++ b/protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.h.jinja @@ -755,6 +755,19 @@ void {{ cb['function_name'] }}( {% endif -%} {% endfor -%} +{# MUX_INVALID_RX #} +// mux_invalid_rx +void sli_zigbee_af_mux_invalid_rx(uint8_t new_rx_channel, uint8_t old_rx_channel) +; +{% for cb in zigbee_stack_callback -%} +{% if cb['callback_type'] == "mux_invalid_rx" -%} +void {{ cb['function_name'] }}( + uint8_t new_rx_channel, uint8_t old_rx_channel) +; +{% endif -%} +{% endfor -%} + + {# RAW_TRANSMIT_COMPLETE #} // Raw Transmit Complete diff --git a/protocol/zigbee/app/framework/common/zigbee_app_framework_callback.h b/protocol/zigbee/app/framework/common/zigbee_app_framework_callback.h index 34b851284f..39ee05dfdc 100644 --- a/protocol/zigbee/app/framework/common/zigbee_app_framework_callback.h +++ b/protocol/zigbee/app/framework/common/zigbee_app_framework_callback.h @@ -363,6 +363,16 @@ void sl_zigbee_af_counter_rollover_cb( // Type of Counter sl_zigbee_counter_type_t type); +/** + * @brief Callback function invoked when an invalid RX channel is detected. + * + * This function is called when the RX channel changes to an invalid state. + * + * @param new_rx_channel The new RX channel that has been detected as invalid. + * @param old_rx_channel The previous RX channel before the change. + */ +void sl_zigbee_af_mux_invalid_rx_cb(uint8_t new_rx_channel, uint8_t old_rx_channel); + /** @brief * A callback invoked by the EmberZNet stack when the MAC has finished * transmitting a raw message. diff --git a/protocol/zigbee/app/framework/common/zigbee_app_framework_host_cb.c b/protocol/zigbee/app/framework/common/zigbee_app_framework_host_cb.c index 2aa6d40cce..b4674d5c75 100644 --- a/protocol/zigbee/app/framework/common/zigbee_app_framework_host_cb.c +++ b/protocol/zigbee/app/framework/common/zigbee_app_framework_host_cb.c @@ -778,6 +778,21 @@ void sl_zigbee_ezsp_counter_rollover_handler(sl_zigbee_counter_type_t type) sl_zigbee_af_counter_rollover_cb(type); sl_zigbee_af_pop_network_index(); } +//sli_zigbee_af_mux_invalid_rx_callback + +// ----------------------------------------------------------------------------- +// Weak implementation of public Callback sl_zigbee_af_mux_invalid_rx_cb +WEAK(void sl_zigbee_af_mux_invalid_rx_cb(uint8_t new_rx_channel, uint8_t old_rx_channel)) +{ +} + +void sl_zigbee_ezsp_mux_invalid_rx_handler(uint8_t new_rx_channel, uint8_t old_rx_channel) +{ + sl_zigbee_af_push_callback_network_index(); + sli_zigbee_af_mux_invalid_rx(new_rx_channel, old_rx_channel); + sl_zigbee_af_mux_invalid_rx_cb(new_rx_channel, old_rx_channel); + sl_zigbee_af_pop_network_index(); +} // ----------------------------------------------------------------------------- // Weak implementation of public Callback sl_zigbee_af_zll_address_assignment_cb diff --git a/protocol/zigbee/app/framework/common/zigbee_app_framework_stack_cb.c b/protocol/zigbee/app/framework/common/zigbee_app_framework_stack_cb.c index 0cb94de353..8619a23c53 100644 --- a/protocol/zigbee/app/framework/common/zigbee_app_framework_stack_cb.c +++ b/protocol/zigbee/app/framework/common/zigbee_app_framework_stack_cb.c @@ -1043,6 +1043,19 @@ void sl_zigbee_counter_rollover_handler( sl_zigbee_af_pop_network_index(); } +// Weak implementation of public Callback sl_zigbee_af_mux_invalid_rx_cb +WEAK(void sl_zigbee_af_mux_invalid_rx_cb(uint8_t new_rx_channel, uint8_t old_rx_channel)) +{ +} + +void sl_zigbee_mux_invalid_rx_handler(uint8_t new_rx_channel, uint8_t old_rx_channel) +{ + sl_zigbee_af_push_callback_network_index(); + sli_zigbee_af_mux_invalid_rx(new_rx_channel, old_rx_channel); + sl_zigbee_af_mux_invalid_rx_cb(new_rx_channel, old_rx_channel); + sl_zigbee_af_pop_network_index(); +} + // ----------------------------------------------------------------------------- // Weak implementation of public Callback sl_zigbee_af_raw_transmit_complete_cb WEAK(void sl_zigbee_af_raw_transmit_complete_cb( diff --git a/protocol/zigbee/app/framework/common/zigbee_stack_rtos_adaptation.c b/protocol/zigbee/app/framework/common/zigbee_stack_rtos_adaptation.c index b89287716e..02a83c5b91 100644 --- a/protocol/zigbee/app/framework/common/zigbee_stack_rtos_adaptation.c +++ b/protocol/zigbee/app/framework/common/zigbee_stack_rtos_adaptation.c @@ -188,7 +188,11 @@ void sli_zigbee_send_ipc_cmd(sli_zigbee_ipc_cmd_handler_t handler, if (zigbee_stack_task_id == osThreadGetId()) { handler(cmd); } else { - osStatus_t ret = osMutexAcquire(zigbee_ipc_mutex_id, 0); + osStatus_t ret = osMutexAcquire(zigbee_ipc_mutex_id, osWaitForever); + if (ret != osOK) { + EFM_ASSERT(false); + return; + } sli_zigbee_ipc_pending_command_handler = handler; sli_zigbee_ipc_pending_command = cmd; @@ -204,12 +208,12 @@ void sli_zigbee_send_ipc_cmd(sli_zigbee_ipc_cmd_handler_t handler, osEventFlagsWait(zigbee_ipc_flags_id, ZIGBEE_IPC_COMMAND_PROCESSED_FLAG, osFlagsWaitAny, - 0); + osWaitForever); osEventFlagsClear(zigbee_ipc_flags_id, ZIGBEE_IPC_COMMAND_PROCESSED_FLAG); ret = osMutexRelease(zigbee_ipc_mutex_id); - (void)ret; + EFM_ASSERT(ret == osOK); } } #endif// SL_CATALOG_ZIGBEE_REAL_IPC_PRESENT diff --git a/protocol/zigbee/app/framework/common/zigbee_token_interface.c b/protocol/zigbee/app/framework/common/zigbee_token_interface.c index 3e0020b732..a59db78e2a 100644 --- a/protocol/zigbee/app/framework/common/zigbee_token_interface.c +++ b/protocol/zigbee/app/framework/common/zigbee_token_interface.c @@ -73,8 +73,9 @@ void sl_zigbee_token_factory_reset(bool exclude_outgoing_fc, bool exclude_boot_c sl_zigbee_set_token_data(token_info.nvm3Key, arrayIndex, &token_data); + // NVM3 write may take a long time to run, thus manually reset the watchdog. + halResetWatchdog(); } - halResetWatchdog(); } } } diff --git a/protocol/zigbee/app/framework/component/scripts/zigbee_cli_task_stack_size.lua b/protocol/zigbee/app/framework/component/scripts/zigbee_cli_task_stack_size.lua new file mode 100644 index 0000000000..19473e38ac --- /dev/null +++ b/protocol/zigbee/app/framework/component/scripts/zigbee_cli_task_stack_size.lua @@ -0,0 +1,18 @@ +local changeset = {} + +local rtos = slc.is_provided("cmsis_rtos2") + +if rtos == true then + local cli_task_stack_size_configuration = slc.config('SL_CLI_EXAMPLE_TASK_STACK_SIZE') + if cli_task_stack_size_configuration ~= nil then + local cli_task_stack_size_value = tonumber(cli_task_stack_size_configuration.value) + if (cli_task_stack_size_value < 600) then + validation.error("To prevent stack overflow when using an RTOS, ensure the CLI task stack size is configured to at least 600 words.", + validation.target_for_defines({"SL_CLI_EXAMPLE_TASK_STACK_SIZE"}), + nil, + nil) + end + end +end + +return changeset \ No newline at end of file diff --git a/protocol/zigbee/app/framework/component/zigbee_cli.slcc b/protocol/zigbee/app/framework/component/zigbee_cli.slcc index c24adc0aa1..db42f9637b 100644 --- a/protocol/zigbee/app/framework/component/zigbee_cli.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_cli.slcc @@ -18,6 +18,8 @@ include: source: - path: protocol/zigbee/app/util/serial/sl_zigbee_command_interpreter.c +validation_helper: + - path: protocol/zigbee/app/framework/component/scripts/zigbee_cli_task_stack_size.lua template_contribution: - name: component_catalog value: zigbee_cli diff --git a/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c b/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c index 2b340b4b09..0bcd2d52f8 100644 --- a/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c +++ b/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c @@ -20,7 +20,6 @@ #include "sl_board_control.h" #include "sl_simple_button_instances.h" -#include "em_assert.h" #include "glib.h" #include "dmd.h" #include "app/framework/include/af.h" diff --git a/protocol/zigbee/app/framework/plugin/throughput/throughput.c b/protocol/zigbee/app/framework/plugin/throughput/throughput.c index 33b8ecd8ad..f61a6c8843 100644 --- a/protocol/zigbee/app/framework/plugin/throughput/throughput.c +++ b/protocol/zigbee/app/framework/plugin/throughput/throughput.c @@ -177,7 +177,7 @@ static void printResult(void) var = testParams.varSendTimeMs * 10 / testParams.messageSuccessCount; if (var > (mean * mean) ) { var -= (mean * mean); - std = sqrt(fabs(var)); + std = (uint32_t)sqrt((double)var); } else { std = 0; } diff --git a/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.c b/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.c index 9425608665..481a44a6c1 100644 --- a/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.c +++ b/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.c @@ -461,6 +461,16 @@ void sli_zigbee_af_zll_commissioning_common_stack_status_callback(sl_status_t st } } +void sl_zigbee_af_zll_unset_factory_new(void) +{ + sl_zigbee_tok_type_stack_zll_data_t token; + sl_zigbee_zll_get_token_stack_zll_data(&token); + if ((token.bitmask & SL_ZIGBEE_ZLL_STATE_FACTORY_NEW)) { + token.bitmask &= ~SL_ZIGBEE_ZLL_STATE_FACTORY_NEW; + sl_zigbee_zll_set_token_stack_zll_data(&token); + } +} + bool sl_zigbee_af_zll_touch_link_in_progress(void) { // Returns true if a touch link is in progress or false otherwise. diff --git a/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.h b/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.h index e76655e49c..c54cd1d7f5 100644 --- a/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.h +++ b/protocol/zigbee/app/framework/plugin/zll-commissioning-common/zll-commissioning-common.h @@ -79,6 +79,15 @@ bool sl_zigbee_af_zll_touch_link_in_progress(void); */ void sl_zigbee_af_zll_reset_to_factory_new(void); +/** + * @brief Unsets the factory new status for a Zigbee device. + * + * This function is used to clear the factory new status of a Zigbee device, + * indicating that the device has been previously commissioned and is no longer + * in its factory default state. + */ +void sl_zigbee_af_zll_unset_factory_new(void); + /** @brief Disable touchlink processing. * * This function will cause the device to refuse network start/join diff --git a/protocol/zigbee/app/framework/util/af-soc.c b/protocol/zigbee/app/framework/util/af-soc.c index 26e3336704..9eb9c8bdf9 100644 --- a/protocol/zigbee/app/framework/util/af-soc.c +++ b/protocol/zigbee/app/framework/util/af-soc.c @@ -276,13 +276,7 @@ uint8_t sl_zigbee_af_get_stack_profile(void) uint8_t sli_zigbee_stack_get_endpoint(uint8_t index) { uint8_t ep; -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_acquire_lock(); -#endif ep = sli_zigbee_af_get_endpoint(index); -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_release_lock(); -#endif // SL_CATALOG_KERNEL_PRESENT return ep; } @@ -291,13 +285,7 @@ bool sli_zigbee_stack_get_endpoint_description(uint8_t endpoint, sl_zigbee_endpoint_description_t *result) { bool status; -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_acquire_lock(); -#endif status = sli_zigbee_af_get_endpoint_description(endpoint, result); -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_release_lock(); -#endif return status; } @@ -308,13 +296,7 @@ uint16_t sli_zigbee_stack_get_endpoint_cluster(uint8_t endpoint, uint8_t listIndex) { uint16_t cluster; -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_acquire_lock(); -#endif cluster = sli_zigbee_af_get_endpoint_cluster(endpoint, listId, listIndex); -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_release_lock(); -#endif return cluster; } @@ -433,12 +415,6 @@ void sli_zigbee_af_print_ezsp_endpoint_flags(uint8_t endpoint) uint8_t sli_zigbee_stack_get_endpoint_count(void) { uint8_t numberOfEndpoints; -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_acquire_lock(); -#endif numberOfEndpoints = sl_zigbee_af_endpoint_count(); -#ifdef SL_CATALOG_KERNEL_PRESENT - sl_zigbee_af_release_lock(); -#endif return numberOfEndpoints; } diff --git a/protocol/zigbee/app/ncp/meta-inf/ezsp.yaml b/protocol/zigbee/app/ncp/meta-inf/ezsp.yaml index dc1d366d41..fc9b7b0d50 100644 --- a/protocol/zigbee/app/ncp/meta-inf/ezsp.yaml +++ b/protocol/zigbee/app/ncp/meta-inf/ezsp.yaml @@ -5460,6 +5460,27 @@ }, ], }, + ## MUX_INVALID_RX_HANDLER + { + value: "0x005D", + needGeneratedHandler : "no", + commandName: "mux_invalid_rx_handler", + description: "This call is fired when mux detects an invalid rx case, + which would be different rx channels for different protocol contexts, + when fast cahnnel switching is not enabled", + responseArguments: [ + { + type: "uint8_t", + name: "new_rx_channel", + description: "", + }, + { + type: "uint8_t", + name: "old_rx_channel", + description: "", + }, + ], + }, ## DELAY_TEST { value: "0x009D", diff --git a/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/app.c b/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/app.c index 9edeac107a..95475d50ef 100644 --- a/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/app.c +++ b/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/app.c @@ -100,6 +100,9 @@ otInstance *otGetInstance(void) return sInstance; } +#define OT_NWK_UP (otThreadGetDeviceRole(sInstance) != OT_DEVICE_ROLE_DISABLED) +#else +#define OT_NWK_UP false #endif //#if defined(OPENTHREAD_FTD) //--------------- @@ -146,14 +149,17 @@ static void finding_and_binding_event_handler(sl_zigbee_af_event_t *event) * of changes to the stack status and take appropriate action. The framework * will always process the stack status after the callback returns. */ +bool zb_nwk_up = false; void sl_zigbee_af_stack_status_cb(sl_status_t status) { // Note, the ZLL state is automatically updated by the stack and the plugin. if (status == SL_STATUS_NETWORK_DOWN) { led_turn_off(COMMISSIONING_STATUS_LED); + zb_nwk_up = false; } else if (status == SL_STATUS_NETWORK_UP) { led_turn_on(COMMISSIONING_STATUS_LED); sl_zigbee_af_event_set_active(&finding_and_binding_event); + zb_nwk_up = true; } } @@ -308,6 +314,15 @@ void sl_zigbee_af_hal_button_isr_cb(uint8_t button, uint8_t state) } #endif // EBER_TEST +void sl_rail_mux_invalid_rx_channel_detected_cb(int new_rx_channel, int old_rx_channel) +{ + if (zb_nwk_up || OT_NWK_UP) { + sl_zigbee_af_core_println("WARNING: MUX detected invalid RX attempts on both %d and %d channels", + new_rx_channel, old_rx_channel); + EFM_ASSERT(false); + } +} + #ifdef SL_CATALOG_BLUETOOTH_PRESENT //------------------------------------------------------------------------------ diff --git a/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/z3-light_ot-ftd_soc.slcp b/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/z3-light_ot-ftd_soc.slcp index 3de0789df8..393be18789 100644 --- a/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/z3-light_ot-ftd_soc.slcp +++ b/protocol/zigbee/app/projects/multiprotocol/z3-light_ot-ftd_soc/z3-light_ot-ftd_soc.slcp @@ -145,7 +145,10 @@ configuration: value: 1 - name: SL_BT_CONFIG_MAX_CONNECTIONS value: 1 - + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 define: - name: OS_CFG_COMPAT_INIT diff --git a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_direct_device_light/zigbee_ble_direct_device_light.slcp b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_direct_device_light/zigbee_ble_direct_device_light.slcp index 7d08693f74..eb9e4a78c5 100644 --- a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_direct_device_light/zigbee_ble_direct_device_light.slcp +++ b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_direct_device_light/zigbee_ble_direct_device_light.slcp @@ -138,7 +138,10 @@ configuration: value: 0 - name: configMAX_TASK_NAME_LEN value: 30 - + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 define: - name: OS_CFG_COMPAT_INIT diff --git a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light.slcp b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light.slcp index 525a4cb7ae..b4b429aed9 100644 --- a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light.slcp +++ b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light.slcp @@ -143,6 +143,10 @@ configuration: value: 53 - name: configMAX_TASK_NAME_LEN value: 30 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 define: - name: OS_CFG_COMPAT_INIT diff --git a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light_minimal.slcp b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light_minimal.slcp index 002150dce3..38bb056f9e 100644 --- a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light_minimal.slcp +++ b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light/zigbee_ble_dynamic_multiprotocol_light_minimal.slcp @@ -132,6 +132,10 @@ configuration: value: 53 - name: configMAX_TASK_NAME_LEN value: 30 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 define: - name: OS_CFG_COMPAT_INIT diff --git a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/app.c b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/app.c index b3b2a2eedc..7d56e5f277 100644 --- a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/app.c +++ b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/app.c @@ -60,7 +60,9 @@ static sl_zigbee_af_event_t button_event; #define led_turn_off(led) sl_led_turn_off(led) #define led_toggle(led) sl_led_toggle(led) #define LED0 (&sl_led_led0) +#if defined(SL_CATALOG_LED1_PRESENT) #define LED1 (&sl_led_led1) +#endif // SL_CATALOG_LED1_PRESENT #else // !SL_CATALOG_LED0_PRESENT #define led_turn_on(led) #define led_turn_off(led) @@ -265,14 +267,18 @@ void sl_zigbee_af_post_attribute_change_cb(uint8_t endpoint, if (status == SL_ZIGBEE_ZCL_STATUS_SUCCESS) { if (data == 0x00) { led_turn_off(LED0); +#if defined(SL_CATALOG_LED1_PRESENT) led_turn_off(LED1); +#endif //SL_CATALOG_LED1_PRESENT sl_dmp_ui_light_off(); #ifdef SL_CATALOG_ZIGBEE_BLE_EVENT_HANDLER_PRESENT zb_ble_dmp_notify_light(DMP_UI_LIGHT_OFF); #endif } else { led_turn_on(LED0); +#if defined(SL_CATALOG_LED1_PRESENT) led_turn_on(LED1); +#endif //SL_CATALOG_LED1_PRESENT #ifdef SL_CATALOG_ZIGBEE_BLE_EVENT_HANDLER_PRESENT zb_ble_dmp_notify_light(DMP_UI_LIGHT_ON); #endif diff --git a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed.slcp b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed.slcp index cb26cec23f..b755cafd0d 100644 --- a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed.slcp +++ b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed.slcp @@ -137,7 +137,10 @@ configuration: value: 53 - name: configMAX_TASK_NAME_LEN value: 30 - + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 define: - name: OS_CFG_COMPAT_INIT diff --git a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed_minimal.slcp b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed_minimal.slcp index 98a707e132..862e774398 100644 --- a/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed_minimal.slcp +++ b/protocol/zigbee/app/projects/multiprotocol/zigbee_ble_dynamic_multiprotocol_light_sed/zigbee_ble_dynamic_multiprotocol_light_sed_minimal.slcp @@ -126,7 +126,10 @@ configuration: value: 53 - name: configMAX_TASK_NAME_LEN value: 30 - + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 define: - name: OS_CFG_COMPAT_INIT diff --git a/protocol/zigbee/app/projects/ncp/ncp-cmp/app.c b/protocol/zigbee/app/projects/ncp/ncp-cmp/app.c index 60eee90b16..0db72280e0 100644 --- a/protocol/zigbee/app/projects/ncp/ncp-cmp/app.c +++ b/protocol/zigbee/app/projects/ncp/ncp-cmp/app.c @@ -86,5 +86,20 @@ void sl_ot_ncp_init(void) { otAppNcpInit(sInstance); } - +#define OT_NWK_UP (otThreadGetDeviceRole(sInstance) != OT_DEVICE_ROLE_DISABLED) +#else +#define OT_NWK_UP false #endif //#if defined(OPENTHREAD_FTD) || defined(OPENTHREAD_RADIO) + +void sl_rail_mux_invalid_rx_channel_detected_cb(uint8_t new_rx_channel, uint8_t old_rx_channel) +{ + sl_zigbee_node_type_t type = SL_ZIGBEE_UNKNOWN_DEVICE; + sli_zigbee_stack_get_network_parameters(type, NULL); + + if (type != SL_ZIGBEE_UNKNOWN_DEVICE + // || sli_zigbee_node_type != SL_ZIGBEE_UNKNOWN_DEVICE + || OT_NWK_UP) { + sl_zigbee_mux_invalid_rx_handler(new_rx_channel, old_rx_channel); + //EFM_ASSERT(false); + } +} diff --git a/protocol/zigbee/app/projects/z3/zigbee_gp_z3_gateway_combo/zigbee_gp_z3_gateway_combo.slcp b/protocol/zigbee/app/projects/z3/zigbee_gp_z3_gateway_combo/zigbee_gp_z3_gateway_combo.slcp index 92baad7a2f..a290ea382e 100644 --- a/protocol/zigbee/app/projects/z3/zigbee_gp_z3_gateway_combo/zigbee_gp_z3_gateway_combo.slcp +++ b/protocol/zigbee/app/projects/z3/zigbee_gp_z3_gateway_combo/zigbee_gp_z3_gateway_combo.slcp @@ -89,6 +89,10 @@ configuration: value: 5 - name: SL_CLI_EXAMPLE_IOSTREAM_HANDLE value: sl_iostream_get_default() + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 include: - path: ./ diff --git a/protocol/zigbee/app/projects/z3/zigbee_gp_z3_light_combo/zigbee_gp_z3_light_combo.slcp b/protocol/zigbee/app/projects/z3/zigbee_gp_z3_light_combo/zigbee_gp_z3_light_combo.slcp index cd99170f31..46ca430829 100644 --- a/protocol/zigbee/app/projects/z3/zigbee_gp_z3_light_combo/zigbee_gp_z3_light_combo.slcp +++ b/protocol/zigbee/app/projects/z3/zigbee_gp_z3_light_combo/zigbee_gp_z3_light_combo.slcp @@ -106,6 +106,10 @@ configuration: value: 5 - name: SL_ZIGBEE_BROADCAST_TABLE_SIZE value: 21 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 source: - path: main.c diff --git a/protocol/zigbee/app/projects/z3/zigbee_minimal/zigbee_minimal.slcp b/protocol/zigbee/app/projects/z3/zigbee_minimal/zigbee_minimal.slcp index b628087688..1fa897f28c 100644 --- a/protocol/zigbee/app/projects/z3/zigbee_minimal/zigbee_minimal.slcp +++ b/protocol/zigbee/app/projects/z3/zigbee_minimal/zigbee_minimal.slcp @@ -61,6 +61,11 @@ configuration: value: 0 - name: SL_PSA_ITS_SUPPORT_V3_DRIVER value: 1 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 + source: - path: main.c - path: app.c diff --git a/protocol/zigbee/app/projects/z3/zigbee_unified_test_harness/zigbee_unified_test_harness.slcp b/protocol/zigbee/app/projects/z3/zigbee_unified_test_harness/zigbee_unified_test_harness.slcp index 5d74ee7af0..bf16938dec 100644 --- a/protocol/zigbee/app/projects/z3/zigbee_unified_test_harness/zigbee_unified_test_harness.slcp +++ b/protocol/zigbee/app/projects/z3/zigbee_unified_test_harness/zigbee_unified_test_harness.slcp @@ -116,6 +116,11 @@ configuration: value: 6096 - name: SL_ZIGBEE_BROADCAST_TABLE_SIZE value: 21 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 + source: - path: main.c - path: app.c diff --git a/protocol/zigbee/app/projects/z3/zigbee_z3_gateway_cpc/app.c b/protocol/zigbee/app/projects/z3/zigbee_z3_gateway_cpc/app.c index e9d8b36ff1..263673d662 100644 --- a/protocol/zigbee/app/projects/z3/zigbee_z3_gateway_cpc/app.c +++ b/protocol/zigbee/app/projects/z3/zigbee_z3_gateway_cpc/app.c @@ -137,6 +137,12 @@ void sl_zigbee_af_main_init_cb(void) zcl_ias_ace_cluster_server_command_handler); } +void sl_zigbee_af_mux_invalid_rx_cb(uint8_t new_rx_channel, uint8_t old_rx_channel) +{ + sl_zigbee_af_core_println("WARNING: MUX detected invalid RX attempts on both %d and %d channels", + new_rx_channel, old_rx_channel); +} + #ifdef SL_CATALOG_CLI_PRESENT //------------------------------------- // Custom CLI commands and related code diff --git a/protocol/zigbee/app/projects/z3/zigbee_z3_light/zigbee_z3_light.slcp b/protocol/zigbee/app/projects/z3/zigbee_z3_light/zigbee_z3_light.slcp index 5e425d440e..22fffdce9b 100644 --- a/protocol/zigbee/app/projects/z3/zigbee_z3_light/zigbee_z3_light.slcp +++ b/protocol/zigbee/app/projects/z3/zigbee_z3_light/zigbee_z3_light.slcp @@ -111,6 +111,10 @@ configuration: value: 53 - name: configMAX_TASK_NAME_LEN value: 30 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 source: - path: main.c diff --git a/protocol/zigbee/app/projects/z3/zigbee_z3_switch/zigbee_z3_switch.slcp b/protocol/zigbee/app/projects/z3/zigbee_z3_switch/zigbee_z3_switch.slcp index 541ac910c7..ffbbd6258a 100644 --- a/protocol/zigbee/app/projects/z3/zigbee_z3_switch/zigbee_z3_switch.slcp +++ b/protocol/zigbee/app/projects/z3/zigbee_z3_switch/zigbee_z3_switch.slcp @@ -109,6 +109,11 @@ configuration: value: 512 condition: - micriumos_kernel + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 + source: - path: main.c - path: app.c diff --git a/protocol/zigbee/app/projects/zigbee_minimal_rtos/zigbee_minimal_rtos.slcp b/protocol/zigbee/app/projects/zigbee_minimal_rtos/zigbee_minimal_rtos.slcp index acb31c748e..e4440ca6b9 100644 --- a/protocol/zigbee/app/projects/zigbee_minimal_rtos/zigbee_minimal_rtos.slcp +++ b/protocol/zigbee/app/projects/zigbee_minimal_rtos/zigbee_minimal_rtos.slcp @@ -68,6 +68,10 @@ configuration: value: 0 - name: SL_PSA_ITS_SUPPORT_V3_DRIVER value: 1 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 source: - path: main.c diff --git a/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/app.c b/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/app.c index 6d522178fc..416d2c2d7b 100644 --- a/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/app.c +++ b/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/app.c @@ -1443,7 +1443,7 @@ void sli_srft_cli_customSilabsLocalReport(sl_cli_command_arg_t *arguments) // Callbacks ////////////////////////////////////////////// -void app_init(void) +void sl_zigbee_af_main_init_cb(void) { // Initialize events sl_zigbee_af_event_init(&change_channel_with_ping_event, change_channel_with_ping_event_handler); diff --git a/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/main.c b/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/main.c index 6b813fd414..28cbe84864 100644 --- a/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/main.c +++ b/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/main.c @@ -32,7 +32,9 @@ #define main nodeMain #endif -void app_init(void); +void app_init(void) +{ +} void app_process_action(void) { diff --git a/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/zigbee_standardized_rf_testing.slcp b/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/zigbee_standardized_rf_testing.slcp index 3d6a65ade2..bc3e027137 100644 --- a/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/zigbee_standardized_rf_testing.slcp +++ b/protocol/zigbee/app/projects/zigbee_standardized_rf_testing/zigbee_standardized_rf_testing.slcp @@ -56,6 +56,10 @@ configuration: value: 0 - name: SL_PSA_ITS_SUPPORT_V3_DRIVER value: 1 + - name: SL_CLI_EXAMPLE_TASK_STACK_SIZE + value: 600 + condition: + - cmsis_rtos2 source: - path: main.c - path: app.c diff --git a/protocol/zigbee/app/util/ezsp/command-functions.h b/protocol/zigbee/app/util/ezsp/command-functions.h index 3d9fbd4261..748eb9c96d 100644 --- a/protocol/zigbee/app/util/ezsp/command-functions.h +++ b/protocol/zigbee/app/util/ezsp/command-functions.h @@ -4429,6 +4429,15 @@ static void callbackDispatch(void) break; } + case SL_ZIGBEE_EZSP_MUX_INVALID_RX_HANDLER: { + uint8_t new_rx_channel; + uint8_t old_rx_channel; + new_rx_channel = fetchInt8u(); + old_rx_channel = fetchInt8u(); + sl_zigbee_ezsp_mux_invalid_rx_handler(new_rx_channel, old_rx_channel); + break; + } + case SL_ZIGBEE_EZSP_CUSTOM_FRAME_HANDLER: { uint8_t payloadLength; uint8_t *payload; diff --git a/protocol/zigbee/app/util/ezsp/command-prototypes.h b/protocol/zigbee/app/util/ezsp/command-prototypes.h index 81bf272a33..123bbc9aaf 100644 --- a/protocol/zigbee/app/util/ezsp/command-prototypes.h +++ b/protocol/zigbee/app/util/ezsp/command-prototypes.h @@ -407,6 +407,12 @@ void sl_zigbee_ezsp_counter_rollover_handler( // Type of Counter sl_zigbee_counter_type_t type); +// Callback +// This call is fired when mux detects an invalid rx +void sl_zigbee_ezsp_mux_invalid_rx_handler( + uint8_t new_rx_channel, + uint8_t old_rx_channel); + // Used to test that UART flow control is working correctly. void sl_zigbee_ezsp_delay_test( // Data will not be read from the host for this many milliseconds. diff --git a/protocol/zigbee/app/util/ezsp/ezsp-callbacks.c b/protocol/zigbee/app/util/ezsp/ezsp-callbacks.c index 82f223aa09..137e49369c 100644 --- a/protocol/zigbee/app/util/ezsp/ezsp-callbacks.c +++ b/protocol/zigbee/app/util/ezsp/ezsp-callbacks.c @@ -245,6 +245,10 @@ WEAK(void sl_zigbee_ezsp_zll_scan_complete_handler(sl_status_t status)) { } +WEAK(void sl_zigbee_ezsp_mux_invalid_rx_handler(uint8_t new_rx_channel, uint8_t old_rx_channel)) +{ +} + WEAK(void sl_zigbee_ezsp_zll_address_assignment_handler( // Address assignment information. sl_zigbee_zll_address_assignment_t *addressInfo, diff --git a/protocol/zigbee/app/util/ezsp/ezsp-enum-decode.c b/protocol/zigbee/app/util/ezsp/ezsp-enum-decode.c index ec7cd1b6b3..dff6cefe3b 100644 --- a/protocol/zigbee/app/util/ezsp/ezsp-enum-decode.c +++ b/protocol/zigbee/app/util/ezsp/ezsp-enum-decode.c @@ -360,6 +360,7 @@ const char *decodeFrameId(uint16_t value) case SL_ZIGBEE_EZSP_READ_AND_CLEAR_COUNTERS: return "SL_ZIGBEE_EZSP_READ_AND_CLEAR_COUNTERS"; case SL_ZIGBEE_EZSP_READ_COUNTERS: return "SL_ZIGBEE_EZSP_READ_COUNTERS"; case SL_ZIGBEE_EZSP_COUNTER_ROLLOVER_HANDLER: return "SL_ZIGBEE_EZSP_COUNTER_ROLLOVER_HANDLER"; + case SL_ZIGBEE_EZSP_MUX_INVALID_RX_HANDLER: return "SL_ZIGBEE_EZSP_MUX_INVALID_RX_HANDLER"; case SL_ZIGBEE_EZSP_DELAY_TEST: return "SL_ZIGBEE_EZSP_DELAY_TEST"; case SL_ZIGBEE_EZSP_GET_LIBRARY_STATUS: return "SL_ZIGBEE_EZSP_GET_LIBRARY_STATUS"; case SL_ZIGBEE_EZSP_GET_XNCP_INFO: return "SL_ZIGBEE_EZSP_GET_XNCP_INFO"; diff --git a/protocol/zigbee/app/util/ezsp/ezsp-enum.h b/protocol/zigbee/app/util/ezsp/ezsp-enum.h index 02033b544c..d7a7a1da99 100644 --- a/protocol/zigbee/app/util/ezsp/ezsp-enum.h +++ b/protocol/zigbee/app/util/ezsp/ezsp-enum.h @@ -783,6 +783,7 @@ enum { SL_ZIGBEE_EZSP_READ_AND_CLEAR_COUNTERS = 0x0065, SL_ZIGBEE_EZSP_READ_COUNTERS = 0x00F1, SL_ZIGBEE_EZSP_COUNTER_ROLLOVER_HANDLER = 0x00F2, + SL_ZIGBEE_EZSP_MUX_INVALID_RX_HANDLER = 0x005D, SL_ZIGBEE_EZSP_DELAY_TEST = 0x009D, SL_ZIGBEE_EZSP_GET_LIBRARY_STATUS = 0x0001, SL_ZIGBEE_EZSP_GET_XNCP_INFO = 0x0013, diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release/libncp-cbke-library.a index 31d4ddeec6..4f56be574e 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a3bf61610c4a7b80223a89f9650594eba01818f9c596b6cab730276b560fdada -size 58690 +oid sha256:c45e85e83ecfdf7dd2014129772a5301eb65b93aa3dfd69215a4f2a516a7161c +size 58754 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index 31d4ddeec6..4f56be574e 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a3bf61610c4a7b80223a89f9650594eba01818f9c596b6cab730276b560fdada -size 58690 +oid sha256:c45e85e83ecfdf7dd2014129772a5301eb65b93aa3dfd69215a4f2a516a7161c +size 58754 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release/libncp-gp-library.a index 5d561d48b8..02a2825ac0 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:03f6f825b80795376f744eaef72e145747e970b721d6dd04568a4c186382087f -size 31896 +oid sha256:49aedeb0d7a220d3bb74332a921a1770fba307e583e71268e33983eee05c948f +size 31968 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index 5d561d48b8..02a2825ac0 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:03f6f825b80795376f744eaef72e145747e970b721d6dd04568a4c186382087f -size 31896 +oid sha256:49aedeb0d7a220d3bb74332a921a1770fba307e583e71268e33983eee05c948f +size 31968 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release/libncp-mfglib-library.a index 223df9e2e0..4d2a8b4684 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d6273e49d606c7b69592844a14f0b14e8d3518f988f777aca2daa4f61531473b -size 35456 +oid sha256:b4cefcbacab3da7aa632a48013882d314506b722bd5c787a067c9c1e49ffb739 +size 35520 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index 223df9e2e0..4d2a8b4684 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d6273e49d606c7b69592844a14f0b14e8d3518f988f777aca2daa4f61531473b -size 35456 +oid sha256:b4cefcbacab3da7aa632a48013882d314506b722bd5c787a067c9c1e49ffb739 +size 35520 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release/libncp-pro-library.a index 6ac71f071c..dfc2b2f0b4 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3d717a981a44c92b018e57e9480477e89555050e8f0c763a0307962864440e92 -size 320170 +oid sha256:dfbe50c14184829e298d1edf14cc13a6f7dc1fbf1b0cc51534df6988f9649c63 +size 320426 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index 1a2868fddd..28cf36b856 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:19773da3ee7535ae272a8cbfbb1dd301a7a6d4880b7bafb56b1d2e5eb1ccef86 -size 315586 +oid sha256:16157594430590e0e4987d65cb9652a6be5b8fb53884bd2d74c419e22205a367 +size 315858 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release/libncp-source-route-library.a index 061edf30e8..e92ef0c1a2 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1ba5829cdbfb44b7cb6cfb70cfee0e2b1e5efa2e63acd8080b7ad7af2a41c8b9 -size 36870 +oid sha256:0030c5156a1490dc9fb34d4beca60c2fc05d0c8b1c79a6afde4db9ea4d436549 +size 36934 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index 061edf30e8..e92ef0c1a2 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1ba5829cdbfb44b7cb6cfb70cfee0e2b1e5efa2e63acd8080b7ad7af2a41c8b9 -size 36870 +oid sha256:0030c5156a1490dc9fb34d4beca60c2fc05d0c8b1c79a6afde4db9ea4d436549 +size 36934 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release/libncp-zll-library.a index 71174bcb62..9a89bbd137 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:af6c79649e1ce8edc05fe107d4488920b39a14ee66d0293db4d2c00ab889eaa3 -size 43808 +oid sha256:1533f7afcfde5c21d81abdf1f24c7900667a2f52f76b13cb0c4f5ea53b773bec +size 43880 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 71174bcb62..9a89bbd137 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:af6c79649e1ce8edc05fe107d4488920b39a14ee66d0293db4d2c00ab889eaa3 -size 43808 +oid sha256:1533f7afcfde5c21d81abdf1f24c7900667a2f52f76b13cb0c4f5ea53b773bec +size 43880 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release/libzigbee-gp.a index c459ed15e8..c1c55b53fb 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6d5db8c5119e861531282ffa0cc0ba9771267ff3b79e5fa2a6453412035edc8 +oid sha256:69f8171e73acff8616f9469deb28edbf54a2804966ee3b83611791b494cf53ba size 158890 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release_singlenetwork/libzigbee-gp.a index 53782ff2e0..640336930d 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eeabeb6ab69aca0d4a4176a6bf8a45fe180142fdd43156f2d3748dc99cfdf4b3 +oid sha256:01a6f9207a1418a400a5a46ff2b3dc69362e8b95c4bf68f8f1b2749f78576eef size 157538 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-multi-network/release/libzigbee-multi-network.a index 612a2421c0..c3e9188ca8 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:81dfd3832e255669c2adc66c7d55136f6fd201ad269db228b477aae744bf1663 +oid sha256:4f0ebbf5bee1a79a524007a0aa182bf9c769a614f144dfd54b0ff35b2411c7ce size 57788 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index b86be34867..2cb8da9440 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b36cd1d67821d4dce05216635b64e4b49143a677d7f18b33a6bde5bc92c5b63f -size 278076 +oid sha256:deb389bcc585c71bd6b9f799ba242f4786fc09f586202e762652e68e98d35942 +size 278838 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index 93cfb8f99b..ff5cb09260 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:93018f018589d7c176856c177809d1dd6a497fe340e45ba647e0c94fd2caec7c -size 271492 +oid sha256:18a7242528d81f9570dd97db28f3fe0aae72273ab27d0108284a11ca2270e7c6 +size 272254 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 58eea5983e..a3fd335cdf 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:89d8127d68783de156733f3120156fe5fb711e3a1be9c6543d740de5344fc117 -size 2415418 +oid sha256:8f612dd7b091c0b8a93f28a29dbb5f1383085f16976961515b85daa027c33d77 +size 2415410 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index 99e1d878bd..290158a981 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6ac04d1d396bfa077dcd91b2e95ffdae8b9e6ffc8314fa5ea0c48e6a65b8744e -size 2222610 +oid sha256:429b620f18cf1d727b9c139fa859fbafbcc20a786ddd8dda4f84ffa7b73ceda0 +size 2222602 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index c3bcd94162..c7426112c0 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9a5f4a25fa7537e20b9b4fc3f90ea192edeb3d32f71ba740f4ad38fb150818be -size 2661382 +oid sha256:ac157880cd360355259e5503674fcba5926f1061c270c724cf0d3cfe3223683b +size 2661502 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index f7235f8cb2..f8e3a4eef9 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:157b34750fd612aca27806a60eaa2a409ca2755152b84d4f679be2e892f7ef17 -size 2438800 +oid sha256:77622489a22e2f1ea1837d3e9498cc1205188228764c7f53f7f1f3585c3adb05 +size 2438912 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index 78b3ad15f8..cdf77e96b9 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f68af52a51f88a9531c96605264f4531940572946a8ccedbd1a2eba8d6f99651 -size 2749412 +oid sha256:95007fc5d38016bea71f01b0a9738c4fafcb1ec1cba836c7ae199bb5b5e262cb +size 2749532 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index a54fbba1fe..1cf3ea0f97 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2bb9bfc55e2236b8b0ef85a286bf3a8d5ac5101786e332fde53aab355bcaf2d3 -size 2506318 +oid sha256:144e03573e48327b5e80ece5c364e7c7c3dffbc04f727fd64551d7116b95d90a +size 2506430 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release/libzigbee-pro-stack.a index f9caedde46..f247cf9d2a 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b1d99ed719691b0ccada8f9dfeb9b494d7c0cacad473f28a31cf3bfffc7f3586 -size 2744416 +oid sha256:1953b81e6170677339879886422ea1cddeaa4d91c514c6a506eb7c51b1c76403 +size 2744536 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index 6d3c7911e6..8280b507b3 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4cb2cdc87bec4ff9d80618e42cf5f87a451f80cb95511d7141a7d443c2f69f85 -size 2501842 +oid sha256:7eb39bcea12c7c61fb9bb59fb41f864f0b655c3ccf71e94469dd34382b8cdfde +size 2501954 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index fbf60bef36..8b06defc48 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:025edc406ec581faad68070fd7489a220d44cc41d5f9e8eaeb208089b8bc2e1f +oid sha256:ffebd3e3cf62de95e39801c13faed7eb62a81df4ed1a2abe632a10344159543d size 85632 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index 1e8b7e30d8..ffdd14bd2f 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7dd674a92ec338f565af2d4217598a230fcf08b1de9a14fb725df2f920062401 +oid sha256:2d917d1efecde4ac8c65e187603d32ea1275577611c88d553ea855ab0dadd4c1 size 81128 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release/libzigbee-r22-support.a index 724389f348..98a64c3bdb 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94161aabd119602ada91c5cf04c14ef847166d070d7a954239827f5bb3f81974 +oid sha256:9238abcc7535e60f5a26f15b95519c9d487b85a3753d2cc586e04b8d6d798680 size 85468 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index e139582899..e83b3b0dfe 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:81e1b5716e450c9313d7071edc96fc477baf98ea497aa1e6ed79f93a292f76c7 +oid sha256:43ddaa335967c2ff30793a79ace20834db226492d2d32e9bf4f113260332df7a size 80964 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release/libzigbee-source-route.a index 4b0b2b72db..6ba3b737a4 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:afe42a961706c3b69c2d9f01ed049a1a37a778eafc59dad57e07a492c107bc74 +oid sha256:ad1da68bb2147a29b61dc1edc9d2a3559ba105967860ae75b6980ff6d38ed599 size 53104 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index 43c641c0af..e1aa1c552c 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d362e309ed232bc3fcae7bb71fd6d80d18550b37aef95824b2815d59fb2f72da +oid sha256:32e44160f395c5d943757107e5bd63755705099d19f52bb1a7d99ec31365aa73 size 43392 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release/libzigbee-xncp.a index 1ca8590ded..a6b287b7de 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c7620eda6b1cb893bae2ce78623c3a2dfed66c7afb2ae96c0db7c99d2ed7d564 -size 34298 +oid sha256:94b3ef523085997e3b46b6d321578228430aa78cbeb1f545ade2608600f39c91 +size 34362 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 1ca8590ded..a6b287b7de 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c7620eda6b1cb893bae2ce78623c3a2dfed66c7afb2ae96c0db7c99d2ed7d564 -size 34298 +oid sha256:94b3ef523085997e3b46b6d321578228430aa78cbeb1f545ade2608600f39c91 +size 34362 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release/libzigbee-zll.a index 54b3eb7f35..52ad5c0a29 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6f393da0aae1d7a4f164b5031c8eee7100a0dcd7fad5c386481a4ab6c892bb9d -size 189298 +oid sha256:3e40f4cce7d13aee01859bf3d67c0225999dbc3e3c79ffba1cd1bbb2d72c7f1a +size 189450 diff --git a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release_singlenetwork/libzigbee-zll.a index 0927b2d6a7..639b3229b0 100644 --- a/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/aarch64_cortex-a72_gcc-12.3.0_musl/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:09a139da92728741c0d789ce5e53d60794a0d210ac38ab1c164948c14ba7024e -size 184114 +oid sha256:4625a5d70d8f1773671704dc8a7742b28708e80d0bfe8ce1789b88a31ff475da +size 184202 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a index 569399a594..fecee4de79 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:76c48e472e6b33efc4aa1186b57138c3ad85a9d788665e444b670f3551f88c9a -size 77346 +oid sha256:9824d238218e3f9dacc8fb854d8a7c3bfbebb5201a8655bef2eeed70869fff4f +size 77410 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index d09464f86c..7cc92001ac 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:34289e19a4c487f70ebdee4c1fe2f5945b5d378320db5a788267f79f1544ca11 -size 75538 +oid sha256:9371dd4028b79481fbd86749432256e73032617681793ee2e32cff3aaf38f634 +size 75602 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a index f82c610a50..5a612a2fba 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a650f2192bb8f8d1301c4222a3cb8b3be9dc1fa0065454694d0a16827cbdf8e2 -size 50184 +oid sha256:4f4387867232f913e4c678502f20c5794a077b7edfa46cc17350fc6aa50f5b2f +size 50256 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index e6de7016ca..d77d6c1805 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a1560023db8e6b71f992331f5cdd5a6d75e422eec9cc24dca09fdb7ad788645f -size 48392 +oid sha256:70a67977a06b70919e7afb192b4c4acbec06fc777c50ca7047b270192bea972d +size 48464 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a index de77fa4cff..c0872d600c 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ddcf79a27f59c3becb3b6a65ab08937dac3916b3a16812540ec2cbefcb9acc7b -size 53968 +oid sha256:3684b6ab3648184b8696946aeef4750d7ab00face17fafcad1d25c418616e004 +size 54040 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index a696c6a3bc..9e2d8a0058 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0099d669750f20c52f4268b4fd581d301cedfc0d15b35a5048bc1d44c9160813 -size 52160 +oid sha256:4124f3a432208b72409f9f6032869a69e2bc5249974d4c513aa60e7ec4e6b13d +size 52232 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a index a3e9470661..81084ae75c 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:26b5ffa20889889c69b9ba4e4c2b504797cdca0d6045c1eb416b497e8c9c4c64 -size 408490 +oid sha256:43f806b73aaa959a781cd015a1d63c20eb8c37fcf298c941739e88cf82736be4 +size 408770 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index d1f5314fc3..9976d75cd6 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c63409842c67dd11f460d82d82de07c04eef1b0852a02de358faf954b1090b67 -size 399154 +oid sha256:60f4b6436031211720fe1669b58ed0960f365b32329a0bda6fb3a9da7bc03031 +size 399426 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a index bb71b8f868..7fbb9a2d56 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:77de90662bd0447764662265890ffcb2b4f5b68f4f6e0dee38256bca55b26721 -size 55774 +oid sha256:b1c3576aa954eefdc2c250bff319a49a37dddc099d5252376cbc7fd60e015767 +size 55846 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index 7005ae5967..e75e4048f7 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6c1a2fbd0e14fcb6d526a0eceb7166e3e619aa52e996a9ef9429b6292965171f -size 53966 +oid sha256:0e8dd3f08cceeeeafc3fc9df597417d27522dfbf048f3aa4d2e74d8b4a2e7de0 +size 54038 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a index 49eddc57c6..cf45b9d6d2 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:606d793518bc066af68aa7527eb4b6e5f87500e8feca90c5ad6ed28851b5c359 -size 62744 +oid sha256:1da50cb3b97d38093aaa0a544338732a3aeb14a2d6c8adf16912b597484f9e6f +size 62808 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index cb792735d2..fb64101246 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7b896286ff9c317bfdd845f3eaf46c24c7cfa1f6d5947a4799c482c05b43f107 -size 60960 +oid sha256:02e35e55d15dff059bc059f70e50eb4e32ae2112e74bc343e790c2dabf9f85e3 +size 61032 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a index d87b92d169..1f948ef3ae 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eaa6c302ce667112e283c940e3545abc22cce8a21611cb9006bc32f0209a9ad7 +oid sha256:87b46c8ca75057b213f6a29fbbfd6a436bd3b56d9b7e4fdd1b593f3b8d29b21c size 42166 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a index ff4a98c228..7ddb14ffb3 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3b2294a3470696e0200215a8879e16b72aac60e044ab39e51318b4880e50acf8 +oid sha256:3b75562cf356a4ab87218d39ba014c4e0d2226bad00b5e48cfc6694c2f6ef6d6 size 40478 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a index 66d77568f3..415dc4d169 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d544ff0fc57f9e3d26f20ac9fe27f04863943608b9edffce26569a23596ab412 +oid sha256:98f6c8533169efa8286cc10b9bc1c307685f56e0cc587509f6a80719e65eb9bf size 151248 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a index feaa68c278..095514c585 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4402bce40a97f564ef9b07d1b0034bba87b658a7bbf77200609af89f59b81a9f +oid sha256:5f5c2509bc7c290aad6bc8a423dcf7826ffd16cd95ca248da8afc4fa03791af2 size 147496 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a index 8febad72da..209548ae5b 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1c6a8d5e923107da74e2d2aad8c10341acb93797cea20dcc6e3616316de9ec1f +oid sha256:5c42c273082da70cbba17a19e21190e0f815d7ddec11cb30b5996c5f288b8bf5 size 184778 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a index a283962975..f07bec5c39 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1dc4682fe16e779ed46e8d3a9b4d4e08b3a1a06f347b0aad45d120632f355775 +oid sha256:abc6c2095204e297098f9a5f3f50f835a64f1eca96657bd6859c65ae68c03475 size 182618 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a index 6a63faa578..b3f2d93941 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dc2d2e76aaa9f0c182b097ad76e7a2e167d1069ff89d3ec3f98f05452a7ffbe5 +oid sha256:a8ea2d718343975f98fdef59813b49365e6986cd09dd93a0d16e34a4b9aaf477 size 38356 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a index bc3ec56717..756be7eaa8 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:61f8e6fb7dfff26a417f1ce91ee4d20adaf18e54c786fc8211b53e16fa98a696 +oid sha256:52f0178138d7496916ac8c17b0f1ef191aa74e6db0dbc5b533c67b71fdfba4c3 size 36396 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a index 5b12de247d..120e6ba4fd 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fc4bf34870226c1da8991f9713b390e86e0ec8d7894755fd733306f692f5737d +oid sha256:f8dbca18245d9858b5c5b769135c8d5b866d0f811319338c22ad75e48dc984c7 size 62660 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index 3cd64b5483..5c0b7608eb 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:404ff4b74dd97707caee9215c6ef1a40d3cbf2890f6f1584061f6156e566809d -size 362268 +oid sha256:3d72bd1e4abbaf9e58356beeca15bbb5be9c64e0d28bae7c5b2caa30d5e6d305 +size 363118 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index f964885024..a1f54e4214 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:77268d42bb1bc318187e606be4e0628811ec8d110f20d11c00cfbc81f23c54f7 -size 351380 +oid sha256:c0c7f501f59db99836df6ac1842f47235929d2dc30d5026ff88e1314bed64be0 +size 352246 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index b1a237c6eb..70801a4607 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:023af9cd2ab4c32370448ee41e8f7964eed287fdf3758ed3166bae35e1818f8f -size 3094202 +oid sha256:4fbae6ca8ba7f04e047f68b3589984419516690e900701f9e603a6267779bf97 +size 3094194 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index d6660bb276..ada25cccd6 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aae9169d34e76d14a41cce6edc5910a0714fb03e246bb17c0e5d62806aab3112 -size 2934026 +oid sha256:4d772443716a7e4f124f04db5766ce3201afbe7bfe4d361961f99afe6054ac42 +size 2934018 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index e89159ddc4..432bf5dc30 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6d3b1ae26ca794927c9170013744c9ad5746451e0fc55a18ac99d0b42a141753 -size 3355750 +oid sha256:a65477acdfec2fc48a4f2843d795ad72cd94f2815e3a5aef78c1ee10b3acca80 +size 3355862 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index 59dc00a888..ad95f582df 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:17744b55e457e21edc072a8f7e2b330fb2c5becbdba1f751af2276c4eed19938 -size 3177464 +oid sha256:94cb032273701d329d31fce4312724fbf1a03f7b4fd7fbcb0b2b804e7c43005a +size 3177576 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index bfb5ccc724..53b6486ba8 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3eaac3ad8d3125fa0a458921fb048bdebca07e7ad4c62b3149bdd2599c894435 -size 3430340 +oid sha256:8cec0b2e2cc91a7e13e538cbfe6ad45e443c7ed680ffc906108249328b73bb4d +size 3430452 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 70364d6224..275a375ebd 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:62fcd0259466bef473ccc4dc725d854c82bf18eaf264f5da589c555b22d5e2c8 -size 3234038 +oid sha256:6639b3dc3b8021e0f4dd2ad16121042934ad8afe349e490c3a360df68a7a13fa +size 3234150 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a index 0fd4da7eb5..2b92bc06c8 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2243fe639c4f4a1d5f14f0d25a081d36237af878ba13a0249930d6646858c165 -size 3414808 +oid sha256:c96bde596c273c27836a4eefc695201b5b4b18b29c6763af6420530c75e2043d +size 3414920 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index abffba2124..d2cc984f9e 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:91ec4ef26658da8587adba802bebb1cd2d6d012069ce4c95fbac586926d1b1ce -size 3218426 +oid sha256:57db8bbfaaf3b2107b2841fd09c42a198755f15bddb4c928ece3f434314a1627 +size 3218538 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index 6d5505bf75..48e56b813c 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:52bfe923a4c03ee27da36cbb1771fa077714ee50ebb134cd58e61e5a1ee5a4c6 +oid sha256:665fb92097375326a4512a6a3403cff06faf7f89fa8e82bce4bae3971a302ce7 size 134280 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index f4b52b4ae9..9fc775145b 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:76c7ab1226b37ca66d4aa65501f9b3b2b860826c7b490d9b6e17644c971b58dc +oid sha256:199229659a325e81071dc13aa4479cd5617d0c1ce242ed0f05107b33c49d32a4 size 126608 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a index ebef7e738c..3652449a87 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:221964918d948fbebe027c410213d0594c820866b975bb4d01c14e0b11c24015 +oid sha256:e87527b7828169c160ebe340c6da9bdccdb3d5045e861f7edb4822303dff946c size 133892 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index 575cca8d38..e3e3732798 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d87d8a2e24f5c4c5a2849c03874e22f8ea3088e379f7914eabfe4e9d3df05068 +oid sha256:54bcedca72373e0d4bba4c628da09bf1c50bda7bae105648296493560a3eff8a size 126228 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a index 68c6e47c59..7019584d11 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3bcae712f6ca1faf58591e73c97af4bb214b76fbb3ca82b2123b77d127d5d582 +oid sha256:731eeb549152e408f0cb7fcb55be6c253711aa8e7cd4f913946b5bcb1403c7b3 size 429714 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a index 63ffddd2b6..667c9b4aa0 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:66610eedf68587ec1ed1e568a43c1827227bcdd1f568c04fb74ab1f40656943e +oid sha256:0e7e321299118f96684d0871eb954876d9f8d9ef592b53f75632d72a2ae8dfb1 size 414754 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a index 9e851caa8f..d8345c73d2 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0f1fc5778adee13d187e0e46fe4008dee00c44f8fddd61b8930068f8d315f3e0 +oid sha256:0866e1dddb51a41480cc6c8e53793ccbc9d33a140ec044f78735629f43210282 size 79192 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index 7bdf6dd846..6a60123b4a 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:057d25d38f9a82bc8bf47c7176377d9b74e8eadd34916144c3538c8b45d6343f +oid sha256:db438df9bcb1f681977e6eba1e95b9417579503db218805ec86e4c817473a775 size 67208 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a index 739d5152ea..912a26a45c 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ff2c47e684e351c279a7b2bcf85e33a0c575ba560331d75daa010564ce08ec9b -size 35962 +oid sha256:0d4a37b4eed1203a31b49e2128a4da8c1a00cda5b5dabd984f3c7278df463c1f +size 36034 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 739d5152ea..912a26a45c 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ff2c47e684e351c279a7b2bcf85e33a0c575ba560331d75daa010564ce08ec9b -size 35962 +oid sha256:0d4a37b4eed1203a31b49e2128a4da8c1a00cda5b5dabd984f3c7278df463c1f +size 36034 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a index 3c84a7ee13..51958a7f11 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fc9a0208151c1d33601885d345b9dabcb2f8fb98aa04f8199c70fdd7c754c617 -size 238162 +oid sha256:366a40d1d25673af7013d7df58cf1b33ddfcf6dfd2c62d586a72aec83bce446c +size 238322 diff --git a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a index 5f476df8b0..ffb9098d05 100644 --- a/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/aarch64_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1f8109c4765016b9f295b35a07a9283eb78379a77beb1f4d54c00df7eb11909d -size 232906 +oid sha256:56654d9a58ff13c3a58a5d8fb6891a68c1c31dd8ea065fa50fd29533599fc018 +size 232994 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release/libncp-cbke-library.a index d2c2480594..fbe927f945 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f8fe176240c0fab1c744713dea3feaaa54db310924ea0c82ffb14e495d12cc82 -size 43922 +oid sha256:b89b4cb7af7abfde647a8ecae92206ad95859fb6d92fec283bb6f37b6a65c711 +size 43974 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index d2c2480594..fbe927f945 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f8fe176240c0fab1c744713dea3feaaa54db310924ea0c82ffb14e495d12cc82 -size 43922 +oid sha256:b89b4cb7af7abfde647a8ecae92206ad95859fb6d92fec283bb6f37b6a65c711 +size 43974 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release/libncp-gp-library.a index bb958fa111..ee92ccdccc 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bfa28f738c27d2ddd4fc5ee0d06349f9ad40eecf19d2d83021e8b49639adbc64 -size 24040 +oid sha256:764d923b89367a9ebb400d510d2bd213904e0fd7f558154412d476f88862a256 +size 24092 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index bb958fa111..ee92ccdccc 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bfa28f738c27d2ddd4fc5ee0d06349f9ad40eecf19d2d83021e8b49639adbc64 -size 24040 +oid sha256:764d923b89367a9ebb400d510d2bd213904e0fd7f558154412d476f88862a256 +size 24092 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release/libncp-mfglib-library.a index d2337dcb03..fe8c99e033 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7f60e98983240c9bdafced7950f9dd430d50171bcf7f9099ccd7ef5353e6269c -size 26680 +oid sha256:d9a6bc9f8ead43b829308144b80515cde3ffa909326585a1554342eb2a77a07f +size 26732 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index d2337dcb03..fe8c99e033 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7f60e98983240c9bdafced7950f9dd430d50171bcf7f9099ccd7ef5353e6269c -size 26680 +oid sha256:d9a6bc9f8ead43b829308144b80515cde3ffa909326585a1554342eb2a77a07f +size 26732 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release/libncp-pro-library.a index ac4588f06f..436cc73741 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1161f2f5110e61da64cddd4c68738e8f374a5901ee9f458364cdc73aa9e3401e -size 239094 +oid sha256:a2fe204ee6a141d772a861593f4ae636a855f3f99f2523358be3b3cacd25228a +size 239302 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index e155b2f092..4bd390e388 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6cc37c87171e67778c533b08c663e67baeef720393ac4f94652fc2238586c1ff -size 235910 +oid sha256:280fb77f0cee5eb473b3fa75049bf1d1acbe1cb25415130267d10a7231e83eb9 +size 236118 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release/libncp-source-route-library.a index b96340b733..ed0a3874d5 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94a7344d7373c21b0771352378c6c435446e51a3c1b80e3390731535000e0708 -size 28070 +oid sha256:2c951939ae3c2f989df60a6124473ddeb8884786edd3ed4819bc5313def0b793 +size 28122 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index b96340b733..ed0a3874d5 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94a7344d7373c21b0771352378c6c435446e51a3c1b80e3390731535000e0708 -size 28070 +oid sha256:2c951939ae3c2f989df60a6124473ddeb8884786edd3ed4819bc5313def0b793 +size 28122 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release/libncp-zll-library.a index 4672f4c774..1efdedf8b1 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8833781fe4b04281888b86dd7d450034e0470ae99298053a0ba0482d4efa3245 -size 32672 +oid sha256:af1d6674c5c1faedd0b45f04cfc3030cbe9c6a8e92478a28a511a746179bc8c7 +size 32724 diff --git a/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 4672f4c774..1efdedf8b1 100644 --- a/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/arm32v7/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8833781fe4b04281888b86dd7d450034e0470ae99298053a0ba0482d4efa3245 -size 32672 +oid sha256:af1d6674c5c1faedd0b45f04cfc3030cbe9c6a8e92478a28a511a746179bc8c7 +size 32724 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release/libzigbee-gp.a index 92eb67d004..3f75d5a473 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b60cf3c1c462bbdaa28be9c47b7850ac131b24aeb2cee737150cd75f67ee54c4 +oid sha256:0503a4245a8737fbb15c398d9cfb2f6030014ac4da00a1ad5550667ea2b91773 size 107698 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release_singlenetwork/libzigbee-gp.a index 74058dd821..26b3987f8a 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f1281a8d61ec9965745ed078f0263c658f0350a4c346cef90e824d8d85cf9ca9 +oid sha256:365f7705cd0a208e90036939639da408400f456baf484db9e11288f7fc13861a size 106738 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-multi-network/release/libzigbee-multi-network.a index b5b7d23108..d74c5b0dd4 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6b7744d8e2644b0d869d5c1d8d18c5d62a0a38587d9e870a7796dc0aac782bf9 +oid sha256:07cb587430c7c2a5c8e0e3ec01cffb9973354215875b086a6837e11932f38615 size 39672 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index 44951aef98..254fb4492a 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ee772a698a3d50de2e8c0d706a3aa9eabbe5af9aa5800c5a3b218d5d480c7cd8 -size 202224 +oid sha256:6f8c066d6d9881890e828219a7678ed81602b70ef0573e1be1635f9719fcf4ee +size 202786 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index f4a2c2ffeb..46b2c546f8 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f57214011f0b528983b90653148ea6c30d0b9bb5c5a926b2c86bc976962c412 -size 196388 +oid sha256:9f9e4c166d129858994fde8c7be7f6c5e615a5681574b872bf877a889bf93c15 +size 196950 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 03599617b8..0a49921007 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eba47ee3380c01f78af435bfa19bba33831f6c93f802c4f240ee15a9bbee41df -size 1685598 +oid sha256:037d138a260c67140e2f8ac007aef857c318444a1d20cbbfda32b895c0edf457 +size 1685594 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index 90c1ad24cc..084ca11de8 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ab102e6fc7d2e4407bbf8d6e167fc49f13bdd24048775b5f02b69f417327a562 -size 1576226 +oid sha256:7bb41b5a16166349d2a7754106b6a4a9aeebfda45656351ebb97218833a1581a +size 1576222 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index 6411462dc6..219cba2b13 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1229ab4b0daef0976c6abbecad718511c02a7f20188fc8d9064b5c45f2b667d8 -size 1851974 +oid sha256:ab8cd52f0d9f2027c773e29c9e1631901d4b69ec327638df3f869adb4f745879 +size 1852030 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index b994e1729b..5699587322 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:043ebe81457b94639f552ef67f25fed9d9a23c1b1250611414d34154965d0c9e -size 1725492 +oid sha256:78419e190cfad8359067b88251c9754d51bc9e2cf1c31a9bc2de82fbd0ae78f6 +size 1725540 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index 1af8ec48a5..b49612d79b 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0f3e3a4c2b3d863cb768dbd1879106843c999d93fab5e1af94172f61d3d9d753 -size 1898772 +oid sha256:39ff04ee428b48879bc5befdcac6fb7866f7164dbfeb84790ddca242a4fcad44 +size 1898828 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 432dd0fb22..a3be059cdb 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:65001a88066bc8d09753b1647020bc1daab231b9664c3da06ae3c638e9df7258 -size 1767186 +oid sha256:81f2efcc0255a16a62a82a1b9d8c8ee5ce208ff2d38b24d24c57b3ae0bef11a6 +size 1767234 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release/libzigbee-pro-stack.a index ee4e61ad35..cced5344a5 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:388d3ecbbc4444a740c0e5ce3ee734305d5d251b072d77a9ea68e6c3eedd778b -size 1895256 +oid sha256:50b45e65e708e6f443f882804280ec7fdf7b3e73776c74bd2db082eb84b1c821 +size 1895312 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index ef9f2d1601..9655259531 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f677c1afb30c4206164e43a9b1aeede0ed0564d6d52fcd0a40ee47e1e2378c26 -size 1764086 +oid sha256:8ae420936a2ebdc9080f021ff5719c409a1d45726229bfaa7615750d212e3cc8 +size 1764134 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index 08f43d6d5b..62725506d5 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ba3bc355713e5d1d3a8a42ae650433e8376696b4c7b9c154fa764d27be4c82ed +oid sha256:ba8b7e2e1c0ad4855318a0f9f1baa43ce3268599a2dc01cd2ddff5770b825982 size 61016 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index b8d67e686c..71383f40fe 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e3aa182d5349c97a7df95d11e6ad0f05697a641fd7a35271ca656aeb9fcbd8d +oid sha256:35f3ba0c4f69263545ee96cf4c2528211c16e1c3483af7092dd65387a4c089b8 size 58108 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release/libzigbee-r22-support.a index ca6d2a10d2..8b08763462 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:82ba2ec8e6692a29ee98af3bfc64a654ab0ccbfa2673f982fd1d4d49a51daa89 +oid sha256:91cb45e4fd52d925241b3045188c43e1029108bdf13e8e9445f95ec1175908b2 size 60892 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index 8d99d15772..ce68f1f393 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:403a2713cae6f0a68039cc626d3d2f09c1ef43a885482f42c2c15bd71c4e8d48 +oid sha256:6b768d5df5fe25f39525b21edbbe49c6390b99fa619c32e1c4b3aa207c28dedd size 57984 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release/libzigbee-source-route.a index d4890cd0e3..44afee12bb 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9faffef0a2d3b4551216f070b690f1a5327ef38a5215638a3b2b77fc36c300a5 +oid sha256:1d3e341977dacaa4b9420ac02518db6483834b7e16f84149691e03c8f386a34a size 33308 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index 3c0b405c52..259133da1a 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e23f0a42c12a12f43c5a56e06d86860e67d1853458d27229f6ce6d84010d13d1 +oid sha256:ab1967b5d93a4e32c309a2ddfad9681d9b9b34951de8ca63f20baea08f5db2fc size 29140 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release/libzigbee-xncp.a index 85de9c296a..51985b4e0b 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0b8386ac1276f377788d651f6c459915eec8c645c7dbbd0870cb259c99d26428 -size 25550 +oid sha256:8f62c915ddc0e81799ac8c4fba013e8a47d0f8b7da9fb07b39afa1a8d5cd0a5a +size 25602 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 85de9c296a..51985b4e0b 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0b8386ac1276f377788d651f6c459915eec8c645c7dbbd0870cb259c99d26428 -size 25550 +oid sha256:8f62c915ddc0e81799ac8c4fba013e8a47d0f8b7da9fb07b39afa1a8d5cd0a5a +size 25602 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release/libzigbee-zll.a index 1942f239ba..bba4b1f371 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bc642ec9cbe88e29d85838c50bfc5895cbe34b5e09e992782b547e6095c6f519 -size 133638 +oid sha256:4714158f56f6fa682bf5759ecbaf161b12ae31f996dd8a4bd3d29f680b5c9a54 +size 133714 diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release_singlenetwork/libzigbee-zll.a index ca0010eac6..b671be40d6 100644 --- a/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/arm32v7/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:858af7818b8c454aaf9d4058bf93c2bee89268f7a510cf3cf1c6207e967d133f -size 130310 +oid sha256:450fde9e026674dfe242fc61ab7d3d5690e882a85e0da75e15eec5c9687c6436 +size 130362 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release/libncp-cbke-library.a index b73c40ddc2..8cfa1a6455 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4233773809e70c35cfaf681ed7911b195162a29327f07c38c2e5feb6609d4574 -size 58754 +oid sha256:cef0a722bd55b457df24fb9acaca3832be24de56681169be7f918f9df3778f21 +size 58826 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index b73c40ddc2..8cfa1a6455 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4233773809e70c35cfaf681ed7911b195162a29327f07c38c2e5feb6609d4574 -size 58754 +oid sha256:cef0a722bd55b457df24fb9acaca3832be24de56681169be7f918f9df3778f21 +size 58826 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release/libncp-gp-library.a index ccadd4f6da..328576fab1 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0c965b67eac39a941bbe3030bf537e8528a3aeb5cc17110c1a5f930a2fe74258 -size 31984 +oid sha256:a111de10c79ce9cdc1679187b97018e2ba8594dbf7f4e86cd6490380ee1c9c82 +size 32048 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index ccadd4f6da..328576fab1 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0c965b67eac39a941bbe3030bf537e8528a3aeb5cc17110c1a5f930a2fe74258 -size 31984 +oid sha256:a111de10c79ce9cdc1679187b97018e2ba8594dbf7f4e86cd6490380ee1c9c82 +size 32048 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release/libncp-mfglib-library.a index 1d8e4c1b72..d66fbc9460 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:590548203efe563999fcca0beb17274bf304719a7108f2e80e6ef63109f07e21 -size 35520 +oid sha256:2914a2a3873ff3d4e40565c1c4596857fbe51ccd4883f4eb0271f178f2d1e58f +size 35592 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index 1d8e4c1b72..d66fbc9460 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:590548203efe563999fcca0beb17274bf304719a7108f2e80e6ef63109f07e21 -size 35520 +oid sha256:2914a2a3873ff3d4e40565c1c4596857fbe51ccd4883f4eb0271f178f2d1e58f +size 35592 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release/libncp-pro-library.a index 11efed8aea..6eb40626ac 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fa1c59eb937c4ff760efaad2ab6feeacf0302f8ed82719a9a00a3f8cbdd18ae1 -size 322986 +oid sha256:df83df074b8ed72780c9f3516c707a1c41f44bb998e5a811915bad49df4d81fe +size 323266 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index 96494db7a6..6255213220 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9a4a6c6151066fdce837f040ef23ccd5816dbae3d6ac3cd7d56bc02ca7920594 -size 318378 +oid sha256:0f7730fdee5ce15627322dab6e15853f00ebdc5dc5c86d2a5101f60aac65a072 +size 318658 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release/libncp-source-route-library.a index 2392e82370..ee55295155 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:03d93ed0dc2f577eb575fd657ad3b8d7b14fe5d6d7369e3712491adbffe96a92 -size 36950 +oid sha256:a4b770cd2bc4aa06317d3c713d908fa9bf896efbf2a634c54f61cb627d861022 +size 37014 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index 2392e82370..ee55295155 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:03d93ed0dc2f577eb575fd657ad3b8d7b14fe5d6d7369e3712491adbffe96a92 -size 36950 +oid sha256:a4b770cd2bc4aa06317d3c713d908fa9bf896efbf2a634c54f61cb627d861022 +size 37014 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release/libncp-zll-library.a index 16fb022ab8..f436c51630 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:31b2bc855a60503f4e6e10711e699919921ac80ab848e722dc0b824ac008b6b8 -size 43880 +oid sha256:6858f18644d029891cea0052fa931c72a738f02a78cb39491d38aeba94c729f9 +size 43944 diff --git a/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 16fb022ab8..f436c51630 100644 --- a/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/arm64v8/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:31b2bc855a60503f4e6e10711e699919921ac80ab848e722dc0b824ac008b6b8 -size 43880 +oid sha256:6858f18644d029891cea0052fa931c72a738f02a78cb39491d38aeba94c729f9 +size 43944 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release/libzigbee-gp.a index 6de2f076bf..24be980e97 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f17761e0196597103c98f91cfde9c387c58397d114dd1a4994dcf7756016e50d +oid sha256:c3434490b6e0d41d670d13c7a76009ee08a9f8425a6b25c265c76ec3a3e1c474 size 159266 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release_singlenetwork/libzigbee-gp.a index ea617cbd12..aea696a7dd 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ac42fe8193c989792d4378104bec3f04ad4faa11aabe4ee3b31ba31c3943d6cc +oid sha256:3999b3c6a5766667b1f2d345f07b1763c3e3503a46fd7ba663687ab08b4d81cc size 157914 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-multi-network/release/libzigbee-multi-network.a index 730d5edb8f..3a997dc804 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ae42151511e978279b492b66b2b73e330bd5767d94a22b8eec7e7b1bf58181f0 +oid sha256:08ef9a68299796f91a2924fefba9651cc0cb9b0e89cc11493a105dfb20894361 size 58004 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index 8bb20b67d9..1f48addabf 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3b1799449db9756e9e271c480d9b43e9054d5a8917ecf84347af8daae581fcb6 -size 280876 +oid sha256:e58d7d8c802c3c864c54da05bdc7baff7dc9c94d1e0e212427db5fcdf75ab706 +size 281630 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index 9f3ccf1592..24d23b27c7 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b2e6b6ab76119860cd88ff98c4eca4feb131fb0ce747f9cb26ac0244faddaaf9 -size 272324 +oid sha256:739f4f4aaff64d383d96003bb6f8a140460891ee92e4e653a8dcdc729831b42f +size 273078 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index acf76b1f74..a92db0b6a0 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0a04a265e724c88201403da6c8bba709ccc472e18431ffc38250af5f22fe1bf9 -size 2430986 +oid sha256:4def3353c8e6494a8b4ddbcff58466ad016dbcb30531829eac197b61e2143a26 +size 2430978 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index b6aed0c09b..800a202465 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ac3de5d41bbb7d469743210fc9c9c707e1c64a7cb8ea4f354a738650f07a0dce -size 2239306 +oid sha256:d7329e016c89cb0e00823234c7dbfd69c25c4d29d9f15418dea7d2837b1ec417 +size 2239298 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index 2132b8abd3..96d0dc1411 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bfb1ebec259c342d08734f1e777192523e8a92515c4cdc4c47ce32ae83e66e03 -size 2681134 +oid sha256:077667a7546fd34a204704f62948fdb59ece20c62f3cd923364769adb1513feb +size 2681246 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index b239b937db..f228310eee 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5fd517c074329f685694dbbf5895784269058d31fee1b93973b62bd09abf6e82 -size 2459800 +oid sha256:9a98066b9f52b09ce96b22b6d988bdf69192a551991f85789c713ba42749f703 +size 2459912 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index b07bec0e82..1333180741 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:98094c325dbfc951c61be055b16a23810a1b85e3b954eb2ad6d85e2c4e8b7545 -size 2768588 +oid sha256:4cdd18af6c599228f9f872811ceb0a64128a7133fc4e0a6e50beb8a3465dee27 +size 2768700 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 9df14edde2..416f241532 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:739b53ffe462368e699b00483f42de1d7f19c9b97612808e57a99ab09e993a87 -size 2527590 +oid sha256:0170ae6a286b7935e2b431856a5f6979b6c62c7133e65acf90c8255832e99b40 +size 2527702 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release/libzigbee-pro-stack.a index 938c8337fe..94a74eeed8 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a7db64e2a6170a2a035bd722ffb4cedc4104f7ad7993ece0b8a40d292ea9bb6d -size 2763456 +oid sha256:f110d96c0f152907571426193622c8223bed14a0a709496754ead3b05b5028a3 +size 2763568 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index d9b9268ad1..7172a31a9a 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:01ee70f074f17a13546e79bacc27113062dd48f1741438fa6977e9fb316f68fa -size 2522954 +oid sha256:ba9870e187c8802dba301ba2b3558183b3cc254a076816e12080a431cbfe283e +size 2523066 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index 46766a793f..9f5ec50714 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7a69be6298ba3e8557e8748163e6791cff92268c1be22435b1a8e16229fb6bc6 +oid sha256:27bfbbb9f1ee334c8450b1432adad9695fbff0de4f02c5c47dba292537e4d8be size 87880 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index d2c40d2899..e186132a62 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c90a04bfbc0a67d04d17d83febe53277f18a252de29d43500d3a73d7f6a176f3 +oid sha256:81400f90a7f4a2865529de62aeddf24003ab1fd5f50a61268ef3e7df193ad531 size 83368 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release/libzigbee-r22-support.a index 1e17b946a3..97ce1be9d7 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8dfdc4008039f9cd8fc769a63b524db25c2624ecb3ec3fa30fc24ae21b6f6a46 +oid sha256:4b9aa326b382ab764e50aa1a783cd52d72e8a4f9f9e931a4ebf6a136f997d7c0 size 87716 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index e3448ba90b..58e6b79c4c 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9956817bfadffadb72952bcca722b8092cc91b5f005f3584ae797756e3495d57 +oid sha256:f9a425ca9b15c234c13c1c74c607742657c67e077505a1d353efdf0232e3732a size 83204 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release/libzigbee-source-route.a index dacdfc0b93..d4aab1b7ef 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4beec91e9ff32d9f8f75093edeaca4608e78034c1802ddd106ab65e4da61286d +oid sha256:b1e07782a83e78e8295cb2d886f11ba52ff70c1b80fa8133621f0e8b3f921a50 size 53040 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index a553e9c5ec..d3435df0c1 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:528bb7cdb4ef2856464e27bd02d3690117bbba40f55a61bb513e921b8aae02c2 +oid sha256:71eb600731500776b1d587caba1ef3a243e78312724b1507de8542c62ba67abb size 43496 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release/libzigbee-xncp.a index d6bf026710..42729c80b3 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e21a83a131c1805caae9d498c65071af38173fae455f41e488dfd20ddf487ca0 -size 34402 +oid sha256:9c624107fcd38f36b083d91537faa2aa5ace115316d9a17a015e279c97e6553e +size 34466 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index d6bf026710..42729c80b3 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e21a83a131c1805caae9d498c65071af38173fae455f41e488dfd20ddf487ca0 -size 34402 +oid sha256:9c624107fcd38f36b083d91537faa2aa5ace115316d9a17a015e279c97e6553e +size 34466 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release/libzigbee-zll.a index a85df82e31..29441021a0 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7e834c3eec9a233f28477e672ff1d6f79e404b23a4cbc61454f174df331a7604 -size 189930 +oid sha256:6ab78892d502e26ab5e16bce3bdf68d9db5ca0074c0431c07daf92164c47cb65 +size 190090 diff --git a/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release_singlenetwork/libzigbee-zll.a index a2397ec5bb..664312b95c 100644 --- a/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/arm64v8/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:db80e872fc45fed651d5aee72c0e47cc3391a4d26f05bf6d80209f4c9e921c79 -size 184738 +oid sha256:7b2f538e0f20d1ae208f366bb0d4e673c48a6eaed063016b829d6b628057fad9 +size 184826 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a index bc12c09c43..88ef45764c 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bb570b9319ec03138676d09b4e37e0c55988438a1e00611a1e8244952675b4fd -size 58438 +oid sha256:31e5a85bb37174f9c6b32f8f0d4bc75a6ae21e62157a5b213e7594de092efa7e +size 58490 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index 91ffb9352a..f1813ce4b2 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:189ba5d0e18668f40f62ed2e0728224413fc511538bb7e742afd42286171ad2f -size 57174 +oid sha256:12dd511499de2f2710344f3a928779a0f3f94470d6a4faca92a36bceefaf388c +size 57226 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a index 0161232c73..ec8b3ff768 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:876804bbd0ac4622eb6b7631520f477cfcd661d0072e4af73b16ddd0e6bb1f33 -size 38080 +oid sha256:1f218106865b44905e3596a7148c2df6f6698c58a391bcf99bddbab51d2ae13a +size 38132 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index d89c6a6f1f..283962f052 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5b4224e66c66c6e049fd4621341d9cd97da557e08029423c3171f13f85492901 -size 36836 +oid sha256:6af74970a0905d505a7f0b3261ee63b81100c0568a492b49666bd41039b0b54c +size 36888 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a index eddf7cfd92..bcc9a68638 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:53285c1567afd03ed8b6dee230c9ecb41cb1b8b58faa1f9ac513a84aa1309575 -size 40948 +oid sha256:c0b845f1df76f30a6d7b547e6d80a472d1b1b0208ce6da82feb4d221bce53054 +size 41000 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index b278757c2f..fe6b8dbebe 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e95aa65fc0609d77af583b1efbcae33c8ef01060544a76b93784f048aba2347c -size 39684 +oid sha256:40f62ed0b539c9140c231c845ff20afc48555d2c0a51ce70530a680c57834223 +size 39736 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a index c1ab8bee0b..c44325dcc8 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:65463b1976e5bf5a01b16ce87103bf21a06b053e20755edfd8585d1aefa0c725 -size 311270 +oid sha256:87440706bf0dd15712e5d886bb681ce609a762ab41b1aa9cbc21b6c8e8e5998a +size 311478 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index 5fd443c4a1..0099f97efd 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2d1fe2a06edd9360c347a8cb496d918808404c43d55b3c719b23d278f548ed77 -size 304750 +oid sha256:664ab7e0a1ffa6f4e79b9f1c6d5bd668dce5c785d965e8e777d8989a001db3b7 +size 304958 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a index 10f73e7d92..52a44e5028 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:33b597bf9475a9a6735feb7a43ef908070baf2512689e0513c238599d37f8f1e -size 42490 +oid sha256:4c35224d07b67bf70bc6caf4114653a4c38d90a19d1c74d77d41c5946d2f1ed9 +size 42542 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index 5f6a97688c..1916a2f15d 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b27ea6bbea69f0f9db5030fcb3e3b01629851b54446e38b320c62c2f64f8ca28 -size 41226 +oid sha256:be14ac88d3997866fac2bbcc067d1a678afbb21f8096ee58768893797442c35f +size 41278 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a index b479d9a523..7bc97d36a4 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3dfc66858805ace9bc105be6a59c90d48da94074475f742be0298c706aa0b330 -size 47436 +oid sha256:9bc3d628febadd4de734783aee7ec4d6f9b1005f34aa72ab1e9e4ab377c8ce8c +size 47488 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 38368a87da..087db6e36f 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e66b560a81d959f230df085326671dfdcf8b56baf94401e7cc4886cc137d967d -size 46200 +oid sha256:bda511b3580a017efceb3a01985dac98c1504d6adff8505fb79db5e3b8de5f06 +size 46252 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a index fec3980f1b..48be2dd4ed 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:420653591ba080575385089ceb2357ae16be73beb2db4af33b14f04274555dbc +oid sha256:b74dd8f2336e069aefefd0bbb71493e64e8ea0c1ae505794138b06bbdd4d40de size 31710 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a index 1baf9f8a11..6e7a622a75 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7736499f01a6a5e80d9849f79f91481d2bb821c0ddd2f9989c8a124effd437cb +oid sha256:f681ef0aa73f273aa8c89a83cf6b4d3af148c846f3c0946f4664f027c008ac02 size 30546 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a index a8efd883fc..2cd167b739 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8014a4e44dabfc15a30c9d2284196100645f6254b0dc9ecfda0885a44943ec7f +oid sha256:e4917dc1e396b587dc3896dc9f87b5347bb20c23787dde28c3f10d9c536939e0 size 112756 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a index 7e810d8cb9..7a8210c0b1 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6f14a50b8463f8d1a1735b9b3837fcfbc98b6f8314ac7ce936e023b828527af9 +oid sha256:0da157849ea5940abfec38f69ea5746bbccee01b68da306722b1a4a8e3a6cdef size 110148 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a index 9f080284e5..c2dbb1db19 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2298ade6a4b883511f030cb312edb84b045ad68d58cef754c796f6b217468672 +oid sha256:c9fb1b2b2248584d73e784afde2ffb8494dd9aa140f08939aa737ee061e131cb size 136638 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a index d71a49e93f..d25111717c 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:78c19b040e785620b78e7922d30889176220a7ea92eeab48330952f044d5f235 +oid sha256:c74a765401efa0d5aa6ce6ae85426a110ad7ef52ffa2d851cbdd3ea5c0c15aae size 135138 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a index ed16e0a1d4..970679fd30 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aaeab53c655f62f46f9eb1df89f5bf59ec63003a9153f065d71df877dfa17c2d +oid sha256:23e2b8e371b0452f79d8681b1bb4b5e6acdc9e49949e97245f5c4c304dcdff23 size 27808 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a index f32e29019e..9e224c03d0 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cad2cba1c7203e68ffb80a679d19f7f19a9186a2c7a115361dc7bfbd970ebe2e +oid sha256:d0ed9857a92d7975beea253c7c276f1334cc84e9a8c9b014e7882c4600fe07e4 size 26464 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a index 60e665a15d..1182658584 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c2274c06095b7c6fd174f467e23b159e5aca282af661899bb22d1903d46ceeaf +oid sha256:fa29075fe977ca815d1d876c1db36b4a087931aeb0135c5be6d39fd0bc3a1830 size 44972 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index 6349395dd5..c52bfa32dc 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:39214aa3d39a12056b65e6f694abb9c244e94ec41d64328ff3e2066880322b82 -size 274392 +oid sha256:427eaf383555eb2565fad3eb79875668f797085027d8747f7bdb54d2583fa192 +size 275034 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index 264a0f130e..cf44eeca85 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:392973f176f9197fa9bc2f4eafa9db3f5a306ea1ddde22a01e8b10a9dcc5bfc5 -size 266764 +oid sha256:5c53e3ca0da70ed3ed8986080bc546f5adf4cbe4c2d4373013508e3b68475c5b +size 267406 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 2cd8f58635..e437425484 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0014d74e9bd48107d86ae06b38dec5901e23fec0fd5de4bf354a4b96cc2ad8ff -size 2280982 +oid sha256:8163e80d73865f31eba6749cc90bca1f641935758e457587a05185ee9a1a24e8 +size 2280974 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index 5131c5e6ae..e13dd47c3c 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2d9d56f6efa8514d4965710a7be13826bb0060d5f3893e8c59bf44c3e9deec4d -size 2178054 +oid sha256:7c5397aff6d88537b536c3aadf753f0656e6b390dda749487d39b8fb496a57a1 +size 2178046 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index fa93786877..4449fe5cb5 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f3f56529fb38b85e5fa6f53b6e0d58b24c66d762b38e28f18cfbc2152922dacb -size 2473626 +oid sha256:ac64cf91eb28f94bd2afbd238be645c5aba95a069f3651f9b9f69de1f85bd4b4 +size 2473698 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index a6e01fc5b0..c36b179cf2 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a8f2c4f38d68429b095b1df948c0d6cfb4a17a6e95b825c630078c6d6abdf3e7 -size 2359396 +oid sha256:2d810e309830770b0db5a0324965c7c4660e699c2867072b9f032e9fbd56db97 +size 2359464 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index 8dccaa3f64..09955c2076 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a7c491cdb240b88de0a35db16451bb252c1be62180d7de95de2c48f1de296d96 -size 2523108 +oid sha256:6c5fcc41536d52e257ff1ce72bcac76078b9a7a33d62a0af9fa86d9603ff8f14 +size 2523176 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index c360164554..8135247547 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e8c0025f805feadc5a826eeb6ee5e268e89be68ced00825de501c29eb2b25aee -size 2399074 +oid sha256:4b75281989eec5bde22414e22620af93035855faf2b1187109f884e2e6b54fe6 +size 2399146 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a index cfa0b3d047..b4c1840ad1 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0f0b429a5e8953e90fa6747ce1801a2d3780cca658e347f7c0cbdfe3941d71b9 -size 2511084 +oid sha256:f832e6910f2e80fc82b576fd9bf7b1e528f0dd4fbe856cf113ec1c19edf45cec +size 2511156 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index b8a6071e75..e8ecfc2d07 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:154001fae7d6ddc02873c7b7daeee0b5b191814b9d148d9bc0afd8a5204385c3 -size 2387038 +oid sha256:e876ae89192d749a7da3b28a1365dec3da2bfacff93e1cfcfee7febc77a1c716 +size 2387106 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index 73783cd4a5..8df0d2e5f7 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d28922536b53f674dfe652eaddc80f150c98ff2bc3efa6a6d910963fc2cf9ed9 +oid sha256:677bb0728cf8df54d1affb8a9ef0bb4219d93eacd10430529e15efc3eb0563e3 size 100036 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index 7897d3558a..c3afc79c53 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8c565bcd467fb87d74ca7e98e27760753a9da101f592168bbc579c8e724ac26c +oid sha256:67af435e78df8c7d96b91f4ab7ad26bdf8948173c8923176226c6fdbae14b92c size 94844 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a index ebe1d891e3..4ee78ed703 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1f401ccfdb910d173351ba5dca22c968b7ab766cb07144f42ec6ec2c64ee8a41 +oid sha256:99dd8cdc6a646e66883406602cbc8da5bc38c2e79eece0b058742d0b97f752a4 size 99744 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index 4197447334..09fdd985d4 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f676bb074281d23298131450e16e6bb9acf34fb927c188e8d6a70e50a38b83da +oid sha256:def692aafa5467affa4646114414bf9da371395e091f266782d038b0229a5947 size 94560 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a index 60e16d61c6..8d06b1feae 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4bb61bf80c3e90296bfa57a628d5efdf40447f78a00bc6442cdc393e8adde0d7 +oid sha256:7486fc033ee9d8f961d22a620a2bb3dd4d35cac9798472e13e45d15e24fde46c size 323762 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a index 9c81e3fa1f..232a45d719 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:653ca1e83dc9cefa32e6ee4574437108bda93009cf887048a981f500344bdf35 +oid sha256:d55673458bfdf8c1bd6471f5fac3d22399a481c94b4001460ecd02c0313d0a68 size 313526 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a index e257b3ddbc..d43d66c2a3 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:af6a46eff8fe2811c91d854eeb60b85b4b5d5521b0a9319f756250ab2179251f +oid sha256:b2d680af96b5bb98019c63688ef110bad23ceecd0bfdc21c427391c643c78b53 size 56856 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index c4ef453e92..abfcfb167f 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0cd01c1669a106d358d3e2518fc431d8c01ef435edc6eb8813f1ca50c65688d5 +oid sha256:a9c77d2fd30da4c9b59817c22a19d6569f357096fa91eae9ce886a15c3f96cc2 size 49624 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a index 8aa33df5ed..db3d8b3c6d 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0f476442c41d13b2d2ac218ff468927735a022f012c552ecc12ffb4b9f54d830 -size 27182 +oid sha256:bf059c6b9cf50ed35de1d824f3062069f41531265df953a9cf5ba0e398f08c71 +size 27234 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 8aa33df5ed..db3d8b3c6d 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0f476442c41d13b2d2ac218ff468927735a022f012c552ecc12ffb4b9f54d830 -size 27182 +oid sha256:bf059c6b9cf50ed35de1d824f3062069f41531265df953a9cf5ba0e398f08c71 +size 27234 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a index be56b8b589..8f41064b92 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:68a92a1889e81e60c26a7001f717e697c845b101d967555d1de6e34a79a3d585 -size 176266 +oid sha256:62e2768f6cbf8305a6c4c5b260145f128a1a61d82678df0484a951ecc8126ef5 +size 176366 diff --git a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a index 8164c5dd79..e97ba2d38f 100644 --- a/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/armv7l_tizen-0.1-13.1_gcc-9.2-softfp/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd5da982022d19adc1b4da1f17d97e3b69bb26d9d1b6dd115cbe9c54652c9ba2 -size 172770 +oid sha256:1499dca3206c074ad33fa797b02e38f2216326c467bb6a99d6ced9d7676a6405 +size 172838 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a index 82684b1d73..99d19c10c5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f97ba55e2ccf40494a6d93c6dcc5a9539d5f43f957b1b340355749e8a8c55346 +oid sha256:cd1356ca2cfe749587e19889a0f7246369f29812053d08475edbc200891633f0 size 6380 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a index 82684b1d73..99d19c10c5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f97ba55e2ccf40494a6d93c6dcc5a9539d5f43f957b1b340355749e8a8c55346 +oid sha256:cd1356ca2cfe749587e19889a0f7246369f29812053d08475edbc200891633f0 size 6380 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a index 82684b1d73..99d19c10c5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f97ba55e2ccf40494a6d93c6dcc5a9539d5f43f957b1b340355749e8a8c55346 +oid sha256:cd1356ca2cfe749587e19889a0f7246369f29812053d08475edbc200891633f0 size 6380 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index 82684b1d73..99d19c10c5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f97ba55e2ccf40494a6d93c6dcc5a9539d5f43f957b1b340355749e8a8c55346 +oid sha256:cd1356ca2cfe749587e19889a0f7246369f29812053d08475edbc200891633f0 size 6380 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release/libncp-gp-library.a index 38ae9573bf..f24c585a54 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e2e0df4a25283bb2520eb44a747c2fbfdd7021e9cd15385b40290d4a39a6c34 +oid sha256:8a1f8d64d3dcbb46af92992059b30ce57be5a79af0a561b69453b4aedbbb6222 size 2198 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a index 38ae9573bf..f24c585a54 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e2e0df4a25283bb2520eb44a747c2fbfdd7021e9cd15385b40290d4a39a6c34 +oid sha256:8a1f8d64d3dcbb46af92992059b30ce57be5a79af0a561b69453b4aedbbb6222 size 2198 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a index 38ae9573bf..f24c585a54 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e2e0df4a25283bb2520eb44a747c2fbfdd7021e9cd15385b40290d4a39a6c34 +oid sha256:8a1f8d64d3dcbb46af92992059b30ce57be5a79af0a561b69453b4aedbbb6222 size 2198 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index 38ae9573bf..f24c585a54 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e2e0df4a25283bb2520eb44a747c2fbfdd7021e9cd15385b40290d4a39a6c34 +oid sha256:8a1f8d64d3dcbb46af92992059b30ce57be5a79af0a561b69453b4aedbbb6222 size 2198 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a index 93df4bf158..398733061f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:228933b913e4e0ca99937b2489cf72d1ce860eed5bdc7baacc2f1cc58b589b19 +oid sha256:61593acfecda3581dbf37a67cdae13766a2d4f52090166264f59e3c5e7096f2b size 2818 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a index 93df4bf158..398733061f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:228933b913e4e0ca99937b2489cf72d1ce860eed5bdc7baacc2f1cc58b589b19 +oid sha256:61593acfecda3581dbf37a67cdae13766a2d4f52090166264f59e3c5e7096f2b size 2818 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a index 93df4bf158..398733061f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:228933b913e4e0ca99937b2489cf72d1ce860eed5bdc7baacc2f1cc58b589b19 +oid sha256:61593acfecda3581dbf37a67cdae13766a2d4f52090166264f59e3c5e7096f2b size 2818 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index 93df4bf158..398733061f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:228933b913e4e0ca99937b2489cf72d1ce860eed5bdc7baacc2f1cc58b589b19 +oid sha256:61593acfecda3581dbf37a67cdae13766a2d4f52090166264f59e3c5e7096f2b size 2818 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release/libncp-pro-library.a index 62b385da70..6e776b75c8 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:93c5e57d69634a94e957b616b32d132ac80fd52a308a3e095359aea1fb8aaf93 +oid sha256:ca18d30d2a551736e87b59b62beeadcd5c9c7f5469dee524840f70bd0a88d37f size 53644 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a index 62b385da70..6e776b75c8 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:93c5e57d69634a94e957b616b32d132ac80fd52a308a3e095359aea1fb8aaf93 +oid sha256:ca18d30d2a551736e87b59b62beeadcd5c9c7f5469dee524840f70bd0a88d37f size 53644 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a index 844e024af6..ff9b8a5ec3 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b3aa6718baa3e11f7a7f041229bbd9f4ec2c7f05bba112398fe01f88c933ce32 +oid sha256:a223e9314e266f74e87522dc418b060e0b95da8c89387e641c1ef61739738d4f size 53128 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index 844e024af6..ff9b8a5ec3 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b3aa6718baa3e11f7a7f041229bbd9f4ec2c7f05bba112398fe01f88c933ce32 +oid sha256:a223e9314e266f74e87522dc418b060e0b95da8c89387e641c1ef61739738d4f size 53128 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a index 81ea03a0ac..ac66ddb3f0 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:26d6b1fcf9d4d880ad0396295fb40e08a32c2ba03e5745a29c3dae74822396a4 +oid sha256:6fd5efc053c7e5ed4033e7853cddb547a61d7dabc8bc79092a870d166aa6fdaa size 3896 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a index 1451fef2d6..ac66ddb3f0 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2338c8897be3fc9590f3804908145e8b512a6bbd05eebf18af9add1c8827d059 +oid sha256:6fd5efc053c7e5ed4033e7853cddb547a61d7dabc8bc79092a870d166aa6fdaa size 3896 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a index 1451fef2d6..ac66ddb3f0 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2338c8897be3fc9590f3804908145e8b512a6bbd05eebf18af9add1c8827d059 +oid sha256:6fd5efc053c7e5ed4033e7853cddb547a61d7dabc8bc79092a870d166aa6fdaa size 3896 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index 81ea03a0ac..ac66ddb3f0 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:26d6b1fcf9d4d880ad0396295fb40e08a32c2ba03e5745a29c3dae74822396a4 +oid sha256:6fd5efc053c7e5ed4033e7853cddb547a61d7dabc8bc79092a870d166aa6fdaa size 3896 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release/libncp-zll-library.a index 450e2f8a68..63c2ba2cd5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:65ce73388deaceb64704e7679bb1564a587b9fa698b15144fb6a510eb6613dd4 +oid sha256:03b0e36d9a7cb64aeefd48101df9b9b372271d97b17292c500611f26a7ccef40 size 4538 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a index 450e2f8a68..63c2ba2cd5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:65ce73388deaceb64704e7679bb1564a587b9fa698b15144fb6a510eb6613dd4 +oid sha256:03b0e36d9a7cb64aeefd48101df9b9b372271d97b17292c500611f26a7ccef40 size 4538 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a index 450e2f8a68..63c2ba2cd5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:65ce73388deaceb64704e7679bb1564a587b9fa698b15144fb6a510eb6613dd4 +oid sha256:03b0e36d9a7cb64aeefd48101df9b9b372271d97b17292c500611f26a7ccef40 size 4538 diff --git a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 450e2f8a68..63c2ba2cd5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:65ce73388deaceb64704e7679bb1564a587b9fa698b15144fb6a510eb6613dd4 +oid sha256:03b0e36d9a7cb64aeefd48101df9b9b372271d97b17292c500611f26a7ccef40 size 4538 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a index 4750dc98ef..f18b0ff382 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:742f63bab56cacfa90726f331f3e9e6c96daac1ee8e15d1b75bddd8d4eda80bb +oid sha256:ec63780af947ca03dfa183a12baa082c6b1f0c43de624a0935588893e988fdf8 size 17036 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a index 4750dc98ef..f18b0ff382 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:742f63bab56cacfa90726f331f3e9e6c96daac1ee8e15d1b75bddd8d4eda80bb +oid sha256:ec63780af947ca03dfa183a12baa082c6b1f0c43de624a0935588893e988fdf8 size 17036 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a index 8320af168f..4c9b919493 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7cb3992ae04b648c6f18da739cf564f7e2c3d32f3c691defca04388058c99069 +oid sha256:2271f08e46a09d5c8b7c7b59fed53a5928a055c38dec0d05e8555fbd29100600 size 16776 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a index 8320af168f..4c9b919493 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7cb3992ae04b648c6f18da739cf564f7e2c3d32f3c691defca04388058c99069 +oid sha256:2271f08e46a09d5c8b7c7b59fed53a5928a055c38dec0d05e8555fbd29100600 size 16776 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a index 69c08a56de..1db9b93315 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd084b006f5dfb52271d08b1472eb6fa07bbb079d1bef9245e5147f1e811d864 +oid sha256:9ddc04fff2867ad2714203be18715198d8b8681f45cd7c0d3c8ddd831e44b9d2 size 16198 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a index 69c08a56de..1db9b93315 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd084b006f5dfb52271d08b1472eb6fa07bbb079d1bef9245e5147f1e811d864 +oid sha256:9ddc04fff2867ad2714203be18715198d8b8681f45cd7c0d3c8ddd831e44b9d2 size 16198 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a index 26207305a3..98e6b157ad 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d09a369827e4a132f8bb10ec97ba94ae57f583ce5270f7a99098b3624c4a4da2 +oid sha256:7993eb4ad235e6cd90dcbb66adb408e29b2ac9d9826282c48a9ffe770e4e9e6a size 15942 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a index 26207305a3..98e6b157ad 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d09a369827e4a132f8bb10ec97ba94ae57f583ce5270f7a99098b3624c4a4da2 +oid sha256:7993eb4ad235e6cd90dcbb66adb408e29b2ac9d9826282c48a9ffe770e4e9e6a size 15942 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a index cd759b4517..de4566fd3b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8b25b391cdc5f516ab17f84741656f24acb576f04276941616cd21d530f5d4ba +oid sha256:14a78dd38dfdde6d0a135d4185731c1d8362f479f5e4d2a79ca732d451c5f4aa size 7692 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a index cd759b4517..de4566fd3b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8b25b391cdc5f516ab17f84741656f24acb576f04276941616cd21d530f5d4ba +oid sha256:14a78dd38dfdde6d0a135d4185731c1d8362f479f5e4d2a79ca732d451c5f4aa size 7692 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a index cd759b4517..de4566fd3b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8b25b391cdc5f516ab17f84741656f24acb576f04276941616cd21d530f5d4ba +oid sha256:14a78dd38dfdde6d0a135d4185731c1d8362f479f5e4d2a79ca732d451c5f4aa size 7692 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a index cd759b4517..de4566fd3b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8b25b391cdc5f516ab17f84741656f24acb576f04276941616cd21d530f5d4ba +oid sha256:14a78dd38dfdde6d0a135d4185731c1d8362f479f5e4d2a79ca732d451c5f4aa size 7692 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a index b13e413456..650acfd56a 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f6c6e12d747a9ec4e9a6783f6ab74eb46fe1cdaa6753fc254cfb7ff5bcbd7cc6 +oid sha256:cbaef87d83760bc09878f280359aa81700798681d9703eb1612a36ed395f3a2b size 4274 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a index b13e413456..650acfd56a 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f6c6e12d747a9ec4e9a6783f6ab74eb46fe1cdaa6753fc254cfb7ff5bcbd7cc6 +oid sha256:cbaef87d83760bc09878f280359aa81700798681d9703eb1612a36ed395f3a2b size 4274 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a index 8d734b55c2..cb6c3957a4 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:db9478f1f80123cfc69cf10d8aef8c812395596bd5f26b0701c9cc9d2f0fd7ce +oid sha256:76393a969940d9b2c66cf63da2a1abff65b4d971ae68de3f2243c526f9bef9e8 size 4114 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a index 8d734b55c2..cb6c3957a4 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:db9478f1f80123cfc69cf10d8aef8c812395596bd5f26b0701c9cc9d2f0fd7ce +oid sha256:76393a969940d9b2c66cf63da2a1abff65b4d971ae68de3f2243c526f9bef9e8 size 4114 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a index 69324b3dc5..597d0f2ac7 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eec4d62fb791831dacf922640bb10301457da6eed7334aa5e7991821e76335ab +oid sha256:257090888788438131939dfda2f16fa9f9112716212d0fc7b83da8f4b460f0a8 size 3448 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a index 69324b3dc5..a9ea3943b0 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eec4d62fb791831dacf922640bb10301457da6eed7334aa5e7991821e76335ab +oid sha256:dd526862d6af17fd826c28cf72f73862a2bc1b20bcd42d5a43eb3f2b52a0cd1b size 3448 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a index 4f58f018ae..cf5b84d956 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f0aceeba35d20c5b2bc1884426b4e9161e3292b4b3ebb7582876da2aa78f1afe +oid sha256:c52ad73e5fb644718d6b5a28a3b58b614b923482c679a58ae1793a556ad9ddca size 3304 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a index 4f58f018ae..cf5b84d956 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f0aceeba35d20c5b2bc1884426b4e9161e3292b4b3ebb7582876da2aa78f1afe +oid sha256:c52ad73e5fb644718d6b5a28a3b58b614b923482c679a58ae1793a556ad9ddca size 3304 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a index 500f45c2a1..7d7e6f552b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eaa51145b9f045f7529ecd4d220f96248526f7c976519367a4758c53eb291a59 +oid sha256:1b1b553890d4349d361ea0f3d6619aa0f249a7fe825f968e5286947fa6ed554d size 3338 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a index 500f45c2a1..7d7e6f552b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eaa51145b9f045f7529ecd4d220f96248526f7c976519367a4758c53eb291a59 +oid sha256:1b1b553890d4349d361ea0f3d6619aa0f249a7fe825f968e5286947fa6ed554d size 3338 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a index 0dd4a9c09d..2060d98007 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3e9e98c48863bff93ecd1051375b8b8b7c207887b174729323581e715a3b08e7 +oid sha256:2fd1b34397bfb7ae58124eff7bbfd91329b16ef3036b0d029a680fc2ccf55823 size 3190 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a index 0dd4a9c09d..2060d98007 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3e9e98c48863bff93ecd1051375b8b8b7c207887b174729323581e715a3b08e7 +oid sha256:2fd1b34397bfb7ae58124eff7bbfd91329b16ef3036b0d029a680fc2ccf55823 size 3190 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a index a8ecc67d37..4f0d749733 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a66966769b31018652aafaa594767ee4578dc6cf0cf547644f575c4cfc998cc1 +oid sha256:6a711d06613bbfff856d46f65276b518e46f5da0dc0fa4a98c05c42bb51c7e7b size 6308 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a index a8ecc67d37..4f0d749733 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a66966769b31018652aafaa594767ee4578dc6cf0cf547644f575c4cfc998cc1 +oid sha256:6a711d06613bbfff856d46f65276b518e46f5da0dc0fa4a98c05c42bb51c7e7b size 6308 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a index a8ecc67d37..4f0d749733 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a66966769b31018652aafaa594767ee4578dc6cf0cf547644f575c4cfc998cc1 +oid sha256:6a711d06613bbfff856d46f65276b518e46f5da0dc0fa4a98c05c42bb51c7e7b size 6308 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a index a8ecc67d37..4f0d749733 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a66966769b31018652aafaa594767ee4578dc6cf0cf547644f575c4cfc998cc1 +oid sha256:6a711d06613bbfff856d46f65276b518e46f5da0dc0fa4a98c05c42bb51c7e7b size 6308 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a index cd004c2067..d6ab12d0a2 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:936a5dc4a44bd1de5c2d48c29e22f12ceaf708c3f63d87c24131504956c7a210 +oid sha256:9d2da3afd338c91af5b99899c7e77231aa39e0dfd04ac240ab3a1a1a0e255ace size 4128 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a index cd004c2067..d6ab12d0a2 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:936a5dc4a44bd1de5c2d48c29e22f12ceaf708c3f63d87c24131504956c7a210 +oid sha256:9d2da3afd338c91af5b99899c7e77231aa39e0dfd04ac240ab3a1a1a0e255ace size 4128 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a index 6c8c2e1e41..d6ab12d0a2 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d905dbc800e6a3d9da290f406e38e156a9175406d7beefc0c6011c31cfd8c91f +oid sha256:9d2da3afd338c91af5b99899c7e77231aa39e0dfd04ac240ab3a1a1a0e255ace size 4128 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a index 6c8c2e1e41..d6ab12d0a2 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d905dbc800e6a3d9da290f406e38e156a9175406d7beefc0c6011c31cfd8c91f +oid sha256:9d2da3afd338c91af5b99899c7e77231aa39e0dfd04ac240ab3a1a1a0e255ace size 4128 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a index d5551b2af2..bc10a0aece 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f24431dce4730c13e8edda6c2ede30d5f93f774080d4ea4c53b0ecfca3d2ef78 +oid sha256:674c4c7dcaaf344ae5ae8c556c26f09e0e5dfbdbc56f94280f63529e6480be6f size 25280 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a index 63415b7929..bc10a0aece 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f9527dd6186c6d68b04ba5a6e1c8e42c0ab0b8769b0c269ce897af0c525f2af9 +oid sha256:674c4c7dcaaf344ae5ae8c556c26f09e0e5dfbdbc56f94280f63529e6480be6f size 25280 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a index a43abd39dd..2fd7836637 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cca2ccbe0173a2f5d74a62618d502f261b5bedaedbcf46a338f59db5b9f33f6f +oid sha256:d3ff980a6f1edcb1d10625d1d14225442aa52125b22118eeba169ae9dc91b29b size 25212 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a index e738cccd2e..2fd7836637 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7e913d0d36558c6cd88f19b027077de528a5f4673403514944d440771ddb6e3f +oid sha256:d3ff980a6f1edcb1d10625d1d14225442aa52125b22118eeba169ae9dc91b29b size 25212 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release/libzigbee-gp.a index 5c23f70d3b..9fa6577f2c 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6b1c78fffef0d918de373b07be34d42516b284184930ccde1b321ed125461b06 +oid sha256:bb62f1bb4ab20678e208df647e9196934779e310af78495087efa26c2944169f size 37834 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a index 5c23f70d3b..9fa6577f2c 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6b1c78fffef0d918de373b07be34d42516b284184930ccde1b321ed125461b06 +oid sha256:bb62f1bb4ab20678e208df647e9196934779e310af78495087efa26c2944169f size 37834 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a index 86f924d4f6..6bb8b0d65b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:41709422bcac76060edaae0ca3e0e5d9f5307d6dda4b422e43028ffb269243d7 +oid sha256:fb8c774bab78d5146fbc358c50e2a2e991d018407ea8100e821277e20195dae6 size 37358 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a index 86f924d4f6..6bb8b0d65b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:41709422bcac76060edaae0ca3e0e5d9f5307d6dda4b422e43028ffb269243d7 +oid sha256:fb8c774bab78d5146fbc358c50e2a2e991d018407ea8100e821277e20195dae6 size 37358 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a index 3de464a78f..8f7eebfccc 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8f0ac8fa008e3631529293797a42ff4b2da0388dd888333157905fb2ac4a551b +oid sha256:ed6ec469780c51bd851c50ce586ce8c75b3795cb95b1b53d6f52c2d627016e41 size 9064 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a index e13ccac119..e5bf5a55fd 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c8b634c6bd564f2944f7e321af0158650d87874386f56d6abbead5f9d8d54279 +oid sha256:0b6e00e3138e1d0907a7028f8003966e0b708db463e4402b7175cb05143540ab size 12384 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a index aece5062ec..88c0a370cf 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:52a8c5c155c741a449d1f24eb40951a942f1b60242067015cbbb2d2774dfc4a1 +oid sha256:8187394c2cc136caa859cc485a5711eddf2f771d108dd5f56b52289af459725f size 12280 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a index e1cc100089..3170ee45a9 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1a5474837b8111175c7a5e7d6cea27e0ed25b4443a96cf82e0c7edfd667a28b0 +oid sha256:b7ab18b03a10f02031b2bb4a0c614e39668ac83cc24100fbd26ce9b98f45e71b size 8976 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a index 1e6303be61..476ba39062 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a0fc2dcab55c4e36648576cdb39f58728e1a15d7144d276f1ae5344e064acbc7 +oid sha256:1c2270d02cbb1e802d55e5a8cd15b813d208413b6a8c0facec5c9c9ca34b5318 size 16706 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a index 3995b95bbe..5e0f4981c4 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1299545ddc61f8bb3c7d6d7f0397c4a7c12315cb9e9119b1094b7bd6a7099253 +oid sha256:b13a95336e93f1d5cf367736fa9c41f5110b98191238b84e462951ac55a855c8 size 5282 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a index 68ffc40ec7..4089151305 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:69de46d4014e4ab1270845653820c8caebd67526f0082d92b5238b8c0a3d930f -size 64176 +oid sha256:68b09d315b6782666cfbbc6b8f6f2e2398df23839bc6acca517d2458d49774ea +size 65256 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a index e5396f33eb..5f01238d14 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a250b572f0e449afdb6df77e2d496d39561bf6c48989e06c739814c0325aa067 -size 64176 +oid sha256:40cf36b2a4ef0006a2f5be2131c0011893e123c02da43c1fd07f646e556291ec +size 65256 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a index 7a44906886..a1a78ddd8d 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7a2abbf0c85e8da2b563c7857814283fff9905632466e542e04e42806cb1d0af -size 63596 +oid sha256:dceb4c0e7b779b52ff861c064708a6e482b26760672871c4a4d76351d8d9ca63 +size 64672 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a index de80958ee9..ea7829ce61 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8f90fc69fb68ab84a8b3ad1c2753d0493b4000fdcaca06369bf5a3de69908c0a -size 63596 +oid sha256:bd32a6e0d16480d207df4743f3df2bf9afd8760525979b3fa348cecce85d4842 +size 64672 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a index 029c11da27..b5792ddd9d 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b96731d23a23c4ad6f61e510b6330aeaacb220a52544070549dd5bddfe8f25ab -size 60004 +oid sha256:64b773ad5c96c25296eb4836bb3a9a1d694809bbccaea83340a2d689610a8829 +size 60314 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a index fe3340cee6..97134f1156 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ec887951cf015810759efabc3c01e8f20cad07a55d8a394b8e348593b9b1a85f -size 60004 +oid sha256:4ce5282584424a13191544265b8bba639db03714bc247577e4c47a4749ba3afa +size 60314 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a index ec072ac1ee..1aa4e44266 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:33d39499a6891ce9215f74f81170d54615f86fc42d3181766107b649ca3059a0 -size 59420 +oid sha256:6ac1abbf67a750e2936e213c7da244c3eadba76922d1440dfc50ee40ae56863d +size 59726 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a index 21d860f97c..853718d1bb 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:36df045c90b6746f86bf144e8cfcb447a00c5e067f9911d13f82bf3b41011cb5 -size 59420 +oid sha256:cbdcf8408e6f07f9a65afde9429b8d778ae39613efe3c51134a380a6ec20b7fb +size 59726 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index 66b48ce6fc..33ec8f6d72 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0e0c031d7cdf0600029430d2514ef7de7b9cb64a574c269935e6796e51c2824e -size 55350 +oid sha256:984eb549b8189ad1598ae8bdc337ba8211cb2a550f6bb5a28b8833e95740e2cf +size 55656 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a index 147f6c8890..ab486a8464 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9c8605fbc3d3f1f1a6dfe8b7c31b9c0d05f57ee5d551b13fcc311683cfbf66c7 -size 55350 +oid sha256:f4dd6f4914da420cd84cc29de754d64e7653afe699104c625498017d843bdb03 +size 55656 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a index ec8ae1f837..46722a5a7f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:690b7d6e224b613093a03cd022667823d17f64107bdfd3dbd393c2c2c6a0935e -size 54766 +oid sha256:22a2cef7ce29e3cb6530a4b6e1593760b23c585c9c18b497a3caf6fc717cfaf7 +size 55076 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index 2af62e29bb..14df05b1ca 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:29d5854281b838fe2e5e4badabe5682a92518721ea2b22dbd305f98b4bfe17fb -size 54766 +oid sha256:d71362a3c31dd4ab036126639ccf451518b3484fbc5addefdce1606cd5301db4 +size 55076 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a index fa38a02625..d46ee91ce1 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:99a240ee73137096482f322d894265c78b4f3eb2866717a22b14c116664bc671 +oid sha256:3cbacb3b9ae5607e4ca16228746a7937d657ed9cb84a4148077256ab20843ae3 size 617234 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a index 1207bd8be4..7202472f03 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:69f7fb4b0eae6707ddbe38697a0a04cd9e97a7c8f820a66a19d7b52535788d44 -size 803850 +oid sha256:551687404f8b3d79b62e1e70be411ef052d5ca035452ce3a3044f902ba176d2a +size 803846 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a index 836e020401..53c594ab9a 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:69e6e3c98fc63117ef7db605e42be24a471e49e3a7128999cbc73f2ae74d489c -size 781558 +oid sha256:9d6dfa1c0122af4570426036273d9f4d8923607282da081b4a80ea89ea79930e +size 781554 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a index 47d9b73fbf..2347f7955e 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bbb2b26b7cb1d286740009557a275170748db6e25e0ebadc33764b2bde6dcc85 +oid sha256:5ea6c9fea11aa14309d0b41fc65b14b6b574022715b7a03f46249c61a28cf3c9 size 594138 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 6fb9bbf4c5..fb94df07ed 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:27d226ae7d0af81d1a8e267a892f2d80b605a432a5c589e4b2472977216e33ff +oid sha256:f1c6d960f328ca0220d5ca89b587c26e022b168a38e20668eb050dbad3771c63 size 613868 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a index d53344a931..6cf75fa5d5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:989b56395ddcdb2c067a02ce42ce345d1c9ea974a5d9fc129a297db6c33441de -size 800440 +oid sha256:94852f60790dfa62b7acc1e4213b249d34a6a694fdabcc15c3921700dd7868e9 +size 800436 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a index f101fd11f4..f035da2c1f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5ecb8efc150f4f9527e4a1c92fb37b0631930f1ffc9ea9302fc80fbb3e3dd729 -size 778196 +oid sha256:de276ad6ca2d62b96f679373da2fc6270a22b8183943e619f23ced430ff9c670 +size 778192 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index 4e30047971..8b605cd6e1 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f1b346b01dd689f23b73598790f14b9366b261c2549480db192e13f2dfc37f86 +oid sha256:e277f284bae87e95adca980398b4bc3e71454ae5cd90bd8a7f31939fabc4e875 size 590788 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a index fd777035fa..beba6781bd 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ccaf923e012a97d26e0b7899403196b22330a0a1c782140d232b30a75fbae78c -size 668448 +oid sha256:4c5aaa82523246c0bfc7c57b98ae0eb749fd683500f3af624180f978a4d01056 +size 668496 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a index b8fd7bf4c2..d98d2324be 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2e3a95200306d12317bfc50c944878a81a8099fe94a39ecb80505544104f4091 -size 641770 +oid sha256:7887c86d46ea671f88826cc30d0d3f0066c596fef67930a9b013a136faf416c7 +size 641818 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a index cae21af43e..dd4a831e79 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:41c41154000fec56fb5bc35ea180c0d6a3ac4c0c4f213751e0d1fdf5c147795c -size 672862 +oid sha256:48243c55d9f774afa267949bad5bbc25004dd96da63f6ee97ddc475eaae81ff1 +size 672910 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a index fab19360c6..071af899d1 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5674609108b2f472a6df5096d54fc3a2c0ea2ea713f54471854117c65fd9fcd8 -size 646144 +oid sha256:90bad3fbc7a1c0a57c3c3f4758fc3b2d8533117877edd1ac15cb07e594ce897b +size 646192 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a index f11c33d081..0799ce066a 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:745aadcc30e2a5c05d9af07a557bbd513be202a1ef257d99f8af6a21074fcfa7 -size 671178 +oid sha256:9fe8d44addd4a97efe0c5c55565721266d9642ec285f53c508d08ad9020d3bc6 +size 671226 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a index 1a2411330f..08981c1a5d 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d47257388b31e3e44d520928f6b06e91d1112125256c4315450ce2d5818cc817 -size 644460 +oid sha256:b24a8a95cb06c55e44b9c990ca1cbed3cb9af6a8bbf3695347c2990221febebb +size 644508 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index 7df14cc9e0..1fc4ac492b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3000ad7cf51f1b4f432408187d437ebd3bbd937848a19fa93499eb2200ef0586 -size 666834 +oid sha256:303e894f0c2fdb0a3f8dc59b1e325c485c3c576c96e9966b0c172cbc7bb4f678 +size 666882 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a index 0e6cdcc856..e1d98e8b55 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9bd9f1cf0d4e7515d3a1c78586e0d1194b1ce46809d4c26557e3d5287cd41937 -size 854626 +oid sha256:d013c8859f755a5984cf1d5d42d2fa98d0e84501a2138635bb9d7a905714d5d0 +size 854670 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a index 22d43fdd76..235ab31b87 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1594bb61062cacc80b0219c66db5db3d3abf63ab73d40bcf64bf77ee43ffe813 -size 828868 +oid sha256:f5a4a1c86dd06c1878414b875d2525e3b3319e96d4c25b18e4aae3e98cd7a3cf +size 828912 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index 35e1d4a0b4..a0a6631757 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cf4291b912d9308572924b864317c3c50ac087da29f5ba5e3537f19a8c4d24ec -size 640168 +oid sha256:d7ea066ceefd3e8d19f2f7856fd0c727cff197ab15dc92c6fec23c6287ea1ef4 +size 640216 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a index 75c67def4a..85b919851f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9048d73d8453a073d151872540f8e8fea45860db7979cfbbdc408ba092cb9c55 -size 691572 +oid sha256:b3de1f5db62cdb87facd4f4a0c0e3d60e6120c65cecbb5a6eb116434f1b55894 +size 691620 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a index ef72e73652..1d644fa4f2 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:88e099b83739be11275f9f949f16204cee2dd9ad48a5bc31fb6665becc2da25a -size 877546 +oid sha256:7cc782825bebb01b1e7cae7b39ea378b988050a682ca65b23f5ad36e3e391320 +size 877594 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a index 3abf1ddd3e..9d09b2fdf6 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aaacf48ae09f0b744aed06fc9cb2c27233f02dfc4a61602c8823a3837b566917 -size 851068 +oid sha256:6de8986eeb469b1d7c78306fa9d198775b31cf7f653fef8c83b52b90d4204bf0 +size 851116 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a index 1ee0160e40..1c484ad1a8 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1bf59896742792a63fb7daf0b5b3074225e144c9344e89d1b890b623e68da909 -size 664326 +oid sha256:ed34d37c8d1412736192dfd006c1e4116bfb8c4773cfdfd076481f27a4fce569 +size 664374 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index add1b93da5..a80ad255b7 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:32f14ce288f39b0355c1aa660e87a80933a4f90d2c190ac3136d47e3a15b0247 -size 683676 +oid sha256:ca860f1381dea716972745cdf69525af6ff1de9c1175d1138f677ec3dd6d3d93 +size 683724 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a index 8316f0688b..da422b0ea6 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2d33dfdfb9c1cec77a762774e9509a306446b9c08a94aea4da422295782270f9 -size 873008 +oid sha256:796b6ed495ba4b1c39e0323f494cc31b22976e6696d3b0b4eb4ca61dd781043a +size 873052 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 24ce28b687..77bb0c0330 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fc0589b6f2e286998d4d525ed5fe143f039df141f543bb86d7efbdeb88f92379 -size 846674 +oid sha256:d8c8c933e585daf29417749da5ee18e5ef77fd4c196ba12ab8a0d7059d3cf2e4 +size 846718 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index f014c0075f..215c14b76b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ad21b082de39b807e7a8066638c520979553aa4bb0f4faa5a3d8429f8290816d -size 656586 +oid sha256:8ee64a40caf57716e49f28110275630302eeb00250dfd5d986263c7f4a530426 +size 656634 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a index 1f0b677faf..1e11412510 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6e91e19fc57ebca599bffae761b87ba7cfdd684a07030c8eced514c9c0a04a8e -size 684342 +oid sha256:0dd87c81dd63f1f0cdd4314e1c57490c8c8a8c274c9186d0c9bfe2a4e978efc6 +size 684386 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a index db4feb30fc..3bf685074b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cb0824ba42d358775d315d751250e605286fd8e04b5976e9174e2216fb646b05 -size 871304 +oid sha256:16e751e164da9661225a08239b9fd8b62df0c043bde66536a734c8fd9eaeff70 +size 871348 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a index 1a37d0dee9..f1942b36f4 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ace842f056624f429e9dc1e88b6b9bde309ccae24cc64bfe390fdc8d33e8e966 -size 844934 +oid sha256:2522fcb7c67f8656254fd4138de52d6d8c7a0aa21a3d859a75de6f70845b6adc +size 844978 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a index 50caddb0c8..d6ed0e2e71 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d33c01b380eced951a64869472161da45c0597b1660d3da577916adc50a6e7e9 -size 657216 +oid sha256:c5b4e4a1e98a20dd60d646821cf00e1c0310bad3804e049d6d45158d4ddbd726 +size 657260 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a index 4808e837a6..2a186a3ec7 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a792e2de32491b9de359aea8f2b6be24a82f31148eac499f0bbd525f6a2318fe -size 681612 +oid sha256:2cd5cdde0fb1da9fa048742ca7ecf8a6033ebae32444f7708add678be17e6b92 +size 681660 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a index a4be30e9be..3db6e432ec 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3c948d5e2f3849027f9a9179b3825c509957ec4abdd98bc18e9ae179948c8fff -size 654510 +oid sha256:804399823c204876a5e42082a6704abade2f1d24f80d14eb123560a230f7f1f6 +size 654558 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a index cfa9841c31..6ef56b301f 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f83e43a16e4d56018d19e9eca79499d3796de65e88c1051a50a953ee267d4718 -size 686024 +oid sha256:372152e242bdddcb1785715c72a50ecdd6050031779ae83603e45c90b39f6c0b +size 686072 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a index 8b4147b90d..835769690b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b96f4095eaed7460c02ba2928208cc58b14a0155ad9935c7906b5be97089c6df -size 658882 +oid sha256:3dd89e8cae45e3c2fc0a1d9e6cbe1d71f00ba2068323ebf17be55c74a9c0e6ec +size 658930 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a index 00615599bb..3f38a6c34b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a600ab9833386731ae999444c82edbe7f6ffbf7fbc85bdf34b57e44d4d20bc87 -size 684342 +oid sha256:ddccec751340fda4099180339724b098f4e6050a6587a25c08eafa3e7af54541 +size 684390 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a index 2cdb4e9e7c..5386fa83c5 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:31a664dd8d010482f18f494876198d64dc4f5a03d6accb9b96d8775ff79d0ba0 -size 657200 +oid sha256:16de4f90b9c2ce8b5f738d8224bd553a782edfd04e55ef64fc27ec385e79eda7 +size 657248 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a index 0953ef49cd..f1e2d44869 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cb76e33c1fc3aaab88db90b20a7726f5f71ca9be73dc3c3b5328410855e73082 -size 679996 +oid sha256:04c603cb301aedb28990d5e64bab061c7ec462cbf21dfef134cdbb248fd20947 +size 680044 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a index 2321847f07..87295507f4 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d53eded378e3d97eabd9dcf38961b62558b1fadb2b9440263ea38ad6cdaffc8b -size 869288 +oid sha256:33309d08065f74a543da6342d82c24a20df4dc2a859f29c69c80bbdfb4f43fb9 +size 869332 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a index bb30673798..3e030ddc53 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ea8eddd6cc6a855b03afe5b5c486e7745ac5f0b1d3160b0f1e4cdf507d19f5fa -size 842974 +oid sha256:0b58867c044ca12711c1260e02887f9e3cee3d10b5749d26a17104aedbbab64b +size 843018 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index cb5488a72d..cd8d4f40b9 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94044b09b279328ec4cdf0247b00554b0689b1ae1ae10948be93522f2bf68218 -size 652906 +oid sha256:242b45f57c90246c967b375a98720fb073fc9d291c9a4b2b7fce678ed15ff867 +size 652954 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index ac7af0dce3..0012c88ef3 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:08cb5cf8799a23e084616d6d3352066c0ed6303504e26994757931bbd8ee253b +oid sha256:6838ab9401a0072181d66db59205a15905ba1c7bfcbd2e0ef62f21daeb3d6b99 size 19954 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a index a1a1d4aac1..0e072364d8 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:82b5c2c5a985d3f9ab7d5871c0a773e0186a03c60b76405db110549a8a06f0e8 +oid sha256:2928eb2db565b641420c9c9d179e128c2f048354c03bf31d52f775a047f78cce size 19954 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index 5080e1dcd1..51f69e27c6 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6b4989f9168b40795f930290631914990c0d3062cb0921827ba0c89408f41ff4 +oid sha256:3d58c439f3058fbf960663f993a4683fe2e15e2566f071008d8248cddaceefc6 size 19782 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index fdcec89ce1..7b560f3a8d 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ecfed60af320c077e14fac6b31b66165dade0396d96d1c4db28d13fb6e2deed0 +oid sha256:c4af6697d593a9d597f18c48715ed30072ae1b3ca5a1226ff38f0e2a06389b49 size 19634 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a index f2d95c02c4..2c1a84aa60 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7f5c41d3c731323ab75b1a49f78169914c19b91c8aad38466540918cbb25ad0a +oid sha256:7e305023250f87673aafb8054fbe0649407dda7729a91eda8fec7d1f08990138 size 19786 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a index 2c3019d013..a0afd33ef1 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:37904677085483d44ef494e276e8dc6f217fa7613620651002c6e07db40eb0bd +oid sha256:6451146d5d88f3ff0effff91f651cfbd99e84622682d2c825fa96da36184c2d0 size 19786 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a index 99a5db8369..9c549faf3d 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:68156e3deaa7eb3ff0bb9271ccfaeb072530f7311e95e426f0a335a4647c373a +oid sha256:15fe56438377ece59ea6f36e07dd5a243f7d17cb37cd7a8b14afbda22ee5cd45 size 19614 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index 76e06caf2b..bb9838f66b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a5e0e9021a418cd0a5c6f9228c653b3f5a914a61e8789fd1eb7401e163976be8 +oid sha256:663289dd6c8a71f4e4ba352161875abbef6b3a4e81068c84f46330ff20733fef size 19466 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a index 382844eb13..8c6e724423 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5c6b38acdaa96ded510773f20be8833ea328ce62de25fbe83aff816bb9ba869a +oid sha256:18e0625a78987b7153f4eab9e7d6516fd384d7f74dd083c05921b4f37bf8cef9 size 79484 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a index 382844eb13..8c6e724423 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5c6b38acdaa96ded510773f20be8833ea328ce62de25fbe83aff816bb9ba869a +oid sha256:18e0625a78987b7153f4eab9e7d6516fd384d7f74dd083c05921b4f37bf8cef9 size 79484 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a index 2b047636ee..faf74f2672 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c749c036b88c8cf1bd13565a43f0f929c6c906da39a1e97b3bd9de16ce7586d1 +oid sha256:62703e470a30019f5ddcde59e986af46e39e2e0c8f4377354c27c1f42b22fb2f size 79124 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a index 2b047636ee..0f5627294e 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c749c036b88c8cf1bd13565a43f0f929c6c906da39a1e97b3bd9de16ce7586d1 +oid sha256:d233d3d64c9f60958e4ad4d80a769e46a10366dd4116fbbedb0798eac4667d39 size 79124 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a index 924cc36aac..23df4448c4 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f82d53846eccb2340b4ec30906ca2335c0c68b6e947d4155abf12a78b8049b0a +oid sha256:aacfd194171faef1a38cc67fa3620e8ea8dddd83fb2cf65054143c00d1784897 size 15316 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a index 68ebc2cc2c..23df4448c4 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9a59b5d6996bbc680c8ba3f24ff76dec30a55e2703ad8933c97c61246c3c0b5f +oid sha256:aacfd194171faef1a38cc67fa3620e8ea8dddd83fb2cf65054143c00d1784897 size 15316 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a index d4bf4114f9..752ba9e335 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:24b8cf92506eca8d6fc5fb4d298e802d5329a540088956fb10db26cc6526a959 +oid sha256:aefb70a5695af654c6c61d3af45f7b423baaedf92d67dbc1ecdee0c0899e1f3f size 12968 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index d4bf4114f9..752ba9e335 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:24b8cf92506eca8d6fc5fb4d298e802d5329a540088956fb10db26cc6526a959 +oid sha256:aefb70a5695af654c6c61d3af45f7b423baaedf92d67dbc1ecdee0c0899e1f3f size 12968 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a index 448e08fd5d..e8fe10deaf 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6b6f17e8ff46c22c1e4a1d2cb0f19f45d2780ca7d1bfaab206ca7f74184d1ca +oid sha256:35d8c871cfd646e03347e7c4ff5e0fbab2768bdddd4e2001f9a36f93c7e3395e size 3626 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a index 448e08fd5d..e8fe10deaf 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6b6f17e8ff46c22c1e4a1d2cb0f19f45d2780ca7d1bfaab206ca7f74184d1ca +oid sha256:35d8c871cfd646e03347e7c4ff5e0fbab2768bdddd4e2001f9a36f93c7e3395e size 3626 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a index 448e08fd5d..e8fe10deaf 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6b6f17e8ff46c22c1e4a1d2cb0f19f45d2780ca7d1bfaab206ca7f74184d1ca +oid sha256:35d8c871cfd646e03347e7c4ff5e0fbab2768bdddd4e2001f9a36f93c7e3395e size 3626 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 448e08fd5d..e8fe10deaf 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6b6f17e8ff46c22c1e4a1d2cb0f19f45d2780ca7d1bfaab206ca7f74184d1ca +oid sha256:35d8c871cfd646e03347e7c4ff5e0fbab2768bdddd4e2001f9a36f93c7e3395e size 3626 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release/libzigbee-zll.a index c3a817642f..7a48d83e9b 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d1093da54875064d9eec6df48fa0b93a672816644114904561700badc8c20190 -size 51726 +oid sha256:c1ec9cb6b65c7f9f7a692bd647186584ea41a51bfd30a9fe0f524788b425c669 +size 51794 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a index 23babbf963..d1143ae9ba 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cb3b8416115c9538935f799a8842f2ab8cfda06b26caf24bc77de48c08c2dd91 -size 51726 +oid sha256:c39565f6a57067fe0f7ee71828cfda1da4643bd16a0130e132ae91c82b9294b1 +size 51794 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a index e803f59359..4809d03585 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b18e8334c679a3b1b299e765b76a48a57fb400eee3a4ba3707953841a23b2e43 -size 51046 +oid sha256:af4d2ba46c5b17418949d84f6cad1aeced22a88acc0f47d5fca2220f1acb7f53 +size 51086 diff --git a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a index 2ee7ff767b..4809d03585 100644 --- a/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5fe72cf1a08d8ffb5378e2796fff11e66934c0b0336937923245670b0e22fba8 -size 51046 +oid sha256:af4d2ba46c5b17418949d84f6cad1aeced22a88acc0f47d5fca2220f1acb7f53 +size 51086 diff --git a/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release/libncp-cbke-library.a index c698e55802..8a8705b404 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:444185937ad76fdce8598d8115e413dda1751cfb69aca3f8a91007b74d836b3f -size 45014 +oid sha256:7126da34650412d849aa318b16081026a6fe37addd9f0ea70db75d823b79f229 +size 45066 diff --git a/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index c698e55802..8a8705b404 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:444185937ad76fdce8598d8115e413dda1751cfb69aca3f8a91007b74d836b3f -size 45014 +oid sha256:7126da34650412d849aa318b16081026a6fe37addd9f0ea70db75d823b79f229 +size 45066 diff --git a/protocol/zigbee/build/gcc/i386/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/i386/ncp-gp-library/release/libncp-gp-library.a index f118f9f3a7..b3c03ca602 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1b607bed11f59204ca1104e9b1942c21cb921f0fe29b881bc860ac39dfe2df2a -size 24866 +oid sha256:5b92a644bbd252f4f8ff889807598be7056aabf74a56782bce22437329423e1e +size 24918 diff --git a/protocol/zigbee/build/gcc/i386/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/i386/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index f118f9f3a7..b3c03ca602 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1b607bed11f59204ca1104e9b1942c21cb921f0fe29b881bc860ac39dfe2df2a -size 24866 +oid sha256:5b92a644bbd252f4f8ff889807598be7056aabf74a56782bce22437329423e1e +size 24918 diff --git a/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release/libncp-mfglib-library.a index 512eb2e157..8be051caf6 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:23ec5feae8dd2f92fc9e37e01b21a72a39edcc4990da4034888e21e4e2308e97 -size 27540 +oid sha256:438880ff76d5a470bce436fc88dda40947a2632b17a00aa2c1d583344654fbfe +size 27592 diff --git a/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index 512eb2e157..8be051caf6 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:23ec5feae8dd2f92fc9e37e01b21a72a39edcc4990da4034888e21e4e2308e97 -size 27540 +oid sha256:438880ff76d5a470bce436fc88dda40947a2632b17a00aa2c1d583344654fbfe +size 27592 diff --git a/protocol/zigbee/build/gcc/i386/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/i386/ncp-pro-library/release/libncp-pro-library.a index 8ab379be85..b4205ce8ef 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f327d9a016f88b3d61d736845a8c2f6ad741a61eb71db30d88e8e614514f849d -size 250450 +oid sha256:66276ba5d4b8566c78b8d579cb18c7cf2d0f1fa53ff8f7012f20a6d5d119d5a2 +size 250658 diff --git a/protocol/zigbee/build/gcc/i386/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/i386/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index 03e01c88d7..bc4f042e35 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:acaacaac567295add927867564937c05607a16d98c79a7e642a699b898bbc569 -size 247230 +oid sha256:a16f718ec785f189e513d3d0728603e0fd3669be37d7a8c471a828af7c09568c +size 247438 diff --git a/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release/libncp-source-route-library.a index bd08e612af..3cdc56b90e 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1fae95abff276ff9dc23fc511a2eb297dd8caca086155e7b55c8d3746447b0d0 -size 29062 +oid sha256:cebf0cfb5f26d78861e674fbf46a68b05acb95cca87798f0cc3bdd25824e4dba +size 29114 diff --git a/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index bd08e612af..3cdc56b90e 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1fae95abff276ff9dc23fc511a2eb297dd8caca086155e7b55c8d3746447b0d0 -size 29062 +oid sha256:cebf0cfb5f26d78861e674fbf46a68b05acb95cca87798f0cc3bdd25824e4dba +size 29114 diff --git a/protocol/zigbee/build/gcc/i386/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/i386/ncp-zll-library/release/libncp-zll-library.a index 37528036e3..31e9399152 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:21fb0a41076d00dfa4cee54aaf717d2177596a171f8d0dba4963da7951d62dd5 -size 33912 +oid sha256:50c043541b1363542cd0ae1817ccc51718ad9491f27df0e75e9c604e4ce49b79 +size 33964 diff --git a/protocol/zigbee/build/gcc/i386/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/i386/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 37528036e3..31e9399152 100644 --- a/protocol/zigbee/build/gcc/i386/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/i386/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:21fb0a41076d00dfa4cee54aaf717d2177596a171f8d0dba4963da7951d62dd5 -size 33912 +oid sha256:50c043541b1363542cd0ae1817ccc51718ad9491f27df0e75e9c604e4ce49b79 +size 33964 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/i386/zigbee-gp/release/libzigbee-gp.a index 47c5dbb5bd..23e22e0d49 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b6811c41fad7308a8b108fafa1693596551111a9be817f012dcd17f7d4dffe3c +oid sha256:e7d9558f958b083dde42098bf8a7481393d1d29a8abee544180823355454baf0 size 115518 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/i386/zigbee-gp/release_singlenetwork/libzigbee-gp.a index ec1392235a..a50a7f45f2 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:195e6f77d6009c6ad9cd10f1b174e75171dbc6316bed8c59069acf6e6eefc94a +oid sha256:8813332258a2438d3b537089f2e398070cd631ebc27deed0f04dccf419c683c0 size 114502 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/i386/zigbee-multi-network/release/libzigbee-multi-network.a index b1fa49268a..19f0143a48 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dae6d3e2cd7d7163575b12c8ea759e6e7b1e8b934bed2f5c4700aea442577199 +oid sha256:1aaabeb1d6ed433aeba4ea00a7a1ce09c69a88bda44147b10395281ebe271fa9 size 40830 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index fe8d438fa4..a2e633c1c7 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3becc87ab379e87f96941865aea0e166bc91700e207f07aee35ce681cd252fb2 -size 216666 +oid sha256:1d66aee1751c9af16775be21bd9742ad06679bbdedc7304136a0d5bfeb0c25a0 +size 217272 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index 2fa035fc0e..916aef1d17 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:15e601de7875a07ecaec1ee7e0bdd299d6251d46e123326519ba8249576f169f -size 210758 +oid sha256:4a91a07f19bf0db37d9b7b15e6ccfb7c501124490e6b61aac1371761c5626c40 +size 211368 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 75f4f59930..839d9c28c2 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:398ba213a5bc42206a69a687d338e556c7e12a740e57a60db2153c14a035df00 -size 1773932 +oid sha256:635b98ed501d522447ddfdf63e95a7b6b58e01b397e925f61463eff21cdb29d6 +size 1773924 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index 0d5cfd06f8..2c2861efdd 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e42c9c419b473077147034f5e7891e0801d625e1d7dc14397740f2cdd5cec2d1 -size 1657654 +oid sha256:3f3c2dcf4f6d846fa780f27d1f69e296553313cf79ecc4207d598c85a78b6d2a +size 1657646 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index 25184def4e..cc71e61486 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4967eaff20f4b8d7005e096390cc360a9988d191fb054a769f3b94cc3ca2e14b -size 1951438 +oid sha256:26c830c87a118d951fa002934a379f26af61c42b6b9e981eb3baf76704ca1136 +size 1951506 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index 0f65acfd22..791502b13e 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:975db455f7cfea278200b8c11655bc293f9ca93ffc54f4e821e1302c7906f39e -size 1817088 +oid sha256:7d6f7935454cc1d053d7bfc8683155e7ac067a27f66f5706b728c020dfe2b41e +size 1817160 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index 5ec0c6a433..406a01b8b8 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b40dbabc6efa1faff7bec11d27638e04edec46cb3a50d6ca517c92d23e0af114 -size 2001804 +oid sha256:7dc12118ba97cae29e7718756838afbe3288c37eb85c2a61c53f842b36cf2dba +size 2001872 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 4cce08187f..04dcd90968 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4f283a7f1f0f4975e0693fc3d311b71ede47528bfe2efd0ebacdab40ec40752f -size 1859922 +oid sha256:cf035081050bd34518d2661a09cd5afacf5bd2e983aae4ce083d72797bef8ef8 +size 1859994 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release/libzigbee-pro-stack.a index de11fe48bd..0d46c229e2 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b8363fc2095c77d1b92ac6d1bb2c6561c6ff0c04733186abada9892282283b37 -size 1998488 +oid sha256:fb6dad99328a7a30b070ef4a216c95fcdf91368ba9a407f7effb8a8e096365e2 +size 1998556 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index 2632520431..6051d18f8a 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cbc1cd8d8cf468a9f75bc731cd387bc806d760ef07c7a6b1b311c4a56b4d1e19 -size 1857082 +oid sha256:29e65f823ddf209c48e909f86cd83a67a1cd5a8343e7e78983815cf90932efaa +size 1857154 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index bf13692819..3f6423ea0a 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:670c9ff0cc83acb6104e262b26ef468abdeedb84e8b6f81380e9b27e68a9653e +oid sha256:ca16c006185bb0ffc4c664a7c265460542319db99badca972781633faf1fdb40 size 64446 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index 7ef155724e..ff9bfaebed 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:09c930e7fb645835de32da93a75c6780f3e3fb17be346766f00580d3a9c5087d +oid sha256:f9d1e406fd6bd3e1275a0a72f380789baa81b9f2e88768dc2e1be31992e39b91 size 61486 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release/libzigbee-r22-support.a index 9f58f6deb8..c5d0f5cd83 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:78c8e04b151f82186b886f0977103bb198ccc304ed7997459e89c58a6ec5fa05 +oid sha256:0d055800b8ab14b24d956b45b58442f3345e6021e9bf5a57cb957c60b2d71ae1 size 64326 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index cb63597b42..e8d5b85065 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f9e92138cc6d52f535f0374b49c9130e3044ab9dc98db8be00cd1b91142fb785 +oid sha256:62dc120fd48e6545bce17b8086ba363082e6243e36160006ffcfbf4adbbb79e3 size 61366 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/i386/zigbee-source-route/release/libzigbee-source-route.a index 8dac4dc009..8790f31d1c 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:55de2c5cda4ee148f6c44bbd610c2f55bf9ebc1e040c85db77a019c47a598da2 +oid sha256:843ed86c9006f5eff327a1fcc3fc5e7268679abdc13671d82aecfbced5ea7936 size 36508 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/i386/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index 93a08b1889..4f44079d88 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a183b615270b9f389bbc77f4764bc6ee08eec38fd2cf9f185e153533b505a539 +oid sha256:3ada9a3a8dd6109aa908521d388aa86a07e369fdd012f118c1485fffe23942eb size 31428 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/i386/zigbee-xncp/release/libzigbee-xncp.a index 9813ca7ee2..adcd6da6da 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0a6721919c3efe8c5b6f0ad0ff6dbfdedc2cc668823141f9b64a03bd28543022 -size 26502 +oid sha256:83cb20a4c7be47210bdb6adb406095022ee376c0deda1cc7a4d0921aaad1f774 +size 26554 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/i386/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 9813ca7ee2..adcd6da6da 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0a6721919c3efe8c5b6f0ad0ff6dbfdedc2cc668823141f9b64a03bd28543022 -size 26502 +oid sha256:83cb20a4c7be47210bdb6adb406095022ee376c0deda1cc7a4d0921aaad1f774 +size 26554 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/i386/zigbee-zll/release/libzigbee-zll.a index 6e6d51be13..20350ae5ea 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c983e5fe9b63c90d3818f882fd8301e4041931ae56a3d0cbff5c97c3967216e4 -size 140216 +oid sha256:50d9a98b8c2d12e73b36212d204bebf5ff5bb5a951a884132bde2c30a9c5c422 +size 140332 diff --git a/protocol/zigbee/build/gcc/i386/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/i386/zigbee-zll/release_singlenetwork/libzigbee-zll.a index d024651af6..1ab4b7c9e4 100644 --- a/protocol/zigbee/build/gcc/i386/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/i386/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4f1fca4c589822372b6626b13ec955394b5ce1f061f121a4489135c2ba6df0e8 -size 136796 +oid sha256:c0d1d9ab5f99903227b4320f134d5b1c66c415e259f933eb2a993276ac1e6678 +size 136856 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release/libncp-cbke-library.a index c057404dea..2dc8075f00 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:106fc984145260a5317a35082a9cc536829f18be64613e27949cde5fe20544c5 -size 58170 +oid sha256:5c4ee6ffddbfc1c18d4959b7cb38395beebc78ab5bde7cd581233fb7ebe29079 +size 58242 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index c057404dea..2dc8075f00 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:106fc984145260a5317a35082a9cc536829f18be64613e27949cde5fe20544c5 -size 58170 +oid sha256:5c4ee6ffddbfc1c18d4959b7cb38395beebc78ab5bde7cd581233fb7ebe29079 +size 58242 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release/libncp-gp-library.a index f9faccafda..531afb9cf2 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:026741cc4659450ab8b21a3cb70883d3aef1cdb82fd20915bc073844604fe479 -size 31784 +oid sha256:609e23f42646f77bb4c433c200f6737f5ab8655c37091acd440f792efeb33f05 +size 31848 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index f9faccafda..531afb9cf2 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:026741cc4659450ab8b21a3cb70883d3aef1cdb82fd20915bc073844604fe479 -size 31784 +oid sha256:609e23f42646f77bb4c433c200f6737f5ab8655c37091acd440f792efeb33f05 +size 31848 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release/libncp-mfglib-library.a index 6025f62e69..3e1889b59e 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bfa3d4c6c50ba2b028d1151e5de3d4da5f0f6415e28d8784beced25d20f20f43 -size 35256 +oid sha256:6191c9e7e66e21ee3ffe5156244cb44bacf6732b574298b877e9ac9f95f9ec32 +size 35320 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index 6025f62e69..3e1889b59e 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bfa3d4c6c50ba2b028d1151e5de3d4da5f0f6415e28d8784beced25d20f20f43 -size 35256 +oid sha256:6191c9e7e66e21ee3ffe5156244cb44bacf6732b574298b877e9ac9f95f9ec32 +size 35320 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release/libncp-pro-library.a index f712e81732..0b1e6c7e32 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:76f9fbf80173296160cdf8dc0afec867cc23d5ed0b83034bdb4ea9be74fb8f67 -size 322586 +oid sha256:6467509f647f93b687c8d35e7cf2c97a27417956a5d40c621a78862b70ce44b3 +size 322850 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index e890d60309..702f40ec11 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c689396aefb17e9eab0cfcc4ccadcb713aca2294e0ae4da5f6cebef1976b7c1d -size 317898 +oid sha256:3b73d89778209d91bf3ddb623a9e9ea71b250bc8a348d1f02d1ed481ff68741c +size 318170 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release/libncp-source-route-library.a index f13192cbbc..fbe99c9daf 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c4893c027d755451e56f097b766fd67eca33a99d9706797486feb38099233561 -size 36718 +oid sha256:343754e7d84d4986c944ce3f77abff5d93de8fd9aacf450dec4db7737276dfea +size 36782 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index f13192cbbc..fbe99c9daf 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c4893c027d755451e56f097b766fd67eca33a99d9706797486feb38099233561 -size 36718 +oid sha256:343754e7d84d4986c944ce3f77abff5d93de8fd9aacf450dec4db7737276dfea +size 36782 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release/libncp-zll-library.a index d8573126dd..d4f7a1353f 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f91a535cad9c3ded6a605efdac02ec220a8d174a809e702569b7916069374e42 -size 43496 +oid sha256:27b4d75169da7380dd2328a0e33beadb30d109e041ac57050afa3682d3873861 +size 43568 diff --git a/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index d8573126dd..d4f7a1353f 100644 --- a/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/gcc/x86-64/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f91a535cad9c3ded6a605efdac02ec220a8d174a809e702569b7916069374e42 -size 43496 +oid sha256:27b4d75169da7380dd2328a0e33beadb30d109e041ac57050afa3682d3873861 +size 43568 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release/libzigbee-gp.a index 13983c0409..de5d6950f0 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f895bbe84fb53744f9513d6c313872145ee49dbf1a679b9c86570405729e49d2 +oid sha256:76b2a9d2e3c272a5cfb563cafa13b8c8d0681242a15ddd4e37d6c9e626f61867 size 148874 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release_singlenetwork/libzigbee-gp.a index 47f7cdd900..5b4db32ce0 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:098e25cf1c38017e30128f7ddb452e4f630449b9360a89d4c80e460099a557c6 +oid sha256:a89db211748a35abd65e61b46f142e6d2af5f4adcf2bafc8d1d8144275615b04 size 147498 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/gcc/x86-64/zigbee-multi-network/release/libzigbee-multi-network.a index 58252ba467..dde195f934 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cfcc62fc2df5a2427e492ad37a1b76c2bdd89f8fe34fb8c2b23083e9a874bdd5 +oid sha256:362a32a35a8ce7a77e567082569c62aa3427839c972380269915806984546abe size 53844 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index d55571d1d3..aef2ffc9bc 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3aba299ef3b4cb098b237666f1555dbe7d734beacbb0528a8696accbade1a0cf -size 288396 +oid sha256:c6a1c23f212eeb32742b31b74f0eb2ed66c34b4fd8a958dd1d8d4bdc15a86026 +size 289166 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index 842b37c598..a8222a279f 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:93c1c455cea964504143805df17bd5c838afd284286128a44f4c8d0e3ac48911 -size 280164 +oid sha256:3763aa5d2e17ad11c9419c4f2e435d6f5e5c72cbfe48d8750dcb3c9e934c6bc4 +size 280934 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 2f5e569fd0..3b371e9a3a 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f8a3619ffb49602b3ec8e7c005dd6ca2ca5c66130ff6904f412f71c4b7e7a60 -size 2311474 +oid sha256:14ef9d6cd4951d3502d81841c5bf0e2f33a09930e5853c31204e3edc125e23a6 +size 2311466 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index 363ad50367..74b1a550dc 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:575678c3be5329ee560c1e4fa372451decea4c11062f8d6f6c7a17acb6212f64 -size 2139090 +oid sha256:cb0e906343dba965d19d015f12674334a8d5e05360965a1889b937c8375f83e7 +size 2139082 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index 2f58e0cae3..6ad35df97a 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:356756583d2ca0953f2657551f5b5b47dd62d3d10f189e45a1f26f5bd0e010d5 -size 2543374 +oid sha256:55478ae6349ae45028e64c632c535c14079a2f0aa9b039232ed73cb215aaa8bf +size 2543494 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index 8b4dcb5ed3..9fe36f5ac2 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:52d5a6bd435d29dd0300878401c43dd7aa85ae6f653697b7f77e88dd9c741e6f -size 2344296 +oid sha256:c6eadd6c25cb2248079c7f1a992cee17c9f3ca4e3e93fbaa28b58c3dea75aa2d +size 2344416 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index 53e9babb16..e9cce72f24 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:138da8e533c29c5de9a0532db88923fd7a08e670fd65b20bb61ef674a7ace0be -size 2616708 +oid sha256:0063d5a02b37226e8ca15e040d079db9fdb55d63436cf52e2afec31c5dabf1e1 +size 2616828 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 0c959c5645..d89c1cadd1 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cddfc8a9868b07166bf13818375f017a2b0be9b153ca0717c30aa62752ea4b0c -size 2402630 +oid sha256:46ec1bd8b10ef1f65432b2888070d736b4b4fa35d4829e6ec1da270b14435b02 +size 2402742 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release/libzigbee-pro-stack.a index 3706edbff3..d7ed422ca7 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f6556ad78a8815078346741e279b231520d374109672490cd84d7c43046c99f2 -size 2612136 +oid sha256:3204b207b90a421890e0749655dd7c7be86f3d518131fa1b928aba139a4920e7 +size 2612256 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index ea46360be2..8ce52bfa15 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fb2076a6697135e27887af4ef773c1c609ddd0110d28feb0b6badb23efd2afba -size 2398642 +oid sha256:f90c0870ca9aee93338dac765190181a7043033dd02994565bbfd2a6b7ba43b8 +size 2398762 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index dc97ed4321..f01e9e8938 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:073304b2f85a0342cdda545683938f4bbc9cd63d311a32f2b9f7e00990dbea50 +oid sha256:bc49f40831324d4af5c4b2d4f183503ebbdc0991d2c5f0ba033aa45092ccbd7a size 83376 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index 9a9c06ce55..e3e14978cc 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:471818cf9f4e44aea56bcac6c23e020a63a7ad62551c26f8f337c34a2e61faf3 +oid sha256:07c820b3eea5ef9abb899061b8a57fe9f057e805b991c03c3a2789f326da4f98 size 79096 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release/libzigbee-r22-support.a index cb3979bd67..9f396501a2 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c8dede49b18ebe3e0e27b798b4b01e5126d70f75e140cd8a1136f0a0d5f7bc6c +oid sha256:3d26b6796260a6eba2b0cc34006e4d4d68353c1d16a0e64f1b727f6cc5b51577 size 83212 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index 037d4deb96..b5769394e6 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:489f55c9c767b0a94ffca12716cf5c4fb9e01febaa69cfad63a845aaf4cafa82 +oid sha256:f39a7c2f002f21741f4afcc76a396dfc49ecde48169be945b707d95780e760d6 size 78932 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release/libzigbee-source-route.a index 2bea5b3375..18a130e90a 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d84cc459bb1fc4c5ee2b9beb8a2df3450c95329fdc3e5b1324e43be129605466 +oid sha256:962e4eb78a9b5fb3e80974f0409ab3ab123b3915fbb7b236e5eb5ba0ca174816 size 47736 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index 8e99be20b0..172cf661c9 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d077d2906eec270925b18c7b8aaae40acc02a4a73be0fdbff6b4eb7d2d19e482 +oid sha256:8a2ab622eeee220066bdc5bcaa64a4bfccc2373fe2ef57b4ba766fd92ededfd6 size 39352 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release/libzigbee-xncp.a index 39455cabaf..2bb603eb56 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fa10b6c7c185f392abe477e86c2e130955dc38bd3c3a9c6ee91559ddb632ee36 -size 34146 +oid sha256:1c08ed13c4951b1e215a57d4642e8349469e9935767e2e17c93de0dd3d399cce +size 34210 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 39455cabaf..2bb603eb56 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fa10b6c7c185f392abe477e86c2e130955dc38bd3c3a9c6ee91559ddb632ee36 -size 34146 +oid sha256:1c08ed13c4951b1e215a57d4642e8349469e9935767e2e17c93de0dd3d399cce +size 34210 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release/libzigbee-zll.a index 32a53f8fe8..665a749b7c 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:720b9f09385f36b1e4bc78d34289aa646cc2f89d531e8e557a26b241f3766bfe -size 180722 +oid sha256:e2ec89ce1f147dc487c290b691e0ff3d4dc5f07e5bc40d4606bebfcb508bf612 +size 180898 diff --git a/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release_singlenetwork/libzigbee-zll.a index 963d0968c9..7616a2be41 100644 --- a/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/gcc/x86-64/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ba0ca460cff13165a22873da1caa20f6e170b6c6a927d1d81fc7682a5d9be77f -size 175690 +oid sha256:d53fe8725ab609054993e3865d228b3d244844a4f213951c495658217e98a25b +size 175810 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a index 0684274771..a78047a038 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8bbeee434794257fa24d49d92b4911bfcfb41ae838fa6cc22d1afe5a3a57cf14 +oid sha256:da5055e1776f97b8c6fcee868536018faa2d2817095231fe46c20b4c7fd84a91 size 19864 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a index 915a06692e..4dd977d3d3 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:efbcf4b4cb3013eeda30dc49557edc8e5aaf3969b9a2cc935d6fc515f12e605e +oid sha256:1efbce2a6cbbcd6a96329721bc91dfbc29ade1c00e95c4ea5ea770e8f5159ed7 size 21104 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a index afb3f2d0d1..7dd35d59e2 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_dualrail_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a18da5caa3368d308a232786451b5b35120111b5f79fa0f3f25e41838c8c1367 +oid sha256:55b61bf3a3b3ce7b2ec5c899a731044c596494d4387d8427591b0fcb2e5d048f size 21180 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index 60d7143609..cbdb01b73e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:55411bfbd9110ec2244628e342cc816546e9b488c535fa95f85351c6dd55a5ef +oid sha256:6dd899fbac773aaf61a7dca5b4b3b919897758286bcfe009a2f6e746881659ec size 19942 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection/libncp-cbke-library.a index 9523b1ecbc..58e44d62ae 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4b88082a3718db3d469560befd2f83aca90a1cd1db4030192eef65d655e508e4 +oid sha256:ad5655a3163b600ac0ab5b6ced186e073997fac6d7d9b647ec692e306d3f52de size 21778 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail/libncp-cbke-library.a index 2a888b5205..e80699cf3d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:62ddccb5ea0a4a1b5420acafe9620539bbc914840426f78cfe44717dba7d54ae +oid sha256:f0df803a3c87a12b9c37dbaeba3977461298e87f51751f8d72168c392e3d41da size 23018 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail_singlenetwork/libncp-cbke-library.a index dceb98b7dd..47110828ca 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_dualrail_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:27e15d2aa55243461f9bb96a50489d4945abca880aef79a7cd353e76a2d298a1 +oid sha256:003171a877232b3bf5c32e920b9dec5838ec496f8f4435826b1715877451d2f3 size 23094 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_singlenetwork/libncp-cbke-library.a index 1945982e90..26664e7e4f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-cbke-library/release_stackprotection_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d4f918f448df7a7ddf46d19075bcb2ef26392f4bc3099c332fe206d85a8ed3c7 +oid sha256:b86cbb57c5ec882047e022398ed4955753ea70e25055a465e6b188aba80484e1 size 21856 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release/libncp-gp-library.a index b5319f1548..1f8bb9b340 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:15d2e291d09824a86633f0555e231e65c748aa4d2599cdbbeb8119dc6103b415 +oid sha256:bf9ec2144313041d4aea9ec73731587d2c0274210240860385bf5b4210fc0b81 size 9448 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a index 94eb5e116d..97c0f2db7c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e1450178506d27a1b6822596980e4ce6d446acc26f4c3f2f606bb1463fec180b +oid sha256:e165fb922efb5cfbbebc9512efb1f8c1ca075b4482c53f72c87a970a104c52af size 10686 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a index bce931e389..639f042a52 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_dualrail_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:320b94fbe77f1ab6703dfa7db894b5e7ec6a38211d216dafbb65b6f824bae2c7 +oid sha256:14096cdae4546ec4269b04d34aaadd5cbf5d6073309d3aa8fb2cff1ee3d12e81 size 10764 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index ac47e0d92b..0642051e77 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bd3bd473f260723ab9f36f8b0082ecea9daf2bdbb7d36f1b0b85f081ed534e75 +oid sha256:eb9dd0a35cba14c76f542051ee5c619dca88becf9e44857283f5d2ad6866a2c2 size 9524 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection/libncp-gp-library.a index a3ead13730..aaebf74860 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4fbba0b60fb3265e37983f04d249b1792584c84267b0cd42deb4a706948e0de9 +oid sha256:82d977b11a13da64db72f9d60b946014f9c34fbd088bfd16f87326c58d3e66d4 size 9884 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail/libncp-gp-library.a index 560cfcfa1e..923c27ab5d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:846fd1f975405f0cba81d6e82fc31d65929efb2ce264d6fc441c3e26a7d8a5e1 +oid sha256:a2342088b4b387c709f9930de82c3c84971045c2a4988fcb9c5e157ee9d31d09 size 11122 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail_singlenetwork/libncp-gp-library.a index 33586e1c61..3987adbbad 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_dualrail_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:acc2785e6945fdeff86fe3ba432de799f883ce45b585380f3150892819f135b5 +oid sha256:fa147d733a05245136b174396f08ec3f7992a47700dd94ffb95a2623ee226105 size 11200 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_singlenetwork/libncp-gp-library.a index 7110edeab4..810e2c8899 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-gp-library/release_stackprotection_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c095b04e21b8c26beaaa118176b80873afc924daa6cb526f1790b5366db963ab +oid sha256:c73a4a9a5d278cfedc0584da0a302f4e5d4ce08193cae984ceb4c741ac05285b size 9960 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a index 1c79c27245..f04a30f356 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:379a0de6e1aafd7dcfd2100a8c5d7ca06a8fe764cf03ed94dc27c38206081c30 +oid sha256:9819c1d8c536a394fe094afd7e515c12425d533dc02bf32ee10fa7f13b457e3b size 8436 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a index 9d3c5dd030..1b6afe4344 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:296f693bea1def46a1aa7a84d0950b435e89308accf836e0e57fd841f831378f +oid sha256:5dff0b779a0a30224da5581ed28efee986d38c9f1735154b1c14c2bf777f7fe5 size 9772 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a index baab2940bc..4bd9c8cb24 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_dualrail_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b1df1e31b823e78bd1270c0b69958f92f4074630b2a7a61cf4c07e52083ad39c +oid sha256:06eecdd16ffd837f8adc88638ba5ad2127d030ee1c1a367bcdea7be48281d0e2 size 9848 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index 1e241198ce..be890f889e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:31b9fc1fc889ce891bea21989968f9d2a19f6d360dfb4e56293bcc34b9652066 +oid sha256:d9b3f84721c0ba95906882862a851511c1d676dfe8972809c6a4ce938594fb68 size 8512 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection/libncp-mfglib-library.a index 5a1b751e3c..f11c13b478 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:482d9bb0f3418dc489254fafb2f0de612c345f8b5b1b464cc92ce72c0c3ca381 +oid sha256:9107c255fd8ea5168df85dc9ed325ae1a2d02d9c43fa7f4dbf9608cae364b3ef size 8832 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail/libncp-mfglib-library.a index 6d9cf6e953..78a6d2d24a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:28b88c8c1373465ca4f15af9ae785c3dc297557711976318595560b17dc25d5a +oid sha256:b54168bef709fd336582b4ae613076d27d5f27dc649d67325347dc69c11ee48f size 10168 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail_singlenetwork/libncp-mfglib-library.a index 5671a6835c..9605407fd7 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_dualrail_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6c8e4458032d4625544a84b06478eee683dcdf50d18b434a64ec53e4234f70c0 +oid sha256:5180e9e637fdb55291b876317ad15aeb60ef3c6513745ae26f2adf0cf0833127 size 10244 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_singlenetwork/libncp-mfglib-library.a index 97d7ed75aa..2bc0dbd663 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-mfglib-library/release_stackprotection_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:05744c59c8fb2674df60d76d6e01e09d31513c2dd3d201dc66c0e976517d908c +oid sha256:9dfc331926ca865671a4fd9f6d46c51efd0e5fe53eec120be1fe69a35cb59c03 size 8908 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release/libncp-pro-library.a index 5a30d65c13..a1df8b327e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5b48ac09b6cd5176c62880ecac6e0483ac2ea925a4b456db2d6ffa320adf9947 +oid sha256:4f117e528b90eb3ffeb4542c33ebacd904914f1f99bf5aec1e20bf46f183aaa9 size 122474 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a index b995f49c5a..36369a6d85 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8ec9bd28cdbe9cdae188b6bbc9b1076d123504b559b075326da947e76999734d +oid sha256:eeaa259a7f81e7a8e945c851a4ab8d812721c0f8a54dd78e46e210dbb598a0dc size 129912 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a index e673875cb8..941f909db2 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_dualrail_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6fe61e4be065efd1ba073eab6e2fbe55b4d38e6a70bd13f91852b12cb52c65b8 +oid sha256:406847413139f9b57551142e4b7548f3e7abbd93a3e6bc8090c333cd1cf939ae size 129726 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index 2c9cf847c5..ccd6a25780 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f8bc3cc8c87f0fee55e64932184d72da2c37987d1084c20a6b36ff6de17540b0 +oid sha256:a5337a9e10b6b5ce6ea7b90020ff7b3ae5204be21c877ff38e2e323219002851 size 122294 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection/libncp-pro-library.a index e709c2611f..c03e5a9aef 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e3b2a6da627930e039ef12e08b144646ca922dab7138b56364491e862225fe64 +oid sha256:41185a10ef39585e5ade254d4bfd3a00881f3935a328cd6a6d6b31f29aaf9d7c size 128752 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail/libncp-pro-library.a index 7562a588c1..18309b2315 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5484307111bfefcd5317b9a9e871f1c54db046b6ad698264a9c2bc2137017cf2 +oid sha256:148fa1577130d2a11ae2b3c8dce415dc4842bad5d10f787db0e51aa1fb127b8b size 136184 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail_singlenetwork/libncp-pro-library.a index 12a80fc368..292fb3db9a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_dualrail_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:746dcecd3f80e02cf5e60eb18f4d43ea52f1c2a0498f26bfe76fcf6bec4c3206 +oid sha256:1899522c1c88f169cdbd91c4a316261cd2dedce8c63ea65d7c933a9a9d6729a3 size 135988 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_singlenetwork/libncp-pro-library.a index 5343d19f2c..b74cc44271 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-pro-library/release_stackprotection_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ac2ea5b14d1fba6bb8972d128ee02e13b6a3dabcca1813b4d9831c6788642e30 +oid sha256:3690ebd0f548c83c07f5e68af0ab713538b8074fc8e47e8e2940a30fc592dc4b size 128550 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a index e2ab4ccb9d..48c2e4a24d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:edb46a3293f96192c36f2b91aca5a5d57599f333c034a3580ee87d6222a37f7b +oid sha256:2acc046da89ebfe8ec9d13bf600a26c9a2afd65c46678bd530a6f642470137a1 size 10786 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a index 8444ceb55e..10ddefe480 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7a5e192cc0f53d206c5e0aa3620b76221bb346297b4e0b2a110a83782101ba39 +oid sha256:227684ff06c0b84ff1070038b349d59091c7c0bba030c7f811f9726092eb71cb size 12026 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a index e796840eb5..018f591b69 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_dualrail_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d1933ee2fe30ca7aa4e35861100bcdc19911e08f909790b09320f27b9a41f257 +oid sha256:70df577ea2457cfbb95e9b5c70d786d7378eca079d4373845f4ca04b36a45442 size 12102 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index ae0290b630..94cb866d0c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d48bff613cdca21f394a41530721a7b12b0720e11bdd2c8b7c4bb888b7f43416 +oid sha256:936f0a1856710f5e3d266c4d6d0a550cec5e96a63745500e917150bc5ebfd84e size 10864 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection/libncp-source-route-library.a index 3c94e6b6a4..de6183cbf9 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a5dce3b89b8701126f349985b9b85563d57316b115af2a9f14ca99ae9d94ef52 +oid sha256:905aae0409a48b78c332d79d1494372b70d5b76465fb18f127372deb2f395560 size 11106 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail/libncp-source-route-library.a index 284dfe2ec5..47f77f4cae 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4746f398e3685ed91468129a62d18193ecb22fb87de83081403ae8eb124bf8f1 +oid sha256:b9d6d9b7ffacb7a81d668bb1cefd0f3973e355cb5f4de89ff7e04b1cde1008d6 size 12344 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail_singlenetwork/libncp-source-route-library.a index 0c1b5f15df..4534b2b083 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_dualrail_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:99ae265c8a42ff264c18df48471ce23314dc78b5d47a6c8721fd929e078f0b28 +oid sha256:daf5c34a76602a355cc0f430d67734af8742dade58f6554ac73d7b415b1285a3 size 12422 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_singlenetwork/libncp-source-route-library.a index f9798dee1d..a3e3ace625 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-source-route-library/release_stackprotection_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e39efa87e0031f36d4edc11ed74ef91f00d170e163e0dd485bdc2d2db4fbce94 +oid sha256:53eb82108f9ed045551690799b86cb05362aa073b05efd7d5272b200546c77ef size 11182 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release/libncp-zll-library.a index 0020d0065d..1c172c3c1a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a7e7266d458a74ea8e866de089c6daff72759bbc200adceabd4e46851d608f41 +oid sha256:8336d0d6e8a080c2be77a210147fe0e4675c5faf2209d8a6718f9f29aa909768 size 13516 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a index 8e9bb42393..202f97ec9a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e4f2940b5793ed046895c6ac874c91efba9f70b73c332c935cd2abb996df2c29 +oid sha256:5bceafde2a734e9163da28cde579706608a46ba37605e864e8167a3453a81241 size 14756 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a index 6a9f4e3942..6ca8915001 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_dualrail_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fca5ea3cf9b7ce5de36f180af82e9b88ef39ffc3ee1b8b43ab90658b700a8d43 +oid sha256:5f762c17082d8f338223e1839931832f40eb15f54548582aa4a6d88e4e3ea3a0 size 14832 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 9885f2ce57..693b03e615 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b319c25ea0dda46fd2bd94ccc6e72582b065f0faddcc461b2ef16bf34359b3fa +oid sha256:c3c983d4b08c12cb8876a9c0a23fc3a332d05904ca6248bd4d65e23c8a4dda83 size 13594 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection/libncp-zll-library.a index 27b2bc3403..6eb444c1f4 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f71c3c97777edf6aac25e677f20b302150ff6b2e82927cbae22e8950650fab21 +oid sha256:52253f1e3d337c0bc5326dae93a5ba035602248de2631e53952fc7ebebec0ee8 size 14176 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail/libncp-zll-library.a index 3c4a1c0a47..e6437462c6 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:30b884567ef1385a0592c02cfb6680c30c80f5164fcee2a91fbe4340c92c1264 +oid sha256:91d95f82cff55d5297088735af2441244a756537c3c688ec3e103780197187b7 size 15416 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail_singlenetwork/libncp-zll-library.a index 5dbecd5c04..91ca2dacf5 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_dualrail_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:74afe3d2b0b7a9ea9312e4ee4bf4b4b62df53092b430ebf598c2514ba6d53d7c +oid sha256:59de672aae54a184eeef63d7dd4492025ae1d009ef66984f4af8c75c5b726160 size 15492 diff --git a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_singlenetwork/libncp-zll-library.a index f728e8a559..b774e9c1a5 100644 --- a/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/iar/cortex-m33/ncp-zll-library/release_stackprotection_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c06f269decdb117c65bbf4ddd73574c83b0c6cc3e79e94869d8c78d8a6943ce8 +oid sha256:5eb48139925d9b77af71c0f5513bc77e7d4c69889beb1d496aadcb2f2fd73bc0 size 14254 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a index aa89fc20ef..6598227169 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:45008ff15ad7e7c4d97559c2eaba9887649d192466396ac2f5c42230784ac253 +oid sha256:15940d30bf557dcc8c5fb00c846f3f839c7246e51307e2991dd20dfc4bade5a8 size 38118 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a index 1ac1edb718..b2d7b8c583 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c1bccc6c49bab70f5436dccaca1178134f73e3d8ca44d8b730f057d54327d8eb +oid sha256:5352d249da1b7c51e016c90108214abff4477bbbc3cfd637319055b32f834aba size 41836 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a index 561e03fffe..ddc9bf85d2 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_dualrail_singlenetwork/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d571ee8743d0d46213fc31796a80386a3350ced26a0d24eb7ee7120132702333 +oid sha256:5539a7f3fa113c630b3884b3733a0885f90415e2b618face1abcd80eb5a71140 size 41700 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a index b3ae740a12..438ebc0caa 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_singlenetwork/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2f136183c4257aff9851fc2d8a9dc8751182157319634440ee77c4a80f6eedb2 +oid sha256:5725b3c5ed6dda002b5b0d57269f8ef1f6b51505c6cd51bbac33bf4dca24baee size 37984 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection/libzigbee-cbke-163k1.a index a3dff9d596..a80cc537dc 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c117962d007c665ccd7e72ce29771084b5aa6e601146615c190ccfe7036b5b0f +oid sha256:b74fcaf295674fef0f3e0498a10603d9ad7f23d9ee1e039e457b015fc0077b05 size 39564 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail/libzigbee-cbke-163k1.a index 17f2bc8eb4..648f53796b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9388a2cc05a2a0683d2864201c7d180e34d63eb887aafb5ef2c59a10b43df73f +oid sha256:78b345659f4d195de578bfe426afc356e25640d08f247e6f2c0398c376aa38d8 size 43282 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-163k1.a index a458abc1a1..d53bdf5e1f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:11c263640ea3ef9aa3c8020940d18698cd168a7592d912723e440b336fc343c1 +oid sha256:3ac630f4319354fd9ae766d8cfd976f6cad1587cd6a7891397c70504933cfaee size 43152 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_singlenetwork/libzigbee-cbke-163k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_singlenetwork/libzigbee-cbke-163k1.a index 49029449af..d44e5cf8d1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_singlenetwork/libzigbee-cbke-163k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-163k1/release_stackprotection_singlenetwork/libzigbee-cbke-163k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e84653a6451ca2626daa3bc6dfd02cb0bb8eb07536cedf50cc0e79d5d057dee0 +oid sha256:9275cd0caa5ed0e7687eb261be0154d4d7af79413fddffd61217db1e8cc73be3 size 39434 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a index 9b96906cb7..0092d3849e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:14c166e125fb982dbab24a7818cc1689d57b39a71aa6bc90a1674a7a59400d1f +oid sha256:6e557fc29a6890097ba034a60ecdd42f74fbc68bd3c973c62d59f282edaf7354 size 35116 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a index abdce38edd..142814ca62 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3773d24a321adcf7f1c3bea419e9948201ad4207025babe08c4815aa2bb31f0c +oid sha256:3d9ded57148f902f7d8e992c5d79192399ea3be555b59b69a4d64c08aae37394 size 38834 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a index ec332e1d0b..4495603321 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_dualrail_singlenetwork/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dce3266c1c76440cd2e91ebf8eb90e9ff90e149163834baa7a10796449724cf4 +oid sha256:cd59a9ebe9c6b5ea12482fe6da5d000b5fcea044586eb35ac9e2e78d5c60f5af size 38698 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a index e1b14d0651..7e3db22201 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_singlenetwork/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:121ddae5b84c630c54a25c44d87f328c826031546065a27d94a51cda82c335a2 +oid sha256:8e3930cf2e2262a115e37f0288b5ebad559116e59aea3b3cfdc226ff8a75e911 size 34982 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection/libzigbee-cbke-283k1.a index 9d99fce84d..15f75a3607 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2d004d606705a4fda9fff50c7e34dffa1ea74e73d54decf58d44bd99a1f11f25 +oid sha256:0f9b97318a4fd25c82ab3c358584ce19e94497c63c84549fb6f8b34763bf60cc size 36190 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail/libzigbee-cbke-283k1.a index 6c3eb3e55d..2fb8157ddb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ffceb4bdc7870106537be7cb28b447e0f2e1784baa2ff20dab1e5bfaab760e33 +oid sha256:a34e25b9e16afa1081607061becdde3acdcc5ab9e89354447ad35bf1060bf2a9 size 39908 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-283k1.a index b7c16d9afa..07ef8ec167 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:212d261ba92c651385a436fca50e093f563645502d524bbd96b4c9afe83d07cf +oid sha256:c14111f45094baed5ceffbedcf85d06e94785eac8087458fb1aa7be9f373ba4a size 39768 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-283k1.a index fca16155d0..e07d6274bd 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9720f1da3ceca4235248fa3e266a7d28a59f65665f689edf5f9ae37157d5c1c5 +oid sha256:015a870d68d32a9980248dbf5c6f966057036940fcd606cd87b4a089d465271f size 36052 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a index 95de6ee4ee..6cf82fff4e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4608147bd3708949fc8fd8408566afff16fe311bf9eabfc5ff72c3c1c264eb03 +oid sha256:5b165fdfe8fcfedfc67a42d86fcf814b10ac61b62e0636ece22a522d76d9ea02 size 14388 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a index 5642c1cd52..4d81344f4f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1048687c08b73682d1c7aa80e550d5642ad1f8a049d9abbe6baeae43a897275c +oid sha256:e179217bf2ccf9303ba1ec59c1b828a40b054877dfe047f61be55baa771efeb3 size 15626 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a index 7fb0bdbd35..3b80e4f41e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_dualrail_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8a2bf25b469b6e22c2cafb0981135d6b0eb96b8fa724b418e9e8088df6fe49b3 +oid sha256:c17410895d6f465b0a28cf5289f5ccfc621123920c244ac2fa4f308f24ff8545 size 15704 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a index e291393e77..c4433bb6b7 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:67ff99d648e96a7f0e91fd61dd006f850e139ead45a9e7b7af9fc32febf8fa8b +oid sha256:a75bc8cccbc6a2b553684a806ec27c2c38f490f7ee27d1c98a713254f708c881 size 14464 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection/libzigbee-cbke-core.a index 254ca4ce0c..c544d6a177 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ee4458732418c0f93ee85bfa81905065393752bb0260ab61a4a43def2ef3cb80 +oid sha256:d5fb457ccfa0c0823c14c0fc905e891cbfdd153692ad22f9909298ba931d8e55 size 14814 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail/libzigbee-cbke-core.a index f343a5e32b..83bb77b829 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f61f71f23b6994827cde20d1f6d9984d1f08c030383188ec8db81a6200d4910 +oid sha256:3e5de6027bf414571d3ea85300d9e6faf2e69ec4fcc3f797201a656c1ce887a8 size 16054 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-core.a index ac4a306477..69cda83d64 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7fbebdc0038f058e619a938e26dcb4f4fd3cc39e25c42357000e3f0564108128 +oid sha256:8c2c2999bc9042135d6f0edc52b7933e93ceeda4e0b6e54ddd0172a361b1ab42 size 16130 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_singlenetwork/libzigbee-cbke-core.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_singlenetwork/libzigbee-cbke-core.a index 78187d1e3a..f18ad06784 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_singlenetwork/libzigbee-cbke-core.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-core/release_stackprotection_singlenetwork/libzigbee-cbke-core.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:544c20b64317d2cb2c1e356f73b855ebd107d26ee999720fdaf9b974cb9698f3 +oid sha256:ddaca2eb8165b47f2e9a757fd398f68ae5003711ca758ac2ba2025bf330f0dc3 size 14892 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a index 0980e46187..6bd5261874 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4cd59bef3f8fa85afc3fb740dc892c9f39478b91c0269cf67fadb24f3a0892b4 +oid sha256:ac76f29c205507b0e17b7bf8385c71ddf75d27d1309042aec8b7904068a97f98 size 11302 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a index b11cac162c..1194a86868 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fda4245b92916dd604f2e513658ca218ecb0ac4d3341a281a40ca475e638c482 +oid sha256:7fbce0108ee15072a8e6cd31a361faa5d101d24ed1708c38103634987c0c8f0f size 12540 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a index 00fc5dd210..6e29e98cba 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d2d83b1fdb7ec59eea7c795a54d5c8c0bc293fb459a708af78343f127e7276d0 +oid sha256:191fd90f56751ca4e4b1397b3fab2354b54d64e1b8fd76f928b47eb54f18fb32 size 12382 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a index aa84eb576c..046cb78df2 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_singlenetwork/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:14039266bc6919f6aa37fabe832c32efb98b632863d29bd659e71d40e1bd8373 +oid sha256:270a3a993d7fb4cdce5f820ca4a06a2c6de972508595a8895432539ddb2e1b77 size 11144 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection/libzigbee-cbke-dsa-sign.a index 2f07b57345..b5d08803e3 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1db344ed3911c1bb1cd351af962495c76e02bce09557d14dc1b92715b988f086 +oid sha256:358e2edd48978d866006d5c5b62556475d829cbaacbf4e6539a0114306018ac1 size 11602 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail/libzigbee-cbke-dsa-sign.a index a56ba8609b..338a5afad2 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e53d49157ca1bd2f11e8c57bf1c7808a1b42f023a2a763a0a5587d95700efd6a +oid sha256:33fc0783425fe0573c5b5cf558f5aa51e06eff81a322ab97261cce4941c8ed84 size 12840 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a index eb9fdc0b3e..0fbf5adae7 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:78a89215eb2f27e4ef0ea0ab40073e943b9add5e02482eaabc5c772fefe76e28 +oid sha256:791fef786ec1f5c29a26ea7caabbae91be623cba1cb12cde257379db863e4aa9 size 12698 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-sign.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-sign.a index 979e3810c3..7d8a698200 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-sign.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-sign/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-sign.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bf438e674fed7b7c4db8e6f303d6ead72266925361eb1bdbef40979dac9af59c +oid sha256:72790dec66520be2098214e3c1eb7edb2992f283c7c4073a8ca4390da669e537 size 11458 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a index be88e9e15c..22b7887dab 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1eb6acce8c242e4d0ca4bf034ae9bfae66026133c8a03265c39635dc026037ca +oid sha256:87e2eb0d92f00fd13d3000714a741f26c14e6bd1f215696b6f41b578d9677aa4 size 8966 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a index 030ce7ee6a..f33a7d1642 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:695c442309a6ce9d3ac9dd98448455cc7b33a46bdbe0717fc495398e664cd8ef +oid sha256:b9b76518c8872e3d8443786417969b05692f95eeea7e2807b2c67b9becb0093a size 10204 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a index 836b48f10d..2d27a17e31 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ac792df4466eb673070e73a52a5740998ce520f22cb8af54c3a3a6718e79b9d2 +oid sha256:37fa3a6eae9feb7ee4c8620908ec077ea80b6d4632f0aca6d8c1045afa7d0553 size 10160 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a index 8a342ab286..87fae1762b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d02e74fd37899e0874e38485d48f18c3146352578233e258b6a25420c5fe0af0 +oid sha256:63c7af4f93490cb72c5a2c0fee62acbfc93c6510da46b5dd2b1518842af99cf2 size 8922 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection/libzigbee-cbke-dsa-verify-283k1.a index 8bd9fb9e3c..96d3b25ff3 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8431396a39e7bf92625242eaaa0248beaad3c2364f27b1f43f52f0d7959e9283 +oid sha256:69b8834967442ae1e826c60a702ab5d5f036e87348a0ce17c178fbac2276c495 size 9368 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify-283k1.a index 8a62a8fcb1..1893791828 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5354537c9b5313b56f5a9df431993ef4a146135ca3b0512562983fe37da4eff3 +oid sha256:0bdc62b6a8389d4e3032bd429167dedd7a139ca99c85b0ab1c53f9801bc53a58 size 10606 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a index 0794400e91..e0c710edbc 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ae581afe67f0b0326a19b55053a1207ca305cdc51a882768badf154e6941c94e +oid sha256:c370dd7f3799fd0a62ef9ff4375f56946a15919c6769eaae68a7ba44ba67089e size 10558 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a index a9c9c6efa3..a27dfe5301 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify-283k1/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify-283k1.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6ff96553a28a9ed7c375e4941fcd5da22d522189f502b1831d71fd9bcb50e9e9 +oid sha256:ba88a26b1e186bc763d43b17abbf156eeede2a20cb1ef4ba1e943da97f6d686b size 9320 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a index 3e8d719022..1db041268c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d8cd6264c4906c39e078415a9f26407b6d4af2e1f253d341f9a5ad4e9bf86784 +oid sha256:7de60ab9697b5c0d7d684d3c97f0cfb3c6a3784e5e6087f99c70a42b8661352d size 8758 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a index 0aee411616..76c99a1efa 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a12a3b4414abc65fcc4f48fe9ee119982b3e44d442018381ad5bb1c85eac5a3f +oid sha256:7ed3e6be2fbed11f3e628383080f68f28cef0f401592d0149e76027b95bce83b size 9996 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a index 9ec991f5d4..1bad86c0e1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd10b98f5cf8c739621a5aeca9b05af8d53d14576b12a61c3c341d87e2b97849 +oid sha256:79ad059d3150257e4dd63d536fe8645ba47bd30aebf6c47fe708bc2a54b980ba size 9948 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a index 52f0f0bbed..be131095d1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_singlenetwork/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fa254fbd8fea33b263a3a8df832bfef25c0bf627683bc5544bf5b47857f56a1c +oid sha256:eaac347e906c88faa58607f6d5fa0a121677f2ab71ca11dcad713dafc49e551e size 8708 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection/libzigbee-cbke-dsa-verify.a index a417227886..ccfee6268d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:58e7fa7c92fce0c369e7414a8cb385af8b6e81efd0fe79be9f97e12ba5279d0b +oid sha256:e97c0f7184f0bbd5b295932a1cfd34b168d8b6fbcf5d11c08f873e3e7f98ac40 size 9146 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify.a index 98d10d7f20..65dd230424 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cc76cf07aad547b6242b332863d669fcb511b5c048ec09f0890f6c68d965118c +oid sha256:b2a883537d477715c581373720afbd86eee4ef6991fd1f4e5cb11f28ee8cd7c2 size 10384 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a index 297d923fa0..82ae19a4df 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_dualrail_singlenetwork/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:540879ec615c2064763841a11035b36d0b6cc743cf1a01fb4749b333e7c0efe8 +oid sha256:5df091e42644722cdcf65c204798bbaccdc7bf1c617ed7ce0339fce429214e74 size 10336 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify.a index 9a9893260c..5717350c81 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-cbke-dsa-verify/release_stackprotection_singlenetwork/libzigbee-cbke-dsa-verify.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fc8c071362749795408f1c94a27d9dc95aebc09f112ab26b01b53dceb00c47e9 +oid sha256:897917113040c9f3fdb86fdb1dfdb675de46ed21cb0e104da27b8c88e539902d size 9096 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a index 9a599386d4..30991b7609 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b0cf2252689f75e67716a41bd505eb45276bc6702c20219e04739393c505d2a6 +oid sha256:b1dd1b2957ea3a03e7dc23553ebba54df3e9efc7182b211202f85eab955b8b42 size 13168 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a index abf3e58e36..5dfbf4b26d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:da80c4b254721b1f25af1c878b87f748df090d187d39d9ffb1c1bf44c869d823 +oid sha256:cf1061c88be43452c76af6abc3727241f95a68d20702b0bb3114c60c3ee739af size 14408 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a index 5cd4a728d6..1d74db90b1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_dualrail_singlenetwork/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0b77cde85b452c35419d950fa245f4073b3df515db2dca6c021792aa80f09869 +oid sha256:e54d5eb168d8998b9438f3a6bb1dd3a31f37c6760fd89a3396f4e3f39ddf370b size 14484 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a index a08d4fac02..497cabb730 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_singlenetwork/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7e2fd9796af2c85ca8d421c96940ed108535221ecf445875e0c2f1217d56e42c +oid sha256:fa5f6c767b135cad486566661e3edf5dc5dcecabde37a7e66e2d450ec37ac2b1 size 13246 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection/libzigbee-debug-basic.a index ffe5724f22..7f52a4691e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2e39663358112d5d8d98e3933c213e7c410a278c806ca60fe3867836ce8b3b2c +oid sha256:d1066cff2ffde2b2f9aa98e81f947e6cf9ae5d7f2a0fcf9632f357e643d40838 size 13686 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail/libzigbee-debug-basic.a index 10776f0f9c..4456a9ca24 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bae889c0b088f1ae9b01f20b9f42cd7701a3a4e267a4ff309634c300b7f6553f +oid sha256:cfb94535e203bb2859164273b98cd22ea71241adbb66e800ae7eea5cc28bc355 size 14926 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-basic.a index 1c2eeb60ab..d951cc676d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0034604b4f2b3e1e51bfd5b2eb06d2d35657f90bb0298f87f5dad0a701c544a7 +oid sha256:a78d505a269673aa718009d338d31b3ce4ce8ca25aaa3643276baf0fdc524378 size 15002 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_singlenetwork/libzigbee-debug-basic.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_singlenetwork/libzigbee-debug-basic.a index ecbdb72af1..eb1013dd17 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_singlenetwork/libzigbee-debug-basic.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-basic/release_stackprotection_singlenetwork/libzigbee-debug-basic.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:557cf17b762158d5f3f7793170db7ce4cbe844b64661b090d2e11282fd7e68bb +oid sha256:ccd54b61e8ae342ac2bb18e3788c4668fdbb808033fe1cbd8c19dba5a7cb3c87 size 13764 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a index 394be3b3a3..ed3d37ee0c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dab99efbc4fbd12573a384ffded0b82ddf6ef4c2081d23c949dbd251c0e64389 +oid sha256:d6ecc5bf11d71623242f6592ea4659f94420d48572e223f8b6ddfcdba8c1e13f size 9658 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a index 391e04f82a..f5b476d2cb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b7f221094ca8f73a1621b808c00e51cb4c05d07275cfbaa5062c7b6c91ff8eaa +oid sha256:8742a8d5e8ad33fd77d4c1035870455764c53bf4e86f31f539d22ccba97c1b8c size 10896 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a index fe3a9ea5c5..be3aaa797b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_dualrail_singlenetwork/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c243354603b5625f7c4f4596c82c81ce956c9e78942faa5e481b9ab6abada07f +oid sha256:b8dcc129097bb614626fe302b6923cb3ac426c77d4fc40c85fd30a98bae34aec size 10974 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a index 0352a6ad3f..bd4f964fb4 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_singlenetwork/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4fd0a428c8f29a3f620901ecf60dffdd86a3492746bb3f45ff7d15ed2b8acc25 +oid sha256:3878662f502c311def9d419539422ad1c3029ec6e7bed8ff4e2a8d1dc35565ac size 9734 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection/libzigbee-debug-extended.a index 26f4d50838..07a6f93841 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1c973f8f9e06785d0cc4c6fc708e66abc889597b8fa62fad422f246679e0401d +oid sha256:233cfba720d0fa2b71a5e669e1caf7b784054a5c8faa67538bcded238fbb916e size 10052 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail/libzigbee-debug-extended.a index e8717d9348..91ec830f7e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e7f2f1f15a486712f5e867d6ea2f618565832f57ef646edd03597e6a3626882c +oid sha256:841f20aad1335dfd958ad12ce11f50adc31902934d19b3b0ad788d87537f8d6a size 11290 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-extended.a index b87f26fa1b..b0b823775c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_dualrail_singlenetwork/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f8e1a5f5c47674881ef630db7ed947206c4c786f8905e30a920ce3f9305354bb +oid sha256:7a5e816cffc64ae849939f7cc1ea11c5b7cd8fc6c9bd36466898bb0f047626aa size 11368 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_singlenetwork/libzigbee-debug-extended.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_singlenetwork/libzigbee-debug-extended.a index 0fc1646a68..ca88bfabe9 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_singlenetwork/libzigbee-debug-extended.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-debug-extended/release_stackprotection_singlenetwork/libzigbee-debug-extended.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ec912ba0b0c59f6bda6ee1593ea865da3fe13dd26bde317a6641d485f7d6da9a +oid sha256:3b6296a6f86def0c6cb5e369980d7b651a212f733ca6a1eeee1b532f1cd379e0 size 10128 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a index 315393ec5e..b05d89c85d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:41b88a473a6eec14dbe98ef52313a8ff429d9d00ea037eb9452267cab5b1be96 +oid sha256:b4e6c6739c54afa3871537d10c4572acce82b2932be1d8fc6f38c1e157a84bcd size 60388 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a index f039abd60f..2ae4c9c4a6 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:329de7f2bf6590ab1d337fb7c0626c1beaada990d80562efb0064d002a722c52 +oid sha256:2eeba9a96b6c9480628fd859cba60fb9044cd6073fe967e56c14c8e9401a6be9 size 65344 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a index 046b57d789..621476e920 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:60945d1d3b0c4b1ef0ed70c0dc1fb4db0a10602703a35f98c3b07cb18a2d4006 +oid sha256:2f3737b3cf5dea2a6003dfd7a3de31736dc4112bd4c3fff3c0f50cce257bcf41 size 65524 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a index 97c3dfcbd3..0b16e9c73b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:95d22e03e20e4f0b523741ceeda7508fbb0f7b81f42559910143f729e0e41770 +oid sha256:29548ffdefd049173aae3ec8199a1473fb348528752303b2d1b010d3fe570b09 size 60566 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection/libzigbee-dynamic-commissioning.a index 4b0fabcb4b..eb084be6fa 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:692d677fdafe8ae8bd3746197ed9dc18443bcd6493d5d98a03ba2cdf6cd41ce9 +oid sha256:f0379e17efa576c71e315cd2ed695ac3798d38828ee36219d909b86a0cde69a0 size 63844 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail/libzigbee-dynamic-commissioning.a index 448ac17977..5dc910473d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2d68789794a8fb01459fb85ff6bb38a5a1e13c94e447890f6b18d603f3559b47 +oid sha256:aac18e8e7285626db003c7135a858b26170b5fef498bd415e3845ffd7d5768dc size 68802 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a index 3dca4af5b2..0f3987f58f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_dualrail_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:20d4ee0d39c102ef06697a0a8a929fd228176ce2ddbfa83dabb495d2571214de +oid sha256:256cd6304560e7234a75cc71952fc48f3e1de463eaa48d59c6088cff3b46cb54 size 68980 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_singlenetwork/libzigbee-dynamic-commissioning.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_singlenetwork/libzigbee-dynamic-commissioning.a index 91ac0b70c7..a960e6e757 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_singlenetwork/libzigbee-dynamic-commissioning.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-dynamic-commissioning/release_stackprotection_singlenetwork/libzigbee-dynamic-commissioning.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd3ed37c7b322701b605f35016b589602036a5282b732e5adf1cfce4283f4886 +oid sha256:c48a637a0a41be1bb9e0bdb174a8ba3ec965be69b3896a838b183466ddd3f78a size 64024 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release/libzigbee-gp.a index b2ec5d5d99..003b0c194a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:177ab82f0895b8294f56d4768080d033a3a1245e5c7943c2a19e7d6ee98e9963 +oid sha256:0a93dc5e2150acd6e9fdf37d98001332cd4619a5f3d2ae598d9c9f7322e3e00c size 99354 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a index 0b9051045d..e0ced21c30 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5cc4808b71e7f788dfa46f4bd65d2753a333af9d3fa1614655e1427c04572444 +oid sha256:039135487d7689ac3411d8d2e6e18d047a013a71bb27385e246242563fe74a7f size 104308 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a index f789a1b33c..bfe7cbc624 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_dualrail_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6dcb4e7880e5e8493852933db4e9e76a57f2020a4957b356a2b8009da26d2806 +oid sha256:006985e2383bfb989437a32c9b917951b6a9490a610200a98740a2ec8d45196c size 103956 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a index 92ef4a1d24..a9b278afd1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cedd8a72277887a12e8cc2cee1a604f517b8e7609be5bba0e64c1c4df70d2ee9 +oid sha256:c8c1bbdfb7370e511323c4e3a50b7ccb5e439651bb070786a50c649a036d762c size 98998 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection/libzigbee-gp.a index bf236fa650..16050280fc 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bcb48b93268ca12f4f10eed8d5e82e4e294aa1abb9da5b0f09860a002b6de025 +oid sha256:2a23134c242d6ad2d30d48e8487661270d32fd717d8410be564430512a242dcd size 101290 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail/libzigbee-gp.a index 67268a0d66..9662e71e04 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:57abb9cb5ac5bc1753a2803cb4592aaf88148078b16daef134a7013984416280 +oid sha256:bcbfe5f93455a43fd9897eefb64e1bf7b61c08455d548ff95fdada7ef4da88a3 size 106244 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail_singlenetwork/libzigbee-gp.a index f52911bd70..8516edbcc1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_dualrail_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7dad21051ac9aa48cfef0ab0b3f4e587cd156dbd8b845ab5ddcc4854f09d1e68 +oid sha256:ce19945cfb35cee9a0875ed0bbdb9a54c8e275336085bce8faa293d3ca2cd1fb size 105894 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_singlenetwork/libzigbee-gp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_singlenetwork/libzigbee-gp.a index 44c3e05ca0..bf6f105f92 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_singlenetwork/libzigbee-gp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-gp/release_stackprotection_singlenetwork/libzigbee-gp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:12934cbca2bfe28ead44dbbb4b94259690abafc5fb70a5b93483f75a3239e422 +oid sha256:f2ed8238e93037f6c950a42a0b8f9d79e6f871306c58cbbb11f9f279f91bac08 size 100936 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a index a6d2024293..5e3ae1c53b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5f04d71d51c76640075feb1214b2668291e350210add6e07738f541f50723cd3 +oid sha256:04133a74ad1fc897f1839eada25bffafcd237f4761cea8e8e30059d890dd6cf6 size 19050 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a index c4691e898a..31d3517c34 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d203528a96ec3c2567b7c8ba4ee095d75e8b104cbe6fce82622ff58017e18f5f +oid sha256:b20c065f09d3738ca6756a891ca1857c5dee46fb1ccc1b813d0f6aeda6aa863a size 27930 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a index 9aaf1351f9..7c0268df2d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_dualrail_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:34a89f2768724e3f87dd68cad783abb8d07b247ee082f0a665c1e08f94312876 +oid sha256:cbf0d3ded7b6473acf9beef9b9f5c011d1e5f561c211610682de059c521c1631 size 27828 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a index 2e786d600d..34b551bc3b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2c25578d121e58be940cd7285e853ac67c1c81dd5414acbc9302896f370bb858 +oid sha256:4429ad8561bac63f99a60120b4a65c56e7f78379e55fe67f53220bde58dfde1c size 18952 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection/libzigbee-mfglib.a index e6cd54e092..77bb4fcf68 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:55a8e779aed703113c224eaffd2258b9849f635a1f84877fada55fa1a85fa3d4 +oid sha256:d549120a4c9bd4bd28ef8d123b9bf9462fa35a5e3158082f729dbac4cf50f4ab size 19334 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail/libzigbee-mfglib.a index 3beb2462e1..35048abe24 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c8883f66e0b16676efde368bc2f3af97b9352541550fac20434818ed5e5f0719 +oid sha256:64f966797e61557ad39eaad3c3ee0422becea79fd163597be650d8d9f10d3f7d size 28214 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail_singlenetwork/libzigbee-mfglib.a index 4f3b45b9cd..3a1d9e624d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_dualrail_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:13b433d19d185a4df27b24961741cce97ba42c95489970ef82b52c98044c1dbf +oid sha256:6858ebf82c49b8ea9c092e126220cc2cee9a61ab349689c785682aebf6a032ed size 28114 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_singlenetwork/libzigbee-mfglib.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_singlenetwork/libzigbee-mfglib.a index 65fcc84fc3..971ff2962f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_singlenetwork/libzigbee-mfglib.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-mfglib/release_stackprotection_singlenetwork/libzigbee-mfglib.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a255c4aeb410bf1aaa2907ee8723ead457581ef0277b2bf4de0b11995f57677e +oid sha256:df0dfd47ab23d8af0d570b4262757d1177fb22e71e410cf2b31b9f4548fffb8d size 19236 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a index 3a555277a6..964d207c0a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9aa8371996be10d0d5c40794dd3dd1f0e7a9300c48e133b0d5b42cba7a66cabf +oid sha256:572817461a9e4d451b81044cfeff99902a02509bbcf1fc95630f29957a42827d size 32428 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release_stackprotection/libzigbee-multi-network.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release_stackprotection/libzigbee-multi-network.a index 619b4ddd0d..b5e39d2da6 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release_stackprotection/libzigbee-multi-network.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-network/release_stackprotection/libzigbee-multi-network.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:98dd76f112149a95ea645a8de119d024a891e3af0d7952735fe0720f8c95ca0d +oid sha256:10883b2e95c9294073d151768d390102524de37aa63f6b85517c208b6666912b size 33370 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a index d983b9dade..4a6ad3bf58 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release/libzigbee-multi-pan.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:62185ecce46d9eae38f9229309883360129d9cfedeccaf44bd7f5cdedeaf395a +oid sha256:8e0c08848728f58487dc204036c8356bcb06dc9744cead6ab885d1a01249c0b6 size 13876 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release_stackprotection/libzigbee-multi-pan.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release_stackprotection/libzigbee-multi-pan.a index f5630204df..d6bca35ace 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release_stackprotection/libzigbee-multi-pan.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-multi-pan/release_stackprotection/libzigbee-multi-pan.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0df81f5a027d5a53dad7063790e7123c741653c7553c4211ade4d4e5f3720641 +oid sha256:aab84f73a39667cf15d52b1284c10fbdcbf5666466bb980c5aec0c72a66b5ad3 size 14222 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a index 1da34cd292..a208e1d5d2 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9324fe1fc17ceeb4eb298021c2e250639aadc7be1f945b568ee774c3a9244423 -size 180534 +oid sha256:ab2ea810b41230883c2e8962086a431a59c03a3eaf92906506f537caf8ac8749 +size 182790 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a index f3aea1720c..674dedf05f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cb64b6e99b9ca635c39e9780f555bc68f1ff6f9570cbaabe0e4af75011eab54f -size 183334 +oid sha256:5666ea67575abd4a9b9b38f0023be3df602458c0d01854aacc01cd9112b40b65 +size 185590 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a index cf40c48eaa..6087557e8d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_dualrail_singlenetwork/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ce753669b5e1c57383cbe4d61b76a2cb9f852b97decdf9739d439efc24f5437d -size 183036 +oid sha256:3a43c9b74e89d95b3ebaec65a876f436309e5460846f8486044ef3afcda1542c +size 185292 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a index 8ad1a197eb..3467439456 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_singlenetwork/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fbb08ad4386ab930a43d93083a32e27526354e16b7cd19e3b3282609699d08cd -size 180236 +oid sha256:5fd0f1344159dacf66ad223b0609f26e946a87652aa76c059aff92996db955a8 +size 182492 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection/libzigbee-ncp-cpc.a index 7ba393b93e..bd1d48ce14 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:93f512aeaf2db54f4b80f373737664a8dc4532b1efe3513c5ddce08bd1c34636 -size 183288 +oid sha256:ef3443f4869a10a95524e1bcbec21f3aa699b409f52ac4369dfe68e6d02615c7 +size 186104 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail/libzigbee-ncp-cpc.a index e6a31dfd06..626b9c49eb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b7a7c4de6db78d870842b0a2c8f9f62355c8d2fe7782a07ca728e2df121b0988 -size 186088 +oid sha256:c59b89a46fb3943e41de348467458efcc4222af8075a14967b2adbbe2f05835b +size 188904 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-cpc.a index 379c3ebaa6..ff7ad8d34e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:77649561c14478f64e49a62f399e09b8a647322b0679028958b8f5727bf56e05 -size 185788 +oid sha256:878bc5944427fb2d6e2657eac6effd82341c34d3c65ee21f4d428f36cdf8bfd6 +size 188604 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_singlenetwork/libzigbee-ncp-cpc.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_singlenetwork/libzigbee-ncp-cpc.a index 7aa3be37fd..eab36c4d07 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_singlenetwork/libzigbee-ncp-cpc.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-cpc/release_stackprotection_singlenetwork/libzigbee-ncp-cpc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:80ee4b252ed76facf22361ce181f65501a1607fe848ca9219a76418f65f49bcd -size 182988 +oid sha256:63b8c581ee25362957a9d49be8f0dda34b9ee29e198a9c65a93189e420ebb1fb +size 185804 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a index 78244a4221..4c62f24848 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e58ae28ed26925683fa8a39c5c338c4db37417d1ea201e67cc0e43105fdd7a07 -size 170816 +oid sha256:c3ade544518702dab8d658ff9dff8e3abe8d3c4ecae9cdc02268f84d84b9b923 +size 172434 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a index eba763210e..e1798a8507 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b979c9ee9b6f00f23ec02e0de58546ffd445687db0f4e472e96b327177e9e273 -size 174562 +oid sha256:e8cd79202129d1e0ef9faff52f7ca4bac2108410fca761095e4e7bdbc8905a14 +size 176180 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a index 6f4342bf07..7a208e62f9 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_dualrail_singlenetwork/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e33176ac7acd9970f1b94dc8f62675bc66b52a54cb4cfdd474b2fb392c0295d5 -size 174256 +oid sha256:c47b770a3e94ab3faf8a9b3daca5ee0c467deb69816557aa16cf61efeb8526ec +size 175874 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a index e7ae00d1a4..6aa503d66a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_singlenetwork/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4ecdb12470e0cf388da3151a1b0ee401beafaa79525536d33c958cd4210aeeb7 -size 170516 +oid sha256:f448e992a387f733149679a4d35c09b86d302bc0996f2505b2576ed7ee83e377 +size 172134 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection/libzigbee-ncp-spi.a index 649cd2dc2c..8cf5b0aae6 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8a87cc459b6b1c102782916b97c86e989902f5cd1b2a7670085900ae4b507633 -size 173346 +oid sha256:19ea3f9105eae0d75281d9ec181f9545c542748a0c8fc7c85afe8faf08323937 +size 175526 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail/libzigbee-ncp-spi.a index c0d9177164..02f4d7d01d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3a21f1af55f507ebd129b8948b089e5bea74f9b1354945dcbf83450072da64cd -size 177090 +oid sha256:aa438a99e6997c98fb7223c20ece0bb2bd30ca236bf9aeda5e852d926de56add +size 179268 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-spi.a index ccb3341162..8b62ee8974 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:597354ccb803cceaaf668a99845898ff7aca0abf712af353c60f1711911a58e2 -size 176792 +oid sha256:2a7cdf2b83e8132ba6da78b470cf06c5bd150060ec1080f1ec6d8c4bdfdfb450 +size 178970 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_singlenetwork/libzigbee-ncp-spi.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_singlenetwork/libzigbee-ncp-spi.a index 4fe4af31d7..612afbcd75 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_singlenetwork/libzigbee-ncp-spi.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-spi/release_stackprotection_singlenetwork/libzigbee-ncp-spi.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:957955a03aa87ae77c94a09726760ed47b6ee02800a0a38d4777e4f3311284d7 -size 173046 +oid sha256:2a695e0f6f7257ec3269518f8917bea093ac40c96246926d94fcffd29ec4197e +size 175226 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index b3801dc0f4..3f3078e465 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:67bd766f1724e5d4578dfda165b2424caa6666af0f36c24fcb1b0fd31390084a -size 158620 +oid sha256:e0ef3481e7a33a424ee45d83bbc36c3528f379c34dd92e5f3dfe88b576832b29 +size 160146 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a index a327a669dd..26b6e90455 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5a7c9a43b9e8a659b14a753f76ef5357e5f35d10228b945329b0a71d80fd580e -size 161832 +oid sha256:29f3d5b9eb387987ac1f8accad1ed959c8a9691db2b26381a77050f4fdded673 +size 163358 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a index 7c37a8c61e..53ea682f0a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_dualrail_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:259b93eda57b62b407500d89a0e61c55eb8f66ab5a1ba2eebf8dcd12d7561349 -size 161456 +oid sha256:35ef1c2c015cf4ceda48405ebd1911ddccd2ef635955369be9088c7aeefaf97b +size 162982 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index a40df9fc45..e0848dd07e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bd790af480d5d60e148de947e257cbdcc893dcd36dbde8de6fd40e68b076f2f0 -size 158246 +oid sha256:b315d4042b484f0e7c30ff8cbff9c52af3df318a2a6e02fac5f12a1f102428f3 +size 159772 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection/libzigbee-ncp-uart.a index 7fc8f92a1e..65457fb1b0 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d42575b2a7538e240cc7b98e1c1a48663d488e39b822e639181234ffda68fb36 -size 161080 +oid sha256:2b04ce5568231458920bf5a2b3dbc6a97046ad08e39de1de82e0a91774683d2d +size 163166 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail/libzigbee-ncp-uart.a index 9c46d954c5..cb7f2867bb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:88719706952482f449d4fbd8aa859cc6b9e79f1c59ddb42afacb2bfc1e145ce8 -size 164290 +oid sha256:5f5d3512f8533096a8a13790d9f7e61d4c9e136270f5e16a5bdcdda3c6cb9a90 +size 166378 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-uart.a index 3e1033ed4a..ae624e1a0c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_dualrail_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a22a972a1813ee1c8bb47d2ca98f8ef063d49cd95f6c3884c957d201bb298b32 -size 163916 +oid sha256:a3c2497c9d784cb8b6eb1cf384e92f27f8ad22798594d2fbc1d0ac66cbe8001a +size 166004 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_singlenetwork/libzigbee-ncp-uart.a index dd2b953bae..8f295b402d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-ncp-uart/release_stackprotection_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4496795c87f3f3289537131925aa7620618e128b5656de01fa93dad482e64ff4 -size 160710 +oid sha256:2b1dd60f985c01a7b1c8c0c57428dad3eb123fec08f38d8a756ee519b4190e45 +size 162796 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a index a40fe12cc1..73beab4a4a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dfea3bb99d09c4955809e98b11b443050bf6335f2b62ee41d20a00f3e597394c +oid sha256:a830dce3c296921669ebf3f65681d290f45ae9d57fe488262c7c3703b526ce3d size 1462032 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a index 525eaaea21..a48c071c41 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:68bba9907850ea782d4c102a5a4a53975f8eefe17762f2083b72d235c315f928 +oid sha256:4d227e925cf44b9684f806e7bceba93c9b189f74c862650a115c2d1561cbc01a size 1931150 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a index e96f8b3977..44491af77e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d2e9c9f57c5c7c6786eb9150736e0a8f7db1b5b2bccb63199fc317f4f7272bf5 +oid sha256:552f7c1f18cb0a4acdf0fbf62552f1e3f8b7cc69f6cc498084ff05e5dac33b4d size 1881842 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a index 7b20be821c..94141d678e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94d73c0fd9a8eec3ccfcfe7cd2f143723a1f1daba0eb445e734d5f0834d2a548 +oid sha256:bcf2d49fac126973bf212913827616600a3d9c3020dd9de66e98ffaff42bc344 size 1406876 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-leaf-stack-mac-test-cmds.a index 5056c28488..c841a812f7 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:87277b8b7e337ca7fb6732883383d05702d7e3dce8b658fbb84e0b6f60699955 +oid sha256:52c27e48db32910dff9db3459b73eda9243c31d8caafc16859751423444e28f1 size 1515088 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a index df8050d817..2c0689e510 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7009c00a920d2812af9e6dd137103c2717c3ef5173caf750905d21f392b82ebf +oid sha256:3eba0d36da439f6b0dbe7b487ecaa3caa317b8085431c1530f408c497bc33e29 size 2002900 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a index bd89dee1b9..b7aea9c9a6 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:186afc3381e43aca7eab6d0940acab51fe86dfb04df88fb577a8ca944cfd421c +oid sha256:0a45880def6014da3a07e34a0cd20aee01d6e039c9b9c6aba699a1ee0c150b6e size 1953078 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a index b0b18d89ad..783fb91172 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:57c3b633a523574a0d4d7fe36ac4f35dd4e48ffbe58649decdea8d9241d0ac10 +oid sha256:9a76e26aeafe8f0e927cee5e441d49115df074dee86a6e54574ebdaceb74c01c size 1460522 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 51f3416732..b70f6ce4eb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:97eba13b55fa52d95589656ac3f39daa58cf6fe8479eb7ad32cc62af07a78c06 +oid sha256:86bfaae7ae4fa42eb3052f49a874bde4cfbb60f961febd8500d166f63da8f7f8 size 1450260 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a index 7dc11890cc..c895e6c4c0 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:975eb76e4bcfa9fbe48dcdde8b9544212b172d7050d4b458b04f78aa87340d5b +oid sha256:8b8a18969ef00aed41abdca1bdbd5436a364324944c5d21c3eee0c89b95e5262 size 1916500 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a index ab3e16cde8..fe68a8e622 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1c3f28de5b7aa9e926794579580227e529f7f426b2a01f2c57e18eebabfd5fd8 +oid sha256:7074ff829354192b33655ab56bd2e8d21fc7620fde33a137326b70dd04079c18 size 1866844 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index 57f5e3f2af..6999de53ba 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bb5231b706396aa56522750417b337195662031f34eacf0839ddb5af06f5b38f +oid sha256:dca743339c6fac76f5a0fc379ab06d747a618e2e275765e24bcab850227bc773 size 1394718 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection/libzigbee-pro-leaf-stack.a index 6b922808a1..46cd4ce6e5 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:175c9700187712f697f7b6beae3aa2b385ec8412b3da3f8c24520260ba3b416d +oid sha256:00a1644d66100e760aaaad985fb8ad4298e85d9a0014cc063a19de086ed2db4f size 1504718 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail/libzigbee-pro-leaf-stack.a index 208baa3525..1c91ba178b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b7cb9f220f16cc1efc8b6443e1705461f9d9df0eee054baed970803d77ddd5af +oid sha256:ba90044879ae874c4d9d11ac866fdf7c355f676e8b31c8e8a10d96311e2c6abc size 1990350 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a index 7d17592e98..32ce6f5038 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1e10ae8b40271e36eab792a530c8fdb2ae53a8b5893c66c32bee9cca06b36126 +oid sha256:0f72b19a991d1af2e4cb414136025f9ac08557440e0127bd040216f682290d40 size 1939424 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack.a index 39370e39a6..b10cb36c42 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-leaf-stack/release_stackprotection_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9b148d373669bc832f591ecafe194a8640f628ba0803c624274de62c66935b2e +oid sha256:8d38e4bbc32c927011bb1f4e54ad99db196f946723da0842c770a3e37f234370 size 1449640 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a index a72db9fb7b..e742b6bbb5 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release/libzigbee-pro-router-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6e0a150cf132e4285a63d7b2b9bcc41fb93f9f35ef8abfaa79385d4254523d84 -size 1583492 +oid sha256:918a1ac906093b7849bc68f99cd10033cd7bf7b4003e8c94226863fe0366f76e +size 1583562 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a index 4d61764bd8..1aa896f8ca 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2e3b684a1691085ed7ae813cc30354c5f42a00eb2edf81506936ee4c54f014e9 -size 1523360 +oid sha256:8a843ca86ceb75816ff3c9889ea6afe2578087f24cc85d310510848fc90a6f4f +size 1523430 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection/libzigbee-pro-router-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection/libzigbee-pro-router-stack-rail-mux.a index 2ecbdf27fc..a118e0bdc5 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection/libzigbee-pro-router-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection/libzigbee-pro-router-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1afba1300f11e69641c72c46f98052de6dafc785bc675fea06fcc4be69976cee -size 1640824 +oid sha256:067d4f2bf0c38a642a42421b58eb73b57772f5bc49621c8b854b75e3c49936ad +size 1640894 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-rail-mux.a index dd0b4b34d2..d52ec42fe7 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8944a66de0ad62d2c9936e27c2b223a3aeefc65b6db0861b76e229f8d18a3f7e -size 1578308 +oid sha256:dd4a477a9bcab0c91d63122b207f8b97bf5b454e03b9810c3d92b3145a777832 +size 1578378 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a index a7bbea9fb5..7a9a06ce49 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2acd207051a0af422032619913c0fff89b74df61b64c4ef0799f5f79a009c924 -size 1599430 +oid sha256:a07c0f08a851d56791fbe8ab490c6d7aa302c8be6fe0f98c80a054b984458fe5 +size 1599500 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a index 74c4421f1b..6d7273b2da 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3c7ac6e671995a6bcef61c28a9401419f5f3a597aeb648e6a2e19d7d53e10a10 -size 1537666 +oid sha256:e716c5c5d697c27cfc8908cd49481ebb41cd7b1ea92ba0d446c48484c91f397e +size 1537736 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a index 2e5115d81a..e7e2b1b69e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f954c8f7c590c4880aad836da6d8ca164f0d3d61c292040535d871859537b4bb -size 1657766 +oid sha256:bd03352285fb7610243a67c4578502ddadf56e18938efda771b85a62d6d36d40 +size 1657836 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a index 4444326d59..b5605fe904 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b0dc2d17456dd38579c8d728271d6e770e0f8eccb056fa48fc79e2da4fc59412 -size 1593382 +oid sha256:6d1c3d28539bb227155062b8276775d2c6bf1f73a862e00323e9f21f46b1a803 +size 1593452 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a index 584fc0a825..781589e607 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release/libzigbee-pro-router-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e30d1d734e7e92c241ec0ca42ac779761e19d07e1546d0ddf80b5b2b5cae8f27 -size 1586432 +oid sha256:f1e3bc3ec23548f991c865f3a3de5a923875e65ae6026ead8d3fbe9988e7ed71 +size 1586502 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a index 91dfa434eb..a0b10312e6 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d75a6ecbc8fd61a7aa1b5e77c40a7e352e84973b74116657e8304539124ff02b -size 1524680 +oid sha256:bf169a46bb8ce217102a140ab3b666be9a22ce652c529511baef85ba43676168 +size 1524750 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy.a index ec6b0e6df3..21184d3dac 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-router-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4fc8cd403939ebaeb1fa32c44751bb22f7065e13788c71b6ef2d1f57fa14774e -size 1644826 +oid sha256:3d1312890a75f753e74b99b98dba70e464ae52ccbf8b12937a690ad5a842322b +size 1644896 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a index 0bf94597db..eda9bd5277 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-router-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6abd5ff962b44f5a69c7095834e3c0e29631f9330aa5c38515e1bbd24b561a65 -size 1580456 +oid sha256:a6f6971476819f7668ee059dcdbe1096760b54bb0f205ab44ec9bb0adb2f6a86 +size 1580526 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index d38906d0a7..a87881ee08 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:50a3d1ddde40d9aba2b351c84885ffcf78e6ca57c52243ed82708d2af987ac53 -size 1569434 +oid sha256:7af7ec7275ec11ed0bd6382298fbdb988aa2ca1ec841ed7459f5571ec4645e38 +size 1569504 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a index 503bb1d8ba..0ffc24a560 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:241488eeb3132d053337960aa2edcd565e32358a6100795702189deb58a14905 -size 2039202 +oid sha256:26a204486db15b78d3c1b6ae73501c3198aa156b21f057972a3ac473fd9e8eac +size 2039272 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a index 105bfda264..f338532d23 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_dualrail_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c699312947b74bea09aa7afdd591ba6fb022d9ada12dbc3a6fcc819e0676d43b -size 1986792 +oid sha256:2a0c396aa4d95ffa0007c95ec8aeacbb92a3927c88b5da8b33379eddaaf14be7 +size 1986862 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index aebc72d38d..ae5692286b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4dd410510afe8cacaadd5344e880b01759d28d512200787b6360089b6f57ee28 -size 1509312 +oid sha256:b74e2768225cf2a3be1c1f0c1d550fd917764f9c2ede04e3c844ee95dd0352e1 +size 1509382 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection/libzigbee-pro-router-stack.a index 70164e7588..1f546a11fb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd89c7da20d96a23db8d6527c944cc1641edb1a12873930f566d2053bca02f0a -size 1627508 +oid sha256:5ad7863c546796e926b1c2ef35acb2e9ad0eeed310c5275ad9eb9bc44f06e7f2 +size 1627578 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail/libzigbee-pro-router-stack.a index 16deaaf3f6..f36e25888b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a55a65a7b38adf1f7096139c6e33aec6d6dc8d239520d2cc931486a19b85a9b0 -size 2117662 +oid sha256:cc36945dd342d5aa1f92ef99a19e40a728272611d95ee55da4a134e501b84f6d +size 2117728 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-router-stack.a index 034aee3f9e..eb7d859023 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:91d584285cced638a1cdbee4ce9b2550f99c412a50ca4c165629e3d9c5a5da45 -size 2059810 +oid sha256:bf4f9935b2ea64b670d1f93a6c72651f9ad24b40a28477e244fa42190a3bd82c +size 2059880 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_singlenetwork/libzigbee-pro-router-stack.a index 075554ede8..84a1af4487 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-router-stack/release_stackprotection_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:933e7fc0d155e8e651e7789e23f044c6d06a602eaa8c32aef549f924b547b743 -size 1565002 +oid sha256:e61b1ae6317a3e869a94bfd8945cc2886e03cc99895e469ac0699e6248943323 +size 1565072 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a index 0f9d9439c1..0ba946301b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:73efd883a1976009f4a78fe6770a21683bff9136776fee4db65bd457d8f2b7dd -size 1772920 +oid sha256:aa16fb7bd23261dbc69612d6b39fa440c0cf145ed915d09ba1a5ff190fe376b7 +size 1772990 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a index f01185790b..56178e977c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2c1b754dbbc8d06c0ec3ba88cc3466446bc6f1f387cd036014170ac69ca4e2e0 -size 2234628 +oid sha256:fd8e8d63b6be36e6b7df15ad4fb1b57c7efb9d855ac48c33d776ebc7b9a04755 +size 2234698 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a index 13de6b3897..4a9aaaa0b0 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:db93428e3aa6a7f544a9cbc55f6cc88d392f99336854399178f050fec82f43c3 -size 2171992 +oid sha256:b73ff76f358c36812fc0be9be621ea5767945abf1811153135272395c1164a38 +size 2172062 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a index 20062ccf8c..ecc1405356 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_singlenetwork/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1745b2eb00e5310b540e8655b80b63a339410c6f02a0291312699a1c192239ef -size 1711114 +oid sha256:20b9395908e27b7f743a60397bdc07bac66261d3cae1323d344fdeb013de95d3 +size 1711184 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection/libzigbee-pro-stack-alt-mac.a index 667ede6afa..3243f1ef7f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4bb046bcfb78867c4ad5a65266e69d056c2af6dde32869a73bc2b9fe0f5166e7 -size 1835334 +oid sha256:b01729a6df535ae7c8a7102b372df1cf59168963c29dd6a4fb2600f9bb10346e +size 1835400 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail/libzigbee-pro-stack-alt-mac.a index 8eae8f7463..8c81f7caaa 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d6ffa9bd8799c758d7a9ce3385110c5600608cd5eb0197082f9dabbabb6692d1 -size 2315402 +oid sha256:77a8c420fd0bf7ab8d5f976a7a8ac58088635305f484789e5820d322e087b2e4 +size 2315468 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a index a84bdc80b3..29f5c02c7b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:00c3bacfa5d87b19ad11876a9d2f1f474d8ddda747bd04f187b0291786ff0986 -size 2252466 +oid sha256:18d424f7a49c6c41d2dbb40f3345ba2e5e4936f819ffee702c92cabeec3a2242 +size 2252536 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-alt-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-alt-mac.a index 5dbbacb1e1..f49b008cdf 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-alt-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-alt-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-alt-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2257a51b6c31c7e9e5665f1c0600d3a50475915f3018c2dba4a7a12d3f18f354 -size 1772962 +oid sha256:21c944e43438903dcd4e1da5c86c901cef8305ca267c1d3a4587c1f07ed9de83 +size 1773032 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index 7ced573871..065fb19076 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:07561542eaab6d53b8b36cf3996a69d0c24b1c6970f91cf8219f9871f346c5ea -size 1756076 +oid sha256:2ba7384522cd3beea7374b99f52fedfe363a9570a09eb454956623c4cf26a33e +size 1756146 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a index b4598e9006..bf41cb753a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:55a2c7425a73f8135624a2d6b7918aa2acb3dbcf3af6be1fd90186da8f0fecb1 -size 2223040 +oid sha256:f152ff1e41fddc411cd944323f371d6963cea7773556240b901fc939edf284c7 +size 2223110 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index de1f87ef79..b35d16d508 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f235492794e390ba9bada606d73103c84eacf989950a93b9cc9985bcc0f41b3d -size 2161890 +oid sha256:3af6732230d0135d0b116cb3c49a2731b39aaa6116220c4354de895f8ba07062 +size 2161960 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index c1692785a5..50cab1d4b1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:239513d4dd9976f15e4971038a76771e5b0d16298aabd24c6d792a8cd5a51c3c -size 1690592 +oid sha256:0ca2324186be81adbe0159553f1d7a46424254e8f8d910d5d381175725b632a9 +size 1690662 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-stack-mac-test-cmds.a index 2f34e66a78..2970ab861d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:510515d98ce14ece3094ea1cbe9a22981cf24b28e1a27f74caa37066073c0355 -size 1813674 +oid sha256:bf11e5a189621ee59083ca1a1ed74df0df9e298970fbf8417f03304ccf02efde +size 1813744 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-stack-mac-test-cmds.a index 04eaf0017f..a9fd43da5c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b01b30d15bfe896622e776150c010d5ddc04c1d5f26f4a3a10329293a7a3a043 -size 2299158 +oid sha256:94a25154c220f7c932a5961290cc943a83cea698bfe3f40c348549fd3d43d226 +size 2299224 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 82e8ce870f..9e66146af9 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fbb458a43a68effd500f3ee1a637d1ec7810d26e23d575f8dae1517c7eee2497 -size 2239088 +oid sha256:28c4f4a13bc288c67210e4c54303441c1d8f8c7ce8bd9f2ef050a518f45e04de +size 2239158 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 8a7be509d5..74d86fdc36 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1917fc521ea791e4dd0c0cd3442b8639d6a5c3157f6071767baeecd268904303 -size 1751606 +oid sha256:d687849394418a2fd21352f0fcdcd4208875d7b1403ec01bd8d90cd24ccc9ea9 +size 1751676 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a index 2423db1119..408ad9bd7f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4eeab0e71ca2af60c526a0486155af5f5fc84ecf88b41df1cdc2c98f0db244ed -size 1759906 +oid sha256:2df94d2a78c448533696882c497fd1b32fc1373195604de80432be6b09d0838c +size 1759976 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a index 67374671f8..f12ee2e6a7 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b66cb8f029bee988d110fde84a20dff30fa1de04656a8238333546585798c95b -size 2221034 +oid sha256:d5eaaedfb8c06016cebd841f5394859cc8c6d4de15fb139f9e42b7ed1230a63c +size 2221104 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a index 2f98faed38..a9b3ef348f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a5c03d72b1894ca3541b685db2af1c9193ff8ff97b8cf05dbeb6d31a57720ba5 -size 2159286 +oid sha256:7bcdaef8b103bffae2f35849f716afaad661835950c3f71c2ee446b471c7650d +size 2159356 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a index b5c0297f8a..0c1e471149 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_singlenetwork/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3014b2faddcad583a66b74659bf0783c981556c2e8bbe7755c4958fcd927b6e0 -size 1693690 +oid sha256:ad7ea90c02fcb1377713865a4f2e1c3d9f4a786744708ad0589538a402c9c1bb +size 1693760 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection/libzigbee-pro-stack-non-default-mac.a index 91283c2f1a..231500a324 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:acee489e9fb8853bf0a7d540c4a6f0b587df63be21e2fea38ae6b964450f9845 -size 1819750 +oid sha256:acd81914b8b6c47bafdee2952519f4f9918521ac42c127d9091e49e2a242bd59 +size 1819816 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail/libzigbee-pro-stack-non-default-mac.a index 522e6b1c3c..ca72acc889 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:12f390482bfc05b34e3f45e6a9294b381802cd4fef59d02ceb42452c728b66d3 -size 2300234 +oid sha256:cd43e88c37c4309429d126fac06329d226b422b49b4ae58966c0952b02f502e1 +size 2300300 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a index 278ee2471c..df42267247 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:07ad0c475e51e9a7adbc21492692de370844baafe8d65419feb00467d5c86701 -size 2237452 +oid sha256:7879e12a7403549ed9d40ba46df942379676cf461b767b6abfdd9561276acda3 +size 2237522 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-non-default-mac.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-non-default-mac.a index 03fd3c4ef4..0595ee0712 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-non-default-mac.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-non-default-mac/release_stackprotection_singlenetwork/libzigbee-pro-stack-non-default-mac.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7c1da4d7d2c85d42e14484bd8bed60a2de0b3dd00ac9d5a3410aaa678822841a -size 1756384 +oid sha256:caf49be2385592399517625c04a2e07a9738a03ecb141b94ab13d0f050cdd1b9 +size 1756454 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a index c764dbc343..cbbeda3095 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release/libzigbee-pro-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b37a057b7c4b881096447b77fa286d4bfa4253934f2d84727f7e49c099ce1c48 -size 1752584 +oid sha256:a1bd48b14fb9e77cfcce8cd2755792dd0c49393c89de92beb3c3b0466ed2044f +size 1752654 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a index b54e479638..e808851c7c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_singlenetwork/libzigbee-pro-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f3ffe3fc9b3469a115194d4171807696a6469df9ec582a08550995b86a3052ac -size 1686930 +oid sha256:a9e954e0590047e51277fbb4a18c03cc352f3eb0279b070e9df5beaad463a2a2 +size 1687000 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection/libzigbee-pro-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection/libzigbee-pro-stack-rail-mux.a index b175621d26..f0ffa286d4 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection/libzigbee-pro-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection/libzigbee-pro-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:79dd619b2651fb1662def7dba302e20703bce8ce30877cca7dba96933983625c -size 1811776 +oid sha256:a089c26798df22b4e8a1185daa3f13fcb75edf58373d77371a47ea38396fb231 +size 1811846 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-rail-mux.a index 616c5d2b08..45b00cc1fc 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6d1579c4e7e64094d543ba43ea7ca4567a92b757da0e58c74f1cd7e90971b0e3 -size 1748760 +oid sha256:1b31e667134b66d5bfd33cc4cd0ba91ba57833d6d90138749dffee0bff3a88b6 +size 1748830 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a index d6a42d86e3..cf9c7df393 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8ed92cdc227b9a2ab5f26cbfee6ae6d7fdcc00acecb1b3cd854613fd574858c0 -size 1768520 +oid sha256:ac6da25b4be03b9511d9b7615f2823609fd3e4ee6af831155e5495f777c62db2 +size 1768590 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a index 0728a5d49a..4233370f31 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0ff779ab5b4c3eae1962980d53ae38d4efc198bf078a7fc2b4ecfdcb11a1304c -size 1701234 +oid sha256:300350b34f68df50de7f00bc217ac9ee1c970693b66950390c386483902c0942 +size 1701304 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a index e1ad3a491e..1b5cc8572f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:266c1650ec5d5b1f2d750240d8a70501fd45aea31555c1386eb4448395fe3b1a -size 1828716 +oid sha256:3e9fb46cb3173061b180643366a3979d871abaa60890ce1b13ea57f36eafdc15 +size 1828786 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a index d691f45962..1efdbd413b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy-rail-mux/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy-rail-mux.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:37bb823905a09acb0b1a657782d51131d4376c2e0dcb95b2ea1efb23e26d79e3 -size 1763832 +oid sha256:f870ba65cba8de5ffa80c7222762eaa28203c53d8d08e6298a29880e9b237942 +size 1763902 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a index e539a29f93..379af7d6ae 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release/libzigbee-pro-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:15274d216b01e92c8769f4b989050859019325fe2fba2685d4f495682457e6aa -size 1755524 +oid sha256:2cdcbfab889bbbe0e776213a268987bb0957a667b67bab11d90c86799d7885e6 +size 1755594 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a index ce57c9564b..4c71d958d9 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4fd87394dc561d071a4963a8116afb28e37d126ef59e30ccd9f10183d2e1f1af -size 1688250 +oid sha256:bbd37690e812e0bac3e6fa11ab0a19e5248774eecf68337381dc4037290c4d97 +size 1688320 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy.a index f780b3f3e7..25f5b9a0b0 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection/libzigbee-pro-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2aefde2b8ea5cae43207299e2f42a66f9fb6dab995e0e5c1e3bdbeeb8e96fc57 -size 1815778 +oid sha256:66593830abdf69395881c0fe0daa0c96ea7d6b8f60a231c26e30a3b23b1fa906 +size 1815848 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a index f69961d287..6bf2d542c8 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack-with-high-datarate-phy/release_stackprotection_singlenetwork/libzigbee-pro-stack-with-high-datarate-phy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3e7595ecd0293149186c49e85b6da5ceb7c1a218012d854f0f61c61c9f887809 -size 1750908 +oid sha256:fe2a8872c2c1e3c2defab7698ac4817f0477b1775a86ece9a3c878ee41135606 +size 1750978 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a index bb741deff9..b6752ce613 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d4d3fbbccf384c3d723e2ac6010de042f13228f24599be1fe134243a1a20c400 -size 1743068 +oid sha256:62c0dd8977541b73f2e6ccead959e669c75ca5ed5805b668625b6f82e7bee0a1 +size 1743138 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a index 4128c7c951..653bc078e5 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e6854d1599f225ef5b8be50b2103f5815911c5a27e458c068dc6b032a9bec3df -size 2207094 +oid sha256:f6e9748973957ae1be48f3170091deaccbe1b1381ee67b05feec39c56952790b +size 2207164 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a index 00b6ad451f..f9dbbaacdf 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_dualrail_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1f8a67551d2d7257222e47cecf138a74073914c9cba358260934105b6cfc5817 -size 2145744 +oid sha256:f60d5a19404e4a26beb0558a189ba7238aa858d0eb71ae583c6c7126c55728ae +size 2145814 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index 015f33f206..d520931ea8 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:88da3e64635222a2fc910156005b1481517fa3134861b2cdead5ee46bf945ce9 -size 1677424 +oid sha256:383122b015cbf6dbffcc1baad7f896495b4defce3578031afe8621dfe57ce225 +size 1677494 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection/libzigbee-pro-stack.a index 2bf73215d4..814903da86 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:77292357f9153155e965fe3f2cfc0cf5bfa5fd20b8ecc804ae347220fec6a1fe -size 1803002 +oid sha256:615edff924615f58273c8c4c622be0c8413e2b2a802916788e0b935702e93739 +size 1803072 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail/libzigbee-pro-stack.a index 4c7cc87eae..251134c445 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dbbf9a56e1ade90a739da95204f884d7d9b20e57bebdb77053d49e4b72ff7edf -size 2286440 +oid sha256:7f5cbafc648348476c5fc7c7688011f600be445a9b6ad820a695ea2d07f625ab +size 2286506 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack.a index 2546aa1518..299ee0fe84 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_dualrail_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94d6fda8ceba0f840a9a35fdc04d548dbff3c0a41c69bd06afe9c4488db5d2f7 -size 2224634 +oid sha256:4d413ec17bfe194ba1c58d7e428586a687eaf351633b50aa2a606dd712dcbc7f +size 2224704 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_singlenetwork/libzigbee-pro-stack.a index 6e11cfec43..7c0a61ff82 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-pro-stack/release_stackprotection_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d78ec77063cdc17c8e54f97a77d37b18250a6236f07f1079d9772b82c0c8f642 -size 1739996 +oid sha256:40262430d0d32841bed912d5f8028c918517ddd2de93c82247d745251a2df114 +size 1740066 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a index ba02e5b989..52291313fb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:15b543f43715681818c2624aaa72d85b181793e6daaf50cdd4068cb22a364c8f +oid sha256:48b50659f7eabea813f147571bc2859e314669562617b46829082eb939a2f663 size 49490 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a index 1e94296baf..92e6752b9d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:519911a29253f516c3372970178b5ddf9460397d17dd1b109d4ce99506989e9c +oid sha256:abe54a806ff7ef116e18f3c3dd23d84ab689fced4217a78497fec3c228b89e63 size 52542 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index ce5d17f18e..f0a23b9e6b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dffd452257e151956d42edc86ff696d7ee0337f464188c328f34cde5052e362d +oid sha256:1bf6b3c01e1e5ec3d2018cdaeecef1e142a315fc4e4abc12d11fe079838a0502 size 54052 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index 977a309733..0fb7c3d6d3 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd6258e1dba717cf815d1fedc3b7612cc79e67f7eca127f3337ac9056efd249d +oid sha256:55cdc41b278318d29d6491a6695cf878919693435b70d7dcc6623511875930b2 size 48850 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection/libzigbee-r22-support-mac-test-cmds.a index 566551ea67..0d57d36e6e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3a27169ee496c79aa09641bf14b8ec91b9e85bea24a26f0c835799d53d4fd517 +oid sha256:4ac0a129acd99059317298b962ef7e34ae648d33cdb0a964343d88f2505dca36 size 51212 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail/libzigbee-r22-support-mac-test-cmds.a index 42dc1ad1d1..1bb7615682 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2a11d7b865152e7a0fca86c31b605a6ebd35bf39ca14f42114ce68025ea61945 +oid sha256:997380f18a0f1666146082776ca535eec6636c0b63d972ec8797e87e051904b7 size 54316 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index f362d1e76d..c447082576 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ae254dd899e1918e6db46a23b12c4c537252d0be7000df10e53722d265e044ae +oid sha256:e4753f3b16469770cf3412cb3d8f5520dd6582df953c51c47ffad98fa7e9726b size 55836 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-r22-support-mac-test-cmds.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-r22-support-mac-test-cmds.a index 9629474d97..fa70c6483c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-r22-support-mac-test-cmds.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support-mac-test-cmds/release_stackprotection_singlenetwork/libzigbee-r22-support-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e913064262f0e17bd33ec1f6c5dfa1cf350b03508ac59136be14cff440e38d8 +oid sha256:331ef03c8e452e0b4a8f2760eec2b4830ec4004c386b4dd5569051f8a7c2d560 size 50632 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a index 38e0bc2ace..a7416bb167 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9452f82a4fc28eb6222a808c23f05f0a03e3530d6153e53c525ddaa474fb1148 +oid sha256:2104d031e441a559147262740137bd2d2dd1727a5a7b63c110f7a0b6baf8c7db size 49000 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a index 8583ca90bd..a50b73b034 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:be1e9535f1e190182153d35919af051cacb11cbe9a10572db3d076877db3ed38 +oid sha256:fc9f1c5392b6ef077f4b0c36fe501b1ab536ad2ddbfe59eb015f76a42e20244f size 52052 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a index c96d3b408a..e7a48bec84 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_dualrail_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0025c29db77db69c87c8cd6ac94e0de124e5d38915f4bd69ce32b423883c2bde +oid sha256:fb0a4c0faf86491ec0d813735335563a5ef75edacfeb27c7d03850227897e0d9 size 53562 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a index 9824b46eb0..bcf18f1181 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e56cef4c120416849e37b87ba9b4d0d0579567644419cab659aff56f1c85f2cc +oid sha256:e171f1d536efca32db208559541b6bc46f30f99b3bcfb51ce12bcb648c90d6b7 size 48360 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection/libzigbee-r22-support.a index c4eeec1c3c..90a0ccc4a0 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:639c5114984da874270ed9d4caeb566cd539dadee654fd21798b9b3c3624b7dd +oid sha256:1eb57decf8dea491535d49ccdcb3b2f2cd3975cc0bdf23f3edc7f8d1d7d64711 size 50722 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail/libzigbee-r22-support.a index de9fa5d46f..3833f2c76b 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bf0bc5e31632b3eec1d9d9c94c67e45734d1ea95357111cb4d77c11b89dc871f +oid sha256:a273a8391fc8a8ef5032744a524b0d739b79e40aa698818d7d1ed961c5a410ab size 53826 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support.a index 1e6076554d..bcaf9f161c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b860dc634f88d5ab9042da596944d9ec6ce8cbf7bb78cf8dc7653059fa4ec86b +oid sha256:8e9f98f5bd1560a4dd6391260c6bf9c251f45ed14973cbff46a9009d106f0b19 size 55346 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_singlenetwork/libzigbee-r22-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_singlenetwork/libzigbee-r22-support.a index 927cfe5589..475ee70909 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_singlenetwork/libzigbee-r22-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r22-support/release_stackprotection_singlenetwork/libzigbee-r22-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:342f9b2fce99f6826ca8245907663ff2c2c7b91e2b996477087436b63edbc5c6 +oid sha256:1231d44554f904cbac60a96644c24b8c2c3d0f094b14cda4ef4c834bee5656bd size 50142 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a index c070f366cd..0b7fa7e31c 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:68496eba4b7b6fe0f47668ec1a96e5b4c7696dc252b5e64428cb08693748c2ae +oid sha256:06d18ca546b17d492670aabcf587678ec53e27024d5aa73dbba352d00f78acaa size 186278 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a index 8ee79acc61..c4597c63df 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f4a73a089a6e047b95e32075ac875db2cb667a652ffbd02a0224f4347428d7a1 +oid sha256:88b30995cdf195f9b7607c2708c9163be80ac9d7d9bc413f7042388826adbe2a size 198674 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a index b36e6980b3..79a4cc1da9 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_dualrail_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e8087f87b1f0bc191c8b9b6a909ea35acf4387bb0f06927bb29d0d85f5d8e8e9 +oid sha256:3cba2d8a1bf01bf23101952b5264537b330cf49c2a7e751455e9805818648ae8 size 198650 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a index fd44a863ae..1c8d91302f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a3ed96e6be44cfee6a8c864863ad5e2c61a5e8e509171e6fc8ff4b5cd58684d5 +oid sha256:429a61f5a96be2382e3f802d89657bb85860412fde1219bf4d431062f118eda4 size 186246 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection/libzigbee-r23-support.a index d7e906fcf2..a160a284f1 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:194cc30b08e03531e40fec78f1049f25763e625705465a1b012907c7e5cde205 +oid sha256:84eed6b9a25db67c0aa036c1abafb36ec361b7566cf5a99b4f635773eafe4c64 size 203096 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail/libzigbee-r23-support.a index 68c91f9c5c..cddc5c6ac9 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c964d5d44e765819b20d6a8aefd9408b5bb4354e40781a6d73c3f4d0d4ecc8d2 +oid sha256:8ce68f88c2adfc564782401b1f7687b13c56bc3ff84bccff374d691ee7bc26fe size 215494 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r23-support.a index 38d7bc8658..24fb929171 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_dualrail_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:46a38186c6f78cc23002f2f0534db493ef161f0556376dc58de92de23e5eab4d +oid sha256:e748b9ca42569dc96f87bb5303cb55ea5d43ce3e6f5c44212b00cb1712cefb92 size 215472 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_singlenetwork/libzigbee-r23-support.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_singlenetwork/libzigbee-r23-support.a index 99e3b2d744..02de9093e4 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_singlenetwork/libzigbee-r23-support.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-r23-support/release_stackprotection_singlenetwork/libzigbee-r23-support.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1bb1c842ecd9f292c1da8c60a0b93d21f2fd9df49df974ef4a35865d57bd57ee +oid sha256:12dda9a65f5b45d81e9ae7163e94d339c1030a4d33a3e5aa275f5f3804bc264a size 203078 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a index 90b4803d1f..638b8b161a 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9a43e80f24d9e9a76e5a721277bb0d2428e76c32bfb27981a0d78b26f1b44f0c +oid sha256:e7e95f1be72bad535815f610862cfc8851112c99e463fd1ef29ebb01a67230e7 size 42640 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a index 8f0d823204..8d1adb186d 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e2a860e877d43a4f6fc20f6bf6795c16991e2f1618a268ab5ab17df88b652c0d +oid sha256:d399907253c986abef6e1cc8668436f390bd797a38934c7ad4967ba0b3a2f0fb size 45116 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a index a11996bd4a..826a20c752 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_dualrail_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2df14784fd9db9132a2b5c3e3004ec09c5e806640b6357cf546ee415eae349df +oid sha256:884572266c9221f38e72dd4f1e6d1026d91f896cda89884ab918bda5afd8616a size 30342 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a index 438056b18a..cfaa2b1d69 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7bdd9378bf3f855f107367d381ac89e152337db7d3341f866815220fa1fa9027 +oid sha256:47af665f428fcb6da66be7e794c9e7fa227cc84edd50d9aaa847c904370ad9cd size 27864 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection/libzigbee-source-route.a index 4dbc5c7620..62e6927ccc 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4e0c5f475d66c3df2842f4d2d605e8d6b875bf3fd763628fb5b25f382641ca26 +oid sha256:a2faa2b04de07e185a9755185516199dbb44f48de215e94256f84dc4227cf47b size 42172 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail/libzigbee-source-route.a index 9e1abf9433..c37198e971 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:084e970527139d43cb5ab5dda9713181aa003d456118e51e0878bcf06b199811 +oid sha256:5c6287b32e6932538f1875dad8e1096ee6dab05e262159cadae410e7e31dc3d7 size 44652 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail_singlenetwork/libzigbee-source-route.a index b5ca321bf7..98c61e9bb5 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_dualrail_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:85983484cfa0ccad13975f42fe859100928d119b358d3d59e52481c55589183b +oid sha256:54afc7229c976b834eb87f38c63e504246d089d5646d821a5387d0842a2a5c6f size 30956 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_singlenetwork/libzigbee-source-route.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_singlenetwork/libzigbee-source-route.a index 4bac07dc67..26da160c0f 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_singlenetwork/libzigbee-source-route.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-source-route/release_stackprotection_singlenetwork/libzigbee-source-route.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5d8a5f438101a2365bb9376cab6706ac2dd6d3b58c671bf4851a954567d2c696 +oid sha256:b1af3b4adeef4175dbafb5a21ad80d4a08d466e330c517352b75577719583594 size 28478 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a index 18ee6a4bd4..472ed64145 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d50f2eb384e38ad6f496f2d8dc10974675003bc89f729ba025e7dbb2bbece0b5 +oid sha256:b19b7bcc7045a9f1e104ba56119959f8920babe25a94c8005724c933cef267a2 size 8708 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a index 7fd32f18f0..4300ffa0bb 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9dddf256b8ce5eeccacbb00c9250c6c04eec4a6a6f052fa1db7bde7afe70b63f +oid sha256:984372135034d14f2aaaec547e742fe13986e00354998f5a15cf6bf865561982 size 9948 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a index cef6a231e3..0de163866e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_dualrail_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dcf5dee64130bc54035f3658b5cea76a0a05fe8f8abf775d61ea4660c0bd036b +oid sha256:e82e20540227c7751ce380257919091b648dfc66a6ec02cbbf7cdde1bcfd74c3 size 10024 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index 879029ddd7..1f5d01d0bc 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:47af5ee713bbf35e3fad9cfa723a652ef9c6125220f2b0d8e6ac20fb819b1710 +oid sha256:78bbc470c96042ea79c97abecc21d3e603c7470c7697cf7aaa0c469ae7411a18 size 8786 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection/libzigbee-xncp.a index 6be5e8fafc..cbb0707a9e 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1c18f834d14d0b648c3c0b1b5fde83b8ac2b616697c4f65a995c60b093b1bf5c +oid sha256:1f77d716bdfd078e365dcbe42abb71ce215d3711a1d7305d051f559714dbadb7 size 9244 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail/libzigbee-xncp.a index 5e62d398e5..a8664e88c3 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:09fbf536629c9ab1ec3bea4c5f9bf44364699d4cd6a83154c0fda9813a49d919 +oid sha256:95930e89fb053b23e909367a059a2eac49675b0f7f9e0c08435247f9bb3d2234 size 10482 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail_singlenetwork/libzigbee-xncp.a index b862601934..de646c7812 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_dualrail_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cd5f29552aebd7000e06c8875155f558e7525cbc421775a913912d6ea56af10a +oid sha256:1eee5a360a2b9e645b9dcd4cea13b4995eac7da1a1e15d1e5df0f27c06ed3332 size 10560 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_singlenetwork/libzigbee-xncp.a index 813e893909..b6b3cdc065 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-xncp/release_stackprotection_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:562463d58858cb6577a198d6f11a4851b2235a29d8b514b3e9867e786cfc3d16 +oid sha256:527c286a9922025498caeed9de7911db68b8805dbed72d8cc5044c45a139192b size 9320 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release/libzigbee-zll.a index bd6088f289..ce471a79b3 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5d1d3467276f703c5dd97a3c4b3a436a4359262c54cd2ffb4d7aa2350752a272 -size 112344 +oid sha256:eb458c441051c523277a2e217349a3d6feba5d144aaf335025631ae50ff90fb2 +size 112630 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a index b285ed0f17..0de8e70145 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:de77d8fcde64fc4fd37364e972ba56abc5a23670eb331610dc457af9b9f9368d -size 118540 +oid sha256:a34b9ce55dced823d9e357ae38350e27db40dae0909f9da75eba1b862d327364 +size 118826 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a index e53641828b..dae5c8ed74 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_dualrail_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:168ce4c2b15f7c5df46150637757cec85c8fe1b9fbcbcbe6e088c2ec2b7da756 -size 118296 +oid sha256:dfb5577dc35cb22b3ed03f7bca8c8cdcbaccc4947884da3867b41ba00440f1eb +size 118350 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a index bfb0c9ec74..07e97a1893 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8d475143ae893698579e111e8501f89544636fd5c1fb0dc7fabaeead461eaa9b -size 112102 +oid sha256:4591ba3297c9908f85ca380d003254551f3703221b0d5f3b451ea84a113cfded +size 112156 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection/libzigbee-zll.a index 891b98f6fe..d3c8aad7c2 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:48185a8e75fdf4b73c8b6c03ee4958c4727cb316a49b184a7f27ed6d4baf3f93 -size 123138 +oid sha256:6067cebb0b0aecefda42e3d1d2ffc9463602b8dd941044d7c5b3c1be8c7094f3 +size 123424 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail/libzigbee-zll.a index 32860d1f00..485a151194 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:26da2dbab3881744977cefe7352b4e7efa2942341068b570140d6d115414ab35 -size 129334 +oid sha256:9e4031e1ace9b7363a1c1077841c934d110a8284ef57b207feb556532cd93c09 +size 129620 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail_singlenetwork/libzigbee-zll.a index 91ab1dee83..6fd6c4ea14 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_dualrail_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:21a45656f1ae403a47687c7c70ddcc4ef8f5fae0fae0ba465da32da6023acf18 -size 129142 +oid sha256:cdfea331380b626867a3564e5f117c0ef7b2358386412974351a554c30f08207 +size 129196 diff --git a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a index 06bcf8752d..536d443996 100644 --- a/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m33/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1f8d406b8c530b110fb9e1d73f91ad2b80a044a32b6dc09951b4a7d4c6c74ee9 -size 122946 +oid sha256:0d6ed74cb64fc4e17e5b6a16fee93d9f6782e8597d41dc41d1988599467d6da9 +size 123000 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release/libncp-cbke-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release/libncp-cbke-library.a index b1c75a7cf7..8f5fde0101 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release/libncp-cbke-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f0939a9bf283ed22eac2fe5382b24393fddd93ffdc5b90c1f7a436d356c50c79 -size 45786 +oid sha256:1a32609d8d0171f0b6f34f052cb3a762e77e5b83e54b2f3aedb1220d6f500316 +size 45858 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a index b1c75a7cf7..8f5fde0101 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-cbke-library/release_singlenetwork/libncp-cbke-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f0939a9bf283ed22eac2fe5382b24393fddd93ffdc5b90c1f7a436d356c50c79 -size 45786 +oid sha256:1a32609d8d0171f0b6f34f052cb3a762e77e5b83e54b2f3aedb1220d6f500316 +size 45858 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release/libncp-gp-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release/libncp-gp-library.a index b66bee0294..b885f3ff04 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release/libncp-gp-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2498c2670b6d411eebf410fdce670d8005ed665a6da3a93949beecdc24d47740 -size 30288 +oid sha256:376031edc32691df871d7aa142764542b42cbfc2b832bb0f8f92b4e2ffb905eb +size 30360 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release_singlenetwork/libncp-gp-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release_singlenetwork/libncp-gp-library.a index b66bee0294..b885f3ff04 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release_singlenetwork/libncp-gp-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-gp-library/release_singlenetwork/libncp-gp-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2498c2670b6d411eebf410fdce670d8005ed665a6da3a93949beecdc24d47740 -size 30288 +oid sha256:376031edc32691df871d7aa142764542b42cbfc2b832bb0f8f92b4e2ffb905eb +size 30360 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release/libncp-mfglib-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release/libncp-mfglib-library.a index 5d13317a82..07df7f1840 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release/libncp-mfglib-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:00c3a5b0610498340cf55fef4a42a2e82476be4417d792d3cbba2ebf8fda99c4 -size 33192 +oid sha256:6ff08b79bf91ec73473be3f6c338a9c6f1356df005b962b9d125e9f5db942746 +size 33256 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a index 5d13317a82..07df7f1840 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-mfglib-library/release_singlenetwork/libncp-mfglib-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:00c3a5b0610498340cf55fef4a42a2e82476be4417d792d3cbba2ebf8fda99c4 -size 33192 +oid sha256:6ff08b79bf91ec73473be3f6c338a9c6f1356df005b962b9d125e9f5db942746 +size 33256 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release/libncp-pro-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release/libncp-pro-library.a index 072c1a9f91..1b7c34ef48 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release/libncp-pro-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5c6fde07193e5fa2b4a33de17ff64cee10af87cad31ec89dc2c05961b211d8c0 -size 261602 +oid sha256:ee294ce239c97e2e4d69ab982a035ada23663dbacc417e3fa175571186f95112 +size 261874 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release_singlenetwork/libncp-pro-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release_singlenetwork/libncp-pro-library.a index 7d126933ca..736262f8e0 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release_singlenetwork/libncp-pro-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-pro-library/release_singlenetwork/libncp-pro-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6874b092f8a820feb28546bbf9e891c33e69c11d75b4f340790b4aa4d8ee638a -size 260690 +oid sha256:80ca6d073f3aedac1e31fd6bda304c82217384838ffc66aef4b2658266c468f0 +size 260954 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release/libncp-source-route-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release/libncp-source-route-library.a index 6ceb66585c..67442a95c9 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release/libncp-source-route-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d3902a8489495cb34fedd536656c15d848755da1e6e2ff6f9841fef7f33bfb82 -size 31526 +oid sha256:7f2f5ec55298ae12d5d328ad8fc6733b090e79e068b37bde18e9000f9c428611 +size 31590 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a index 6ceb66585c..67442a95c9 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-source-route-library/release_singlenetwork/libncp-source-route-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d3902a8489495cb34fedd536656c15d848755da1e6e2ff6f9841fef7f33bfb82 -size 31526 +oid sha256:7f2f5ec55298ae12d5d328ad8fc6733b090e79e068b37bde18e9000f9c428611 +size 31590 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release/libncp-zll-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release/libncp-zll-library.a index 0887036764..4e56b0fb71 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release/libncp-zll-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e7dc756b81e65a7fe7e7048ecf74c1d01facc8a3471802f61766b45b7054491b -size 41200 +oid sha256:c3a3fdd1208ce195b0c17e288e7db2edeb33a0a09e3912f59c5bd614d80639ff +size 41264 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release_singlenetwork/libncp-zll-library.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release_singlenetwork/libncp-zll-library.a index 0887036764..4e56b0fb71 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release_singlenetwork/libncp-zll-library.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/ncp-zll-library/release_singlenetwork/libncp-zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e7dc756b81e65a7fe7e7048ecf74c1d01facc8a3471802f61766b45b7054491b -size 41200 +oid sha256:c3a3fdd1208ce195b0c17e288e7db2edeb33a0a09e3912f59c5bd614d80639ff +size 41264 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release/libzigbee-ncp-uart.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release/libzigbee-ncp-uart.a index fdd0c248bb..232445d743 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:35c3f7951aa339514b0c310d9451c0fd8e0c804dfde0e0f713078630e950369a -size 219500 +oid sha256:24bed51b80857c5b661f64029e224e28144dbc83e694b129d509a6b7e98a8ad8 +size 220278 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a index 32dfd422a3..ee7a8aeacb 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-ncp-uart/release_singlenetwork/libzigbee-ncp-uart.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:29aa2370c09eec9ca19d20dc3b6aab300f7e91184616691586ffeb63a8bbf49e -size 217852 +oid sha256:65d04fced4a0fd444bbd6b0d1ede929d54278db81b130a6e10e3eb9785a12fff +size 218598 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a index 97e6d256d6..f5a459ca33 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f26a4b1868afb7aca666aca6399fff58468b309655528a5b4eb2ad7ae52a7844 +oid sha256:060b53fbec66f7dd49152086be3e86cb9f241628b09d5ff44d9250c37d28a762 size 1836538 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a index d61467f9f2..eaa626646d 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-leaf-stack/release_singlenetwork/libzigbee-pro-leaf-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:599cd1065d2cc4c907d406cf036017b8f9a19162a021a5df691f8e43a2a46dab +oid sha256:f033033d5833fffb44e7fe229a5b9eb9305c90e4d3a709d98a6b07770b0a33c2 size 1781002 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a index d00dce6a4f..3eed136763 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:73bc342fb15281f47a4c2c33dac2ee8112c15e42d403072d2be3ab00e6aecc34 -size 2038430 +oid sha256:8ac20bae64997ecb4fe90192b46e93215a5696a0c7670ff95ad21d4efa6b4113 +size 2038550 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a index 76cf1ea0b9..c643665e09 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-router-stack/release_singlenetwork/libzigbee-pro-router-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a3aa8f3a52d6d2f3a9bfb4a8ab3c7e7efd63585d73e1ccabe0eb4f7992e2d17b -size 1974000 +oid sha256:9b68e66b85308369fa732a908cbb22c358b2362450dbf36008ba6b5a231955a5 +size 1974128 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a index 4e48b8d574..361555ced5 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1d6a1bda1098130c16b6d5facb00cca2b404b91c09c8b48969354606d0436ed5 -size 2091004 +oid sha256:b36e88bb05deee29ebcc052962172f3cc7df3091223642a7be1e258a52e1b3fc +size 2091124 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a index 70514d600c..8eec9e2397 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack-mac-test-cmds/release_singlenetwork/libzigbee-pro-stack-mac-test-cmds.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bc5b1b10b278d7795cbf95ca6e867c2e5b8aa993a0d856cdbc0974c2bc0a555b -size 2024270 +oid sha256:34618e407abc5be5898f30703f5968288a29b40feedebfd3927f29eaa0a48c96 +size 2024398 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release/libzigbee-pro-stack.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release/libzigbee-pro-stack.a index 78c3f561ea..89d003ee6c 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6ff259d969fb628b6c170d7364cc365175dae6e5652742ca384f500762ab452f -size 2086848 +oid sha256:9854fd0d5e927e24993c77a06c8f7a02731ba9e91111d715a5268c60758a0f45 +size 2086968 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a index 07ceaf7c41..87acc29415 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-pro-stack/release_singlenetwork/libzigbee-pro-stack.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5b545e50cbe69ed27269e036970acdc4167a8b7a7323c6add656e21ce6501a4e -size 2020042 +oid sha256:5f28cc41501c50f51371321476f6ffc549c86851e3a64cb1e4abbf19fde3e843 +size 2020170 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release/libzigbee-xncp.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release/libzigbee-xncp.a index aee1ddcbba..777a321a82 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release/libzigbee-xncp.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e312d97704e00a909827f9a602a42c1780e97f19449113e12accbfa66a0b7843 -size 31434 +oid sha256:83050c8a50508bd0cc11434d05b2269f891f10d9fd9616dbc326a86ee6ed8932 +size 31498 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a index aee1ddcbba..777a321a82 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-xncp/release_singlenetwork/libzigbee-xncp.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e312d97704e00a909827f9a602a42c1780e97f19449113e12accbfa66a0b7843 -size 31434 +oid sha256:83050c8a50508bd0cc11434d05b2269f891f10d9fd9616dbc326a86ee6ed8932 +size 31498 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release/libzigbee-zll.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release/libzigbee-zll.a index e479f94c78..4874c8fa12 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release/libzigbee-zll.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2c7103878911749b4dc3464d3a4ea46a61e05ac0e765cb7d62e8a956b823f6fd -size 158954 +oid sha256:1a815180e30acdc314eacd15e5a98a4a78ca49e7992fea2cc1f6863929ec985c +size 159122 diff --git a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release_singlenetwork/libzigbee-zll.a index 3e4a1c448a..4de4370d51 100644 --- a/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/llvm/aarch64-android-ndk-r25c/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a8ea7ec27a2f9fb5a02e07b81651214907a551970d06c083965e523e58682366 -size 157346 +oid sha256:1d21dd312519fb7a0305c9311ae19e7c14252b0ef13ea9d21967ce06b73ceb38 +size 157458 diff --git a/protocol/zigbee/component/zigbee_ncp_framework.slcc b/protocol/zigbee/component/zigbee_ncp_framework.slcc index 859a43cffb..b100414f93 100644 --- a/protocol/zigbee/component/zigbee_ncp_framework.slcc +++ b/protocol/zigbee/component/zigbee_ncp_framework.slcc @@ -133,6 +133,12 @@ template_contribution: value: callback_type: counter_rollover function_name: sli_zigbee_af_counter_rollover_callback + - name: zigbee_stack_callback + value: + callback_type: mux_invalid_rx + function_name: sli_zigbee_af_mux_invalid_rx_callback + condition: + - rail_mux - name: zigbee_stack_callback value: callback_type: stack_token_changed diff --git a/protocol/zigbee/component/zigbee_system_common.slcc b/protocol/zigbee/component/zigbee_system_common.slcc index 0928e31988..f072592ce0 100644 --- a/protocol/zigbee/component/zigbee_system_common.slcc +++ b/protocol/zigbee/component/zigbee_system_common.slcc @@ -52,6 +52,7 @@ requires: - name: rail_lib_multiprotocol condition: - ot_stack + - rail_util_ieee802154_fast_channel_switching # Free RTOS Heap 3 implementation matches Micrium's the closest # Generally, we default to Heap 4. Therefore, we explicitly set this # to heap 3. @@ -157,6 +158,13 @@ toolchain_settings: value: -Werror condition: - zigbee_pro_stack_common_source + # lto sometimes inlines the weak definition and bypass the strong one, + # resulting in run-time failures + # this flag helps to disable funtion inlining globally when lto is used + - option: gcc_compiler_option + value: -fno-inline + condition: + - toolchain_lto template_file: - path: protocol/zigbee/app/framework/common/template/zigbee_stack_callback_dispatcher.h.jinja diff --git a/protocol/zigbee/docs/release-highlights.txt b/protocol/zigbee/docs/release-highlights.txt index f030516177..6346d9924e 100755 --- a/protocol/zigbee/docs/release-highlights.txt +++ b/protocol/zigbee/docs/release-highlights.txt @@ -1,10 +1,5 @@ Zigbee EmberZNet SDK 8.1 - Zigbee - - 250+ entries in APS link key table - - ZigbeeD support on Android 12 (v21.0.6113669) and Tizen (v0.1-13.1) - - xG26 Module support + - Targeted quality improvements and bug fixes. - Multiprotocol - - ZigbeeD and OTBR support on OpenWRT – GA - - DMP BLE + CMP ZB & Matter/OT with Concurrent Listening on MG26 for SoC – GA - - 802.15.4 Unified radio scheduler priority component - - Debian packaging support for MP host applications - Alpha + - Targeted quality improvements and bug fixes. diff --git a/protocol/zigbee/documentation/slEmberZNet_docContent.xml b/protocol/zigbee/documentation/slEmberZNet_docContent.xml index 8fc756b308..2f2eef1759 100644 --- a/protocol/zigbee/documentation/slEmberZNet_docContent.xml +++ b/protocol/zigbee/documentation/slEmberZNet_docContent.xml @@ -1,6 +1,6 @@ - - + + Describes the impact of Wi-Fi on Zigbee and Thread, and methods to improve coexistence. First, methods to improve coexistence without direct interaction between Zigbee/Thread and Wi-Fi radios are described. Second, Silicon Labs's Packet Traffic Arbitration (PTA) support to coordinate 2.5 GHz RF traffic for co-located Zigbee/Thread and Wi-Fi radios is described (for the EFR32MG only). @@ -8,35 +8,35 @@ - + Includes detailed information on using the Silicon Labs Gecko Bootloader with EmberZNet. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. - + Explains how to use Simplicity Commander to check, write, verify, and erase installation codes on Silicon Labs Wireless Gecko (EFR32) devices. - + Includes guidelines for certifying Zigbee 3.0 devices, instructions on setting up and using the Zigbee test harness and Zigbee test tool, and troubleshooting tips. - + Contains three complete PICS documents for Z3ColorControlLight, zigbee_z3_gateway and Z3SmartOutlet reference designs, along with XML files for Z3ColorControlLight clusters. Note that the Z3ColorControlLight was previously released in older SDK distributions, but is no longer shipped in current releases. - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -44,14 +44,14 @@ - + Details methods for testing Zigbee mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - + Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. @@ -59,7 +59,7 @@ - + Describes tokens and shows how to use them for non-volatile data storage in EmberZNet PRO and Silicon Labs Flex applications. @@ -67,14 +67,14 @@ - + Describes how to use the manufacturing library and its associated plugins in Simplicity Studio to perform RF tests during the manufacturing phase. - + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. @@ -82,7 +82,7 @@ - + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. @@ -90,7 +90,7 @@ - + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. @@ -98,14 +98,14 @@ - + Introduces some basic security concepts, including network layer security, trust centers, and application support layer security features. It then discusses the types of standard security protocols available in EmberZNet PRO. Coding requirements for implementing security are reviewed in summary. Finally, information on implementing Zigbee Smart Energy security is provided. - + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. @@ -113,7 +113,7 @@ - + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. @@ -121,7 +121,7 @@ - + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. @@ -129,7 +129,7 @@ - + Describes how to provision and configure Series 2 devices through the DCI and SWD. @@ -137,7 +137,7 @@ - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -145,35 +145,35 @@ - + Provides instructions for configuring various aspects of a component-based NCP application using Zigbee EmberZNet SDK 7.0 and higher with the tools included in Simplicity Studio 5. - + Describes how to configure peripherals running firmware produced with Zigbee 7.0 and higher using Simplicity Studio's Pin Tool and Project Configurator. - + Provides details on developing Dynamic Multiprotocol applications using Bluetooth and Zigbee EmberZNet SDK 7.0 and higher. - + Describes how to use Project Configurator to configure both receive and transmit Antenna Diversity in Zigbee EmberZNet applications. - + Describes how to use the Zigbee Cluster Configurator, an advanced configuration tool within Simplicity Studio that allows developers to manage the Zigbee endpoints, clusters and commands implemented by their device. @@ -181,7 +181,7 @@ - + Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 radio co-processor (RCP) with multiprotocol and multi-PAN support, as well as how to run the Zigbee stack on the EFR32 as a network co-processor (NCP) alongside the OpenThread RCP. @@ -189,14 +189,14 @@ - + Describes how to perform a Zigbee over-the-air (OTA) bootloading session between a ZCL OTA Upgrade cluster client device and server device. The instructions are for EFR32MG12 development kits. Users can also refer to this procedure when setting up or testing Zigbee OTA bootload cluster download in their own development environments with their own hardware. - + Summarizes the results of simultaneous Thread and Zigbee throughput performance testing for the concurrent multiprotocol / multi-PAN RCP, running both OpenThread and Zigbee on the host processor. @@ -204,21 +204,21 @@ - + Describes how to use the backup and restore feature in a zigbee_gp_z3_gateway_combo scenario application. - + Zigbee EmberZNet 7.0 and higher no longer supports compiling host applications in MinGW for Windows. This document offers an alternative solution by using a Docker container to run the NCP Host Application. - + Describes how to run a combination of Zigbee and OpenThread networking stacks and the Zigbee application layer on a System-on-Chip (SoC). @@ -226,14 +226,14 @@ - + This application note summarizes the results of Zigbee/BLE dynamic multiprotocol (DMP) large network performance tests using Zigbee unicast and broadcast packets to measure the reliability, latency, and loss of a variety of scenarios. - + Details the different options for integrating RF testing and characterization into standard test flows for the EFR32. @@ -241,42 +241,42 @@ - + Describes procedures for initial tests of a host connected to a Zigbee processor using EZSP-UART. It assumes that you have already read UG101, the UART Gateway Protocol Reference Guide. You should have a basic understanding of the UART Gateway protocol, as well as the signals needed by the UART interface. - + Provides an overview of the use of install codes and certificates in a Smart Energy network. Describes the components of a Smart Energy certificate and the differences between test certificates and production certificates. Explains how to use Silicon Labs utilities to program, verify and erase install codes and certificates. - + Details the EZSP-SPI Protocol used by a host microcontroller to communicate with an Ember network co-processor (NCP) running the EmberZNet PRO stack. It includes recommended procedures for developing and testing a driver for the EZSP-SPI Protocol on a new host microcontroller. - + Describes how to set up a device with the security resources required to support Smart Energy (SE) security, which is based on certificate-based key establishment (CBKE) using Elliptic-Curve Cryptography (ECC). You should be familiar the Zigbee Smart Energy Profile specification. - + Provides instructions for creating Zigbee Over-the-air (OTA) bootloader files with Image Builder, which takes an existing file (or multiple files) and wraps them in the file format as declared in the Zigbee specification. - + Provides a high-level description of the different options for integrating RF testing and characterization into your standard test flows. It is intended for customers who are moving from the early prototype development stage to the manufacturing production environment and need assistance with manufacturing test. @@ -284,14 +284,14 @@ - + Describes the multi-network stack feature that allows a single-radio chip to be concurrently part of more than one distinct network. Some limitations and restrictions are enforced by the multi-network stack and should be taken into account during the design of a multi-network application. These limitations are mostly related to the role the node assumes on the networks and are discussed here in detail. - + Describes how to initialize a piece of custom hardware (a 'device') based on the EFR32MG and EFR32FG families so that it interfaces correctly with a network stack. The same procedures can be used to restore devices whose settings have been corrupted or erased. @@ -299,49 +299,49 @@ - + Provides an overview and hyperlinks to all packaged documentation. - + Provides basic information on configuring, building, and installing applications for the EFR32MG family of SoCs using the Zigbee EmberZNet Software Development Kit (SDK) v7.0 and higher with Simplicity Studio 5. - + Lists SoC Platform APIs used to interface to the EmberZNet PRO stack, HAL, and status of the application-controlled network. These APIs concern network management, device and stack management, messaging, fragmentation, serial communication, token access, peripheral access, bootload utilities, and others. They are independent of the Application Framework and therefore can be used to develop applications that do not rely on the Zigbee Cluster Library. - + Describes Zigbee Application Framework APIs, the CLI interface, and callbacks. - + A companion to the EmberZNet API references, for developers whose applications require functionality not available through Project Configurator and the application framework, or who prefer working with an API. Includes an introduction to the stack API, a discussion of advanced design issues to consider when developing an application using the API, and provides an example application. - + The Zigbee Application Framework is a body of embedded C code that can be configured by project configuration tools to implement any Zigbee Cluster Library (ZCL) application. This guide covers the structure and usage of the Zigbee Application Framework in SDK 7.0 and higher. - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -349,7 +349,7 @@ - + A detailed overview of all the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform consists of: EMLIB, EMDRV, RAIL Library, NVM3, and the mbedTLS Plugin. @@ -357,28 +357,28 @@ - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Zigbee 7.x stack (and associated utilities) including added/deleted/deprecated features/API, and lists bugs that have been fixed since the last release and any pending ones. - + Describes the EmberZNet Serial Protocol (EZSP), used by a host application processor to interact with the EmberZNet PRO stack running on an NCP over either a SPI or a UART interface. Describes the frame formats for different EZSP-bound stack activities such as network management, messaging, bootloading, and token access. - + Describes the protocol used by EZSP-UART to reliably carry commands and responses between a host processor and a network co-processor. The topics discussed include a brief overview of Ember-designed ASH (Asynchronus Serial Host) protocol, general ASH frame format, different ASH frames, and their operation. - + Introduces some fundamental concepts of wireless networking. These concepts are referred to in other Fundamentals documents. If you are new to wireless networking, read this document first. @@ -386,21 +386,21 @@ - + Describes the key features and characteristics of a Zigbee solution. It also includes a section on Zigbee 3.0. - + Discusses the major decisions that must be made about which wireless protocol you should use, as well as additional decisions to be made if you are designing a Zigbee solution. - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -408,7 +408,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader and describes the file formats used by each. @@ -416,7 +416,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. @@ -424,21 +424,21 @@ - + Compares the ZLL stack and network with the EmberZNet PRO stack and network, with notes about considerations when implementing a ZLL solution. Includes a basic description of ZLL configuration and commissioning, and notes about the interoperability of ZLL and non-ZLL devices. - + Describes the main features and functions of Zigbee Green Power (ZGP) and a basic ZGP network, including its device types and commissioning process, and how EmberZNet supports the ZGP device types. - + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. @@ -446,7 +446,7 @@ - + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread @@ -454,7 +454,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface with EFR32 parts. @@ -462,7 +462,7 @@ - + Describes how to implement a dynamic multiprotocol solution. @@ -470,14 +470,14 @@ - + Introduces Silicon Labs Green Power components within the EmberZNet PRO stack and explains how to enable your network for Green Power. - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. @@ -485,7 +485,7 @@ - + For Zigbee EmberZNet v8 and later: Describes the EmberZNet Serial Protocol (EZSP), used by a host application processor to interact with the EmberZNet PRO stack running on an NCP over either a SPI or a UART interface. Describes the frame formats for different EZSP-bound stack activities such as network management, messaging, bootloading, and token access. diff --git a/protocol/zigbee/esf.properties b/protocol/zigbee/esf.properties index 9ad944e38c..f7af77df14 100644 --- a/protocol/zigbee/esf.properties +++ b/protocol/zigbee/esf.properties @@ -3,16 +3,16 @@ # # This files lists Studio SDK properties pertaining to the ZigBee stack. # -# The version=8.1.0.0 +# The version=8.1.1.0 # release branch, or it should be set to 0.0.0 otherwise. This is the # version that Studio displays for the loaded stack. # id=com.silabs.sdk.stack.znet -version=8.1.0.0 +version=8.1.1.0 label=EmberZNet SDK description=Silicon Labs EmberZNet SDK -prop.subLabel=EmberZNet\\ 8.1.0.0 +prop.subLabel=EmberZNet\\ 8.1.1.0 prop.partCompatibility=.*host.* .*efr32mg2[12467].* .*mgm(21|22|24).* .*rm21.* diff --git a/protocol/zigbee/stack/config/config.h b/protocol/zigbee/stack/config/config.h index 490410f003..850ffd1df1 100644 --- a/protocol/zigbee/stack/config/config.h +++ b/protocol/zigbee/stack/config/config.h @@ -33,11 +33,11 @@ // The 4 digit version: A.B.C.D #define SL_ZIGBEE_MAJOR_VERSION 8 #define SL_ZIGBEE_MINOR_VERSION 1 -#define SL_ZIGBEE_PATCH_VERSION 0 +#define SL_ZIGBEE_PATCH_VERSION 1 #define SL_ZIGBEE_SPECIAL_VERSION 0 // 2 bytes -#define SL_ZIGBEE_BUILD_NUMBER 190 +#define SL_ZIGBEE_BUILD_NUMBER 341 #define SL_ZIGBEE_FULL_VERSION ( ((uint16_t)SL_ZIGBEE_MAJOR_VERSION << 12) \ | ((uint16_t)SL_ZIGBEE_MINOR_VERSION << 8) \ | ((uint16_t)SL_ZIGBEE_PATCH_VERSION << 4) \ diff --git a/protocol/zigbee/stack/config/sl_zigbee_callback_stubs.c b/protocol/zigbee/stack/config/sl_zigbee_callback_stubs.c index ed47e423f1..18d1af28c5 100644 --- a/protocol/zigbee/stack/config/sl_zigbee_callback_stubs.c +++ b/protocol/zigbee/stack/config/sl_zigbee_callback_stubs.c @@ -2037,6 +2037,19 @@ SL_WEAK void sl_zigbee_zigbee_key_establishment_handler( sl_zigbee_af_pop_network_index(); } +// Weak implementation of public Callback sl_zigbee_af_mux_invalid_rx_cb +SL_WEAK void sl_zigbee_af_mux_invalid_rx_cb(uint8_t new_rx_channel, uint8_t old_rx_channel) +{ +} + +SL_WEAK void sl_zigbee_mux_invalid_rx_handler(uint8_t new_rx_channel, uint8_t old_rx_channel) +{ + sl_zigbee_af_push_callback_network_index(); + sli_zigbee_af_mux_invalid_rx(new_rx_channel, old_rx_channel); + sl_zigbee_af_mux_invalid_rx_cb(new_rx_channel, old_rx_channel); + sl_zigbee_af_pop_network_index(); +} + // ----------------------------------------------------------------------------- // Weak implementation of public Callback sl_zigbee_af_generate_cbke_keys_cb SL_WEAK void sl_zigbee_af_generate_cbke_keys_cb( diff --git a/protocol/zigbee/stack/include/message.h b/protocol/zigbee/stack/include/message.h index 075ee06b56..9743ae7b38 100644 --- a/protocol/zigbee/stack/include/message.h +++ b/protocol/zigbee/stack/include/message.h @@ -364,6 +364,8 @@ void sl_zigbee_incoming_network_status_handler(uint8_t errorCode, * @param *relayList The route record. Each relay in the list is an uint16_t node ID. The * list is passed as uint8_t * to avoid alignment problems. * @param consumed if set to true stack won't process the Incoming route record + * @internal SL_ZIGBEE_IPC_ARGS + * {# relayList | length: relayCount | max: MAX_IPC_VEC_ARG_CAPACITY #} */ void sl_zigbee_override_incoming_route_record_handler(sl_zigbee_rx_packet_info_t *packetInfo, uint8_t relayCount, @@ -414,6 +416,8 @@ uint8_t sl_zigbee_internal_override_append_source_route_handler(sl_802154_short_ * @param relayCount The number of relays in relayList. * @param *relayList The route record. Each relay in the list is an uint16_t node ID. The * list is passed as uint8_t * to avoid alignment problems. + * @internal SL_ZIGBEE_IPC_ARGS + * {# relayList | length: relayCount | max: MAX_IPC_VEC_ARG_CAPACITY #} */ void sl_zigbee_incoming_route_record_handler(sl_zigbee_rx_packet_info_t *packetInfo, uint8_t relayCount, @@ -887,8 +891,10 @@ sl_zigbee_packet_action_t sl_zigbee_af_outgoing_packet_filter_cb(sl_zigbee_zigbe * @param proxyTableIndex The proxy table index of the corresponding proxy table entry to the * incoming GPDF. * @param gpdCommandPayloadLength The length of the GPD command payload. - * @param gpdCommandPayload The GPD command payload.. + * @param gpdCommandPayload The GPD command payload. * @param packetInfo Rx packet information. + * @internal SL_ZIGBEE_IPC_ARGS + * {# gpdCommandPayload | length: gpdCommandPayloadLength | max: MAX_IPC_VEC_ARG_CAPACITY #} */ void sl_zigbee_gpep_incoming_message_handler( sl_zigbee_gp_status_t status, diff --git a/protocol/zigbee/stack/internal/inc/internal-callbacks-patch.h b/protocol/zigbee/stack/internal/inc/internal-callbacks-patch.h index b6b64db9e6..c8fe0d818a 100644 --- a/protocol/zigbee/stack/internal/inc/internal-callbacks-patch.h +++ b/protocol/zigbee/stack/internal/inc/internal-callbacks-patch.h @@ -98,6 +98,8 @@ sl_status_t sli_zigbee_stack_pan_id_conflict_handler(int8_t conflictCount); void sl_zigbee_counter_rollover_handler(sl_zigbee_counter_type_t type); +void sl_zigbee_mux_invalid_rx_handler(uint8_t new_rx_channel, uint8_t old_rx_channel); + void sli_zigbee_stack_stack_token_changed_handler(uint16_t tokenAddress); void sli_zigbee_stack_id_conflict_handler(sl_802154_short_addr_t conflictingId); diff --git a/protocol/zigbee/stack/internal/src/ipc/aes-mmo-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/aes-mmo-ipc-command-messages.c index 2466e68232..aa19dadff3 100644 --- a/protocol/zigbee/stack/internal/src/ipc/aes-mmo-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/aes-mmo-ipc-command-messages.c @@ -54,7 +54,7 @@ sl_status_t sl_zigbee_aes_hash_simple(uint8_t totalLength, const uint8_t *data, uint8_t *result) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.aes_hash_simple.request.totalLength = totalLength; if ((totalLength) > (MAX_IPC_VEC_ARG_CAPACITY)) { @@ -82,7 +82,7 @@ sl_status_t sl_zigbee_aes_mmo_hash_final(sl_zigbee_aes_mmo_hash_context_t *conte uint32_t length, const uint8_t *finalData) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.aes_mmo_hash_final.request.context = *context; @@ -106,7 +106,7 @@ sl_status_t sl_zigbee_aes_mmo_hash_final(sl_zigbee_aes_mmo_hash_context_t *conte void sl_zigbee_aes_mmo_hash_init(sl_zigbee_aes_mmo_hash_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.aes_mmo_hash_init.request.context = *context; @@ -123,7 +123,7 @@ sl_status_t sl_zigbee_aes_mmo_hash_update(sl_zigbee_aes_mmo_hash_context_t *cont uint32_t length, const uint8_t *data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.aes_mmo_hash_update.request.context = *context; diff --git a/protocol/zigbee/stack/internal/src/ipc/binding-table-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/binding-table-ipc-command-messages.c index cd625ea3f8..088805aca7 100644 --- a/protocol/zigbee/stack/internal/src/ipc/binding-table-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/binding-table-ipc-command-messages.c @@ -87,7 +87,7 @@ void sli_zigbee_stack_set_reply_binding_process_ipc_command(sli_zigbee_ipc_cmd_t bool sl_zigbee_binding_is_active(uint8_t index) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.binding_is_active.request.index = index; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_binding_is_active_process_ipc_command, &msg); @@ -96,7 +96,7 @@ bool sl_zigbee_binding_is_active(uint8_t index) sl_status_t sl_zigbee_clear_binding_table(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_binding_table_process_ipc_command, &msg); @@ -105,7 +105,7 @@ sl_status_t sl_zigbee_clear_binding_table(void) sl_status_t sl_zigbee_delete_binding(uint8_t index) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.delete_binding.request.index = index; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_delete_binding_process_ipc_command, &msg); @@ -115,7 +115,7 @@ sl_status_t sl_zigbee_delete_binding(uint8_t index) sl_status_t sl_zigbee_get_binding(uint8_t index, sl_zigbee_binding_table_entry_t *result) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_binding.request.index = index; if (result != NULL) { @@ -133,7 +133,7 @@ sl_status_t sl_zigbee_get_binding(uint8_t index, sl_802154_short_addr_t sl_zigbee_get_binding_remote_node_id(uint8_t index) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_binding_remote_node_id.request.index = index; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_binding_remote_node_id_process_ipc_command, &msg); @@ -142,7 +142,7 @@ sl_802154_short_addr_t sl_zigbee_get_binding_remote_node_id(uint8_t index) uint8_t sl_zigbee_get_binding_table_size(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_binding_table_size_process_ipc_command, &msg); @@ -152,7 +152,7 @@ uint8_t sl_zigbee_get_binding_table_size(void) sl_status_t sl_zigbee_note_senders_binding(uint8_t index, sl_802154_short_addr_t source) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.note_senders_binding.request.index = index; msg.data.note_senders_binding.request.source = source; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_note_senders_binding_process_ipc_command, &msg); @@ -163,7 +163,7 @@ sl_status_t sl_zigbee_note_senders_binding(uint8_t index, sl_status_t sl_zigbee_set_binding(uint8_t index, sl_zigbee_binding_table_entry_t *value) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_binding.request.index = index; if (value != NULL) { @@ -182,7 +182,7 @@ sl_status_t sl_zigbee_set_binding(uint8_t index, void sl_zigbee_set_binding_remote_node_id(uint8_t index, sl_802154_short_addr_t id) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_binding_remote_node_id.request.index = index; msg.data.set_binding_remote_node_id.request.id = id; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_binding_remote_node_id_process_ipc_command, &msg); @@ -190,7 +190,7 @@ void sl_zigbee_set_binding_remote_node_id(uint8_t index, sl_status_t sl_zigbee_set_binding_table_size(uint8_t size) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_binding_table_size.request.size = size; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_binding_table_size_process_ipc_command, &msg); @@ -201,7 +201,7 @@ sl_status_t sl_zigbee_set_reply_binding(uint8_t index, sl_zigbee_binding_table_entry_t *entry, sl_802154_short_addr_t source) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_reply_binding.request.index = index; if (entry != NULL) { diff --git a/protocol/zigbee/stack/internal/src/ipc/bootload_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/bootload_ipc_command_messages.c index c9db6ae3e9..5c7e6f752d 100644 --- a/protocol/zigbee/stack/internal/src/ipc/bootload_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/bootload_ipc_command_messages.c @@ -37,7 +37,7 @@ sl_status_t sl_zigbee_send_bootload_message(bool broadcast, uint8_t messageLength, uint8_t *messageContents) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_bootload_message.request.broadcast = broadcast; if (destEui64 != NULL) { diff --git a/protocol/zigbee/stack/internal/src/ipc/cbke-crypto-engine-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/cbke-crypto-engine-ipc-command-messages.c index 4012b8b6c4..16f33e1e99 100644 --- a/protocol/zigbee/stack/internal/src/ipc/cbke-crypto-engine-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/cbke-crypto-engine-ipc-command-messages.c @@ -110,7 +110,7 @@ sl_status_t sl_zigbee_calculate_smacs(bool amInitiator, sl_zigbee_certificate_data_t *partnerCert, sl_zigbee_public_key_data_t *partnerEphemeralPublicKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.calculate_smacs.request.amInitiator = amInitiator; if (partnerCert != NULL) { @@ -138,7 +138,7 @@ sl_status_t sl_zigbee_calculate_smacs_283k1(bool amInitiator, sl_zigbee_certificate_283k1_data_t *partnerCert, sl_zigbee_public_key_283k1_data_t *partnerEphemeralPublicKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.calculate_smacs_283k1.request.amInitiator = amInitiator; if (partnerCert != NULL) { @@ -164,7 +164,7 @@ sl_status_t sl_zigbee_calculate_smacs_283k1(bool amInitiator, sl_status_t sl_zigbee_clear_temporary_data_maybe_store_link_key(bool storeLinkKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.clear_temporary_data_maybe_store_link_key.request.storeLinkKey = storeLinkKey; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_temporary_data_maybe_store_link_key_process_ipc_command, &msg); @@ -173,7 +173,7 @@ sl_status_t sl_zigbee_clear_temporary_data_maybe_store_link_key(bool storeLinkKe sl_status_t sl_zigbee_clear_temporary_data_maybe_store_link_key_283k1(bool storeLinkKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.clear_temporary_data_maybe_store_link_key_283k1.request.storeLinkKey = storeLinkKey; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_temporary_data_maybe_store_link_key_283k1_process_ipc_command, &msg); @@ -182,7 +182,7 @@ sl_status_t sl_zigbee_clear_temporary_data_maybe_store_link_key_283k1(bool store sl_status_t sl_zigbee_dsa_sign(sli_buffer_manager_buffer_t messageToSign) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.dsa_sign.request.messageToSign = messageToSign; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_dsa_sign_process_ipc_command, &msg); @@ -193,7 +193,7 @@ sl_status_t sl_zigbee_dsa_verify(sl_zigbee_message_digest_t *digest, sl_zigbee_certificate_data_t *signerCertificate, sl_zigbee_signature_data_t *receivedSig) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (digest != NULL) { msg.data.dsa_verify.request.digest = *digest; @@ -228,7 +228,7 @@ sl_status_t sl_zigbee_dsa_verify_283k1(const sl_zigbee_message_digest_t *digest, const sl_zigbee_certificate_283k1_data_t *signerCertificate, const sl_zigbee_signature_283k1_data_t *receivedSig) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (digest != NULL) { msg.data.dsa_verify_283k1.request.digest = *digest; @@ -249,7 +249,7 @@ sl_status_t sl_zigbee_dsa_verify_283k1(const sl_zigbee_message_digest_t *digest, sl_status_t sl_zigbee_generate_cbke_keys(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_generate_cbke_keys_process_ipc_command, &msg); @@ -258,7 +258,7 @@ sl_status_t sl_zigbee_generate_cbke_keys(void) sl_status_t sl_zigbee_generate_cbke_keys_283k1(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_generate_cbke_keys_283k1_process_ipc_command, &msg); @@ -267,7 +267,7 @@ sl_status_t sl_zigbee_generate_cbke_keys_283k1(void) sl_status_t sl_zigbee_get_certificate(sl_zigbee_certificate_data_t *result) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (result != NULL) { msg.data.get_certificate.request.result = *result; @@ -284,7 +284,7 @@ sl_status_t sl_zigbee_get_certificate(sl_zigbee_certificate_data_t *result) sl_status_t sl_zigbee_get_certificate_283k1(sl_zigbee_certificate_283k1_data_t *result) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (result != NULL) { msg.data.get_certificate_283k1.request.result = *result; @@ -301,7 +301,7 @@ sl_status_t sl_zigbee_get_certificate_283k1(sl_zigbee_certificate_283k1_data_t * bool sl_zigbee_get_stack_certificate_eui64(sl_802154_long_addr_t certEui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (certEui64 != NULL) { memmove(msg.data.get_stack_certificate_eui64.request.certEui64, certEui64, sizeof(sl_802154_long_addr_t)); @@ -320,7 +320,7 @@ sl_status_t sl_zigbee_set_preinstalled_cbke_data(sl_zigbee_public_key_data_t *ca sl_zigbee_certificate_data_t *myCert, sl_zigbee_private_key_data_t *myKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (caPublic != NULL) { msg.data.set_preinstalled_cbke_data.request.caPublic = *caPublic; @@ -355,7 +355,7 @@ sl_status_t sl_zigbee_set_preinstalled_cbke_data_283k1(const sl_zigbee_public_ke const sl_zigbee_certificate_283k1_data_t *myCert, const sl_zigbee_private_key_283k1_data_t *myKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (caPublic != NULL) { msg.data.set_preinstalled_cbke_data_283k1.request.caPublic = *caPublic; diff --git a/protocol/zigbee/stack/internal/src/ipc/child_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/child_ipc_command_messages.c index 2716372358..15ce7b5377 100644 --- a/protocol/zigbee/stack/internal/src/ipc/child_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/child_ipc_command_messages.c @@ -184,7 +184,7 @@ sl_status_t sl_zigbee_add_child(sl_802154_short_addr_t shortId, sl_802154_long_addr_t longId, sl_zigbee_node_type_t nodeType) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.add_child.request.shortId = shortId; if (longId != NULL) { @@ -203,7 +203,7 @@ sl_status_t sl_zigbee_add_child(sl_802154_short_addr_t shortId, uint8_t sl_zigbee_child_count(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_child_count_process_ipc_command, &msg); @@ -212,7 +212,7 @@ uint8_t sl_zigbee_child_count(void) sl_802154_short_addr_t sl_zigbee_child_id(uint8_t childIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.child_id.request.childIndex = childIndex; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_child_id_process_ipc_command, &msg); @@ -221,7 +221,7 @@ sl_802154_short_addr_t sl_zigbee_child_id(uint8_t childIndex) uint8_t sl_zigbee_child_index(sl_802154_short_addr_t childId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.child_index.request.childId = childId; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_child_index_process_ipc_command, &msg); @@ -230,7 +230,7 @@ uint8_t sl_zigbee_child_index(sl_802154_short_addr_t childId) int8_t sl_zigbee_child_power(uint8_t childIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.child_power.request.childIndex = childIndex; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_child_power_process_ipc_command, &msg); @@ -239,7 +239,7 @@ int8_t sl_zigbee_child_power(uint8_t childIndex) sl_status_t sl_zigbee_clear_message_flag(sl_802154_short_addr_t childId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.clear_message_flag.request.childId = childId; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_message_flag_process_ipc_command, &msg); @@ -248,7 +248,7 @@ sl_status_t sl_zigbee_clear_message_flag(sl_802154_short_addr_t childId) uint16_t sl_zigbee_current_stack_tasks(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_current_stack_tasks_process_ipc_command, &msg); @@ -257,7 +257,7 @@ uint16_t sl_zigbee_current_stack_tasks(void) int8_t sl_zigbee_get_avg_parent_rssi(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_avg_parent_rssi_process_ipc_command, &msg); @@ -267,7 +267,7 @@ int8_t sl_zigbee_get_avg_parent_rssi(void) sl_status_t sl_zigbee_get_child_data(uint8_t index, sl_zigbee_child_data_t *childData) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_child_data.request.index = index; if (childData != NULL) { @@ -285,7 +285,7 @@ sl_status_t sl_zigbee_get_child_data(uint8_t index, sl_zigbee_keep_alive_mode_t sl_zigbee_get_keep_alive_mode(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_keep_alive_mode_process_ipc_command, &msg); @@ -294,7 +294,7 @@ sl_zigbee_keep_alive_mode_t sl_zigbee_get_keep_alive_mode(void) uint8_t sl_zigbee_get_max_end_device_children(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_max_end_device_children_process_ipc_command, &msg); @@ -303,7 +303,7 @@ uint8_t sl_zigbee_get_max_end_device_children(void) uint8_t * sl_zigbee_get_parent_eui64(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_parent_eui64_process_ipc_command, &msg); @@ -312,7 +312,7 @@ uint8_t * sl_zigbee_get_parent_eui64(void) sl_802154_short_addr_t sl_zigbee_get_parent_id(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_parent_id_process_ipc_command, &msg); @@ -321,7 +321,7 @@ sl_802154_short_addr_t sl_zigbee_get_parent_id(void) uint32_t sl_zigbee_get_parent_incoming_nwk_frame_counter(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_parent_incoming_nwk_frame_counter_process_ipc_command, &msg); @@ -330,7 +330,7 @@ uint32_t sl_zigbee_get_parent_incoming_nwk_frame_counter(void) sl_802154_short_addr_t sl_zigbee_get_parent_node_id(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_parent_node_id_process_ipc_command, &msg); @@ -339,7 +339,7 @@ sl_802154_short_addr_t sl_zigbee_get_parent_node_id(void) bool sl_zigbee_parent_token_set(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_parent_token_set_process_ipc_command, &msg); @@ -348,7 +348,7 @@ bool sl_zigbee_parent_token_set(void) sl_status_t sl_zigbee_poll_for_data(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_poll_for_data_process_ipc_command, &msg); @@ -357,7 +357,7 @@ sl_status_t sl_zigbee_poll_for_data(void) sl_status_t sl_zigbee_remove_child(sl_802154_long_addr_t childEui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (childEui64 != NULL) { memmove(msg.data.remove_child.request.childEui64, childEui64, sizeof(sl_802154_long_addr_t)); @@ -375,7 +375,7 @@ sl_status_t sl_zigbee_remove_child(sl_802154_long_addr_t childEui64) void sl_zigbee_remove_neighbor(sl_802154_short_addr_t shortId, sl_802154_long_addr_t longId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.remove_neighbor.request.shortId = shortId; if (longId != NULL) { @@ -391,7 +391,7 @@ void sl_zigbee_remove_neighbor(sl_802154_short_addr_t shortId, sl_status_t sl_zigbee_send_link_power_delta_request(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_send_link_power_delta_request_process_ipc_command, &msg); @@ -401,7 +401,7 @@ sl_status_t sl_zigbee_send_link_power_delta_request(void) sl_status_t sl_zigbee_set_child_data(uint8_t index, const sl_zigbee_child_data_t *childData) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_child_data.request.index = index; if (childData != NULL) { @@ -416,7 +416,7 @@ sl_status_t sl_zigbee_set_child_data(uint8_t index, void sl_zigbee_set_child_power(uint8_t childIndex, int8_t newPower) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_child_power.request.childIndex = childIndex; msg.data.set_child_power.request.newPower = newPower; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_child_power_process_ipc_command, &msg); @@ -424,7 +424,7 @@ void sl_zigbee_set_child_power(uint8_t childIndex, sl_status_t sl_zigbee_set_child_timeout_option_mask(uint16_t mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_child_timeout_option_mask.request.mask = mask; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_child_timeout_option_mask_process_ipc_command, &msg); @@ -433,7 +433,7 @@ sl_status_t sl_zigbee_set_child_timeout_option_mask(uint16_t mask) sl_status_t sl_zigbee_set_keep_alive_mode(sl_zigbee_keep_alive_mode_t mode) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_keep_alive_mode.request.mode = mode; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_keep_alive_mode_process_ipc_command, &msg); @@ -442,14 +442,14 @@ sl_status_t sl_zigbee_set_keep_alive_mode(sl_zigbee_keep_alive_mode_t mode) void sl_zigbee_set_mac_poll_failure_wait_time(uint32_t waitBeforeRetryIntervalMs) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_mac_poll_failure_wait_time.request.waitBeforeRetryIntervalMs = waitBeforeRetryIntervalMs; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_mac_poll_failure_wait_time_process_ipc_command, &msg); } sl_status_t sl_zigbee_set_max_end_device_children(uint8_t max) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_max_end_device_children.request.max = max; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_max_end_device_children_process_ipc_command, &msg); @@ -458,7 +458,7 @@ sl_status_t sl_zigbee_set_max_end_device_children(uint8_t max) sl_status_t sl_zigbee_set_message_flag(sl_802154_short_addr_t childId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_message_flag.request.childId = childId; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_message_flag_process_ipc_command, &msg); @@ -467,7 +467,7 @@ sl_status_t sl_zigbee_set_message_flag(sl_802154_short_addr_t childId) sl_status_t sl_zigbee_set_parent_incoming_nwk_frame_counter(uint32_t value) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_parent_incoming_nwk_frame_counter.request.value = value; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_parent_incoming_nwk_frame_counter_process_ipc_command, &msg); @@ -476,14 +476,14 @@ sl_status_t sl_zigbee_set_parent_incoming_nwk_frame_counter(uint32_t value) void sl_zigbee_stack_power_down(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_stack_power_down_process_ipc_command, &msg); } void sl_zigbee_stack_power_up(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_stack_power_up_process_ipc_command, &msg); } diff --git a/protocol/zigbee/stack/internal/src/ipc/force_sleep_wakeup_stack_interface_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/force_sleep_wakeup_stack_interface_ipc_command_messages.c index 8450c93f10..a273da2689 100644 --- a/protocol/zigbee/stack/internal/src/ipc/force_sleep_wakeup_stack_interface_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/force_sleep_wakeup_stack_interface_ipc_command_messages.c @@ -46,28 +46,28 @@ void sli_mac_stack_lower_mac_force_sleep_process_ipc_command(sli_zigbee_ipc_cmd_ void sl_802154_cancel_polls(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_802154_stack_cancel_polls_process_ipc_command, &msg); } void sl_802154_purge_incoming_queue(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_802154_stack_purge_incoming_queue_process_ipc_command, &msg); } void sl_802154_purge_transmit_queue(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_802154_stack_purge_transmit_queue_process_ipc_command, &msg); } void sl_mac_lower_mac_force_sleep(bool sleep) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.lower_mac_force_sleep.request.sleep = sleep; sli_zigbee_send_ipc_cmd(sli_mac_stack_lower_mac_force_sleep_process_ipc_command, &msg); } diff --git a/protocol/zigbee/stack/internal/src/ipc/gp-proxy-table-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/gp-proxy-table-ipc-command-messages.c index a38cdf396b..18fa82c179 100644 --- a/protocol/zigbee/stack/internal/src/ipc/gp-proxy-table-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/gp-proxy-table-ipc-command-messages.c @@ -52,7 +52,7 @@ void sli_zigbee_stack_gp_proxy_table_process_gp_pairing_process_ipc_command(sli_ sl_status_t sl_zigbee_gp_proxy_table_get_entry(uint8_t proxyIndex, sl_zigbee_gp_proxy_table_entry_t *entry) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_proxy_table_get_entry.request.proxyIndex = proxyIndex; if (entry != NULL) { @@ -70,7 +70,7 @@ sl_status_t sl_zigbee_gp_proxy_table_get_entry(uint8_t proxyIndex, uint8_t sl_zigbee_gp_proxy_table_lookup(sl_zigbee_gp_address_t *addr) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (addr != NULL) { msg.data.gp_proxy_table_lookup.request.addr = *addr; @@ -96,7 +96,7 @@ bool sl_zigbee_gp_proxy_table_process_gp_pairing(uint32_t options, uint32_t gpdSecurityFrameCounter, uint8_t forwardingRadius) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_proxy_table_process_gp_pairing.request.options = options; if (addr != NULL) { diff --git a/protocol/zigbee/stack/internal/src/ipc/gp-sink-table-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/gp-sink-table-ipc-command-messages.c index a6b2dad4f8..fc2882b9e2 100644 --- a/protocol/zigbee/stack/internal/src/ipc/gp-sink-table-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/gp-sink-table-ipc-command-messages.c @@ -100,7 +100,7 @@ void sl_zigbee_gp_sink_table_add_group(uint8_t index, uint16_t sinkGroupId, uint16_t assignedAlias) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_sink_table_add_group.request.index = index; msg.data.gp_sink_table_add_group.request.sinkGroupId = sinkGroupId; msg.data.gp_sink_table_add_group.request.assignedAlias = assignedAlias; @@ -109,14 +109,14 @@ void sl_zigbee_gp_sink_table_add_group(uint8_t index, void sl_zigbee_gp_sink_table_clear_all(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_sink_table_clear_all_process_ipc_command, &msg); } uint8_t sl_zigbee_gp_sink_table_entry_in_use(uint8_t sinkTableIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_sink_table_entry_in_use.request.sinkTableIndex = sinkTableIndex; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_sink_table_entry_in_use_process_ipc_command, &msg); @@ -125,7 +125,7 @@ uint8_t sl_zigbee_gp_sink_table_entry_in_use(uint8_t sinkTableIndex) uint8_t sl_zigbee_gp_sink_table_find_or_allocate_entry(sl_zigbee_gp_address_t *addr) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (addr != NULL) { msg.data.gp_sink_table_find_or_allocate_entry.request.addr = *addr; @@ -143,7 +143,7 @@ uint8_t sl_zigbee_gp_sink_table_find_or_allocate_entry(sl_zigbee_gp_address_t *a sl_status_t sl_zigbee_gp_sink_table_get_entry(uint8_t sinkTableIndex, sl_zigbee_gp_sink_table_entry_t *entry) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_sink_table_get_entry.request.sinkTableIndex = sinkTableIndex; if (entry != NULL) { @@ -161,7 +161,7 @@ sl_status_t sl_zigbee_gp_sink_table_get_entry(uint8_t sinkTableIndex, uint8_t sl_zigbee_gp_sink_table_get_free_entry_index(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_sink_table_get_free_entry_index_process_ipc_command, &msg); @@ -170,7 +170,7 @@ uint8_t sl_zigbee_gp_sink_table_get_free_entry_index(void) uint8_t sl_zigbee_gp_sink_table_get_number_of_active_entries(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_sink_table_get_number_of_active_entries_process_ipc_command, &msg); @@ -179,14 +179,14 @@ uint8_t sl_zigbee_gp_sink_table_get_number_of_active_entries(void) void sl_zigbee_gp_sink_table_init(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_sink_table_init_process_ipc_command, &msg); } uint8_t sl_zigbee_gp_sink_table_lookup(sl_zigbee_gp_address_t *addr) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (addr != NULL) { msg.data.gp_sink_table_lookup.request.addr = *addr; @@ -203,7 +203,7 @@ uint8_t sl_zigbee_gp_sink_table_lookup(sl_zigbee_gp_address_t *addr) void sl_zigbee_gp_sink_table_remove_entry(uint8_t index) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_sink_table_remove_entry.request.index = index; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_sink_table_remove_entry_process_ipc_command, &msg); } @@ -212,7 +212,7 @@ bool sl_zigbee_gp_sink_table_remove_group(uint8_t index, uint16_t sinkGroupId, uint16_t assignedAlias) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_sink_table_remove_group.request.index = index; msg.data.gp_sink_table_remove_group.request.sinkGroupId = sinkGroupId; msg.data.gp_sink_table_remove_group.request.assignedAlias = assignedAlias; @@ -224,7 +224,7 @@ bool sl_zigbee_gp_sink_table_remove_group(uint8_t index, sl_status_t sl_zigbee_gp_sink_table_set_entry(uint8_t sinkTableIndex, sl_zigbee_gp_sink_table_entry_t *entry) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_sink_table_set_entry.request.sinkTableIndex = sinkTableIndex; if (entry != NULL) { @@ -243,7 +243,7 @@ sl_status_t sl_zigbee_gp_sink_table_set_entry(uint8_t sinkTableIndex, void sl_zigbee_gp_sink_table_set_security_frame_counter(uint8_t index, uint32_t sfc) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_sink_table_set_security_frame_counter.request.index = index; msg.data.gp_sink_table_set_security_frame_counter.request.sfc = sfc; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_sink_table_set_security_frame_counter_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/gp-types-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/gp-types-ipc-command-messages.c index c4be9e6d86..f72efdb78d 100644 --- a/protocol/zigbee/stack/internal/src/ipc/gp-types-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/gp-types-ipc-command-messages.c @@ -98,7 +98,7 @@ sl_status_t sl_zigbee_d_gp_send(bool action, uint8_t gpepHandle, uint16_t gpTxQueueEntryLifetimeMs) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.d_gp_send.request.action = action; msg.data.d_gp_send.request.useCca = useCca; @@ -127,7 +127,7 @@ sl_status_t sl_zigbee_d_gp_send(bool action, uint16_t sl_zigbee_get_gp_max_tx_q_list_count(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_gp_max_tx_q_list_count_process_ipc_command, &msg); @@ -136,7 +136,7 @@ uint16_t sl_zigbee_get_gp_max_tx_q_list_count(void) uint16_t sl_zigbee_get_gp_tx_q_list_count(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_gp_tx_q_list_count_process_ipc_command, &msg); @@ -147,7 +147,7 @@ sli_buffer_manager_buffer_t sl_zigbee_gp_add_gp_tx_queue_entry_with_payload(sl_z uint8_t *data, uint16_t dataLength) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (txQueue != NULL) { msg.data.gp_add_gp_tx_queue_entry_with_payload.request.txQueue = *txQueue; @@ -175,7 +175,7 @@ sli_buffer_manager_buffer_t sl_zigbee_gp_add_gp_tx_queue_entry_with_payload(sl_z void sl_zigbee_gp_clear_tx_queue(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_clear_tx_queue_process_ipc_command, &msg); } @@ -185,7 +185,7 @@ sli_buffer_manager_buffer_t sl_zigbee_gp_get_tx_queue_entry_from_queue(sl_zigbee uint16_t *dataLength, uint16_t allocatedDataLength) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (txQueue != NULL) { msg.data.gp_get_tx_queue_entry_from_queue.request.txQueue = *txQueue; @@ -226,7 +226,7 @@ sl_status_t sl_zigbee_gp_get_tx_queue_entry_from_queue_index(uint8_t index, uint8_t *payload, uint16_t *payload_len) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_get_tx_queue_entry_from_queue_index.request.index = index; if (txQueue != NULL) { @@ -264,7 +264,7 @@ sl_status_t sl_zigbee_gp_get_tx_queue_entry_from_queue_index(uint8_t index, sli_zigbee_message_buffer_queue_t * sl_zigbee_gp_get_tx_queue_head(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_get_tx_queue_head_process_ipc_command, &msg); @@ -273,7 +273,7 @@ sli_zigbee_message_buffer_queue_t * sl_zigbee_gp_get_tx_queue_head(void) bool sl_zigbee_gp_remove_from_tx_queue(sl_zigbee_gp_tx_queue_entry_t *txQueue) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (txQueue != NULL) { msg.data.gp_remove_from_tx_queue.request.txQueue = *txQueue; @@ -290,7 +290,7 @@ bool sl_zigbee_gp_remove_from_tx_queue(sl_zigbee_gp_tx_queue_entry_t *txQueue) void sl_zigbee_gp_set_max_tx_queue_entry(uint16_t maxEntries) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.gp_set_max_tx_queue_entry.request.maxEntries = maxEntries; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_gp_set_max_tx_queue_entry_process_ipc_command, &msg); } diff --git a/protocol/zigbee/stack/internal/src/ipc/high_datarate_phy_stack_interface_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/high_datarate_phy_stack_interface_ipc_command_messages.c index 03910fa423..4572a7c1cf 100644 --- a/protocol/zigbee/stack/internal/src/ipc/high_datarate_phy_stack_interface_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/high_datarate_phy_stack_interface_ipc_command_messages.c @@ -54,7 +54,7 @@ void sli_mac_stack_set_mode_switch_sync_detect_process_ipc_command(sli_zigbee_ip void sl_mac_lower_mac_set_high_datarate_csma_params(RAIL_CsmaConfig_t *csma_params) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (csma_params != NULL) { msg.data.lower_mac_set_high_datarate_csma_params.request.csma_params = *csma_params; @@ -69,7 +69,7 @@ void sl_mac_lower_mac_set_high_datarate_csma_params(RAIL_CsmaConfig_t *csma_para void sl_mac_lower_mac_set_high_datarate_phy_radio_priorities(sl_802154_radio_priorities_t *priorities) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (priorities != NULL) { msg.data.lower_mac_set_high_datarate_phy_radio_priorities.request.priorities = *priorities; @@ -85,7 +85,7 @@ void sl_mac_lower_mac_set_high_datarate_phy_radio_priorities(sl_802154_radio_pri sl_status_t sl_mac_send_raw_high_datarate_phy_message(uint8_t nwk_index, uint8_t *payload) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_raw_high_datarate_phy_message.request.nwk_index = nwk_index; if (((payload[1] << 8) + payload[0] + 2) > (MAX_HIGH_DATARATE_PHY_PACKET_LENGTH)) { @@ -107,7 +107,7 @@ sl_status_t sl_mac_send_raw_high_datarate_phy_scheduled_message(uint8_t nwk_inde uint8_t *payload, RAIL_Time_t timestamp) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_raw_high_datarate_phy_scheduled_message.request.nwk_index = nwk_index; if (((payload[1] << 8) + payload[0] + 2) > (MAX_HIGH_DATARATE_PHY_PACKET_LENGTH)) { @@ -128,7 +128,7 @@ sl_status_t sl_mac_send_raw_high_datarate_phy_scheduled_message(uint8_t nwk_inde RAIL_Status_t sl_mac_set_mode_switch_sync_detect(bool enable_f) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_mode_switch_sync_detect.request.enable_f = enable_f; sli_zigbee_send_ipc_cmd(sli_mac_stack_set_mode_switch_sync_detect_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/library_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/library_ipc_command_messages.c index 94ce5aa6c8..8514fc81ae 100644 --- a/protocol/zigbee/stack/internal/src/ipc/library_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/library_ipc_command_messages.c @@ -31,7 +31,7 @@ void sli_zigbee_stack_get_library_status_process_ipc_command(sli_zigbee_ipc_cmd_ sl_zigbee_library_status_t sl_zigbee_get_library_status(sl_zigbee_library_id_t libraryId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_library_status.request.libraryId = libraryId; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_library_status_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.c b/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.c index bf086caec8..96905e353f 100644 --- a/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.c +++ b/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.c @@ -3,7 +3,7 @@ * @brief callback event handlers for message ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this @@ -55,7 +55,7 @@ void sli_zigbee_stack_gpep_incoming_message_handler(sl_zigbee_gp_status_t status cb_event->data.gpep_incoming_message_handler.gpdCommandPayloadLength = gpdCommandPayloadLength; if (gpdCommandPayload != NULL) { - cb_event->data.gpep_incoming_message_handler.gpdCommandPayload = *gpdCommandPayload; + memmove(cb_event->data.gpep_incoming_message_handler.gpdCommandPayload, gpdCommandPayload, sizeof(uint8_t) * (gpdCommandPayloadLength)); } if (packetInfo != NULL) { @@ -156,7 +156,7 @@ void sli_zigbee_stack_incoming_route_record_handler(sl_zigbee_rx_packet_info_t * cb_event->data.incoming_route_record_handler.relayCount = relayCount; if (relayList != NULL) { - cb_event->data.incoming_route_record_handler.relayList = *relayList; + memmove(cb_event->data.incoming_route_record_handler.relayList, relayList, sizeof(uint8_t) * (relayCount)); } cb_event->tag = SLI_ZIGBEE_STACK_INCOMING_ROUTE_RECORD_HANDLER_IPC_EVENT_TYPE; @@ -207,7 +207,7 @@ void sli_zigbee_stack_override_incoming_route_record_handler(sl_zigbee_rx_packet cb_event->data.override_incoming_route_record_handler.relayCount = relayCount; if (relayList != NULL) { - cb_event->data.override_incoming_route_record_handler.relayList = *relayList; + memmove(cb_event->data.override_incoming_route_record_handler.relayList, relayList, sizeof(uint8_t) * (relayCount)); } if (consumed != NULL) { @@ -255,7 +255,7 @@ void sli_zigbee_message_process_ipc_event(sl_zigbee_stack_cb_event_t *cb_event) cb_event->data.gpep_incoming_message_handler.mic, cb_event->data.gpep_incoming_message_handler.proxyTableIndex, cb_event->data.gpep_incoming_message_handler.gpdCommandPayloadLength, - &cb_event->data.gpep_incoming_message_handler.gpdCommandPayload, + cb_event->data.gpep_incoming_message_handler.gpdCommandPayload, &cb_event->data.gpep_incoming_message_handler.packetInfo); break; @@ -290,7 +290,7 @@ void sli_zigbee_message_process_ipc_event(sl_zigbee_stack_cb_event_t *cb_event) case SLI_ZIGBEE_STACK_INCOMING_ROUTE_RECORD_HANDLER_IPC_EVENT_TYPE: sl_zigbee_incoming_route_record_handler(&cb_event->data.incoming_route_record_handler.packetInfo, cb_event->data.incoming_route_record_handler.relayCount, - &cb_event->data.incoming_route_record_handler.relayList); + cb_event->data.incoming_route_record_handler.relayList); break; case SLI_ZIGBEE_STACK_MESSAGE_SENT_HANDLER_IPC_EVENT_TYPE: @@ -306,7 +306,7 @@ void sli_zigbee_message_process_ipc_event(sl_zigbee_stack_cb_event_t *cb_event) case SLI_ZIGBEE_STACK_OVERRIDE_INCOMING_ROUTE_RECORD_HANDLER_IPC_EVENT_TYPE: sl_zigbee_override_incoming_route_record_handler(&cb_event->data.override_incoming_route_record_handler.packetInfo, cb_event->data.override_incoming_route_record_handler.relayCount, - &cb_event->data.override_incoming_route_record_handler.relayList, + cb_event->data.override_incoming_route_record_handler.relayList, &cb_event->data.override_incoming_route_record_handler.consumed); break; diff --git a/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.h b/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.h index 03278c28c4..98bbaec493 100644 --- a/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.h +++ b/protocol/zigbee/stack/internal/src/ipc/message_ipc_callback_events.h @@ -3,7 +3,7 @@ * @brief callback struct and event handlers for message ******************************************************************************* * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + * Copyright 2025 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this @@ -34,7 +34,7 @@ typedef struct { uint32_t mic; uint8_t proxyTableIndex; uint8_t gpdCommandPayloadLength; - uint8_t gpdCommandPayload; + uint8_t gpdCommandPayload[MAX_IPC_VEC_ARG_CAPACITY]; sl_zigbee_rx_packet_info_t packetInfo; } sli_zigbee_stack_gpep_incoming_message_handler_ipc_event_t; @@ -69,7 +69,7 @@ typedef struct { typedef struct { sl_zigbee_rx_packet_info_t packetInfo; uint8_t relayCount; - uint8_t relayList; + uint8_t relayList[MAX_IPC_VEC_ARG_CAPACITY]; } sli_zigbee_stack_incoming_route_record_handler_ipc_event_t; typedef struct { @@ -85,7 +85,7 @@ typedef struct { typedef struct { sl_zigbee_rx_packet_info_t packetInfo; uint8_t relayCount; - uint8_t relayList; + uint8_t relayList[MAX_IPC_VEC_ARG_CAPACITY]; bool consumed; } sli_zigbee_stack_override_incoming_route_record_handler_ipc_event_t; diff --git a/protocol/zigbee/stack/internal/src/ipc/message_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/message_ipc_command_messages.c index b5c8571b36..691448ece3 100644 --- a/protocol/zigbee/stack/internal/src/ipc/message_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/message_ipc_command_messages.c @@ -164,7 +164,7 @@ void slxi_zigbee_stack_add_to_incoming_network_queue_process_ipc_command(sli_zig bool sl_zigbee_address_table_entry_is_active(uint8_t addressTableIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.address_table_entry_is_active.request.addressTableIndex = addressTableIndex; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_address_table_entry_is_active_process_ipc_command, &msg); @@ -175,7 +175,7 @@ sl_status_t sl_zigbee_get_address_table_info(uint8_t addressTableIndex, sl_802154_short_addr_t *nodeId, sl_802154_long_addr_t eui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_address_table_info.request.addressTableIndex = addressTableIndex; if (nodeId != NULL) { @@ -201,7 +201,7 @@ sl_status_t sl_zigbee_get_address_table_info(uint8_t addressTableIndex, uint16_t sl_zigbee_get_aps_ack_timeout_ms(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_aps_ack_timeout_ms_process_ipc_command, &msg); @@ -210,7 +210,7 @@ uint16_t sl_zigbee_get_aps_ack_timeout_ms(void) sl_status_t sl_zigbee_get_extended_timeout(sl_802154_long_addr_t remoteEui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (remoteEui64 != NULL) { memmove(msg.data.get_extended_timeout.request.remoteEui64, remoteEui64, sizeof(sl_802154_long_addr_t)); @@ -227,7 +227,7 @@ sl_status_t sl_zigbee_get_extended_timeout(sl_802154_long_addr_t remoteEui64) sl_zigbee_multicast_table_entry_t * sl_zigbee_get_multicast_table(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_multicast_table_process_ipc_command, &msg); @@ -236,7 +236,7 @@ sl_zigbee_multicast_table_entry_t * sl_zigbee_get_multicast_table(void) uint8_t sl_zigbee_get_multicast_table_size(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_multicast_table_size_process_ipc_command, &msg); @@ -245,7 +245,7 @@ uint8_t sl_zigbee_get_multicast_table_size(void) uint8_t sl_zigbee_maximum_aps_payload_length(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_maximum_aps_payload_length_process_ipc_command, &msg); @@ -254,7 +254,7 @@ uint8_t sl_zigbee_maximum_aps_payload_length(void) bool sl_zigbee_pending_acked_messages(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_pending_acked_messages_process_ipc_command, &msg); @@ -263,7 +263,7 @@ bool sl_zigbee_pending_acked_messages(void) sl_status_t sl_zigbee_proxy_next_broadcast_from_long(const uint8_t *euiSource) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (euiSource != NULL) { memmove(msg.data.proxy_next_broadcast_from_long.request.euiSource, euiSource, sizeof(uint8_t) * (EUI64_SIZE)); @@ -284,7 +284,7 @@ sl_status_t sl_zigbee_send_broadcast(sl_802154_short_addr_t alias, const uint8_t *message, uint8_t *apsSequence) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_broadcast.request.alias = alias; msg.data.send_broadcast.request.destination = destination; msg.data.send_broadcast.request.nwkSequence = nwkSequence; @@ -330,7 +330,7 @@ sl_status_t sl_zigbee_send_multicast(sl_zigbee_aps_frame_t *apsFrame, const uint8_t *message, uint8_t *apsSequence) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (apsFrame != NULL) { msg.data.send_multicast.request.apsFrame = *apsFrame; @@ -371,7 +371,7 @@ sl_status_t sl_zigbee_send_reply(sl_802154_short_addr_t destination, uint8_t messageLength, uint8_t *messageContents) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_reply.request.destination = destination; if (apsFrame != NULL) { @@ -405,7 +405,7 @@ sl_status_t sl_zigbee_send_unicast(sl_zigbee_outgoing_message_type_t type, const uint8_t *message, uint8_t *apsSequence) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_unicast.request.type = type; msg.data.send_unicast.request.indexOrDestination = indexOrDestination; @@ -443,7 +443,7 @@ sl_status_t sl_zigbee_set_address_table_info(uint8_t addressTableIndex, sl_802154_long_addr_t eui64, sl_802154_short_addr_t id) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_address_table_info.request.addressTableIndex = addressTableIndex; if (eui64 != NULL) { @@ -462,7 +462,7 @@ sl_status_t sl_zigbee_set_address_table_info(uint8_t addressTableIndex, void sl_zigbee_set_aps_ack_timeout_ms(uint16_t timeout) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_aps_ack_timeout_ms.request.timeout = timeout; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_aps_ack_timeout_ms_process_ipc_command, &msg); } @@ -470,7 +470,7 @@ void sl_zigbee_set_aps_ack_timeout_ms(uint16_t timeout) sl_status_t sl_zigbee_set_extended_timeout(sl_802154_long_addr_t remoteEui64, bool extendedTimeout) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (remoteEui64 != NULL) { memmove(msg.data.set_extended_timeout.request.remoteEui64, remoteEui64, sizeof(sl_802154_long_addr_t)); @@ -488,7 +488,7 @@ sl_status_t sl_zigbee_set_extended_timeout(sl_802154_long_addr_t remoteEui64, sl_status_t sl_zigbee_set_multicast_table(const sl_zigbee_multicast_table_entry_t *entry) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (entry != NULL) { msg.data.set_multicast_table.request.entry = *entry; @@ -501,7 +501,7 @@ sl_status_t sl_zigbee_set_multicast_table(const sl_zigbee_multicast_table_entry_ sl_status_t sl_zigbee_set_multicast_table_size(uint8_t size) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_multicast_table_size.request.size = size; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_multicast_table_size_process_ipc_command, &msg); @@ -511,7 +511,7 @@ sl_status_t sl_zigbee_set_multicast_table_size(uint8_t size) sl_status_t sl_zigbee_set_passive_ack_config(sl_passive_ack_config_enum_t config, uint8_t minAcksNeeded) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_passive_ack_config.request.config = config; msg.data.set_passive_ack_config.request.minAcksNeeded = minAcksNeeded; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_passive_ack_config_process_ipc_command, &msg); @@ -521,7 +521,7 @@ sl_status_t sl_zigbee_set_passive_ack_config(sl_passive_ack_config_enum_t config void sl_zigbee_set_reply_fragment_data(uint16_t fragmentData) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_reply_fragment_data.request.fragmentData = fragmentData; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_reply_fragment_data_process_ipc_command, &msg); } @@ -530,7 +530,7 @@ sl_status_t slx_zigbee_add_to_incoming_network_queue(int8_t rssi, uint8_t lqi, const sl_nwk_packet_exchange_t *nwk_packet) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.add_to_incoming_network_queue.request.rssi = rssi; msg.data.add_to_incoming_network_queue.request.lqi = lqi; diff --git a/protocol/zigbee/stack/internal/src/ipc/mfglib_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/mfglib_ipc_command_messages.c index 9fdb58605d..5764162eac 100644 --- a/protocol/zigbee/stack/internal/src/ipc/mfglib_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/mfglib_ipc_command_messages.c @@ -113,7 +113,7 @@ void mfglibInternalStopTone_process_ipc_command(sli_zigbee_ipc_cmd_t *msg) sl_status_t mfglibEnd(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalEnd_process_ipc_command, &msg); @@ -122,7 +122,7 @@ sl_status_t mfglibEnd(void) uint8_t mfglibGetChannel(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalGetChannel_process_ipc_command, &msg); @@ -131,7 +131,7 @@ uint8_t mfglibGetChannel(void) uint16_t mfglibGetCtune(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalGetCtune_process_ipc_command, &msg); @@ -140,7 +140,7 @@ uint16_t mfglibGetCtune(void) uint8_t mfglibGetOptions(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalGetOptions_process_ipc_command, &msg); @@ -149,7 +149,7 @@ uint8_t mfglibGetOptions(void) int8_t mfglibGetPower(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalGetPower_process_ipc_command, &msg); @@ -158,7 +158,7 @@ int8_t mfglibGetPower(void) int8_t mfglibGetSynOffset(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalGetSynOffset_process_ipc_command, &msg); @@ -168,7 +168,7 @@ int8_t mfglibGetSynOffset(void) sl_status_t mfglibSendPacket(uint8_t *packet, uint16_t repeat) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if ((packet[0] + 1) > (MAX_IPC_VEC_ARG_CAPACITY)) { assert(false); // "vector packet length exceeds expected maximum @@ -188,7 +188,7 @@ sl_status_t mfglibSendPacket(uint8_t *packet, sl_status_t mfglibSetChannel(uint8_t chan) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.mfgSetChannel.request.chan = chan; sli_zigbee_send_ipc_cmd(mfglibInternalSetChannel_process_ipc_command, &msg); @@ -197,7 +197,7 @@ sl_status_t mfglibSetChannel(uint8_t chan) sl_status_t mfglibSetCtune(uint16_t ctune) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.mfgSetCtune.request.ctune = ctune; sli_zigbee_send_ipc_cmd(mfglibInternalSetCtune_process_ipc_command, &msg); @@ -206,7 +206,7 @@ sl_status_t mfglibSetCtune(uint16_t ctune) sl_status_t mfglibSetOptions(uint8_t options) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.mfgSetOptions.request.options = options; sli_zigbee_send_ipc_cmd(mfglibInternalSetOptions_process_ipc_command, &msg); @@ -216,7 +216,7 @@ sl_status_t mfglibSetOptions(uint8_t options) sl_status_t mfglibSetPower(uint16_t txPowerMode, int8_t power) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.mfgSetPower.request.txPowerMode = txPowerMode; msg.data.mfgSetPower.request.power = power; sli_zigbee_send_ipc_cmd(mfglibInternalSetPower_process_ipc_command, &msg); @@ -226,14 +226,14 @@ sl_status_t mfglibSetPower(uint16_t txPowerMode, void mfglibSetSynOffset(int8_t synOffset) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.mfgSetSynOffset.request.synOffset = synOffset; sli_zigbee_send_ipc_cmd(mfglibInternalSetSynOffset_process_ipc_command, &msg); } sl_status_t mfglibStart(MfglibRxCallback mfglibRxCallback) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.mfgStart.request.mfglibRxCallback = mfglibRxCallback; sli_zigbee_send_ipc_cmd(mfglibInternalStart_process_ipc_command, &msg); @@ -242,7 +242,7 @@ sl_status_t mfglibStart(MfglibRxCallback mfglibRxCallback) sl_status_t mfglibStartStream(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalStartStream_process_ipc_command, &msg); @@ -251,7 +251,7 @@ sl_status_t mfglibStartStream(void) sl_status_t mfglibStartTone(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalStartTone_process_ipc_command, &msg); @@ -260,7 +260,7 @@ sl_status_t mfglibStartTone(void) sl_status_t mfglibStopStream(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalStopStream_process_ipc_command, &msg); @@ -269,7 +269,7 @@ sl_status_t mfglibStopStream(void) sl_status_t mfglibStopTone(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(mfglibInternalStopTone_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/multi-network-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/multi-network-ipc-command-messages.c index e170ec4cf8..ddbb932474 100644 --- a/protocol/zigbee/stack/internal/src/ipc/multi-network-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/multi-network-ipc-command-messages.c @@ -41,7 +41,7 @@ void sli_zigbee_stack_set_current_network_process_ipc_command(sli_zigbee_ipc_cmd uint8_t sl_zigbee_get_callback_network(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_callback_network_process_ipc_command, &msg); @@ -50,7 +50,7 @@ uint8_t sl_zigbee_get_callback_network(void) uint8_t sl_zigbee_get_current_network(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_current_network_process_ipc_command, &msg); @@ -59,7 +59,7 @@ uint8_t sl_zigbee_get_current_network(void) sl_status_t sl_zigbee_set_current_network(uint8_t index) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_current_network.request.index = index; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_current_network_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/multi-phy-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/multi-phy-ipc-command-messages.c index a96f44f797..5bb0d5cb71 100644 --- a/protocol/zigbee/stack/internal/src/ipc/multi-phy-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/multi-phy-ipc-command-messages.c @@ -55,7 +55,7 @@ sl_status_t sl_zigbee_multi_phy_set_radio_channel(uint8_t phyIndex, uint8_t page, uint8_t channel) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.multi_phy_set_radio_channel.request.phyIndex = phyIndex; msg.data.multi_phy_set_radio_channel.request.page = page; msg.data.multi_phy_set_radio_channel.request.channel = channel; @@ -67,7 +67,7 @@ sl_status_t sl_zigbee_multi_phy_set_radio_channel(uint8_t phyIndex, sl_status_t sl_zigbee_multi_phy_set_radio_power(uint8_t phyIndex, int8_t power) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.multi_phy_set_radio_power.request.phyIndex = phyIndex; msg.data.multi_phy_set_radio_power.request.power = power; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_multi_phy_set_radio_power_process_ipc_command, &msg); @@ -81,7 +81,7 @@ sl_status_t sl_zigbee_multi_phy_start(uint8_t phyIndex, int8_t power, sl_zigbee_multi_phy_nwk_config_t bitmask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.multi_phy_start.request.phyIndex = phyIndex; msg.data.multi_phy_start.request.page = page; msg.data.multi_phy_start.request.channel = channel; @@ -94,7 +94,7 @@ sl_status_t sl_zigbee_multi_phy_start(uint8_t phyIndex, sl_status_t sl_zigbee_multi_phy_stop(uint8_t phyIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.multi_phy_stop.request.phyIndex = phyIndex; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_multi_phy_stop_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/network-formation-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/network-formation-ipc-command-messages.c index 6064a9d6f8..5f128f3109 100644 --- a/protocol/zigbee/stack/internal/src/ipc/network-formation-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/network-formation-ipc-command-messages.c @@ -223,7 +223,7 @@ void sli_zigbee_stack_tc_rejoins_using_well_known_key_allowed_process_ipc_comman sl_status_t sl_zigbee_clear_stored_beacons(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_stored_beacons_process_ipc_command, &msg); @@ -232,14 +232,14 @@ sl_status_t sl_zigbee_clear_stored_beacons(void) void sl_zigbee_delayed_join_activate(bool activated) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.delayed_join_activate.request.activated = activated; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_delayed_join_activate_process_ipc_command, &msg); } bool sl_zigbee_delayed_join_is_activated(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_delayed_join_is_activated_process_ipc_command, &msg); @@ -251,7 +251,7 @@ sl_status_t sl_zigbee_find_and_rejoin_network(bool haveCurrentNetworkKey, sl_zigbee_rejoin_reason_t reason, sl_zigbee_node_type_t nodeType) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.find_and_rejoin_network.request.haveCurrentNetworkKey = haveCurrentNetworkKey; msg.data.find_and_rejoin_network.request.channelMask = channelMask; msg.data.find_and_rejoin_network.request.reason = reason; @@ -264,7 +264,7 @@ sl_status_t sl_zigbee_find_and_rejoin_network(bool haveCurrentNetworkKey, sl_status_t sl_zigbee_find_unused_pan_id(uint32_t channelMask, uint8_t duration) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.find_unused_pan_id.request.channelMask = channelMask; msg.data.find_unused_pan_id.request.duration = duration; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_find_unused_pan_id_process_ipc_command, &msg); @@ -274,7 +274,7 @@ sl_status_t sl_zigbee_find_unused_pan_id(uint32_t channelMask, sl_status_t sl_zigbee_form_network(sl_zigbee_network_parameters_t *parameters) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (parameters != NULL) { msg.data.form_network.request.parameters = *parameters; @@ -291,7 +291,7 @@ sl_status_t sl_zigbee_form_network(sl_zigbee_network_parameters_t *parameters) sl_status_t sl_zigbee_get_beacon_classification_params(sl_zigbee_beacon_classification_params_t *param) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (param != NULL) { msg.data.get_beacon_classification_params.request.param = *param; @@ -308,7 +308,7 @@ sl_status_t sl_zigbee_get_beacon_classification_params(sl_zigbee_beacon_classifi sl_zigbee_leave_reason_t sl_zigbee_get_last_leave_reason(sl_802154_short_addr_t *returnNodeIdThatSentLeave) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (returnNodeIdThatSentLeave != NULL) { msg.data.get_last_leave_reason.request.returnNodeIdThatSentLeave = *returnNodeIdThatSentLeave; @@ -325,7 +325,7 @@ sl_zigbee_leave_reason_t sl_zigbee_get_last_leave_reason(sl_802154_short_addr_t sl_zigbee_rejoin_reason_t sl_zigbee_get_last_rejoin_reason(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_last_rejoin_reason_process_ipc_command, &msg); @@ -334,7 +334,7 @@ sl_zigbee_rejoin_reason_t sl_zigbee_get_last_rejoin_reason(void) uint8_t sl_zigbee_get_network_key_timeout(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_network_key_timeout_process_ipc_command, &msg); @@ -343,7 +343,7 @@ uint8_t sl_zigbee_get_network_key_timeout(void) uint8_t sl_zigbee_get_num_stored_beacons(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_num_stored_beacons_process_ipc_command, &msg); @@ -352,7 +352,7 @@ uint8_t sl_zigbee_get_num_stored_beacons(void) bool sl_zigbee_get_permit_joining(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_permit_joining_process_ipc_command, &msg); @@ -362,7 +362,7 @@ bool sl_zigbee_get_permit_joining(void) sl_status_t sl_zigbee_get_stored_beacon(uint8_t beacon_number, sl_zigbee_beacon_data_t *beacon) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_stored_beacon.request.beacon_number = beacon_number; if (beacon != NULL) { @@ -380,7 +380,7 @@ sl_status_t sl_zigbee_get_stored_beacon(uint8_t beacon_number, sl_status_t sl_zigbee_init(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_init_process_ipc_command, &msg); @@ -389,7 +389,7 @@ sl_status_t sl_zigbee_init(void) bool sl_zigbee_is_performing_rejoin(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_is_performing_rejoin_process_ipc_command, &msg); @@ -399,7 +399,7 @@ bool sl_zigbee_is_performing_rejoin(void) sl_status_t sl_zigbee_join_network(sl_zigbee_node_type_t nodeType, sl_zigbee_network_parameters_t *parameters) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.join_network.request.nodeType = nodeType; if (parameters != NULL) { @@ -420,7 +420,7 @@ sl_status_t sl_zigbee_join_network_directly(sl_zigbee_node_type_t localNodeType, int8_t radioTxPower, bool clearBeaconsAfterNetworkUp) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.join_network_directly.request.localNodeType = localNodeType; if (beacon != NULL) { @@ -440,7 +440,7 @@ sl_status_t sl_zigbee_join_network_directly(sl_zigbee_node_type_t localNodeType, sl_status_t sl_zigbee_leave_network(sl_zigbee_leave_network_option_t options) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.leave_network.request.options = options; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_leave_network_process_ipc_command, &msg); @@ -449,7 +449,7 @@ sl_status_t sl_zigbee_leave_network(sl_zigbee_leave_network_option_t options) sl_status_t sl_zigbee_network_init(sl_zigbee_network_init_struct_t *networkInitStruct) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (networkInitStruct != NULL) { msg.data.network_init.request.networkInitStruct = *networkInitStruct; @@ -466,7 +466,7 @@ sl_status_t sl_zigbee_network_init(sl_zigbee_network_init_struct_t *networkInitS sl_status_t sl_zigbee_permit_joining(uint8_t duration) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.permit_joining.request.duration = duration; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_permit_joining_process_ipc_command, &msg); @@ -475,7 +475,7 @@ sl_status_t sl_zigbee_permit_joining(uint8_t duration) sl_status_t sl_zigbee_reschedule_link_status_msg(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_reschedule_link_status_msg_process_ipc_command, &msg); @@ -484,7 +484,7 @@ sl_status_t sl_zigbee_reschedule_link_status_msg(void) bool sl_zigbee_send_pan_id_update(sl_802154_pan_id_t newPan) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_pan_id_update.request.newPan = newPan; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_send_pan_id_update_process_ipc_command, &msg); @@ -494,7 +494,7 @@ bool sl_zigbee_send_pan_id_update(sl_802154_pan_id_t newPan) sl_status_t sl_zigbee_send_zigbee_leave(sl_802154_short_addr_t destination, sl_zigbee_leave_request_flags_t flags) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_zigbee_leave.request.destination = destination; msg.data.send_zigbee_leave.request.flags = flags; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_send_zigbee_leave_process_ipc_command, &msg); @@ -504,7 +504,7 @@ sl_status_t sl_zigbee_send_zigbee_leave(sl_802154_short_addr_t destination, sl_status_t sl_zigbee_set_beacon_classification_params(sl_zigbee_beacon_classification_params_t *param) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (param != NULL) { msg.data.set_beacon_classification_params.request.param = *param; @@ -521,7 +521,7 @@ sl_status_t sl_zigbee_set_beacon_classification_params(sl_zigbee_beacon_classifi sl_status_t sl_zigbee_set_beacon_jitter_duration(uint8_t beaconJitterDuration) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_beacon_jitter_duration.request.beaconJitterDuration = beaconJitterDuration; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_beacon_jitter_duration_process_ipc_command, &msg); @@ -530,7 +530,7 @@ sl_status_t sl_zigbee_set_beacon_jitter_duration(uint8_t beaconJitterDuration) sl_status_t sl_zigbee_set_num_beacons_to_store(uint8_t numBeacons) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_num_beacons_to_store.request.numBeacons = numBeacons; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_num_beacons_to_store_process_ipc_command, &msg); @@ -540,7 +540,7 @@ sl_status_t sl_zigbee_set_num_beacons_to_store(uint8_t numBeacons) sl_status_t sl_zigbee_set_nwk_update_id(uint8_t nwkUpdateId, bool set_when_on_network) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_nwk_update_id.request.nwkUpdateId = nwkUpdateId; msg.data.set_nwk_update_id.request.set_when_on_network = set_when_on_network; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_nwk_update_id_process_ipc_command, &msg); @@ -550,14 +550,14 @@ sl_status_t sl_zigbee_set_nwk_update_id(uint8_t nwkUpdateId, void sl_zigbee_set_pending_network_update_pan_id(uint16_t panId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_pending_network_update_pan_id.request.panId = panId; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_pending_network_update_pan_id_process_ipc_command, &msg); } sl_status_t sl_zigbee_set_tc_rejoins_using_well_known_key_allowed(bool allow) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_tc_rejoins_using_well_known_key_allowed.request.allow = allow; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_tc_rejoins_using_well_known_key_allowed_process_ipc_command, &msg); @@ -566,7 +566,7 @@ sl_status_t sl_zigbee_set_tc_rejoins_using_well_known_key_allowed(bool allow) sl_status_t sl_zigbee_set_tc_rejoins_using_well_known_key_timeout_sec(uint16_t timeout_sec) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_tc_rejoins_using_well_known_key_timeout_sec.request.timeout_sec = timeout_sec; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_tc_rejoins_using_well_known_key_timeout_sec_process_ipc_command, &msg); @@ -575,7 +575,7 @@ sl_status_t sl_zigbee_set_tc_rejoins_using_well_known_key_timeout_sec(uint16_t t sl_status_t sl_zigbee_setup_delayed_join(uint8_t networkKeyTimeoutS) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.setup_delayed_join.request.networkKeyTimeoutS = networkKeyTimeoutS; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_setup_delayed_join_process_ipc_command, &msg); @@ -585,7 +585,7 @@ sl_status_t sl_zigbee_setup_delayed_join(uint8_t networkKeyTimeoutS) sl_status_t sl_zigbee_sleepy_to_sleepy_network_start(sl_zigbee_network_parameters_t *parameters, bool initiator) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (parameters != NULL) { msg.data.sleepy_to_sleepy_network_start.request.parameters = *parameters; @@ -605,7 +605,7 @@ sl_status_t sl_zigbee_start_scan(sl_zigbee_network_scan_type_t scanType, uint32_t channelMask, uint8_t duration) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.start_scan.request.scanType = scanType; msg.data.start_scan.request.channelMask = channelMask; msg.data.start_scan.request.duration = duration; @@ -616,7 +616,7 @@ sl_status_t sl_zigbee_start_scan(sl_zigbee_network_scan_type_t scanType, sl_status_t sl_zigbee_stop_scan(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_stop_scan_process_ipc_command, &msg); @@ -628,7 +628,7 @@ sl_status_t sl_zigbee_survey_beacons(bool useStandardBeacons, sl_zigbee_network_found_callback_t networkFoundCallback, sl_zigbee_scan_complete_callback_t scanCompleteCallback) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.survey_beacons.request.useStandardBeacons = useStandardBeacons; msg.data.survey_beacons.request.channel_mask = channel_mask; msg.data.survey_beacons.request.networkFoundCallback = networkFoundCallback; @@ -640,7 +640,7 @@ sl_status_t sl_zigbee_survey_beacons(bool useStandardBeacons, bool sl_zigbee_tc_rejoins_using_well_known_key_allowed(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_tc_rejoins_using_well_known_key_allowed_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/raw-message-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/raw-message-ipc-command-messages.c index f0d883f1bb..e2817e7cb1 100644 --- a/protocol/zigbee/stack/internal/src/ipc/raw-message-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/raw-message-ipc-command-messages.c @@ -60,7 +60,7 @@ void sli_zigbee_stack_set_mac_passthrough_flags_process_ipc_command(sli_zigbee_i sl_802154_short_addr_t sl_zigbee_get_embernet_passthrough_source_address(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_embernet_passthrough_source_address_process_ipc_command, &msg); @@ -69,7 +69,7 @@ sl_802154_short_addr_t sl_zigbee_get_embernet_passthrough_source_address(void) sl_zigbee_mac_passthrough_type_t sl_zigbee_get_mac_passthrough_flags(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_mac_passthrough_flags_process_ipc_command, &msg); @@ -81,7 +81,7 @@ sl_status_t sl_zigbee_send_raw_message(const uint8_t *message, sl_zigbee_transmit_priority_t priority, bool useCca) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if ((message_length) > (MAX_IPC_VEC_ARG_CAPACITY)) { assert(false); // "vector message length exceeds expected maximum @@ -98,7 +98,7 @@ sl_status_t sl_zigbee_send_raw_message(const uint8_t *message, void sl_zigbee_set_embernet_passthrough_source_address(sl_802154_short_addr_t address) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_embernet_passthrough_source_address.request.address = address; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_embernet_passthrough_source_address_process_ipc_command, &msg); } @@ -106,7 +106,7 @@ void sl_zigbee_set_embernet_passthrough_source_address(sl_802154_short_addr_t ad sl_status_t sl_zigbee_set_mac_filter_match_list(const sl_zigbee_mac_filter_match_data_t *macFilterMatchList, uint8_t listLength) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if ((listLength) > (MAX_IPC_VEC_ARG_CAPACITY)) { assert(false); // "vector macFilterMatchList length exceeds expected maximum @@ -121,7 +121,7 @@ sl_status_t sl_zigbee_set_mac_filter_match_list(const sl_zigbee_mac_filter_match void sl_zigbee_set_mac_passthrough_flags(sl_zigbee_mac_passthrough_type_t type) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_mac_passthrough_flags.request.type = type; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_mac_passthrough_flags_process_ipc_command, &msg); } diff --git a/protocol/zigbee/stack/internal/src/ipc/security_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/security_ipc_command_messages.c index e5eb29693a..7a4446f44f 100644 --- a/protocol/zigbee/stack/internal/src/ipc/security_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/security_ipc_command_messages.c @@ -171,7 +171,7 @@ sl_status_t sl_zigbee_aps_crypt_message(bool encrypt, uint8_t apsHeaderEndIndex, sl_802154_long_addr_t remoteEui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.aps_crypt_message.request.encrypt = encrypt; msg.data.aps_crypt_message.request.length = length; @@ -197,7 +197,7 @@ sl_status_t sl_zigbee_aps_crypt_message(bool encrypt, sl_status_t sl_zigbee_clear_key_table(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_key_table_process_ipc_command, &msg); @@ -206,14 +206,14 @@ sl_status_t sl_zigbee_clear_key_table(void) void sl_zigbee_clear_transient_link_keys(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_transient_link_keys_process_ipc_command, &msg); } sl_status_t sl_zigbee_erase_key_table_entry(uint8_t index) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.erase_key_table_entry.request.index = index; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_erase_key_table_entry_process_ipc_command, &msg); @@ -223,7 +223,7 @@ sl_status_t sl_zigbee_erase_key_table_entry(uint8_t index) uint8_t sl_zigbee_find_key_table_entry(sl_802154_long_addr_t address, bool linkKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (address != NULL) { memmove(msg.data.find_key_table_entry.request.address, address, sizeof(sl_802154_long_addr_t)); @@ -241,7 +241,7 @@ uint8_t sl_zigbee_find_key_table_entry(sl_802154_long_addr_t address, sl_status_t sl_zigbee_generate_random_key(sl_zigbee_key_data_t *keyAddress) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (keyAddress != NULL) { msg.data.generate_random_key.request.keyAddress = *keyAddress; @@ -258,7 +258,7 @@ sl_status_t sl_zigbee_generate_random_key(sl_zigbee_key_data_t *keyAddress) uint32_t sl_zigbee_get_aps_frame_counter(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_aps_frame_counter_process_ipc_command, &msg); @@ -267,7 +267,7 @@ uint32_t sl_zigbee_get_aps_frame_counter(void) sl_status_t sl_zigbee_get_current_security_state(sl_zigbee_current_security_state_t *state) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (state != NULL) { msg.data.get_current_security_state.request.state = *state; @@ -284,7 +284,7 @@ sl_status_t sl_zigbee_get_current_security_state(sl_zigbee_current_security_stat sl_status_t sl_zigbee_get_extended_security_bitmask(sl_zigbee_extended_security_bitmask_t *mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (mask != NULL) { msg.data.get_extended_security_bitmask.request.mask = *mask; @@ -301,7 +301,7 @@ sl_status_t sl_zigbee_get_extended_security_bitmask(sl_zigbee_extended_security_ uint32_t sl_zigbee_get_incoming_tc_link_key_frame_counter(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_incoming_tc_link_key_frame_counter_process_ipc_command, &msg); @@ -310,7 +310,7 @@ uint32_t sl_zigbee_get_incoming_tc_link_key_frame_counter(void) sl_status_t sl_zigbee_get_mfg_security_config(sl_zigbee_mfg_security_struct_t *settings) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (settings != NULL) { msg.data.get_mfg_security_config.request.settings = *settings; @@ -327,7 +327,7 @@ sl_status_t sl_zigbee_get_mfg_security_config(sl_zigbee_mfg_security_struct_t *s sl_zigbee_aps_rejoin_mode_t sl_zigbee_get_rejoin_mode(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_rejoin_mode_process_ipc_command, &msg); @@ -336,7 +336,7 @@ sl_zigbee_aps_rejoin_mode_t sl_zigbee_get_rejoin_mode(void) uint32_t sl_zigbee_get_security_frame_counter(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_security_frame_counter_process_ipc_command, &msg); @@ -345,7 +345,7 @@ uint32_t sl_zigbee_get_security_frame_counter(void) uint16_t sl_zigbee_get_transient_key_timeout_s(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_transient_key_timeout_s_process_ipc_command, &msg); @@ -354,7 +354,7 @@ uint16_t sl_zigbee_get_transient_key_timeout_s(void) sl_status_t sl_zigbee_request_link_key(sl_802154_long_addr_t partner) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (partner != NULL) { memmove(msg.data.request_link_key.request.partner, partner, sizeof(sl_802154_long_addr_t)); @@ -371,7 +371,7 @@ sl_status_t sl_zigbee_request_link_key(sl_802154_long_addr_t partner) sl_status_t sl_zigbee_set_extended_security_bitmask(sl_zigbee_extended_security_bitmask_t mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_extended_security_bitmask.request.mask = mask; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_extended_security_bitmask_process_ipc_command, &msg); @@ -380,14 +380,14 @@ sl_status_t sl_zigbee_set_extended_security_bitmask(sl_zigbee_extended_security_ void sl_zigbee_set_incoming_tc_link_key_frame_counter(uint32_t frameCounter) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_incoming_tc_link_key_frame_counter.request.frameCounter = frameCounter; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_incoming_tc_link_key_frame_counter_process_ipc_command, &msg); } sl_status_t sl_zigbee_set_initial_security_state(sl_zigbee_initial_security_state_t *state) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (state != NULL) { msg.data.set_initial_security_state.request.state = *state; @@ -405,7 +405,7 @@ sl_status_t sl_zigbee_set_initial_security_state(sl_zigbee_initial_security_stat sl_status_t sl_zigbee_set_mfg_security_config(uint32_t magicNumber, const sl_zigbee_mfg_security_struct_t *settings) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_mfg_security_config.request.magicNumber = magicNumber; if (settings != NULL) { @@ -419,7 +419,7 @@ sl_status_t sl_zigbee_set_mfg_security_config(uint32_t magicNumber, sl_status_t sl_zigbee_set_outgoing_aps_frame_counter(uint32_t desiredValue) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_outgoing_aps_frame_counter.request.desiredValue = desiredValue; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_outgoing_aps_frame_counter_process_ipc_command, &msg); @@ -428,7 +428,7 @@ sl_status_t sl_zigbee_set_outgoing_aps_frame_counter(uint32_t desiredValue) sl_status_t sl_zigbee_set_outgoing_nwk_frame_counter(uint32_t desiredValue) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_outgoing_nwk_frame_counter.request.desiredValue = desiredValue; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_outgoing_nwk_frame_counter_process_ipc_command, &msg); @@ -437,21 +437,21 @@ sl_status_t sl_zigbee_set_outgoing_nwk_frame_counter(uint32_t desiredValue) void sl_zigbee_set_rejoin_mode(sl_zigbee_aps_rejoin_mode_t mode) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_rejoin_mode.request.mode = mode; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_rejoin_mode_process_ipc_command, &msg); } void sl_zigbee_set_transient_key_timeout_s(uint16_t seconds) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_transient_key_timeout_s.request.seconds = seconds; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_transient_key_timeout_s_process_ipc_command, &msg); } sl_status_t sl_zigbee_start_writing_stack_tokens(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_start_writing_stack_tokens_process_ipc_command, &msg); @@ -460,7 +460,7 @@ sl_status_t sl_zigbee_start_writing_stack_tokens(void) sl_status_t sl_zigbee_stop_writing_stack_tokens(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_stop_writing_stack_tokens_process_ipc_command, &msg); @@ -469,7 +469,7 @@ sl_status_t sl_zigbee_stop_writing_stack_tokens(void) sl_status_t sl_zigbee_update_tc_link_key(uint8_t maxAttempts) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.update_tc_link_key.request.maxAttempts = maxAttempts; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_update_tc_link_key_process_ipc_command, &msg); @@ -478,7 +478,7 @@ sl_status_t sl_zigbee_update_tc_link_key(uint8_t maxAttempts) bool sl_zigbee_writing_stack_tokens_enabled(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_writing_stack_tokens_enabled_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_address_info_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_address_info_ipc_command_messages.c index c1835c339b..f92b11f6a8 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_address_info_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_address_info_ipc_command_messages.c @@ -39,7 +39,7 @@ void sli_zigbee_stack_make_device_id_pair_process_ipc_command(sli_zigbee_ipc_cmd bool sl_zigbee_device_id_matches(const sl_zigbee_address_info *set_a, const sl_zigbee_address_info *set_b) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (set_a != NULL) { msg.data.device_id_matches.request.set_a = *set_a; @@ -57,7 +57,7 @@ bool sl_zigbee_device_id_matches(const sl_zigbee_address_info *set_a, sl_zigbee_address_info sl_zigbee_make_device_id_pair(const sl_802154_short_addr_t short_id, const sl_802154_long_addr_t long_id) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.make_device_id_pair.request.short_id = short_id; if (long_id != NULL) { diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_alternate_mac_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_alternate_mac_ipc_command_messages.c index e54ba6bb12..d1a9d2eeec 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_alternate_mac_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_alternate_mac_ipc_command_messages.c @@ -31,7 +31,7 @@ void sli_zigbee_stack_alt_mac_init_process_ipc_command(sli_zigbee_ipc_cmd_t *msg sl_zigbee_mac_interface_id_t sl_zigbee_alt_mac_init(const sl_zigbee_alt_mac_config_t *config) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (config != NULL) { msg.data.alt_mac_init.request.config = *config; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dlk_negotiation_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dlk_negotiation_ipc_command_messages.c index 641d3234bb..ad5c6fe836 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dlk_negotiation_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dlk_negotiation_ipc_command_messages.c @@ -56,7 +56,7 @@ void sli_zigbee_stack_dlk_start_key_exchange_process_ipc_command(sli_zigbee_ipc_ void sl_zigbee_dlk_close_key_exchange(sl_zigbee_dlk_negotiation_context_t *dlk_negotiation_ctx) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_negotiation_ctx != NULL) { msg.data.dlk_close_key_exchange.request.dlk_negotiation_ctx = *dlk_negotiation_ctx; @@ -74,7 +74,7 @@ sl_status_t sl_zigbee_dlk_finish_key_exchange(sl_zigbee_dlk_negotiation_context_ const uint8_t *partner_key, size_t partner_key_length) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_negotiation_ctx != NULL) { msg.data.dlk_finish_key_exchange.request.dlk_negotiation_ctx = *dlk_negotiation_ctx; @@ -107,7 +107,7 @@ sl_status_t sl_zigbee_dlk_open_key_exchange(sl_zigbee_dlk_negotiation_context_t sl_zigbee_dlk_start_complete_callback dlk_start_complete_callback, sl_zigbee_dlk_finish_complete_callback dlk_finish_complete_callback) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_negotiation_ctx != NULL) { msg.data.dlk_open_key_exchange.request.dlk_negotiation_ctx = *dlk_negotiation_ctx; @@ -138,7 +138,7 @@ sl_status_t sl_zigbee_dlk_open_key_exchange(sl_zigbee_dlk_negotiation_context_t sl_status_t sl_zigbee_dlk_start_key_exchange(sl_zigbee_dlk_negotiation_context_t *dlk_negotiation_ctx, const sl_zigbee_address_info *partner) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_negotiation_ctx != NULL) { msg.data.dlk_start_key_exchange.request.dlk_negotiation_ctx = *dlk_negotiation_ctx; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_duty_cycle_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_duty_cycle_ipc_command_messages.c index edbade7407..b04aac0a48 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_duty_cycle_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_duty_cycle_ipc_command_messages.c @@ -48,7 +48,7 @@ void sli_zigbee_stack_set_duty_cycle_limits_in_stack_process_ipc_command(sli_zig sl_status_t sl_zigbee_get_current_duty_cycle(uint8_t maxDevices, sl_zigbee_per_device_duty_cycle_t *arrayOfDeviceDutyCycles) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_current_duty_cycle.request.maxDevices = maxDevices; if ((maxDevices) > (SL_ZIGBEE_MAX_CHILDREN_FOR_PER_DEVICE_DUTY_CYCLE_MONITOR)) { @@ -68,7 +68,7 @@ sl_status_t sl_zigbee_get_current_duty_cycle(uint8_t maxDevices, sl_status_t sl_zigbee_get_duty_cycle_limits(sl_zigbee_duty_cycle_limits_t *returnedLimits) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (returnedLimits != NULL) { msg.data.get_duty_cycle_limits.request.returnedLimits = *returnedLimits; @@ -85,7 +85,7 @@ sl_status_t sl_zigbee_get_duty_cycle_limits(sl_zigbee_duty_cycle_limits_t *retur sl_status_t sl_zigbee_get_duty_cycle_state(sl_zigbee_duty_cycle_state_t *returnedState) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (returnedState != NULL) { msg.data.get_duty_cycle_state.request.returnedState = *returnedState; @@ -102,7 +102,7 @@ sl_status_t sl_zigbee_get_duty_cycle_state(sl_zigbee_duty_cycle_state_t *returne sl_status_t sl_zigbee_set_duty_cycle_limits_in_stack(const sl_zigbee_duty_cycle_limits_t *limits) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (limits != NULL) { msg.data.set_duty_cycle_limits_in_stack.request.limits = *limits; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dynamic_commissioning_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dynamic_commissioning_ipc_command_messages.c index 6d78864917..d1a0c086b8 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dynamic_commissioning_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_dynamic_commissioning_ipc_command_messages.c @@ -43,7 +43,7 @@ void sli_zigbee_stack_dynamic_commissioning_set_open_for_interview_process_ipc_c void sl_zigbee_device_interview_status_update(sl_zigbee_address_info *ids, sl_zigbee_dynamic_commissioning_event_t event) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (ids != NULL) { msg.data.device_interview_status_update.request.ids = *ids; @@ -59,7 +59,7 @@ void sl_zigbee_device_interview_status_update(sl_zigbee_address_info *ids, bool sl_zigbee_dynamic_commissioning_is_open_for_interview(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_dynamic_commissioning_is_open_for_interview_process_ipc_command, &msg); @@ -68,7 +68,7 @@ bool sl_zigbee_dynamic_commissioning_is_open_for_interview(void) void sl_zigbee_dynamic_commissioning_set_open_for_interview(bool open_interview) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.dynamic_commissioning_set_open_for_interview.request.open_interview = open_interview; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_dynamic_commissioning_set_open_for_interview_process_ipc_command, &msg); } diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_random_api_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_random_api_ipc_command_messages.c index 7473a1ef4c..13cdb4aa32 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_random_api_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_random_api_ipc_command_messages.c @@ -42,7 +42,7 @@ void sli_zigbee_stack_get_strong_random_number_array_process_ipc_command(sli_zig uint16_t sl_zigbee_get_pseudo_random_number(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_pseudo_random_number_process_ipc_command, &msg); @@ -51,7 +51,7 @@ uint16_t sl_zigbee_get_pseudo_random_number(void) sl_zigbee_entropy_source_t sl_zigbee_get_strong_random_entropy_source(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_strong_random_entropy_source_process_ipc_command, &msg); @@ -61,7 +61,7 @@ sl_zigbee_entropy_source_t sl_zigbee_get_strong_random_entropy_source(void) sl_status_t sl_zigbee_get_strong_random_number_array(uint16_t *randomNumber, uint8_t count) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if ((count) > (MAX_IPC_VEC_ARG_CAPACITY / sizeof(uint16_t))) { assert(false); // "vector randomNumber length exceeds expected maximum diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_ipc_command_messages.c index a81267e9cf..17f432dae1 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_ipc_command_messages.c @@ -71,7 +71,7 @@ void sli_zigbee_stack_sec_man_speke_expand_shared_secret_process_ipc_command(sli sl_status_t sl_zigbee_sec_man_ecc_derive_link_key(sl_zigbee_sec_man_dlk_ecc_context_t *dlk_ecc_ctx) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_ecc_derive_link_key.request.dlk_ecc_ctx = *dlk_ecc_ctx; @@ -90,7 +90,7 @@ sl_status_t sl_zigbee_sec_man_ecc_expand_shared_secret(sl_zigbee_sec_man_dlk_ecc const uint8_t *our_eui, const uint8_t *their_eui) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_ecc_expand_shared_secret.request.dlk_ecc_ctx = *dlk_ecc_ctx; @@ -117,7 +117,7 @@ sl_status_t sl_zigbee_sec_man_ecc_extract_shared_secret(sl_zigbee_sec_man_dlk_ec const uint8_t *peer_public_key, size_t peer_key_len) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_ecc_extract_shared_secret.request.dlk_ecc_ctx = *dlk_ecc_ctx; @@ -140,7 +140,7 @@ sl_status_t sl_zigbee_sec_man_ecc_extract_shared_secret(sl_zigbee_sec_man_dlk_ec void sl_zigbee_sec_man_ecc_free(sl_zigbee_sec_man_dlk_ecc_context_t *dlk_ecc_ctx) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_ecc_free.request.dlk_ecc_ctx = *dlk_ecc_ctx; @@ -157,7 +157,7 @@ sl_status_t sl_zigbee_sec_man_ecc_generate_keypair(sl_zigbee_sec_man_dlk_ecc_con uint8_t *public_key_buff, size_t *key_len_out) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_ecc_generate_keypair.request.dlk_ecc_ctx = *dlk_ecc_ctx; @@ -192,7 +192,7 @@ sl_status_t sl_zigbee_sec_man_ecc_init(sl_zigbee_sec_man_dlk_ecc_context_t *dlk_ sl_zb_dlk_ecc_config_t *config, const uint8_t *psk) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_ecc_init.request.dlk_ecc_ctx = *dlk_ecc_ctx; @@ -223,7 +223,7 @@ sl_status_t sl_zigbee_sec_man_speke_expand_shared_secret(sl_zigbee_sec_man_dlk_e const uint8_t *our_eui, const uint8_t *their_eui) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_speke_expand_shared_secret.request.dlk_ecc_ctx = *dlk_ecc_ctx; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_test_vectors_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_test_vectors_ipc_command_messages.c index 2c401367a5..0d312880d2 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_test_vectors_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_security_manager_dlk_ecc_test_vectors_ipc_command_messages.c @@ -44,7 +44,7 @@ void sli_zigbee_stack_sec_man_ecc_init_with_test_vector_process_ipc_command(sli_ sl_zigbee_dlk_ecc_test_vector_profile_data_t * sl_zigbee_dlk_ecc_test_vector_get_profile(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_dlk_ecc_test_vector_get_profile_process_ipc_command, &msg); @@ -53,7 +53,7 @@ sl_zigbee_dlk_ecc_test_vector_profile_data_t * sl_zigbee_dlk_ecc_test_vector_get void sl_zigbee_dlk_ecc_test_vector_set_profile(const sl_zigbee_dlk_ecc_test_vector_profile_data_t *profile) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (profile != NULL) { msg.data.dlk_ecc_test_vector_set_profile.request.profile = *profile; @@ -67,7 +67,7 @@ sl_status_t sl_zigbee_sec_man_ecc_init_with_test_vector(sl_zigbee_sec_man_dlk_ec uint8_t *psk, sl_zigbee_dlk_ecc_test_vector_bundle_t *vector_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (dlk_ecc_ctx != NULL) { msg.data.sec_man_ecc_init_with_test_vector.request.dlk_ecc_ctx = *dlk_ecc_ctx; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_stack_specific_tlv_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_stack_specific_tlv_ipc_command_messages.c index e76c752f86..f314edaa47 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_stack_specific_tlv_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_stack_specific_tlv_ipc_command_messages.c @@ -119,7 +119,7 @@ sl_status_t sl_zigbee_global_tlv_add_configurations(sli_buffer_manager_buffer_t uint8_t tag_c, const uint8_t *tag_v) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (buffer != NULL) { msg.data.global_tlv_add_configurations.request.buffer = *buffer; @@ -144,7 +144,7 @@ sl_status_t sl_zigbee_global_tlv_add_configurations(sli_buffer_manager_buffer_t sl_status_t sl_zigbee_global_tlv_beacon_appendix_encapsulation(sl_zigbee_global_tlv_beacon_appendix_encap_t *encapTlv) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (encapTlv != NULL) { msg.data.global_tlv_beacon_appendix_encapsulation.request.encapTlv = *encapTlv; @@ -161,7 +161,7 @@ sl_status_t sl_zigbee_global_tlv_beacon_appendix_encapsulation(sl_zigbee_global_ sl_zigbee_global_tlv_configuration_params_t sl_zigbee_global_tlv_configuration_params_from_bitmask(uint16_t mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.global_tlv_configuration_params_from_bitmask.request.mask = mask; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_configuration_params_from_bitmask_process_ipc_command, &msg); @@ -170,7 +170,7 @@ sl_zigbee_global_tlv_configuration_params_t sl_zigbee_global_tlv_configuration_p uint16_t sl_zigbee_global_tlv_configuration_params_get_bitmask(sl_zigbee_global_tlv_configuration_params_t *tlv) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (tlv != NULL) { msg.data.global_tlv_configuration_params_get_bitmask.request.tlv = *tlv; @@ -187,7 +187,7 @@ uint16_t sl_zigbee_global_tlv_configuration_params_get_bitmask(sl_zigbee_global_ sl_zigbee_global_tlv_device_capability_extension_t sl_zigbee_global_tlv_device_capability_extension_param(uint16_t bitmask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.global_tlv_device_capability_extension_param.request.bitmask = bitmask; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_device_capability_extension_param_process_ipc_command, &msg); @@ -196,7 +196,7 @@ sl_zigbee_global_tlv_device_capability_extension_t sl_zigbee_global_tlv_device_c sl_zigbee_global_tlv_fragmentation_param_t sl_zigbee_global_tlv_fragmentation_param(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_fragmentation_param_process_ipc_command, &msg); @@ -206,7 +206,7 @@ sl_zigbee_global_tlv_fragmentation_param_t sl_zigbee_global_tlv_fragmentation_pa sli_buffer_manager_buffer_t sl_zigbee_global_tlv_get_configurations(uint8_t tag_c, const uint8_t *tag_v) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.global_tlv_get_configurations.request.tag_c = tag_c; if ((tag_c) > (10)) { @@ -221,7 +221,7 @@ sli_buffer_manager_buffer_t sl_zigbee_global_tlv_get_configurations(uint8_t tag_ sl_status_t sl_zigbee_global_tlv_joiner_encapsulation(sl_zigbee_global_tlv_joiner_encap_t *encapTlv) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (encapTlv != NULL) { msg.data.global_tlv_joiner_encapsulation.request.encapTlv = *encapTlv; @@ -238,7 +238,7 @@ sl_status_t sl_zigbee_global_tlv_joiner_encapsulation(sl_zigbee_global_tlv_joine uint32_t sl_zigbee_global_tlv_next_channel_change_get_bitmask(sl_zigbee_global_tlv_next_channel_change_t *tlv) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (tlv != NULL) { msg.data.global_tlv_next_channel_change_get_bitmask.request.tlv = *tlv; @@ -256,7 +256,7 @@ uint32_t sl_zigbee_global_tlv_next_channel_change_get_bitmask(sl_zigbee_global_t sl_zigbee_global_tlv_next_channel_change_t sl_zigbee_global_tlv_next_channel_from_pg_ch(uint8_t page, uint8_t channel) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.global_tlv_next_channel_from_pg_ch.request.page = page; msg.data.global_tlv_next_channel_from_pg_ch.request.channel = channel; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_next_channel_from_pg_ch_process_ipc_command, &msg); @@ -266,7 +266,7 @@ sl_zigbee_global_tlv_next_channel_change_t sl_zigbee_global_tlv_next_channel_fro sl_zigbee_global_tlv_next_pan_id_t sl_zigbee_global_tlv_next_pan_from_pan(sl_802154_pan_id_t pan_id) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.global_tlv_next_pan_from_pan.request.pan_id = pan_id; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_next_pan_from_pan_process_ipc_command, &msg); @@ -275,7 +275,7 @@ sl_zigbee_global_tlv_next_pan_id_t sl_zigbee_global_tlv_next_pan_from_pan(sl_802 sl_802154_pan_id_t sl_zigbee_global_tlv_next_pan_get_pan(sl_zigbee_global_tlv_next_pan_id_t *tlv) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (tlv != NULL) { msg.data.global_tlv_next_pan_get_pan.request.tlv = *tlv; @@ -292,7 +292,7 @@ sl_802154_pan_id_t sl_zigbee_global_tlv_next_pan_get_pan(sl_zigbee_global_tlv_ne sl_zigbee_global_tlv_pan_id_conflict_t sl_zigbee_global_tlv_pan_id_conflict(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_pan_id_conflict_process_ipc_command, &msg); @@ -301,7 +301,7 @@ sl_zigbee_global_tlv_pan_id_conflict_t sl_zigbee_global_tlv_pan_id_conflict(void sl_zigbee_global_tlv_router_information_t sl_zigbee_global_tlv_router_information(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_router_information_process_ipc_command, &msg); @@ -310,7 +310,7 @@ sl_zigbee_global_tlv_router_information_t sl_zigbee_global_tlv_router_informatio uint16_t sl_zigbee_global_tlv_router_information_get_bitmask(sl_zigbee_global_tlv_router_information_t *tlv) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (tlv != NULL) { msg.data.global_tlv_router_information_get_bitmask.request.tlv = *tlv; @@ -327,7 +327,7 @@ uint16_t sl_zigbee_global_tlv_router_information_get_bitmask(sl_zigbee_global_tl sl_zigbee_global_tlv_supp_key_negotiation_t sl_zigbee_global_tlv_supp_key_negotiation(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_global_tlv_supp_key_negotiation_process_ipc_command, &msg); @@ -336,7 +336,7 @@ sl_zigbee_global_tlv_supp_key_negotiation_t sl_zigbee_global_tlv_supp_key_negoti sl_zigbee_global_tlv_symmetric_passphrase_t sl_zigbee_global_tlv_symmetric_passphrase(const uint8_t *passphrase) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (passphrase != NULL) { msg.data.global_tlv_symmetric_passphrase.request.passphrase = *passphrase; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_configuration_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_configuration_ipc_command_messages.c index 58f552fc11..55ddcf8267 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_configuration_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_configuration_ipc_command_messages.c @@ -50,7 +50,7 @@ sl_status_t sl_zigbee_zdo_get_configuration_req(sl_802154_short_addr_t device_sh uint8_t *tag_ids, uint8_t count) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.zdo_get_configuration_req.request.device_short = device_short; msg.data.zdo_get_configuration_req.request.encrypt = encrypt; @@ -74,7 +74,7 @@ sl_status_t sl_zigbee_zdo_set_add_configuration(uint8_t tag_id, size_t zdo_config_arg_len, const uint8_t *zdo_config_arg) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.zdo_set_add_configuration.request.tag_id = tag_id; msg.data.zdo_set_add_configuration.request.zdo_config_arg_len = zdo_config_arg_len; @@ -91,7 +91,7 @@ sl_status_t sl_zigbee_zdo_set_add_configuration(uint8_t tag_id, sl_status_t sl_zigbee_zdo_set_send_configuration_req(sl_802154_short_addr_t device_short, bool encrypt) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.zdo_set_send_configuration_req.request.device_short = device_short; msg.data.zdo_set_send_configuration_req.request.encrypt = encrypt; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zdo_set_send_configuration_req_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_dlk_negotiation_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_dlk_negotiation_ipc_command_messages.c index e06156acc4..a7ac90555c 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_dlk_negotiation_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_dlk_negotiation_ipc_command_messages.c @@ -67,7 +67,7 @@ void slxi_zigbee_stack_gu_zdo_dlk_override_supported_params_process_ipc_command( bool sl_zigbee_zdo_dlk_enabled(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zdo_dlk_enabled_process_ipc_command, &msg); @@ -77,7 +77,7 @@ bool sl_zigbee_zdo_dlk_enabled(void) void sl_zigbee_zdo_dlk_get_supported_negotiation_parameters(sl_zigbee_dlk_supported_negotiation_method *method_mask, sl_zigbee_dlk_negotiation_supported_shared_secret_source *secret_mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (method_mask != NULL) { msg.data.zdo_dlk_get_supported_negotiation_parameters.request.method_mask = *method_mask; @@ -102,7 +102,7 @@ sl_status_t sl_zigbee_zdo_dlk_start_key_negotiation(sl_zigbee_address_info *part sl_zigbee_dlk_negotiation_method selected_method, sl_zigbee_dlk_negotiation_shared_secret_source selected_secret) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (partner != NULL) { msg.data.zdo_dlk_start_key_negotiation.request.partner = *partner; @@ -123,7 +123,7 @@ sl_status_t sl_zigbee_zdo_dlk_start_key_update(sl_zigbee_address_info *target, sl_zigbee_dlk_negotiation_method selected_method, sl_zigbee_dlk_negotiation_shared_secret_source selected_secret) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (target != NULL) { msg.data.zdo_dlk_start_key_update.request.target = *target; @@ -142,7 +142,7 @@ sl_status_t sl_zigbee_zdo_dlk_start_key_update(sl_zigbee_address_info *target, bool slx_zigbee_gu_zdo_dlk_mangle_packet(sli_buffer_manager_buffer_t *buffer) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (buffer != NULL) { msg.data.gu_zdo_dlk_mangle_packet.request.buffer = *buffer; @@ -159,7 +159,7 @@ bool slx_zigbee_gu_zdo_dlk_mangle_packet(sli_buffer_manager_buffer_t *buffer) bool slx_zigbee_gu_zdo_dlk_override_psk(uint8_t *key_buffer) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (key_buffer != NULL) { msg.data.gu_zdo_dlk_override_psk.request.key_buffer = *key_buffer; @@ -177,7 +177,7 @@ bool slx_zigbee_gu_zdo_dlk_override_psk(uint8_t *key_buffer) void slx_zigbee_gu_zdo_dlk_override_supported_params(sl_zigbee_dlk_supported_negotiation_method *method_mask, sl_zigbee_dlk_negotiation_supported_shared_secret_source *secret_mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (method_mask != NULL) { msg.data.gu_zdo_dlk_override_supported_params.request.method_mask = *method_mask; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_management_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_management_ipc_command_messages.c index b2910086ea..18e17e8a79 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_management_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_management_ipc_command_messages.c @@ -37,7 +37,7 @@ sl_status_t sl_zigbee_request_beacon_survey(sl_802154_short_addr_t dest, uint32_t *channel_masks, uint8_t scan_config_mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.request_beacon_survey.request.dest = dest; msg.data.request_beacon_survey.request.channel_page_count = channel_page_count; diff --git a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_security_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_security_ipc_command_messages.c index 8a267c4676..20c3afd245 100644 --- a/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_security_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/sl_zigbee_zdo_security_ipc_command_messages.c @@ -53,7 +53,7 @@ void sli_zigbee_stack_retrieve_authentication_token_process_ipc_command(sli_zigb sl_status_t sl_zigbee_get_authentication_level(sl_802154_short_addr_t dest, sl_802154_long_addr_t target) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_authentication_level.request.dest = dest; if (target != NULL) { @@ -73,7 +73,7 @@ sl_status_t sl_zigbee_get_symmetric_passphrase(sl_802154_long_addr_t eui64, sl_802154_short_addr_t short_id, uint8_t *passphrase) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui64 != NULL) { memmove(msg.data.get_symmetric_passphrase.request.eui64, eui64, sizeof(sl_802154_long_addr_t)); @@ -102,7 +102,7 @@ sl_status_t sl_zigbee_initiate_security_challenge(sl_802154_short_addr_t partner sl_802154_long_addr_t partnerLong, uint8_t keyIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.initiate_security_challenge.request.partnerNodeId = partnerNodeId; if (partnerLong != NULL) { @@ -122,7 +122,7 @@ sl_status_t sl_zigbee_initiate_security_challenge(sl_802154_short_addr_t partner void sl_zigbee_retrieve_authentication_token(sl_802154_short_addr_t destination, sl_zigbee_aps_option_t options) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.retrieve_authentication_token.request.destination = destination; msg.data.retrieve_authentication_token.request.options = options; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_retrieve_authentication_token_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/source-route-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/source-route-ipc-command-messages.c index 73857dba23..b3f3fbcad8 100644 --- a/protocol/zigbee/stack/internal/src/ipc/source-route-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/source-route-ipc-command-messages.c @@ -103,7 +103,7 @@ void sli_zigbee_stack_set_source_route_discovery_mode_process_ipc_command(sli_zi void sl_zigbee_concentrator_note_delivery_failure(sl_zigbee_outgoing_message_type_t type, sl_status_t status) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.concentrator_note_delivery_failure.request.type = type; msg.data.concentrator_note_delivery_failure.request.status = status; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_concentrator_note_delivery_failure_process_ipc_command, &msg); @@ -112,7 +112,7 @@ void sl_zigbee_concentrator_note_delivery_failure(sl_zigbee_outgoing_message_typ void sl_zigbee_concentrator_note_route_error(sl_status_t status, sl_802154_short_addr_t nodeId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.concentrator_note_route_error.request.status = status; msg.data.concentrator_note_route_error.request.nodeId = nodeId; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_concentrator_note_route_error_process_ipc_command, &msg); @@ -120,21 +120,21 @@ void sl_zigbee_concentrator_note_route_error(sl_status_t status, void sl_zigbee_concentrator_start_discovery(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_concentrator_start_discovery_process_ipc_command, &msg); } void sl_zigbee_concentrator_stop_discovery(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_concentrator_stop_discovery_process_ipc_command, &msg); } sl_zigbee_assume_trust_center_concentrator_type_t sl_zigbee_get_assumed_trust_center_concentrator_type(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_assumed_trust_center_concentrator_type_process_ipc_command, &msg); @@ -143,7 +143,7 @@ sl_zigbee_assume_trust_center_concentrator_type_t sl_zigbee_get_assumed_trust_ce uint8_t sl_zigbee_get_source_route_overhead(sl_802154_short_addr_t destination) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_source_route_overhead.request.destination = destination; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_source_route_overhead_process_ipc_command, &msg); @@ -154,7 +154,7 @@ sl_status_t sl_zigbee_get_source_route_table_entry(uint8_t index, sl_802154_short_addr_t *destination, uint8_t *closerIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_source_route_table_entry.request.index = index; if (destination != NULL) { @@ -180,7 +180,7 @@ sl_status_t sl_zigbee_get_source_route_table_entry(uint8_t index, uint8_t sl_zigbee_get_source_route_table_filled_size(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_source_route_table_filled_size_process_ipc_command, &msg); @@ -189,7 +189,7 @@ uint8_t sl_zigbee_get_source_route_table_filled_size(void) uint8_t sl_zigbee_get_source_route_table_total_size(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_source_route_table_total_size_process_ipc_command, &msg); @@ -199,7 +199,7 @@ uint8_t sl_zigbee_get_source_route_table_total_size(void) sl_status_t sl_zigbee_send_many_to_one_route_request(uint16_t concentratorType, uint8_t radius) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_many_to_one_route_request.request.concentratorType = concentratorType; msg.data.send_many_to_one_route_request.request.radius = radius; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_send_many_to_one_route_request_process_ipc_command, &msg); @@ -209,7 +209,7 @@ sl_status_t sl_zigbee_send_many_to_one_route_request(uint16_t concentratorType, void sl_zigbee_set_assumed_trust_center_concentrator_type(sl_zigbee_assume_trust_center_concentrator_type_t type) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_assumed_trust_center_concentrator_type.request.type = type; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_assumed_trust_center_concentrator_type_process_ipc_command, &msg); } @@ -222,7 +222,7 @@ sl_status_t sl_zigbee_set_concentrator(bool on, uint8_t deliveryFailureThresholdParam, uint8_t maxHopsParam) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_concentrator.request.on = on; msg.data.set_concentrator.request.concentratorTypeParam = concentratorTypeParam; msg.data.set_concentrator.request.minTime = minTime; @@ -237,7 +237,7 @@ sl_status_t sl_zigbee_set_concentrator(bool on, uint32_t sl_zigbee_set_source_route_discovery_mode(sl_zigbee_source_route_discovery_mode_t mode) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_source_route_discovery_mode.request.mode = mode; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_source_route_discovery_mode_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/stack-info-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/stack-info-ipc-command-messages.c index 99c4472b04..89bf3b344e 100644 --- a/protocol/zigbee/stack/internal/src/ipc/stack-info-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/stack-info-ipc-command-messages.c @@ -436,7 +436,7 @@ void slxi_zigbee_stack_routing_set_route_record_policy_process_ipc_command(sli_z uint16_t sl_802154_get_tx_power_mode(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_802154_stack_get_tx_power_mode_process_ipc_command, &msg); @@ -445,7 +445,7 @@ uint16_t sl_802154_get_tx_power_mode(void) sl_status_t sl_802154_radio_get_scheduler_priorities(sl_802154_radio_priorities_t *priorities) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (priorities != NULL) { msg.data.radio_get_scheduler_priorities.request.priorities = *priorities; @@ -462,7 +462,7 @@ sl_status_t sl_802154_radio_get_scheduler_priorities(sl_802154_radio_priorities_ sl_status_t sl_802154_radio_get_scheduler_sliptime(uint32_t *slipTime) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (slipTime != NULL) { msg.data.radio_get_scheduler_sliptime.request.slipTime = *slipTime; @@ -479,7 +479,7 @@ sl_status_t sl_802154_radio_get_scheduler_sliptime(uint32_t *slipTime) sl_status_t sl_802154_radio_set_scheduler_priorities(const sl_802154_radio_priorities_t *priorities) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (priorities != NULL) { msg.data.radio_set_scheduler_priorities.request.priorities = *priorities; @@ -492,7 +492,7 @@ sl_status_t sl_802154_radio_set_scheduler_priorities(const sl_802154_radio_prior sl_status_t sl_802154_radio_set_scheduler_sliptime(uint32_t slipTime) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.radio_set_scheduler_sliptime.request.slipTime = slipTime; sli_zigbee_send_ipc_cmd(sli_802154_stack_radio_set_scheduler_sliptime_process_ipc_command, &msg); @@ -501,7 +501,7 @@ sl_status_t sl_802154_radio_set_scheduler_sliptime(uint32_t slipTime) sl_status_t sl_802154_set_tx_power_mode(uint16_t txPowerMode) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_tx_power_mode.request.txPowerMode = txPowerMode; sli_zigbee_send_ipc_cmd(sli_802154_stack_set_tx_power_mode_process_ipc_command, &msg); @@ -510,14 +510,14 @@ sl_status_t sl_802154_set_tx_power_mode(uint16_t txPowerMode) void sl_mac_calibrate_current_channel(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_mac_stack_calibrate_current_channel_process_ipc_command, &msg); } void sl_mac_get_csma_params(sl_mac_csma_parameters_t *csma_params) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (csma_params != NULL) { msg.data.get_csma_params.request.csma_params = *csma_params; @@ -532,7 +532,7 @@ void sl_mac_get_csma_params(sl_mac_csma_parameters_t *csma_params) int8_t sl_mac_get_ed_cca_threshold(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_mac_stack_get_ed_cca_threshold_process_ipc_command, &msg); @@ -541,14 +541,14 @@ int8_t sl_mac_get_ed_cca_threshold(void) void sl_mac_set_cca_threshold(int8_t threshold) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_cca_threshold.request.threshold = threshold; sli_zigbee_send_ipc_cmd(sli_mac_stack_set_cca_threshold_process_ipc_command, &msg); } void sl_mac_set_csma_params(sl_mac_csma_parameters_t *csma_params) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (csma_params != NULL) { msg.data.set_csma_params.request.csma_params = *csma_params; @@ -563,7 +563,7 @@ void sl_mac_set_csma_params(sl_mac_csma_parameters_t *csma_params) sl_status_t sl_zigbee_clear_counters(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_clear_counters_process_ipc_command, &msg); @@ -572,7 +572,7 @@ sl_status_t sl_zigbee_clear_counters(void) bool sl_zigbee_counter_requires_destination_node_id(sl_zigbee_counter_type_t type) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.counter_requires_destination_node_id.request.type = type; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_counter_requires_destination_node_id_process_ipc_command, &msg); @@ -581,7 +581,7 @@ bool sl_zigbee_counter_requires_destination_node_id(sl_zigbee_counter_type_t typ bool sl_zigbee_counter_requires_phy_index(sl_zigbee_counter_type_t type) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.counter_requires_phy_index.request.type = type; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_counter_requires_phy_index_process_ipc_command, &msg); @@ -590,7 +590,7 @@ bool sl_zigbee_counter_requires_phy_index(sl_zigbee_counter_type_t type) uint8_t sl_zigbee_get_endpoint(uint8_t index) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_endpoint.request.index = index; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_endpoint_process_ipc_command, &msg); @@ -601,7 +601,7 @@ uint16_t sl_zigbee_get_endpoint_cluster(uint8_t endpoint, sl_zigbee_cluster_list_id_t listId, uint8_t listIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_endpoint_cluster.request.endpoint = endpoint; msg.data.get_endpoint_cluster.request.listId = listId; msg.data.get_endpoint_cluster.request.listIndex = listIndex; @@ -612,7 +612,7 @@ uint16_t sl_zigbee_get_endpoint_cluster(uint8_t endpoint, uint8_t sl_zigbee_get_endpoint_count(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_endpoint_count_process_ipc_command, &msg); @@ -622,7 +622,7 @@ uint8_t sl_zigbee_get_endpoint_count(void) bool sl_zigbee_get_endpoint_description(uint8_t endpoint, sl_zigbee_endpoint_description_t *result) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_endpoint_description.request.endpoint = endpoint; if (result != NULL) { @@ -640,7 +640,7 @@ bool sl_zigbee_get_endpoint_description(uint8_t endpoint, uint8_t * sl_zigbee_get_eui64(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_eui64_process_ipc_command, &msg); @@ -649,7 +649,7 @@ uint8_t * sl_zigbee_get_eui64(void) void sl_zigbee_get_extended_pan_id(uint8_t *resultLocation) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (resultLocation != NULL) { memmove(msg.data.get_extended_pan_id.request.resultLocation, resultLocation, sizeof(uint8_t) * (16)); @@ -664,7 +664,7 @@ void sl_zigbee_get_extended_pan_id(uint8_t *resultLocation) uint8_t sl_zigbee_get_initial_neighbor_outgoing_cost(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_initial_neighbor_outgoing_cost_process_ipc_command, &msg); @@ -673,7 +673,7 @@ uint8_t sl_zigbee_get_initial_neighbor_outgoing_cost(void) uint16_t sl_zigbee_get_manufacturer_code(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_manufacturer_code_process_ipc_command, &msg); @@ -682,7 +682,7 @@ uint16_t sl_zigbee_get_manufacturer_code(void) uint8_t sl_zigbee_get_max_nwk_retries(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_max_nwk_retries_process_ipc_command, &msg); @@ -692,7 +692,7 @@ uint8_t sl_zigbee_get_max_nwk_retries(void) sl_status_t sl_zigbee_get_neighbor(uint8_t index, sl_zigbee_neighbor_table_entry_t *result) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_neighbor.request.index = index; if (result != NULL) { @@ -711,7 +711,7 @@ sl_status_t sl_zigbee_get_neighbor(uint8_t index, sl_status_t sl_zigbee_get_neighbor_frame_counter(sl_802154_long_addr_t nodeEui64, uint32_t *returnFrameCounter) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (nodeEui64 != NULL) { memmove(msg.data.get_neighbor_frame_counter.request.nodeEui64, nodeEui64, sizeof(sl_802154_long_addr_t)); @@ -737,7 +737,7 @@ sl_status_t sl_zigbee_get_neighbor_frame_counter(sl_802154_long_addr_t nodeEui64 sl_status_t sl_zigbee_get_network_parameters(sl_zigbee_node_type_t *node_type, sl_zigbee_network_parameters_t *parameters) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (node_type != NULL) { msg.data.get_network_parameters.request.node_type = *node_type; @@ -762,7 +762,7 @@ sl_status_t sl_zigbee_get_network_parameters(sl_zigbee_node_type_t *node_type, sl_status_t sl_zigbee_get_node_descriptor(sl_zigbee_node_descriptor_info_t *descriptor) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (descriptor != NULL) { msg.data.get_node_descriptor.request.descriptor = *descriptor; @@ -779,7 +779,7 @@ sl_status_t sl_zigbee_get_node_descriptor(sl_zigbee_node_descriptor_info_t *desc sl_802154_short_addr_t sl_zigbee_get_node_id(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_node_id_process_ipc_command, &msg); @@ -788,7 +788,7 @@ sl_802154_short_addr_t sl_zigbee_get_node_id(void) sl_802154_pan_id_t sl_zigbee_get_pan_id(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_pan_id_process_ipc_command, &msg); @@ -797,7 +797,7 @@ sl_802154_pan_id_t sl_zigbee_get_pan_id(void) uint8_t sl_zigbee_get_phy_interface_count(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_phy_interface_count_process_ipc_command, &msg); @@ -806,7 +806,7 @@ uint8_t sl_zigbee_get_phy_interface_count(void) uint8_t sl_zigbee_get_radio_channel(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_radio_channel_process_ipc_command, &msg); @@ -816,7 +816,7 @@ uint8_t sl_zigbee_get_radio_channel(void) sl_status_t sl_zigbee_get_radio_parameters(uint8_t phyIndex, sl_zigbee_multi_phy_radio_parameters_t *parameters) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_radio_parameters.request.phyIndex = phyIndex; if (parameters != NULL) { @@ -834,7 +834,7 @@ sl_status_t sl_zigbee_get_radio_parameters(uint8_t phyIndex, int8_t sl_zigbee_get_radio_power(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_radio_power_process_ipc_command, &msg); @@ -843,7 +843,7 @@ int8_t sl_zigbee_get_radio_power(void) void * sl_zigbee_get_rail_handle(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_rail_handle_process_ipc_command, &msg); @@ -853,7 +853,7 @@ void * sl_zigbee_get_rail_handle(void) sl_status_t sl_zigbee_get_route_table_entry(uint8_t index, sl_zigbee_route_table_entry_t *result) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_route_table_entry.request.index = index; if (result != NULL) { @@ -871,7 +871,7 @@ sl_status_t sl_zigbee_get_route_table_entry(uint8_t index, uint8_t sl_zigbee_get_route_table_size(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_route_table_size_process_ipc_command, &msg); @@ -880,7 +880,7 @@ uint8_t sl_zigbee_get_route_table_size(void) uint8_t sl_zigbee_get_routing_shortcut_threshold(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_routing_shortcut_threshold_process_ipc_command, &msg); @@ -889,7 +889,7 @@ uint8_t sl_zigbee_get_routing_shortcut_threshold(void) uint8_t sl_zigbee_get_source_route_table_size(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_source_route_table_size_process_ipc_command, &msg); @@ -898,7 +898,7 @@ uint8_t sl_zigbee_get_source_route_table_size(void) uint8_t sl_zigbee_get_stack_compliance_revision(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_stack_compliance_revision_process_ipc_command, &msg); @@ -907,7 +907,7 @@ uint8_t sl_zigbee_get_stack_compliance_revision(void) uint8_t sl_zigbee_get_token_count(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_token_count_process_ipc_command, &msg); @@ -918,7 +918,7 @@ sl_status_t sl_zigbee_get_token_data(uint32_t token, uint32_t index, sl_zigbee_token_data_t *tokenData) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_token_data.request.token = token; msg.data.get_token_data.request.index = index; @@ -938,7 +938,7 @@ sl_status_t sl_zigbee_get_token_data(uint32_t token, sl_status_t sl_zigbee_get_token_info(uint8_t index, sl_zigbee_token_info_t *tokenInfo) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.get_token_info.request.index = index; if (tokenInfo != NULL) { @@ -956,7 +956,7 @@ sl_status_t sl_zigbee_get_token_info(uint8_t index, bool sl_zigbee_is_local_eui64(sl_802154_long_addr_t eui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui64 != NULL) { memmove(msg.data.is_local_eui64.request.eui64, eui64, sizeof(sl_802154_long_addr_t)); @@ -973,7 +973,7 @@ bool sl_zigbee_is_local_eui64(sl_802154_long_addr_t eui64) bool sl_zigbee_is_reset_rejoining_neighbors_frame_counter_enabled(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_is_reset_rejoining_neighbors_frame_counter_enabled_process_ipc_command, &msg); @@ -983,7 +983,7 @@ bool sl_zigbee_is_reset_rejoining_neighbors_frame_counter_enabled(void) sl_status_t sl_zigbee_lookup_eui64_by_node_id(sl_802154_short_addr_t nodeId, sl_802154_long_addr_t eui64Return) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.lookup_eui64_by_node_id.request.nodeId = nodeId; if (eui64Return != NULL) { @@ -1002,7 +1002,7 @@ sl_status_t sl_zigbee_lookup_eui64_by_node_id(sl_802154_short_addr_t nodeId, sl_status_t sl_zigbee_lookup_node_id_by_eui64(sl_802154_long_addr_t eui64, sl_802154_short_addr_t *node_id) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui64 != NULL) { memmove(msg.data.lookup_node_id_by_eui64.request.eui64, eui64, sizeof(sl_802154_long_addr_t)); @@ -1027,7 +1027,7 @@ sl_status_t sl_zigbee_lookup_node_id_by_eui64(sl_802154_long_addr_t eui64, uint32_t sl_zigbee_ms_to_next_stack_event(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_ms_to_next_stack_event_process_ipc_command, &msg); @@ -1036,7 +1036,7 @@ uint32_t sl_zigbee_ms_to_next_stack_event(void) uint8_t sl_zigbee_neighbor_count(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_neighbor_count_process_ipc_command, &msg); @@ -1045,7 +1045,7 @@ uint8_t sl_zigbee_neighbor_count(void) sl_zigbee_network_status_t sl_zigbee_network_state(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_network_state_process_ipc_command, &msg); @@ -1054,7 +1054,7 @@ sl_zigbee_network_status_t sl_zigbee_network_state(void) uint8_t sl_zigbee_next_zigbee_sequence_number(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_next_zigbee_sequence_number_process_ipc_command, &msg); @@ -1064,7 +1064,7 @@ uint8_t sl_zigbee_next_zigbee_sequence_number(void) void sl_zigbee_read_and_clear_counters(uint16_t *counter_array, uint8_t len) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if ((len) > (SL_ZIGBEE_COUNTER_TYPE_COUNT)) { assert(false); // "vector counter_array length exceeds expected maximum @@ -1084,7 +1084,7 @@ void sl_zigbee_read_and_clear_counters(uint16_t *counter_array, void sl_zigbee_read_counters(uint16_t *counter_array, uint8_t len) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if ((len) > (SL_ZIGBEE_COUNTER_TYPE_COUNT)) { assert(false); // "vector counter_array length exceeds expected maximum @@ -1103,7 +1103,7 @@ void sl_zigbee_read_counters(uint16_t *counter_array, sl_status_t sl_zigbee_reset_counters_thresholds(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_reset_counters_thresholds_process_ipc_command, &msg); @@ -1112,14 +1112,14 @@ sl_status_t sl_zigbee_reset_counters_thresholds(void) void sl_zigbee_reset_rejoining_neighbors_frame_counter(bool reset) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.reset_rejoining_neighbors_frame_counter.request.reset = reset; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_reset_rejoining_neighbors_frame_counter_process_ipc_command, &msg); } uint8_t sl_zigbee_security_level(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_security_level_process_ipc_command, &msg); @@ -1128,7 +1128,7 @@ uint8_t sl_zigbee_security_level(void) sl_status_t sl_zigbee_set_broken_route_error_code(uint8_t errorCode) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_broken_route_error_code.request.errorCode = errorCode; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_broken_route_error_code_process_ipc_command, &msg); @@ -1138,7 +1138,7 @@ sl_status_t sl_zigbee_set_broken_route_error_code(uint8_t errorCode) sl_status_t sl_zigbee_set_counter_threshold(sl_zigbee_counter_type_t type, uint16_t threshold) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_counter_threshold.request.type = type; msg.data.set_counter_threshold.request.threshold = threshold; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_counter_threshold_process_ipc_command, &msg); @@ -1148,7 +1148,7 @@ sl_status_t sl_zigbee_set_counter_threshold(sl_zigbee_counter_type_t type, sl_status_t sl_zigbee_set_initial_neighbor_outgoing_cost(uint8_t cost) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_initial_neighbor_outgoing_cost.request.cost = cost; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_initial_neighbor_outgoing_cost_process_ipc_command, &msg); @@ -1157,7 +1157,7 @@ sl_status_t sl_zigbee_set_initial_neighbor_outgoing_cost(uint8_t cost) sl_status_t sl_zigbee_set_logical_and_radio_channel(uint8_t channel) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_logical_and_radio_channel.request.channel = channel; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_logical_and_radio_channel_process_ipc_command, &msg); @@ -1167,7 +1167,7 @@ sl_status_t sl_zigbee_set_logical_and_radio_channel(uint8_t channel) sl_status_t sl_zigbee_set_neighbor_frame_counter(sl_802154_long_addr_t nodeEui64, uint32_t frameCounter) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (nodeEui64 != NULL) { memmove(msg.data.set_neighbor_frame_counter.request.nodeEui64, nodeEui64, sizeof(sl_802154_long_addr_t)); @@ -1185,7 +1185,7 @@ sl_status_t sl_zigbee_set_neighbor_frame_counter(sl_802154_long_addr_t nodeEui64 sl_status_t sl_zigbee_set_node_descriptor(sl_zigbee_node_descriptor_info_t *descriptor) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (descriptor != NULL) { msg.data.set_node_descriptor.request.descriptor = *descriptor; @@ -1202,7 +1202,7 @@ sl_status_t sl_zigbee_set_node_descriptor(sl_zigbee_node_descriptor_info_t *desc sl_status_t sl_zigbee_set_node_id(sl_802154_short_addr_t nodeId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_node_id.request.nodeId = nodeId; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_node_id_process_ipc_command, &msg); @@ -1211,7 +1211,7 @@ sl_status_t sl_zigbee_set_node_id(sl_802154_short_addr_t nodeId) sl_status_t sl_zigbee_set_power_descriptor(uint16_t descriptor) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_power_descriptor.request.descriptor = descriptor; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_power_descriptor_process_ipc_command, &msg); @@ -1220,7 +1220,7 @@ sl_status_t sl_zigbee_set_power_descriptor(uint16_t descriptor) sl_status_t sl_zigbee_set_radio_channel(uint8_t channel) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_radio_channel.request.channel = channel; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_radio_channel_process_ipc_command, &msg); @@ -1229,7 +1229,7 @@ sl_status_t sl_zigbee_set_radio_channel(uint8_t channel) sl_status_t sl_zigbee_set_radio_ieee802154_cca_mode(uint8_t ccaMode) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_radio_ieee802154_cca_mode.request.ccaMode = ccaMode; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_radio_ieee802154_cca_mode_process_ipc_command, &msg); @@ -1238,7 +1238,7 @@ sl_status_t sl_zigbee_set_radio_ieee802154_cca_mode(uint8_t ccaMode) sl_status_t sl_zigbee_set_radio_power(int8_t power) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_radio_power.request.power = power; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_radio_power_process_ipc_command, &msg); @@ -1247,14 +1247,14 @@ sl_status_t sl_zigbee_set_radio_power(int8_t power) void sl_zigbee_set_route_table_size(uint8_t size) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_route_table_size.request.size = size; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_route_table_size_process_ipc_command, &msg); } sl_status_t sl_zigbee_set_routing_shortcut_threshold(uint8_t costThresh) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_routing_shortcut_threshold.request.costThresh = costThresh; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_routing_shortcut_threshold_process_ipc_command, &msg); @@ -1263,21 +1263,21 @@ sl_status_t sl_zigbee_set_routing_shortcut_threshold(uint8_t costThresh) void sl_zigbee_set_security_level(uint8_t securityLevel) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_security_level.request.securityLevel = securityLevel; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_security_level_process_ipc_command, &msg); } void sl_zigbee_set_source_route_table_size(uint8_t size) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_source_route_table_size.request.size = size; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_source_route_table_size_process_ipc_command, &msg); } void sl_zigbee_set_stack_profile(uint8_t stackProfile) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_stack_profile.request.stackProfile = stackProfile; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_stack_profile_process_ipc_command, &msg); } @@ -1286,7 +1286,7 @@ sl_status_t sl_zigbee_set_token_data(uint32_t token, uint32_t index, sl_zigbee_token_data_t *tokenData) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_token_data.request.token = token; msg.data.set_token_data.request.index = index; @@ -1305,7 +1305,7 @@ sl_status_t sl_zigbee_set_token_data(uint32_t token, bool sl_zigbee_stack_is_up(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_stack_is_up_process_ipc_command, &msg); @@ -1314,7 +1314,7 @@ bool sl_zigbee_stack_is_up(void) uint8_t sl_zigbee_stack_profile(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_stack_profile_process_ipc_command, &msg); @@ -1324,7 +1324,7 @@ uint8_t sl_zigbee_stack_profile(void) void sl_zigbee_token_factory_reset(bool exclude_outgoing_fc, bool exclude_boot_counter) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.token_factory_reset.request.exclude_outgoing_fc = exclude_outgoing_fc; msg.data.token_factory_reset.request.exclude_boot_counter = exclude_boot_counter; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_token_factory_reset_process_ipc_command, &msg); @@ -1332,7 +1332,7 @@ void sl_zigbee_token_factory_reset(bool exclude_outgoing_fc, sl_status_t sl_zigbee_write_node_data(bool erase) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.write_node_data.request.erase = erase; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_write_node_data_process_ipc_command, &msg); @@ -1341,7 +1341,7 @@ sl_status_t sl_zigbee_write_node_data(bool erase) uint8_t slx_zigbee_routing_get_route_record_policy(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(slxi_zigbee_stack_routing_get_route_record_policy_process_ipc_command, &msg); @@ -1350,7 +1350,7 @@ uint8_t slx_zigbee_routing_get_route_record_policy(void) sl_status_t slx_zigbee_routing_set_route_record_policy(sl_zigbee_route_record_policy_type_t policy) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.routing_set_route_record_policy.request.policy = policy; sli_zigbee_send_ipc_cmd(slxi_zigbee_stack_routing_set_route_record_policy_process_ipc_command, &msg); diff --git a/protocol/zigbee/stack/internal/src/ipc/trust-center-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/trust-center-ipc-command-messages.c index 095da3e4e5..9b67af74ba 100644 --- a/protocol/zigbee/stack/internal/src/ipc/trust-center-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/trust-center-ipc-command-messages.c @@ -93,7 +93,7 @@ void sli_zigbee_stack_unicast_current_network_key_process_ipc_command(sli_zigbee sl_status_t sl_zigbee_broadcast_network_key_switch(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_broadcast_network_key_switch_process_ipc_command, &msg); @@ -102,7 +102,7 @@ sl_status_t sl_zigbee_broadcast_network_key_switch(void) sl_status_t sl_zigbee_broadcast_next_network_key(sl_zigbee_key_data_t *key) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (key != NULL) { msg.data.broadcast_next_network_key.request.key = *key; @@ -119,7 +119,7 @@ sl_status_t sl_zigbee_broadcast_next_network_key(sl_zigbee_key_data_t *key) sl_zigbee_app_link_key_request_policy_t sl_zigbee_get_app_link_key_request_policy(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_app_link_key_request_policy_process_ipc_command, &msg); @@ -128,7 +128,7 @@ sl_zigbee_app_link_key_request_policy_t sl_zigbee_get_app_link_key_request_polic uint16_t sl_zigbee_get_transient_device_table_timeout_ms(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_transient_device_table_timeout_ms_process_ipc_command, &msg); @@ -137,7 +137,7 @@ uint16_t sl_zigbee_get_transient_device_table_timeout_ms(void) sl_zigbee_tc_link_key_request_policy_t sl_zigbee_get_trust_center_link_key_request_policy(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_trust_center_link_key_request_policy_process_ipc_command, &msg); @@ -148,7 +148,7 @@ sl_status_t sl_zigbee_send_remove_device(sl_802154_short_addr_t destShort, sl_802154_long_addr_t destLong, sl_802154_long_addr_t deviceToRemoveLong) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_remove_device.request.destShort = destShort; if (destLong != NULL) { @@ -175,7 +175,7 @@ sl_status_t sl_zigbee_send_remove_device(sl_802154_short_addr_t destShort, sl_status_t sl_zigbee_send_trust_center_link_key(sl_802154_short_addr_t destinationNodeId, sl_802154_long_addr_t destinationEui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_trust_center_link_key.request.destinationNodeId = destinationNodeId; if (destinationEui64 != NULL) { @@ -195,7 +195,7 @@ sl_status_t sl_zigbee_send_unicast_network_key_update(sl_802154_short_addr_t tar sl_802154_long_addr_t targetLong, const sl_zigbee_key_data_t *newKey) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.send_unicast_network_key_update.request.targetShort = targetShort; if (targetLong != NULL) { @@ -217,14 +217,14 @@ sl_status_t sl_zigbee_send_unicast_network_key_update(sl_802154_short_addr_t tar void sl_zigbee_set_app_link_key_request_policy(sl_zigbee_app_link_key_request_policy_t policy) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_app_link_key_request_policy.request.policy = policy; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_app_link_key_request_policy_process_ipc_command, &msg); } sl_status_t sl_zigbee_set_transient_device_table_timeout_ms(uint16_t timeout) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_transient_device_table_timeout_ms.request.timeout = timeout; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_transient_device_table_timeout_ms_process_ipc_command, &msg); @@ -233,7 +233,7 @@ sl_status_t sl_zigbee_set_transient_device_table_timeout_ms(uint16_t timeout) void sl_zigbee_set_trust_center_link_key_request_policy(sl_zigbee_tc_link_key_request_policy_t policy) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_trust_center_link_key_request_policy.request.policy = policy; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_trust_center_link_key_request_policy_process_ipc_command, &msg); } @@ -242,7 +242,7 @@ sl_status_t sl_zigbee_unicast_current_network_key(sl_802154_short_addr_t targetS sl_802154_long_addr_t targetLong, sl_802154_short_addr_t parentShortId) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.unicast_current_network_key.request.targetShort = targetShort; if (targetLong != NULL) { diff --git a/protocol/zigbee/stack/internal/src/ipc/zigbee-device-stack-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/zigbee-device-stack-ipc-command-messages.c index fea63bbe22..9bbac69efd 100644 --- a/protocol/zigbee/stack/internal/src/ipc/zigbee-device-stack-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/zigbee-device-stack-ipc-command-messages.c @@ -91,7 +91,7 @@ sl_status_t sl_zigbee_energy_scan_request(sl_802154_short_addr_t target, uint8_t scanDuration, uint16_t scanCount) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.energy_scan_request.request.target = target; msg.data.energy_scan_request.request.scanChannels = scanChannels; msg.data.energy_scan_request.request.scanDuration = scanDuration; @@ -103,7 +103,7 @@ sl_status_t sl_zigbee_energy_scan_request(sl_802154_short_addr_t target, uint8_t sl_zigbee_get_last_stack_zig_dev_request_sequence(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_last_stack_zig_dev_request_sequence_process_ipc_command, &msg); @@ -115,7 +115,7 @@ sl_status_t sl_zigbee_ieee_address_request(sl_802154_short_addr_t target, uint8_t childStartIndex, sl_zigbee_aps_option_t options) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.ieee_address_request.request.target = target; msg.data.ieee_address_request.request.reportKids = reportKids; msg.data.ieee_address_request.request.childStartIndex = childStartIndex; @@ -131,7 +131,7 @@ sl_status_t sl_zigbee_ieee_address_request_to_target(sl_802154_short_addr_t disc sl_zigbee_aps_option_t options, sl_802154_short_addr_t targetNodeIdOfRequest) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.ieee_address_request_to_target.request.discoveryNodeId = discoveryNodeId; msg.data.ieee_address_request_to_target.request.reportKids = reportKids; msg.data.ieee_address_request_to_target.request.childStartIndex = childStartIndex; @@ -146,7 +146,7 @@ sl_status_t sl_zigbee_network_address_request(sl_802154_long_addr_t target, bool reportKids, uint8_t childStartIndex) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (target != NULL) { memmove(msg.data.network_address_request.request.target, target, sizeof(sl_802154_long_addr_t)); @@ -165,7 +165,7 @@ sl_status_t sl_zigbee_network_address_request(sl_802154_long_addr_t target, sl_status_t sl_zigbee_send_device_announcement(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_send_device_announcement_process_ipc_command, &msg); @@ -174,7 +174,7 @@ sl_status_t sl_zigbee_send_device_announcement(void) sl_status_t sl_zigbee_send_parent_announcement(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_send_parent_announcement_process_ipc_command, &msg); @@ -183,7 +183,7 @@ sl_status_t sl_zigbee_send_parent_announcement(void) sl_status_t sl_zigbee_set_manufacturer_code(uint16_t code) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_manufacturer_code.request.code = code; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_manufacturer_code_process_ipc_command, &msg); @@ -192,14 +192,14 @@ sl_status_t sl_zigbee_set_manufacturer_code(uint16_t code) void sl_zigbee_set_pending_network_update_channel(uint8_t channel) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_pending_network_update_channel.request.channel = channel; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_pending_network_update_channel_process_ipc_command, &msg); } void sl_zigbee_set_zdo_configuration_mode(bool enabled) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_zdo_configuration_mode.request.enabled = enabled; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_zdo_configuration_mode_process_ipc_command, &msg); } diff --git a/protocol/zigbee/stack/internal/src/ipc/zigbee-security-manager-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/zigbee-security-manager-ipc-command-messages.c index 5a40244072..1f573a98a3 100644 --- a/protocol/zigbee/stack/internal/src/ipc/zigbee-security-manager-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/zigbee-security-manager-ipc-command-messages.c @@ -201,7 +201,7 @@ sl_status_t sl_zigbee_sec_man_aes_128_crypt_block(bool encrypt, const uint8_t *input, uint8_t *output) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.sec_man_aes_128_crypt_block.request.encrypt = encrypt; if (input != NULL) { @@ -229,7 +229,7 @@ sl_status_t sl_zigbee_sec_man_aes_ccm_extended(uint8_t *nonce, uint8_t mic_length, uint8_t *output) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (nonce != NULL) { memmove(msg.data.sec_man_aes_ccm_extended.request.nonce, nonce, sizeof(uint8_t) * (NONCE_LENGTH)); @@ -267,7 +267,7 @@ sl_status_t sl_zigbee_sec_man_aes_ccm_extended(uint8_t *nonce, sl_status_t sl_zigbee_sec_man_check_key_context(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_check_key_context.request.context = *context; @@ -285,7 +285,7 @@ sl_status_t sl_zigbee_sec_man_check_key_context(sl_zigbee_sec_man_context_t *con bool sl_zigbee_sec_man_compare_key_to_value(sl_zigbee_sec_man_context_t *context, const sl_zigbee_sec_man_key_t *test_key) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_compare_key_to_value.request.context = *context; @@ -306,7 +306,7 @@ bool sl_zigbee_sec_man_compare_key_to_value(sl_zigbee_sec_man_context_t *context sl_status_t sl_zigbee_sec_man_delete_key(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_delete_key.request.context = *context; @@ -323,7 +323,7 @@ sl_status_t sl_zigbee_sec_man_delete_key(sl_zigbee_sec_man_context_t *context) sl_status_t sl_zigbee_sec_man_delete_key_table_key(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_delete_key_table_key.request.context = *context; @@ -340,7 +340,7 @@ sl_status_t sl_zigbee_sec_man_delete_key_table_key(sl_zigbee_sec_man_context_t * sl_status_t sl_zigbee_sec_man_delete_transient_key(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_delete_transient_key.request.context = *context; @@ -358,7 +358,7 @@ sl_status_t sl_zigbee_sec_man_delete_transient_key(sl_zigbee_sec_man_context_t * sl_status_t sl_zigbee_sec_man_export_key(sl_zigbee_sec_man_context_t *context, sl_zigbee_sec_man_key_t *plaintext_key) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_export_key.request.context = *context; @@ -386,7 +386,7 @@ sl_status_t sl_zigbee_sec_man_export_link_key_by_eui(sl_802154_long_addr_t eui, sl_zigbee_sec_man_key_t *plaintext_key, sl_zigbee_sec_man_aps_key_metadata_t *key_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui != NULL) { memmove(msg.data.sec_man_export_link_key_by_eui.request.eui, eui, sizeof(sl_802154_long_addr_t)); @@ -430,7 +430,7 @@ sl_status_t sl_zigbee_sec_man_export_link_key_by_index(uint8_t index, sl_zigbee_sec_man_key_t *plaintext_key, sl_zigbee_sec_man_aps_key_metadata_t *key_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.sec_man_export_link_key_by_index.request.index = index; if (context != NULL) { @@ -465,7 +465,7 @@ sl_status_t sl_zigbee_sec_man_export_link_key_by_index(uint8_t index, sl_status_t sl_zigbee_sec_man_export_symmetric_passphrase(sl_802154_long_addr_t address, sl_zigbee_key_data_t *key_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (address != NULL) { memmove(msg.data.sec_man_export_symmetric_passphrase.request.address, address, sizeof(sl_802154_long_addr_t)); @@ -493,7 +493,7 @@ sl_status_t sl_zigbee_sec_man_export_transient_key_by_eui(sl_802154_long_addr_t sl_zigbee_sec_man_key_t *plaintext_key, sl_zigbee_sec_man_aps_key_metadata_t *key_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui64 != NULL) { memmove(msg.data.sec_man_export_transient_key_by_eui.request.eui64, eui64, sizeof(sl_802154_long_addr_t)); @@ -537,7 +537,7 @@ sl_status_t sl_zigbee_sec_man_export_transient_key_by_index(uint8_t index, sl_zigbee_sec_man_key_t *plaintext_key, sl_zigbee_sec_man_aps_key_metadata_t *key_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.sec_man_export_transient_key_by_index.request.index = index; if (context != NULL) { @@ -571,7 +571,7 @@ sl_status_t sl_zigbee_sec_man_export_transient_key_by_index(uint8_t index, uint8_t sl_zigbee_sec_man_find_symmetric_passphrase_key_table_index(sl_802154_long_addr_t address) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (address != NULL) { memmove(msg.data.sec_man_find_symmetric_passphrase_key_table_index.request.address, address, sizeof(sl_802154_long_addr_t)); @@ -589,7 +589,7 @@ uint8_t sl_zigbee_sec_man_find_symmetric_passphrase_key_table_index(sl_802154_lo sl_status_t sl_zigbee_sec_man_get_aps_key_info(sl_zigbee_sec_man_context_t *context, sl_zigbee_sec_man_aps_key_metadata_t *key_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_get_aps_key_info.request.context = *context; @@ -614,7 +614,7 @@ sl_status_t sl_zigbee_sec_man_get_aps_key_info(sl_zigbee_sec_man_context_t *cont sl_status_t sl_zigbee_sec_man_get_network_key_info(sl_zigbee_sec_man_network_key_info_t *network_key_info) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (network_key_info != NULL) { msg.data.sec_man_get_network_key_info.request.network_key_info = *network_key_info; @@ -631,7 +631,7 @@ sl_status_t sl_zigbee_sec_man_get_network_key_info(sl_zigbee_sec_man_network_key bool sl_zigbee_sec_man_have_link_key(sl_802154_long_addr_t eui) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui != NULL) { memmove(msg.data.sec_man_have_link_key.request.eui, eui, sizeof(sl_802154_long_addr_t)); @@ -650,7 +650,7 @@ void sl_zigbee_sec_man_hmac_aes_mmo(const uint8_t *input, const uint8_t data_length, uint8_t *output) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if ((data_length) > (MAX_IPC_VEC_ARG_CAPACITY)) { assert(false); // "vector input length exceeds expected maximum @@ -676,7 +676,7 @@ void sl_zigbee_sec_man_hmac_aes_mmo(const uint8_t *input, sl_status_t sl_zigbee_sec_man_import_key(sl_zigbee_sec_man_context_t *context, const sl_zigbee_sec_man_key_t *plaintext_key) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_import_key.request.context = *context; @@ -699,7 +699,7 @@ sl_status_t sl_zigbee_sec_man_import_link_key(uint8_t index, sl_802154_long_addr_t address, sl_zigbee_sec_man_key_t *plaintext_key) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.sec_man_import_link_key.request.index = index; if (address != NULL) { @@ -727,7 +727,7 @@ sl_status_t sl_zigbee_sec_man_import_symmetric_passphrase(uint8_t index, sl_802154_long_addr_t address, const sl_zigbee_key_data_t *key_data) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.sec_man_import_symmetric_passphrase.request.index = index; if (address != NULL) { @@ -750,7 +750,7 @@ sl_status_t sl_zigbee_sec_man_import_symmetric_passphrase(uint8_t index, sl_status_t sl_zigbee_sec_man_import_transient_key(sl_802154_long_addr_t eui64, sl_zigbee_sec_man_key_t *plaintext_key) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui64 != NULL) { memmove(msg.data.sec_man_import_transient_key.request.eui64, eui64, sizeof(sl_802154_long_addr_t)); @@ -775,7 +775,7 @@ sl_status_t sl_zigbee_sec_man_import_transient_key(sl_802154_long_addr_t eui64, void sl_zigbee_sec_man_init_context(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_init_context.request.context = *context; @@ -790,7 +790,7 @@ void sl_zigbee_sec_man_init_context(sl_zigbee_sec_man_context_t *context) bool sl_zigbee_sec_man_link_key_slot_available(sl_802154_long_addr_t eui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (eui64 != NULL) { memmove(msg.data.sec_man_link_key_slot_available.request.eui64, eui64, sizeof(sl_802154_long_addr_t)); @@ -807,7 +807,7 @@ bool sl_zigbee_sec_man_link_key_slot_available(sl_802154_long_addr_t eui64) sl_status_t sl_zigbee_sec_man_load_key_context(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_load_key_context.request.context = *context; @@ -824,7 +824,7 @@ sl_status_t sl_zigbee_sec_man_load_key_context(sl_zigbee_sec_man_context_t *cont void sl_zigbee_sec_man_set_context_aes_ecb_alg(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_set_context_aes_ecb_alg.request.context = *context; @@ -839,7 +839,7 @@ void sl_zigbee_sec_man_set_context_aes_ecb_alg(sl_zigbee_sec_man_context_t *cont void sl_zigbee_sec_man_set_context_extended_ccm_alg(sl_zigbee_sec_man_context_t *context) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (context != NULL) { msg.data.sec_man_set_context_extended_ccm_alg.request.context = *context; @@ -855,7 +855,7 @@ void sl_zigbee_sec_man_set_context_extended_ccm_alg(sl_zigbee_sec_man_context_t sl_status_t sl_zigbee_sec_man_update_symmetric_passphrase_eui(sl_802154_long_addr_t old_eui64, sl_802154_long_addr_t new_eui64) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (old_eui64 != NULL) { memmove(msg.data.sec_man_update_symmetric_passphrase_eui.request.old_eui64, old_eui64, sizeof(sl_802154_long_addr_t)); diff --git a/protocol/zigbee/stack/internal/src/ipc/zigbee_direct_stack_interface_ipc_command_messages.c b/protocol/zigbee/stack/internal/src/ipc/zigbee_direct_stack_interface_ipc_command_messages.c index e2a353b0d2..4611cc0407 100644 --- a/protocol/zigbee/stack/internal/src/ipc/zigbee_direct_stack_interface_ipc_command_messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/zigbee_direct_stack_interface_ipc_command_messages.c @@ -55,7 +55,7 @@ void sl_zigbee_direct_send_commissioning_response(uint8_t status, sl_802154_short_addr_t dst, sl_802154_long_addr_t longDest) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.direct_send_commissioning_response.request.status = status; msg.data.direct_send_commissioning_response.request.dst = dst; @@ -77,7 +77,7 @@ bool sl_zigbee_direct_send_ephemeral_key(sl_802154_short_addr_t destinationShort const sl_zigbee_key_data_t *keyData, uint8_t options) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.direct_send_ephemeral_key.request.destinationShortId = destinationShortId; if (destinationLongId != NULL) { @@ -110,7 +110,7 @@ bool sl_zigbee_direct_send_ephemeral_key(sl_802154_short_addr_t destinationShort uint8_t sl_zigbee_get_nwk_update_id(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_nwk_update_id_process_ipc_command, &msg); @@ -119,7 +119,7 @@ uint8_t sl_zigbee_get_nwk_update_id(void) sl_status_t sl_zigbee_transient_device_mgmt_finish(const sl_zigbee_address_info *device_ids) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (device_ids != NULL) { msg.data.transient_device_mgmt_finish.request.device_ids = *device_ids; diff --git a/protocol/zigbee/stack/internal/src/ipc/zll-api-ipc-command-messages.c b/protocol/zigbee/stack/internal/src/ipc/zll-api-ipc-command-messages.c index 1f040d4fbd..79844d25a1 100644 --- a/protocol/zigbee/stack/internal/src/ipc/zll-api-ipc-command-messages.c +++ b/protocol/zigbee/stack/internal/src/ipc/zll-api-ipc-command-messages.c @@ -161,7 +161,7 @@ void sli_zigbee_stack_zll_start_scan_process_ipc_command(sli_zigbee_ipc_cmd_t *m uint32_t sl_zigbee_get_zll_primary_channel_mask(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_zll_primary_channel_mask_process_ipc_command, &msg); @@ -170,7 +170,7 @@ uint32_t sl_zigbee_get_zll_primary_channel_mask(void) uint32_t sl_zigbee_get_zll_secondary_channel_mask(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_get_zll_secondary_channel_mask_process_ipc_command, &msg); @@ -179,7 +179,7 @@ uint32_t sl_zigbee_get_zll_secondary_channel_mask(void) bool sl_zigbee_is_zll_network(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_is_zll_network_process_ipc_command, &msg); @@ -188,35 +188,35 @@ bool sl_zigbee_is_zll_network(void) void sl_zigbee_set_zll_additional_state(uint16_t mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_zll_additional_state.request.mask = mask; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_zll_additional_state_process_ipc_command, &msg); } void sl_zigbee_set_zll_node_type(sl_zigbee_node_type_t nodeType) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_zll_node_type.request.nodeType = nodeType; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_zll_node_type_process_ipc_command, &msg); } void sl_zigbee_set_zll_primary_channel_mask(uint32_t mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_zll_primary_channel_mask.request.mask = mask; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_zll_primary_channel_mask_process_ipc_command, &msg); } void sl_zigbee_set_zll_secondary_channel_mask(uint32_t mask) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.set_zll_secondary_channel_mask.request.mask = mask; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_set_zll_secondary_channel_mask_process_ipc_command, &msg); } void sl_zigbee_zll_clear_tokens(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_clear_tokens_process_ipc_command, &msg); } @@ -224,7 +224,7 @@ void sl_zigbee_zll_clear_tokens(void) sl_status_t sl_zigbee_zll_form_network(sl_zigbee_zll_network_t *networkInfo, int8_t radioTxPower) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (networkInfo != NULL) { msg.data.zll_form_network.request.networkInfo = *networkInfo; @@ -242,7 +242,7 @@ sl_status_t sl_zigbee_zll_form_network(sl_zigbee_zll_network_t *networkInfo, sl_zigbee_zll_policy_t sl_zigbee_zll_get_policy(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_get_policy_process_ipc_command, &msg); @@ -251,7 +251,7 @@ sl_zigbee_zll_policy_t sl_zigbee_zll_get_policy(void) uint8_t sl_zigbee_zll_get_radio_idle_mode(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_get_radio_idle_mode_process_ipc_command, &msg); @@ -260,7 +260,7 @@ uint8_t sl_zigbee_zll_get_radio_idle_mode(void) void sl_zigbee_zll_get_token_stack_zll_data(sl_zigbee_tok_type_stack_zll_data_t *token) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (token != NULL) { msg.data.zll_get_token_stack_zll_data.request.token = *token; @@ -275,7 +275,7 @@ void sl_zigbee_zll_get_token_stack_zll_data(sl_zigbee_tok_type_stack_zll_data_t void sl_zigbee_zll_get_token_stack_zll_security(sl_zigbee_tok_type_stack_zll_security_t *token) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (token != NULL) { msg.data.zll_get_token_stack_zll_security.request.token = *token; @@ -291,7 +291,7 @@ void sl_zigbee_zll_get_token_stack_zll_security(sl_zigbee_tok_type_stack_zll_sec void sl_zigbee_zll_get_tokens_stack_zll(sl_zigbee_tok_type_stack_zll_data_t *data, sl_zigbee_tok_type_stack_zll_security_t *security) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (data != NULL) { msg.data.zll_get_tokens_stack_zll.request.data = *data; @@ -314,7 +314,7 @@ void sl_zigbee_zll_get_tokens_stack_zll(sl_zigbee_tok_type_stack_zll_data_t *dat sl_status_t sl_zigbee_zll_join_target(const sl_zigbee_zll_network_t *targetNetworkInfo) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (targetNetworkInfo != NULL) { msg.data.zll_join_target.request.targetNetworkInfo = *targetNetworkInfo; @@ -327,7 +327,7 @@ sl_status_t sl_zigbee_zll_join_target(const sl_zigbee_zll_network_t *targetNetwo bool sl_zigbee_zll_operation_in_progress(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_operation_in_progress_process_ipc_command, &msg); @@ -336,7 +336,7 @@ bool sl_zigbee_zll_operation_in_progress(void) bool sl_zigbee_zll_rx_on_when_idle_get_active(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_rx_on_when_idle_get_active_process_ipc_command, &msg); @@ -345,7 +345,7 @@ bool sl_zigbee_zll_rx_on_when_idle_get_active(void) void sl_zigbee_zll_scanning_complete(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_scanning_complete_process_ipc_command, &msg); } @@ -353,7 +353,7 @@ void sl_zigbee_zll_scanning_complete(void) sl_status_t sl_zigbee_zll_set_initial_security_state(const sl_zigbee_key_data_t *networkKey, const sl_zigbee_zll_initial_security_state_t *securityState) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (networkKey != NULL) { msg.data.zll_set_initial_security_state.request.networkKey = *networkKey; @@ -370,14 +370,14 @@ sl_status_t sl_zigbee_zll_set_initial_security_state(const sl_zigbee_key_data_t void sl_zigbee_zll_set_non_zll_network(void) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_set_non_zll_network_process_ipc_command, &msg); } sl_status_t sl_zigbee_zll_set_policy(sl_zigbee_zll_policy_t policy) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.zll_set_policy.request.policy = policy; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_set_policy_process_ipc_command, &msg); @@ -386,14 +386,14 @@ sl_status_t sl_zigbee_zll_set_policy(sl_zigbee_zll_policy_t policy) void sl_zigbee_zll_set_radio_idle_mode(sl_zigbee_radio_power_mode_t mode) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.zll_set_radio_idle_mode.request.mode = mode; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_set_radio_idle_mode_process_ipc_command, &msg); } sl_status_t sl_zigbee_zll_set_rx_on_when_idle(uint32_t durationMs) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.zll_set_rx_on_when_idle.request.durationMs = durationMs; sli_zigbee_send_ipc_cmd(sli_zigbee_stack_zll_set_rx_on_when_idle_process_ipc_command, &msg); @@ -402,7 +402,7 @@ sl_status_t sl_zigbee_zll_set_rx_on_when_idle(uint32_t durationMs) sl_status_t sl_zigbee_zll_set_security_state_without_key(const sl_zigbee_zll_initial_security_state_t *securityState) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (securityState != NULL) { msg.data.zll_set_security_state_without_key.request.securityState = *securityState; @@ -415,7 +415,7 @@ sl_status_t sl_zigbee_zll_set_security_state_without_key(const sl_zigbee_zll_ini void sl_zigbee_zll_set_token_stack_zll_data(sl_zigbee_tok_type_stack_zll_data_t *token) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; if (token != NULL) { msg.data.zll_set_token_stack_zll_data.request.token = *token; @@ -432,7 +432,7 @@ sl_status_t sl_zigbee_zll_start_scan(uint32_t channelMask, int8_t radioPowerForScan, sl_zigbee_node_type_t nodeType) { - sli_zigbee_ipc_cmd_t msg; + sli_zigbee_ipc_cmd_t msg = { 0, }; msg.data.zll_start_scan.request.channelMask = channelMask; msg.data.zll_start_scan.request.radioPowerForScan = radioPowerForScan; msg.data.zll_start_scan.request.nodeType = nodeType; diff --git a/protocol/zigbee/stack/platform/zigbee_token_interface.c b/protocol/zigbee/stack/platform/zigbee_token_interface.c index 81db2ba729..4f9e9aa321 100644 --- a/protocol/zigbee/stack/platform/zigbee_token_interface.c +++ b/protocol/zigbee/stack/platform/zigbee_token_interface.c @@ -74,8 +74,9 @@ void sli_zigbee_stack_token_factory_reset(bool exclude_outgoing_fc, bool exclude sli_zigbee_stack_set_token_data(token_info.nvm3Key, arrayIndex, &token_data); + // NVM3 write may take a long time to run, thus manually reset the watchdog. + halResetWatchdog(); } - halResetWatchdog(); } } } diff --git a/protocol/zigbee/tool/image-builder/image-builder-windows.exe b/protocol/zigbee/tool/image-builder/image-builder-windows.exe index 14ca4b12ea..6e856722a2 100755 --- a/protocol/zigbee/tool/image-builder/image-builder-windows.exe +++ b/protocol/zigbee/tool/image-builder/image-builder-windows.exe @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:54a6658bace13ab50d05ff70d639546f72d1a74d73f7d2e96a95aad051758d1d +oid sha256:9b90641e9961d4eff4003ab6f07e1602db8ffaaab0801eaa93ac106d85974530 size 3381743 diff --git a/protocol/zigbee/zigbee_experimental_templates.xml b/protocol/zigbee/zigbee_experimental_templates.xml index 98df7a7d4e..a716c16064 100644 --- a/protocol/zigbee/zigbee_experimental_templates.xml +++ b/protocol/zigbee/zigbee_experimental_templates.xml @@ -21,7 +21,7 @@ - + diff --git a/protocol/zigbee/zigbee_production_demos.xml b/protocol/zigbee/zigbee_production_demos.xml index 2a0da7aff5..98baa32a6a 100644 --- a/protocol/zigbee/zigbee_production_demos.xml +++ b/protocol/zigbee/zigbee_production_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + @@ -25,7 +25,7 @@ - + @@ -35,7 +35,7 @@ - + @@ -45,7 +45,7 @@ - + @@ -56,7 +56,7 @@ - + @@ -66,7 +66,7 @@ - + @@ -76,7 +76,7 @@ - + @@ -86,7 +86,7 @@ - + diff --git a/protocol/zigbee/zigbee_production_templates.xml b/protocol/zigbee/zigbee_production_templates.xml index 7b94174545..30a668c86e 100644 --- a/protocol/zigbee/zigbee_production_templates.xml +++ b/protocol/zigbee/zigbee_production_templates.xml @@ -21,7 +21,7 @@ - + @@ -36,7 +36,7 @@ - + @@ -51,7 +51,7 @@ - + @@ -66,7 +66,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -111,7 +111,7 @@ - + @@ -126,7 +126,7 @@ - + @@ -141,7 +141,7 @@ - + @@ -156,7 +156,7 @@ - + @@ -171,7 +171,7 @@ - + @@ -186,7 +186,7 @@ - + @@ -201,7 +201,7 @@ - + @@ -231,7 +231,7 @@ - + @@ -261,7 +261,7 @@ - + @@ -276,7 +276,7 @@ - + @@ -306,7 +306,7 @@ - + @@ -321,7 +321,7 @@ - + @@ -336,7 +336,7 @@ - + @@ -366,7 +366,7 @@ - + @@ -426,8 +426,8 @@ - - + + @@ -441,7 +441,7 @@ - + diff --git a/simplicity_sdk.slcs b/simplicity_sdk.slcs index 34d6c7d04f..689fd97b0d 100644 --- a/simplicity_sdk.slcs +++ b/simplicity_sdk.slcs @@ -2,7 +2,7 @@ id: "simplicity_sdk" label: "Simplicity SDK Suite" description: |- Simplicity SDK Suite for EFM32 and EFR32 microcontrollers and radios. -sdk_version: "2024.12.0" +sdk_version: "2024.12.1" specification_version: 12 supplier: "Silicon Laboratories, Inc." component_path: @@ -97,31 +97,31 @@ component_path: toolchain_mapping: "platform/common/toolchain/toolchains.slct" documentation: - docset: gecko-platform - version: "5.1.0" + version: "5.1.1" - docset: mbed-tls version: "3.5.0" - docset: connect-stack - version: "4.0.0" + version: "4.0.1" - docset: mcu-bootloader - version: "2.6.0" + version: "3.0.1" - docset: openthread - version: "2.6.0" + version: "2.6.1" - docset: rail - version: "2.18.0" + version: "2.18.1" - docset: wifi/wf200/rtos version: "3.6.2" - docset: wisun - version: "2.3.0" + version: "2.4.0" - docset: zigbee - version: "8.1.0" + version: "8.1.1" - docset: rtl-lib - version: "9.0.0" + version: "9.0.1" - docset: bluetooth - version: "9.0.0" + version: "9.0.1" - docset: protocol-usb - version: "1.4.0" + version: "1.4.1" - docset: machine-learning - version: "1.3.0" + version: "2.0.0" upgrade_manifest: - path: "app/common/upgrade.slcu" - path: "hardware/upgrade.slcu" diff --git a/util/plugin/security_manager/security_manager.c b/util/plugin/security_manager/security_manager.c index 5c8919d3a6..6bdb789f26 100644 --- a/util/plugin/security_manager/security_manager.c +++ b/util/plugin/security_manager/security_manager.c @@ -32,22 +32,6 @@ #define SL_SEC_MAN_AES_BLOCK_SIZE 16 #define SL_SEC_MAN_TRANSIENT_KEY_ID 0x200F0 -static bool is_security_manager_initialised = false; - -psa_status_t sl_sec_man_init(void) -{ - psa_status_t status = PSA_SUCCESS; - if (!is_security_manager_initialised) { - status = psa_crypto_init(); - - if (status == PSA_SUCCESS) { - is_security_manager_initialised = true; - } - } - - return status; -} - static void sl_sec_man_set_key_attributes(psa_key_id_t * sl_psa_key_id, psa_key_attributes_t *sl_psa_key_attr, psa_key_type_t sl_psa_key_type, @@ -77,7 +61,11 @@ static void sl_sec_man_set_key_attributes(psa_key_id_t * sl_psa_key_id, psa_set_key_usage_flags(sl_psa_key_attr, sl_psa_key_usage); psa_set_key_algorithm(sl_psa_key_attr, sl_psa_key_algorithm); psa_set_key_type(sl_psa_key_attr, sl_psa_key_type); - psa_set_key_bits(sl_psa_key_attr, sl_psa_key_len); + + // If we are importing a public key, dont set key bits, as it is not needed + if (!PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(sl_psa_key_type)) { + psa_set_key_bits(sl_psa_key_attr, sl_psa_key_len); + } } psa_status_t sl_sec_man_import_key(psa_key_id_t * sl_psa_key_id, diff --git a/util/plugin/security_manager/security_manager.h b/util/plugin/security_manager/security_manager.h index 7452a878a9..b4499ef580 100644 --- a/util/plugin/security_manager/security_manager.h +++ b/util/plugin/security_manager/security_manager.h @@ -24,16 +24,6 @@ #include "psa/crypto.h" #include "psa/crypto_values.h" -/** - * Initialise the security manager module. - * - * This API will internally initialise the PSA module - * - * @retval A psa_status_t status code. Refer to /ref psa_status_t. - * - */ -psa_status_t sl_sec_man_init(void); - /** * Import a key into PSA ITS. * diff --git a/util/silicon_labs/rtl/lib/gcc/cortex-m33/release/librtl_static.a b/util/silicon_labs/rtl/lib/gcc/cortex-m33/release/librtl_static.a index f7232e9edb..69e09432c7 100644 --- a/util/silicon_labs/rtl/lib/gcc/cortex-m33/release/librtl_static.a +++ b/util/silicon_labs/rtl/lib/gcc/cortex-m33/release/librtl_static.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bc813d39fb78faa45689a99cf5c6606af2e1d36835f3d7644839408e10b96a5f -size 1795648 +oid sha256:89683034626c4ab0fa5de34d1c3dbc18a7df1f24a02df0e2d8a3d55520591010 +size 1794566 diff --git a/util/silicon_labs/rtl/lib/gcc/darwin/x86-64/release/librtl_static.a b/util/silicon_labs/rtl/lib/gcc/darwin/x86-64/release/librtl_static.a index d9224a209d..0cb09c3b5d 100644 --- a/util/silicon_labs/rtl/lib/gcc/darwin/x86-64/release/librtl_static.a +++ b/util/silicon_labs/rtl/lib/gcc/darwin/x86-64/release/librtl_static.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:07d754ef8ef6a36eccae0e8d552df7a31f8f32a3585640cdbddb205c9283b9be -size 1952840 +oid sha256:68714019715b14110a67ef47299f336487015cdbc227e23d2b58341bb61bec0f +size 1951496 diff --git a/util/silicon_labs/rtl/lib/gcc/linux/aarch64/release/librtl_static.a b/util/silicon_labs/rtl/lib/gcc/linux/aarch64/release/librtl_static.a index ef58d9d2e7..ca456b2009 100644 --- a/util/silicon_labs/rtl/lib/gcc/linux/aarch64/release/librtl_static.a +++ b/util/silicon_labs/rtl/lib/gcc/linux/aarch64/release/librtl_static.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d9a7e0ceb34f1a3785613c74ff7c43bbd5011c5e771321a6e6bafb0eacc0932f -size 2254850 +oid sha256:fcfeae3966beeee8c7e42bd2dfd157a83e8cb3f5c745f615c416ecb68e266f93 +size 2253634 diff --git a/util/silicon_labs/rtl/lib/gcc/linux/armv7l/release/librtl_static.a b/util/silicon_labs/rtl/lib/gcc/linux/armv7l/release/librtl_static.a index d099b81991..f395e885f9 100644 --- a/util/silicon_labs/rtl/lib/gcc/linux/armv7l/release/librtl_static.a +++ b/util/silicon_labs/rtl/lib/gcc/linux/armv7l/release/librtl_static.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3521394c45077ffc60d52d33207ecd43592824c6aa9b5271ec8f7ea75f8bb14c -size 2325164 +oid sha256:9c3eb4b084c9d9d2034770b388164a419b6a37ac8710faca0de38e2770e08ec4 +size 2322656 diff --git a/util/silicon_labs/rtl/lib/gcc/linux/x86-64/release/librtl_static.a b/util/silicon_labs/rtl/lib/gcc/linux/x86-64/release/librtl_static.a index 60c59b0c43..10075a459c 100644 --- a/util/silicon_labs/rtl/lib/gcc/linux/x86-64/release/librtl_static.a +++ b/util/silicon_labs/rtl/lib/gcc/linux/x86-64/release/librtl_static.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2df692f9475203ce34231abd449a3503fe001c2856abadc953794a2806279312 -size 2334676 +oid sha256:8bc17ed2fa176cd5a3c4ead8ff7dd805780fcbdcdb97291848ea2b7baca2fc2c +size 2333652 diff --git a/util/silicon_labs/rtl/lib/gcc/windows/x86-64/release/librtl_static.a b/util/silicon_labs/rtl/lib/gcc/windows/x86-64/release/librtl_static.a index 538161f06b..3803eca570 100644 --- a/util/silicon_labs/rtl/lib/gcc/windows/x86-64/release/librtl_static.a +++ b/util/silicon_labs/rtl/lib/gcc/windows/x86-64/release/librtl_static.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fbbaee0562b6168862c77912b92f85324ac529318a32cf4ee00f916211f46218 -size 2461910 +oid sha256:08b952ac54ad35fbe55873768cac0939196143e0b0d11478fa3d3988ab3de73a +size 2460438 diff --git a/util/third_party/cmsis/lib/gcc/cortex-m33/libCMSISDSP.a b/util/third_party/cmsis/lib/gcc/cortex-m33/libCMSISDSP.a index b851923efb..67662bdfbd 100644 --- a/util/third_party/cmsis/lib/gcc/cortex-m33/libCMSISDSP.a +++ b/util/third_party/cmsis/lib/gcc/cortex-m33/libCMSISDSP.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1b3b975b408cedd2bd588fef76dfffa9e4474635988cc7e93bd43f50884584b9 +oid sha256:4f9464b7d07d85ee8fe7eac8f80324e61af98135dc85067996ff57655e022ab3 size 1952820 diff --git a/util/third_party/cmsis/lib/gcc/cortex-m33/libcmsis-nn.a b/util/third_party/cmsis/lib/gcc/cortex-m33/libcmsis-nn.a index 0082850bc6..316b7a3202 100644 --- a/util/third_party/cmsis/lib/gcc/cortex-m33/libcmsis-nn.a +++ b/util/third_party/cmsis/lib/gcc/cortex-m33/libcmsis-nn.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2ea6efb8f728a6ae0ec2a32e468dcc1e039a28ca5b2ac0e26b0fa537711cb26c +oid sha256:e26b676c29c4556cfd6bb8d8d89024b736c393e70ae80a80b2564a44d2394f39 size 124188 diff --git a/util/third_party/cmsis/lib/gcc/cortex-m4/libCMSISDSP.a b/util/third_party/cmsis/lib/gcc/cortex-m4/libCMSISDSP.a index 4a50498c1e..d2a25f3a14 100644 --- a/util/third_party/cmsis/lib/gcc/cortex-m4/libCMSISDSP.a +++ b/util/third_party/cmsis/lib/gcc/cortex-m4/libCMSISDSP.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2e3fca843acd7a65fdc93571d35fc2a90d483b2b6df196e2175ad3ea8255073b +oid sha256:77e35e52a98f25a93d7688ca52c356d2038d9fed165a1ded2c2c09bf040f0981 size 1947600 diff --git a/util/third_party/cmsis/lib/gcc/cortex-m4/libcmsis-nn.a b/util/third_party/cmsis/lib/gcc/cortex-m4/libcmsis-nn.a index c300f32e9e..6b5f91d363 100644 --- a/util/third_party/cmsis/lib/gcc/cortex-m4/libcmsis-nn.a +++ b/util/third_party/cmsis/lib/gcc/cortex-m4/libcmsis-nn.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:48e9c76fe806d38cb1474e7988ee3c54b2177fd53de0ae3bf9574ad9de741106 +oid sha256:77eec25a5ce3e2398d3bef0347ac6e5aedd6d47267d0a8b7a3a3cd52149e38cf size 123496 diff --git a/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a b/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a index 455782e516..3858890d77 100644 --- a/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a +++ b/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7104a621f53445b56945cea4fe2e7c830affaa2ff919ea697bce84b9784c360a +oid sha256:d846143318a86838243b66ba15054522aa4983c4e6c4f26bfc47e215f64ae0b1 size 2742634 diff --git a/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a b/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a index 645233c552..ae097ed843 100644 --- a/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a +++ b/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:df9ed317b22015c4a5120bd8cbdc2000cc959fe1b0cc5fb96cfdb4f0b536c349 +oid sha256:241957162842e7415cfb3d07dc68d5038cbe2f5d611581dd36109bab6e703f0e size 262320 diff --git a/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h b/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h index 1d45fcacfc..7dcd2addea 100644 --- a/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h +++ b/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h @@ -130,6 +130,10 @@ typedef mbedtls_psa_pake_operation_t #include "sli_crypto_transparent_types.h" #endif +#if defined(SLI_MBEDTLS_DEVICE_HC) + #include "sli_hostcrypto_transparent_types.h" +#endif + #endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ /* Define the context to be used for an operation that is executed through the @@ -159,6 +163,9 @@ typedef union { #if defined(SLI_MBEDTLS_DEVICE_S1) sli_crypto_transparent_mac_operation_t sli_crypto_transparent_ctx; #endif /* SLI_MBEDTLS_DEVICE_S1 */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + sli_hostcrypto_transparent_mac_operation_t sli_hostcrypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HC */ #endif } psa_driver_mac_context_t; @@ -181,6 +188,9 @@ typedef union { #if defined(SLI_MBEDTLS_DEVICE_S1) sli_crypto_transparent_aead_operation_t sli_crypto_transparent_ctx; #endif /* SLI_MBEDTLS_DEVICE_S1 */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + sli_hostcrypto_transparent_aead_operation_t sli_hostcrypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HC */ #endif } psa_driver_aead_context_t; diff --git a/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h b/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h index f2b96fdb87..5b73835edf 100644 --- a/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h +++ b/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h @@ -103,6 +103,10 @@ typedef struct { #include "sli_crypto_transparent_types.h" #endif +#if defined(SLI_MBEDTLS_DEVICE_HC) + #include "sli_hostcrypto_transparent_types.h" +#endif + #endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ /* Define the context to be used for an operation that is executed through the @@ -128,6 +132,9 @@ typedef union { #if defined(SLI_MBEDTLS_DEVICE_S1) sli_crypto_transparent_hash_operation_t sli_crypto_transparent_ctx; #endif /* SLI_MBEDTLS_DEVICE_S1 */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + sli_hostcrypto_transparent_hash_operation_t sli_hostcrypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HC */ #endif } psa_driver_hash_context_t; @@ -151,6 +158,9 @@ typedef union { #if defined(SLI_MBEDTLS_DEVICE_S1) sli_crypto_transparent_cipher_operation_t sli_crypto_transparent_ctx; #endif /* SLI_MBEDTLS_DEVICE_S1 */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + sli_hostcrypto_transparent_cipher_operation_t sli_hostcrypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HC */ #endif } psa_driver_cipher_context_t; diff --git a/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h b/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h index fe8eb5dfe6..a8d73619b5 100644 --- a/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h +++ b/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h @@ -84,6 +84,14 @@ #include "sli_crypto_transparent_functions.h" #endif +#if defined(SLI_MBEDTLS_DEVICE_HC) +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_hostcrypto_transparent_functions.h" +#include "sli_hostcrypto_transparent_types.h" +#endif + #if defined(SLI_MBEDTLS_DEVICE_SI91X) #ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT #define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT @@ -113,6 +121,7 @@ #define SLI_SE_OPAQUE_DRIVER_ID (5) #define SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID (6) #define SLI_CRYPTO_TRANSPARENT_DRIVER_ID (7) +#define SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID (8) #endif /* END-driver id */ @@ -1541,6 +1550,22 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_cipher_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_cipher_encrypt( attributes, @@ -1621,6 +1646,40 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt( #else return( PSA_ERROR_NOT_SUPPORTED ); #endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_cipher_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_cipher_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* Add cases for opaque driver here */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) @@ -1707,6 +1766,20 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_cipher_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_cipher_decrypt( attributes, @@ -1777,6 +1850,36 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt( #else return( PSA_ERROR_NOT_SUPPORTED ); #endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_cipher_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_cipher_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* Add cases for opaque driver here */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) @@ -1852,6 +1955,18 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_cipher_encrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_cipher_encrypt_setup( &operation->ctx.sli_se_transparent_ctx, @@ -1889,8 +2004,10 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( return( status ); #endif #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + #if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - /* Fell through, meaning no accelerator supports this operation */ + /* Fell through, meaning no accelerator supports this operation + irrespective of key location */ status = mbedtls_psa_cipher_encrypt_setup( &operation->ctx.mbedtls_ctx, attributes, key_buffer, @@ -1904,6 +2021,33 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( #endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ return( PSA_ERROR_NOT_SUPPORTED ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_cipher_encrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_cipher_encrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) #if defined(PSA_CRYPTO_DRIVER_TEST) @@ -1973,6 +2117,18 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_cipher_decrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_cipher_decrypt_setup( &operation->ctx.sli_se_transparent_ctx, @@ -2010,8 +2166,10 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( return( status ); #endif #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + #if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - /* Fell through, meaning no accelerator supports this operation */ + /* Fell through, meaning no accelerator supports this operation + irrespective of key location */ status = mbedtls_psa_cipher_decrypt_setup( &operation->ctx.mbedtls_ctx, attributes, key_buffer, @@ -2025,6 +2183,33 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( return( PSA_ERROR_NOT_SUPPORTED ); #endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_cipher_decrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_cipher_decrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) #if defined(PSA_CRYPTO_DRIVER_TEST) @@ -2108,6 +2293,12 @@ static inline psa_status_t psa_driver_wrapper_cipher_set_iv( &operation->ctx.sli_crypto_transparent_ctx, iv, iv_length ) ); #endif +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_cipher_set_iv( + &operation->ctx.sli_hostcrypto_transparent_ctx, + iv, iv_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_cipher_set_iv( @@ -2178,6 +2369,13 @@ static inline psa_status_t psa_driver_wrapper_cipher_update( input, input_length, output, output_size, output_length ) ); #endif +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_cipher_update( + &operation->ctx.sli_hostcrypto_transparent_ctx, + input, input_length, + output, output_size, output_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_cipher_update( @@ -2243,6 +2441,12 @@ static inline psa_status_t psa_driver_wrapper_cipher_finish( &operation->ctx.sli_crypto_transparent_ctx, output, output_size, output_length ) ); #endif +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_cipher_finish( + &operation->ctx.sli_hostcrypto_transparent_ctx, + output, output_size, output_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_cipher_finish( @@ -2304,6 +2508,11 @@ static inline psa_status_t psa_driver_wrapper_cipher_abort( return( sli_crypto_transparent_cipher_abort( &operation->ctx.sli_crypto_transparent_ctx ) ); #endif +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_cipher_abort( + &operation->ctx.sli_hostcrypto_transparent_ctx ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_cipher_abort( @@ -2337,6 +2546,12 @@ static inline psa_status_t psa_driver_wrapper_hash_compute( return( status ); #endif #if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_hash_compute( + alg, input, input_length, hash, hash_size, hash_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_hash_compute( alg, input, input_length, hash, hash_size, hash_length ); @@ -2398,6 +2613,15 @@ static inline psa_status_t psa_driver_wrapper_hash_setup( return( status ); #endif #if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_hash_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_hash_setup( &operation->ctx.sli_se_transparent_ctx, alg ); @@ -2463,6 +2687,13 @@ static inline psa_status_t psa_driver_wrapper_hash_clone( &target_operation->ctx.test_driver_ctx ) ); #endif #if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + target_operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + return( sli_hostcrypto_transparent_hash_clone( + &source_operation->ctx.sli_hostcrypto_transparent_ctx, + &target_operation->ctx.sli_hostcrypto_transparent_ctx ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: target_operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; @@ -2510,6 +2741,12 @@ static inline psa_status_t psa_driver_wrapper_hash_update( input, input_length ) ); #endif #if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_hash_update( + &operation->ctx.sli_hostcrypto_transparent_ctx, + input, input_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_hash_update( @@ -2556,6 +2793,12 @@ static inline psa_status_t psa_driver_wrapper_hash_finish( hash, hash_size, hash_length ) ); #endif #if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_hash_finish( + &operation->ctx.sli_hostcrypto_transparent_ctx, + hash, hash_size, hash_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_hash_finish( @@ -2598,6 +2841,11 @@ static inline psa_status_t psa_driver_wrapper_hash_abort( &operation->ctx.test_driver_ctx ) ); #endif #if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_hash_abort( + &operation->ctx.sli_hostcrypto_transparent_ctx ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_hash_abort( @@ -2651,6 +2899,17 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_aead_encrypt( attributes, key_buffer, key_buffer_size, @@ -2713,6 +2972,31 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt( plaintext, plaintext_length, ciphertext, ciphertext_size, ciphertext_length ) ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ); + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ); + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case PSA_KEY_LOCATION_SLI_SE_OPAQUE: @@ -2785,6 +3069,17 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_aead_decrypt( attributes, key_buffer, key_buffer_size, @@ -2847,6 +3142,31 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt( ciphertext, ciphertext_length, plaintext, plaintext_size, plaintext_length ) ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ); + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ); + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case PSA_KEY_LOCATION_SLI_SE_OPAQUE: @@ -2915,6 +3235,15 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + status = sli_hostcrypto_transparent_aead_encrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; status = sli_se_transparent_aead_encrypt_setup( @@ -2953,6 +3282,27 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( return( status ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + status = sli_hostcrypto_transparent_aead_encrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + status = sli_se_transparent_aead_encrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case PSA_KEY_LOCATION_SLI_SE_OPAQUE: @@ -3001,6 +3351,15 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + status = sli_hostcrypto_transparent_aead_decrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; status = sli_se_transparent_aead_decrypt_setup( @@ -3040,6 +3399,27 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( return( status ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + status = sli_hostcrypto_transparent_aead_decrypt_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + status = sli_se_transparent_aead_decrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case PSA_KEY_LOCATION_SLI_SE_OPAQUE: @@ -3080,10 +3460,13 @@ static inline psa_status_t psa_driver_wrapper_aead_set_nonce( return( mbedtls_test_transparent_aead_set_nonce( &operation->ctx.transparent_test_driver_ctx, nonce, nonce_length ) ); - - /* Add cases for opaque driver here */ - #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_aead_set_nonce( + &operation->ctx.sli_hostcrypto_transparent_ctx, + nonce, nonce_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_aead_set_nonce( @@ -3102,6 +3485,9 @@ static inline psa_status_t psa_driver_wrapper_aead_set_nonce( &operation->ctx.sli_crypto_transparent_ctx, nonce, nonce_length ) ); #endif + + /* Add cases for opaque driver here */ + #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_aead_set_nonce( @@ -3138,10 +3524,13 @@ static inline psa_status_t psa_driver_wrapper_aead_set_lengths( return( mbedtls_test_transparent_aead_set_lengths( &operation->ctx.transparent_test_driver_ctx, ad_length, plaintext_length ) ); - - /* Add cases for opaque driver here */ - #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_aead_set_lengths( + &operation->ctx.sli_hostcrypto_transparent_ctx, + ad_length, plaintext_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_aead_set_lengths( @@ -3160,6 +3549,9 @@ static inline psa_status_t psa_driver_wrapper_aead_set_lengths( &operation->ctx.sli_crypto_transparent_ctx, ad_length, plaintext_length ) ); #endif + + /* Add cases for opaque driver here */ + #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_aead_set_lengths( @@ -3196,10 +3588,13 @@ static inline psa_status_t psa_driver_wrapper_aead_update_ad( return( mbedtls_test_transparent_aead_update_ad( &operation->ctx.transparent_test_driver_ctx, input, input_length ) ); - - /* Add cases for opaque driver here */ - #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_aead_update_ad( + &operation->ctx.sli_hostcrypto_transparent_ctx, + input, input_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_aead_update_ad( @@ -3218,6 +3613,9 @@ static inline psa_status_t psa_driver_wrapper_aead_update_ad( &operation->ctx.sli_crypto_transparent_ctx, input, input_length ) ); #endif + + /* Add cases for opaque driver here */ + #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_aead_update_ad( @@ -3259,10 +3657,14 @@ static inline psa_status_t psa_driver_wrapper_aead_update( &operation->ctx.transparent_test_driver_ctx, input, input_length, output, output_size, output_length ) ); - - /* Add cases for opaque driver here */ - #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_aead_update( + &operation->ctx.sli_hostcrypto_transparent_ctx, + input, input_length, output, output_size, + output_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_aead_update( @@ -3284,6 +3686,9 @@ static inline psa_status_t psa_driver_wrapper_aead_update( input, input_length, output, output_size, output_length ) ); #endif + + /* Add cases for opaque driver here */ + #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_aead_update( @@ -3331,10 +3736,14 @@ static inline psa_status_t psa_driver_wrapper_aead_finish( &operation->ctx.transparent_test_driver_ctx, ciphertext, ciphertext_size, ciphertext_length, tag, tag_size, tag_length ) ); - - /* Add cases for opaque driver here */ - #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_aead_finish( + &operation->ctx.sli_hostcrypto_transparent_ctx, + ciphertext, ciphertext_size, + ciphertext_length, tag, tag_size, tag_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_aead_finish( @@ -3356,6 +3765,9 @@ static inline psa_status_t psa_driver_wrapper_aead_finish( ciphertext, ciphertext_size, ciphertext_length, tag, tag_size, tag_length ) ); #endif + + /* Add cases for opaque driver here */ + #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_aead_finish( @@ -3423,10 +3835,14 @@ static inline psa_status_t psa_driver_wrapper_aead_verify( &operation->ctx.transparent_test_driver_ctx, plaintext, plaintext_size, plaintext_length, tag, tag_length ) ); - - /* Add cases for opaque driver here */ - #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_aead_verify( + &operation->ctx.sli_hostcrypto_transparent_ctx, + plaintext, plaintext_size, + plaintext_length, tag, tag_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_aead_verify( @@ -3448,6 +3864,9 @@ static inline psa_status_t psa_driver_wrapper_aead_verify( plaintext, plaintext_size, plaintext_length, tag, tag_length ) ); #endif + + /* Add cases for opaque driver here */ + #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_aead_verify( @@ -3483,10 +3902,12 @@ static inline psa_status_t psa_driver_wrapper_aead_abort( case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: return( mbedtls_test_transparent_aead_abort( &operation->ctx.transparent_test_driver_ctx ) ); - - /* Add cases for opaque driver here */ - #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_aead_abort( + &operation->ctx.sli_hostcrypto_transparent_ctx ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_aead_abort( @@ -3502,6 +3923,9 @@ static inline psa_status_t psa_driver_wrapper_aead_abort( return( sli_crypto_transparent_aead_abort( &operation->ctx.sli_crypto_transparent_ctx ) ); #endif + + /* Add cases for opaque driver here */ + #if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) case SLI_SE_OPAQUE_DRIVER_ID: return( sli_se_opaque_aead_abort( @@ -3546,6 +3970,14 @@ static inline psa_status_t psa_driver_wrapper_mac_compute( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_mac_compute( attributes, key_buffer, key_buffer_size, alg, @@ -3590,6 +4022,23 @@ static inline psa_status_t psa_driver_wrapper_mac_compute( #endif /* MBEDTLS_PSA_BUILTIN_MAC */ return( PSA_ERROR_NOT_SUPPORTED ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + return sli_hostcrypto_transparent_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + return sli_se_transparent_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) #if defined(PSA_CRYPTO_DRIVER_TEST) @@ -3660,6 +4109,19 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_mac_sign_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_mac_sign_setup( &operation->ctx.sli_se_transparent_ctx, @@ -3714,6 +4176,31 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_setup( #endif /* MBEDTLS_PSA_BUILTIN_MAC */ return( PSA_ERROR_NOT_SUPPORTED ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_mac_sign_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + return status; +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_mac_sign_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + return status; +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) #if defined(PSA_CRYPTO_DRIVER_TEST) @@ -3782,6 +4269,19 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + status = sli_hostcrypto_transparent_mac_verify_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) status = sli_se_transparent_mac_verify_setup( &operation->ctx.sli_se_transparent_ctx, @@ -3836,6 +4336,31 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_setup( #endif /* MBEDTLS_PSA_BUILTIN_MAC */ return( PSA_ERROR_NOT_SUPPORTED ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(SLI_MBEDTLS_DEVICE_HC) + case PSA_KEY_LOCATION_SLI_HOSTCRYPTO_TRANSPARENT: + status = sli_hostcrypto_transparent_mac_verify_setup( + &operation->ctx.sli_hostcrypto_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID; + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case PSA_KEY_LOCATION_SLI_SE_TRANSPARENT: + status = sli_se_transparent_mac_verify_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Add cases for opaque driver here */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) #if defined(PSA_CRYPTO_DRIVER_TEST) @@ -3899,6 +4424,12 @@ static inline psa_status_t psa_driver_wrapper_mac_update( &operation->ctx.opaque_test_driver_ctx, input, input_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_mac_update( + &operation->ctx.sli_hostcrypto_transparent_ctx, + input, input_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_mac_update( @@ -3957,6 +4488,12 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_finish( &operation->ctx.opaque_test_driver_ctx, mac, mac_size, mac_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_mac_sign_finish( + &operation->ctx.sli_hostcrypto_transparent_ctx, + mac, mac_size, mac_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_mac_sign_finish( @@ -4015,6 +4552,12 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_finish( &operation->ctx.opaque_test_driver_ctx, mac, mac_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_mac_verify_finish( + &operation->ctx.sli_hostcrypto_transparent_ctx, + mac, mac_length ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_mac_verify_finish( @@ -4066,6 +4609,11 @@ static inline psa_status_t psa_driver_wrapper_mac_abort( return( mbedtls_test_opaque_mac_abort( &operation->ctx.opaque_test_driver_ctx ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HC) + case SLI_HOSTCRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_hostcrypto_transparent_mac_abort( + &operation->ctx.sli_hostcrypto_transparent_ctx ) ); +#endif #if defined(SLI_MBEDTLS_DEVICE_HSE) case SLI_SE_TRANSPARENT_DRIVER_ID: return( sli_se_transparent_mac_abort(